ENA0886 D

Ordering
Orderingnumber
number: :ENA1455A
ENA0886
LC87F7J32A
CMOS IC
FROM 32K byte, RAM 1024 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F7J32A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard
programmable), 1024-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter
(may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs),
four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer
serving as a time-of-day clock, a day and time counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex),
two 12-bit PWM channels,
a 12-bit/8-bit 10-channel AD converter, remote control receive function, a high-speed clock counter, a system clock
frequency divider, an internal reset and a 25-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V,of voltage souce
• Block-erasable in 128-byte units
• 32768 × 8 bits
RAM
• 1024 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
VDD=3.0 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 250ns (4MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
VDD=3.0 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 750ns (4MHz)
VDD=2.2 to 5.5V
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
O1707HKIM 20071009-S00002 No.A0886-1/29
LC87F7J32A
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units 15 (P1n, P30 to P31, P70 to P73, XT2)
Ports whose I/O direction can be designated in 4 bit units 8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• Normal withstand voltage input port
1 (XT1)
• LCD ports
Segment output
24 (S00 to S23)
Common output
4 (COM0 to COM3)
Bias terminals for LCD driver
3 (V1 to V3)
Other functions
Input/output ports
24 (PAn, PBn, PCn,)
Input ports
7 (PLn)
• Dedicated oscillator ports
2 (CF1, CF2)
• Reset pin
1 (RES)
• Power pins
6 (VSS1 to VSS3, VDD1 to VDD3)
LCD Controller
1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
2) Segment output and common output can be switched to general-purpose input/output ports
Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 8: 16-bit timer
Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels (with toggle output)
Mode 1: 16-bit timer with an 8-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock,
and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes
• Day and time counter
1) Using with a base timer,it can be used as 65000 day + minute + second counter.
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
No.A0886-2/29
LC87F7J32A
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12-bits/8-bits × 12 channels
• 12 bits/8 bits AD converter resolution selectable
PWM: Multi frequency 12-bit PWM × 2 channels
Infrared Remote Control Receiver Circuit
1) Noise reduction function
(noise filter time constant: Approx. 120μs, when the 32.768kHz crystal oscillator is selected as the reference
voltage source.)
2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding
3) X’tal HOLD mode release function
Watchdog Timer
• External RC watchdog timer
• Basetimer watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
No.A0886-3/29
LC87F7J32A
Interrupts
• 25 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/remote control receiver
4
0001BH
H or L
INT3/INT5/BT0/BT1
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC//T6/T7/PWM4/PWM5
10
0004BH
H or L
Port 0/T4/T5
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the diagram above).
Subroutine Stack Levels: 512 levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
For system clock
• CF oscillation circuit:
For system clock, with internal Rf
• Crystal oscillation circuit:
For low-speed system clock, with internal Rf
• Frequency variable RC oscillation circuit (internal): For system clock
1) Adjustable in ±4% (typ) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,
and 76.8μs (at a main clock rate of 10MHz).
Internal Reset Function
• Power-On-Reset (POR) function
1) POR resets the system when the power supply voltage is applied.
2) POR release level is selectable from 4 levels (2.07V, 2.37V, 2.87V, 4.35V) by option.
• Low Voltage Detection reset (LVD) function
1) LVD used with POR resets the system when the supply voltage is applied and when it is lowered.
2) LVD function is selectable from enable/disable and the reset level is selectable from 3 levels (2.31V, 2.81V,
4.28V) by option.
No.A0886-4/29
LC87F7J32A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(Some parts of the serial transfer function stops operation)
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5, pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the remote control circuit.
1) The CF, RC, and frequency variable RC oscillators automatically stop operation
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4,and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the infrared remote control receiver circuit
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QIP64E(14×14):
• TQFP64J(10×10):
Lead-free type
Lead-free type
Development Tools
• On-chip debugger: TCB87-TypeB + LC87F7J32A
Flash ROM Programming Board
Package
Programming boards
QIP64E(14×14)
W87F50256Q
TQFP64J(10×10)
W87F57256SQ
Flash ROM Programmer
Model
Maker
Single
Flash Support Group, Inc.
(Formerly Ando Electric Co., Ltd.)
Supported Version (Note)
AF9708/AF9709/
AF9709B
AF9723 (Main body)
Device
After 0x.xx
After 0x.xx
Gang
AF9833 (Unit)
Our company
SKK (SANYO FWS)
After 0x.xx
After x.xxA
LC87F7J32A
Note: Please check the latest version.
Same Package and Pin Assignment as Mask ROM Version.
1) LC877J00 series options can be set by using flash ROM data. Thus the board used for mass production can
be used for debugging and evaluation without modifications.
2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as
the mask ROM version.
No.A0886-5/29
LC87F7J32A
Package Dimensions
unit : mm (typ)
3159A
33
32
64
17
14.0
49
1
17.2
48
0.8
17.2
14.0
16
0.35
0.8
0.15
0.1
3.0max
(2.7)
(1.0)
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3310
12.0
0.5
10.0
33
32
64
17
10.0
49
1
16
0.5
0.18
12.0
48
0.125
(1.0)
0.1
1.2 MAX
(1.25)
SANYO : TQFP64J(10X10)
No.A0886-6/29
LC87F7J32A
S14/PB6
S15/PB7
VSS3
VDD3
S16/PC0
S17/PC1
S18/PC2
S19/PC3
S20/PC4
S21/PC5
S22/PC6
S23/PC7
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
49
32
S13/PB5
P71/INT1/T0HCP/AN9
50
31
S12/PB4
P72/INT2/T0IN/NKIN
51
30
S11/PB3
P73/INT3/T0IN/RMIN
52
29
S10/PB2
RES
53
28
S9/PB1
XT1/AN10
54
27
S8/PB0
XT2/AN11
55
26
S7/PA7
VSS1
56
25
S6/PA6
CF1
57
24
S5/PA5
CF2
58
23
S4/PA4
VDD1
59
22
S3/PA3
V1/PL4/AN0/DBGP0
60
21
S2/PA2
V2/PL5/AN1/DBGP1
61
20
S1/PA1/URX1
V3/PL6/AN2/DBGP2
62
19
S0/PA0/UTX1
P10/SO0
63
18
P07/T7O
P11/SI0/SB0
64
17
P06/T6O
8
9 10 11 12 13 14 15 16
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/ T1PWML
P17/T1PWMH/BUZ
P30/INT4/T1IN/T0LCP/PWM4
P31/INT5/T1IN/T0HCP/PWM5
VDD2
P04/AN7
7
P05/CKO
6
P03/AN6
5
P02/AN5
4
P01/AN4
3
P00/AN3
2
VSS2
1
P12/SCK0
LC87F7J32A
Top view
QIP64E(14×14) “Lead-free Type”
TQFP64J(10×14) “Lead-free Type”
No.A0886-7/29
LC87F7J32A
PIN No.
NAME
PIN No.
NAME
1
P12/SCK0
33
S14/PB6
2
P13/SO1
34
S15/PB7
3
P14/SI1/SB1
35
VSS3
4
P15/SCK1
36
VDD3
5
P16/T1PWML
37
S16/PC0
6
P17/T1PWMH/BUZ
38
S17/PC1
7
P30/INT4/T1IN/T0LCP1/PWM4
39
S18/PC2
8
P31/INT5/T1IN/T0HCP1/PWM5
40
S19/PC3
9
VDD2
41
S20/PC4
10
VSS2
42
S21/PC5
11
P00/AN3
43
S22/PC6
12
P01/AN4
44
S23/PC7
13
P02/AN5
45
COM0/PL0
14
P03/AN6
46
COM1/PL1
15
P04/AN7
47
COM2/PL2
16
P05/CKO
48
COM3/PL3
17
P06/T6O
49
P70/INT0/T0LCP/AN8
18
P07/T7O
50
P71/INT1/T0HCP/AN9
19
S0/PA0/UTX1
51
P72/INT2/T0IN
20
S1/PA1/URX1
52
P73/INT3/T0IN
21
S2/PA2
53
RES
22
S3/PA3
54
XT1/AN10
23
S4/PA4
55
XT2/AN11
24
S5/PA5
56
VSS1
25
S6/PA6
57
CF1
26
S7/PA7
58
CF2
27
S8/PB0
59
VDD1
28
S9/PB1
60
V1/PL4/AN0/DBGP0
29
S10/PB2
61
V2/PL5/AN1/DBGP1
30
S11/PB3
62
V3/PL6/AN2/DBGP2
31
S12/PB4
63
P10/SO0
32
S13/PB5
64
P11/SI0/SB0
No.A0886-8/29
LC87F7J32A
System Block Diagram
Interrupt control
IR
Standby control
PLA
Flash ROM
RC
VMRC
Clock
generator
CF
PC
X’tal
RES
Reset circuit
(LVD/POR)
ACC
Reset control
WTD
B register
C register
SIO0
Bus interface
ALU
SIO1
Port 0
Base timer
Port 1
Timer 0
(High speed clock counter)
ADC
Timer 1
Port 3
Timer 6
Port 7
Timer 7
LCD Controller
PSW
RAR
RAM
Stack pointer
Watchdog timer
INT0 to 5
Noise Rejection Filter
On-chip debugger
PWM4
PWM5
UART1
Timer 4
Remote control
receiver circuit
Timer 5
Day and time
counter
No.A0886-9/29
LC87F7J32A
Pin Description
Pin Name
VSS1
VSS2
VSS3
VDD1
I/O
Description
Option
-
- power supply pin
No
-
+ power supply pin
No
• 8-bit I/O port
Yes
VDD2
VDD3
PORT0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins
P00 to P04: AD converter input (AN3 to AN7)
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
PORT1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
PORT3
I/O
• 2-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P31
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P30: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/PWM4
P31: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/PWM5
• Interrupt acknowledge type
PORT7
P70 to P73
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
Falling
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input ports: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A0886-10/29
LC87F7J32A
Continued from preceding page.
Pin Name
S0/PA0 to
I/O
I/O
S7/PA7
S8/PB0 to
I/O
I/O
• Segment output for LCD
No
• Segment output for LCD
No
• Can be used as general-purpose I/O port (PC)
I/O
COM3/PL3
V1/PL4 to
No
• Can be used as general-purpose I/O port (PB)
S23/PC7
COM0/PL0 to
Option
• Can be used as general-purpose I/O port (PA)
S15/PB7
S16/PC0 to
Description
• Segment output for LCD
• Common output for LCD
No
• Can be used as general-purpose input port (PL)
I/O
V3/PL7
• LCD output bias power supply
No
• Can be used as general-purpose input port (PL)
• Shared pins
AD converter input ports: AN0 (V1) to AN2 (V3)
On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3)
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port: AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0886-11/29
LC87F7J32A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
Option Selected
in Units of
Output Type
Pull-up Resistor
1
CMOS
2
N-channel open drain
No
1
CMOS
Programmable
2
N-channel open drain
Programmable
1 bit
1
CMOS
Programmable
2
N-channel open drain
Programmable
P70
-
No
N-channel open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
S0/PA0 to S23/PC7
-
No
CMOS
Programmable
COM0/PL0 to COM3/PL3
-
No
Input only
No
No
P10 to P17
P30 to P31
1 bit
Option Type
1 bit
Programmable (Note)
V1/PL4 to V3/PL6
-
No
Input only
XT1
-
No
Input for 32.768 kHz crystal
oscillator (Input only)
XT2
-
No
Output for 32.768kHz crystal oscillator (Nch-open
drain when in general-purpose output mode)
No
No
Note1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
*1 Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI
VDD1
Power
supply
For backup
VDD2
VDD3
VSS1
VSS2 VSS3
*2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the
ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0886-12/29
LC87F7J32A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2,
VDD1=VDD2=VDD3
VLCD
VDD3
V1/PL4, V2/PL5,
VDD1=VDD2=VDD3
voltage
supply voltage for
LCD
V3/PL6
Input voltage
VI(1)
Port L
XT1, CF1, RES
Input/output
VIO(1)
voltage
min
typ
max
-0.3
+6.5
-0.3
VDD
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
Port 0, 1, 3, 7
Port A, B, C
XT2
Peak output
IOPH(1)
current
IOPH(2)
Ports 0, 1
• CMOS output selected
Ports A, B, C
• Current at each pin
Port 3
• CMOS output selected
• Current at each pin
Mean output
IOPH(3)
Port 71 to 73
Current at each pin
IOMH(1)
Ports 0, 1
• CMOS output selected
Ports A, B, C
• Current at each pin
High level output current
current
(Note 1-1)
IOMH(2)
• CMOS output selected
• Current at each pin
IOMH(3)
Ports 71 to 73
Current at each pin
-20
-5
-7.5
-15
-3
Total output
ΣIOAH(1)
Ports 71 to 73
Total of all pins
-5
current
ΣIOAH(2)
Port 1
Total of all pins
-20
Peak output
ΣIOAH(3)
Ports 1, 71 to 73
Total of all pins
-20
ΣIOAH(4)
Port 3
Total of all pins
-25
ΣIOAH(5)
Port 0
Total of all pins
-20
ΣIOAH(6)
Ports 0, 3
Total of all pins
-40
ΣIOAH(7)
Ports A, B
Total of all pins
-25
ΣIOAH(8)
Port C
Total of all pins
-20
ΣIOAH(9)
Ports A, B, C
Total of all pins
-10
IOPL(1)
Ports 0, 1
Current at each pin
current
Mean output
(Note 1-1)
mA
20
Ports A, B, C
IOPL(2)
Port 3
Current at each pin
30
IOPL(3)
Ports 7, XT2
Current at each pin
10
IOML(1)
Ports 0, 1
Current at each pin
15
Ports A, B, C
current
Low level output current
Port 3
-10
IOML(2)
Port 3
Current at each pin
20
7.5
IOML(3)
Ports 7, XT2
Current at each pin
Total output
ΣIOAL(1)
Ports 7, XT2
Total of all pins
15
current
ΣIOAL(2)
Ports 1
Total of all pins
40
ΣIOAL(3)
Ports 1, 7, XT2
Total of all pins
50
ΣIOAL(4)
Port 3
Total of all pins
45
ΣIOAL(5)
Port 0
Total of all pins
40
ΣIOAL(6)
Ports 0, 3
Total of all pins
80
ΣIOAL(7)
Ports A, B
Total of all pins
45
ΣIOAL(8)
Port C
Total of all pins
40
ΣIOAL(9)
Ports A, B, C
Total of all pins
Pd max
QIP64E(14×14)
Ta=-40 to +85°C
TQFP64J(10×10)
Ta=-40 to +85°C
Power dissipation
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
80
298
mW
-40
+85
-55
+125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A0886-13/29
LC87F7J32A
Allowable Operating Condtions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2=VDD3
supply voltage
(Note 2-1)
Memory
VHD
VDD1=VDD2=VDD3
sustaining
min
typ
max
unit
0-237μs≤tCYC≤200μs
3.0
5.5
0-356μs≤tCYC≤200μs
2.5
5.5
0-712μs≤tCYC≤200μs
2.2
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode
supply voltage
High level input
VIH(1)
voltage
• Ports 0, 3
Output disabled
• Ports A, B, C
2.2 to 5.5
0.3VDD
2.2 to 5.5
0.3VDD
2.2 to 5.5
0.85VDD
VDD
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
0.2VDD
2.2 to 5.5
VSS
0.45VDD
2.2 to 5.5
VSS
2.2 to 5.5
VSS
• Port L
VIH(2)
• Port 1
• Output disabled
• Ports 71 to 73
• When INT1VTSL=0
• Port 70 port input/
(P71only)
+0.7
+0.7
VDD
VDD
interrupt side
VIH(3)
VIH(4)
Port 71 interrupt
• Output disabled
side
• When INT1VTSL=1
Port 70 watchdog
Output disabled
timer side
VIH(5)
XT1, XT2, CF1,
RES
Low level input
VIL(1)
voltage
• Ports 0, 3
Output disabled
• Ports A, B, C
• Port L
VIL(2)
• Port 1
• Output disabled
• Ports 71 to 73
• When INT1VTSL=0
• Port 70 port
(P71 only)
input/interrupt side
VIL(3)
VIL(4)
Port 71 interrupt
• Output disabled
side
• When INT1VTSL=1
Port 70 watchdog
timer side
VIL(5)
XT1, XT2, CF1,
RES
Instruction cycle
tCYC
time
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
V
0.15VDD
+0.4
0.2VDD
0.1VDD
+0.4
0.8VDD
-1.0
0.25VDD
3.0 to 5.5
0.237
200
2.5 to 5.5
0.356
200
2.2 to 5.5
0.712
200
3.0 to 5.5
0.1
12
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
4
μs
• System clock frequency
division ratio=1/1
• External system clock
DUTY=50±5%
• CF2 pin open
3.0 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
8
division ratio=1/2
MHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Continued on next page.
No.A0886-14/29
LC87F7J32A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Oscillation
FmCF(1)
CF1, CF2
frequency
range
• 12MHz ceramic oscillation
• See figure 1.
FmCF(2)
CF1, CF2
(Note 2-3)
• 8MHz ceramic oscillation
• See figure 1.
FmCF(3)
CF1, CF2
• 4MHz ceramic oscillation
• See figure 1.
FmRC
Internal RC oscillation
FmVMRC(1)
• Frequency variable RC
min
typ
max
3.0 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
0.3
1.0
unit
2.0
source oscillation
MHz
• When
VMRAJ2 to 0=4,
2.2 to 5.5
10
2.2 to 5.5
4
2.2 to 5.5
32.768
VMFAJ2 to 0=0,
VMSL4M=0
FmVMRC(2)
• Frequency variable RC
source oscillation
• When
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=1
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See figure 2.
Frequency
variable RC
oscillation
OpVMRC(1)
When VMSL4M=0
OpVMRC(2)
When VMSL4M=1
kHz
2.2 to 5.5
8
10
12
2.2 to 5.5
3.5
4
4.5
2.2 to 5.5
8
24
64
2.2 to 5.5
1
4
8
MHz
usable range
Frequency
VmADJ(1)
Each step of VMRAJn
(Wide range)
variable RC
oscillation
VmADJ(2)
%
Each step of VMFAJn
adjustment
(Small range)
range
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
• Ports 0, 1, 3, 7
• Output disabled
• Ports A, B, C
• Pull-up resistor off
• Port L
• VIN=VDD
min
typ
max
unit
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
15
(including output Tr's off
leakage current)
IIH(2)
RES
VIN=VDD
IIH(3)
XT1, XT2
• For input port specification
• VIN=VDD
Low level input
IIH(4)
CF1
VIN=VDD
IIL(1)
• Ports 0, 1, 3, 7
• Output disabled
• Ports A, B, C
• Pull-up resistor off
• Port L
• VIN=VSS
current
2.2 to 5.5
-1
2.2 to 5.5
-1
2.2 to 5.5
-1
2.2 to 5.5
-15
μA
(including output Tr's off
leakage current)
IIL(2)
RES
VIN=VSS
IIL(3)
XT1, XT2
• For input port specification
• VIN=VSS
IIL(4)
CF1
VIN=VSS
Continued on next page.
No.A0886-15/29
LC87F7J32A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level output
VOH(1)
voltage
VDD-1
VOH(2)
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(3)
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(5)
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(6)
IOH=-1mA
2.2 to 5-5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-1mA
4.5 to 5.5
VDD-1
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
Ports 30, 31
Ports 71 to 73
VOH(8)
VOH(9)
Ports A, B, C
VOH(10)
VOH(11)
voltage
VOL(1)
VOL(2)
Ports 0, 1
Ports 3
(PWM function
max
IOL=10mA
4.5 to 5.5
1.5
IOL=1.6mA
3.0 to 5.5
0.4
VOL(3)
output mode)
IOL=1mA
2.2 to 5.5
0.4
VOL(4)
Ports 3
IOL=30mA
4.5 to 5.5
1.5
VOL(5)
(Port function output
IOL=5mA
3.0 to 5.5
0.4
IOL=2.5mA
2.2 to 5.5
0.4
VOL(6)
mode)
VOL(7)
• Port 7
IOL=1.6mA
3.0 to 5.5
0.4
VOL(8)
• XT2
IOL=1mA
2.2 to 5.5
0.4
VOL(9)
Ports A, B, C
IOH=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.2 to 5.5
0.4
VOL(10)
LCD output
typ
4.5 to 5.5
VOH(7)
Low level output
min
IOH=-1mA
VOH(4)
Ports 0, 1
VODLS
S0 to S23
voltage deviation
• IO=0mA
• VLCD, 2/3VLCD, 1/3VLCD
level output
2.2 to 5.5
0
±0.2
2.2 to 5.5
0
±0.2
unit
V
• See Fig. 8.
VODLC
COM0 to COM3
• IO=0mA
• VLCD, 2/3VLCD, 1/2VLCD,
1/3VLCD level output
• See Fig. 8.
LCD bias resistor
RLCD(1)
Resistance per
See Fig. 8.
one bias resister
RLCD(2)
Resistance per
2.2 to 5.5
80
2.2 to 5.5
40
See Fig. 8.
one bias resister
kΩ
1/2R mode
Resistance of
Rpu(1)
Ports 0, 1, 3, 7
pull-up MOS Tr.
Rpu(2)
Ports A, B, C
Hysteresis voltage
VHYS(1)
Ports 1, 7
VOH=0-9VDD
RES
Pin capacitance
CP
All pins
4.5 to 5.5
15
35
80
2.2 to 5.5
18
50
150
2.2 to 5.5
0.1VDD
V
2.2 to 5.5
10
pF
For pins other than that under
test: VIN=VSS
f=1MHz
Ta=25°C
No.A0886-16/29
LC87F7J32A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig. 6.
typ
tSCKH(1)
2.2 to 5.5
pulse width
tSCKHA(1)
1
tCYC
• Continuous data
4
Serial clock
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.2 to 5.5
pulse width
tSCKHA(2)
1/2
• Continuous data
tSCKH(2)
transmission/reception mode
+2tCYC
• CMOS output selected
• See Fig. 6.
Data setup time
Serial input
unit
1
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with
respect to rising edge of
2.2 to 5.5
0.03
2.2 to 5.5
0.03
SIOCLK
Data hold time
Output clock
Input clock
Output
Serial output
max
2
pulse width
High level
min
• See Fig. 6.
thDI(1)
tdDO(1)
delay time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdDO(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdDO(3)
2.2 to 5.5
(1/3)tCYC
+0.05
μs
1tCYC
+0.05
(Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when
serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0886-17/29
LC87F7J32A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig.6.
2.2 to 5.5
tCYC
SCK1(P15)
• CMOS output selected
2
• See Fig. 6.
tSCKL(4)
2.2 to 5.5
pulse width
High level
1/2
tSCK
tSCKH(4)
1/2
Serial output
Serial input
pulse width
Data setup time
unit
1
tSCK(4)
Low level
max
1
tSCKH(3)
Frequency
typ
2
pulse width
High level
min
pulse width
Output clock
Serial clock
VDD[V]
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
thDI(2)
Output delay
tdDO(4)
SO1(P13),
time
SB1(P14)
• Must be specified with respect
μs
to falling edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
(1/3)tCYC
2.2 to 5.5
+0.05
change in open drain output
mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72)
enabled.
min
typ
2.2 to 5.5
1
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
4
2.2 to 5.5
200
max
unit
INT4(P30),
INT5(P31)
tPIH(2)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is
• Event inputs for timer 0 are
1/1
enabled.
tPIH(3)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is
• Event inputs for timer 0 are
1/32
enabled.
tPIH(4)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is
• Event inputs for timer 0 are
1/128
tPIH(5)
RMIN(P73)
tPIL(5)
enabled.
Recognized by the infrared
remote controller receiver circuit
as a signal.
tPIL(6)
RES
tCYC
Resetting is enabled.
RMCK
(Note5-1)
μs
Note 5-1: Represents the period of the reference clock (1tCYC to 128tCYC or the source frequency of the subclock) for the
infrared remote controller receiver circuit
No.A0886-18/29
LC87F7J32A
AD Converter Characteristics at VSS1 = VSS2 = VSS3 =0V
<12bits AD Converter Mode at Ta =-40 to +85°C>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(V1) to
Absolute
ET
AN2(V3),
Conversion
AN7(P04),
TCAD
time
Analog input
typ
3.0 to 5.5
(Note 6-1)
• See Conversion time calculation
AN8(P70),
formulas.
AN9(P71),
(Note 6-2)
max
unit
12
bit
±16
3.0 to 5.5
AN3(P00) to
accuracy
min
4.0 to 5.5
32
115
3.0 to 5.5
64
115
3.0 to 5.5
VSS
VDD
LSB
μs
AN10(XT1),
VAIN
AN11(XT2)
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
1
-1
V
μA
<8bits AD Converter Mode at Ta =-40 to +85°C>
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
Absolute
N
AN0(V1) to
ET
AN2(V3),
Conversion
TCAD
time
Analog input
VAIN
AN7(P04),
(Note 6-1)
• See Conversion time calculation
AN8(P70),
formulas.
AN9(P71),
(Note 6-2)
max
unit
8
bit
3.0 to 5.5
±1.5
4.0 to 5.5
20
90
3.0 to 5.5
40
90
3.0 to 5.5
VSS
VDD
LSB
μs
AN10(XT1),
AN11(XT2)
voltage range
typ
3.0 to 5.5
AN3(P00) to
accuracy
min
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
1
-1
V
μA
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time)=((52/(division ratio)) + 2) × (1/3) ×tCYC
8bits AD Converter Mode: TCAD(Conversion time)=((32/(division ratio)) + 2) × (1/3) ×tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
System division ratio
Cycle time
(SYSDIV)
(tCYC)
AD division
AD conversion time
(TCAD)
ratio
(ADDIV)
12bit AD
8bit AD
4.0V to 5.5V
1/1
250ns
1/8
34.8μs
21.5μs
3.0V to 5.5V
1/1
250ns
1/16
69.5μs
42.8μs
4.0V to 5.5V
1/1
375ns
1/8
52.2μs
32.3μs
3.0V to 5.5V
1/1
375ns
1/16
104.3μs
64.2μs
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
CF-12MHz
CF-8MHz
CF-4MHz
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion
mode.
No.A0886-19/29
LC87F7J32A
Power-on reset (POR) Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
POR release
PORR
• Select from option.
voltage
Detection voltage
(Note 7-1)
POUKS
max
2.07V
1.95
2.07
2.19
2.25
2.37
2.49
2.87V
2.75
2.87
2.99
4.35V
4.21
4.35
4.49
0.7
0.95
(Note 7-2)
PORIS
typ
2.37V
• See Fig. 7.
unknown state
Power supply rise
min
• Power supply rise
time
100
time from 0V to 2.0V.
unit
V
ms
Note7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.
Low voltage detection reset (LVD) Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
LVD reset voltage
LVDET
(Note 8-2)
• Select from option.
(Note 8-1)
(Note 8-3)
• See Fig. 8.
LVD
LVHYS
hysteresys width
Detection voltage
LVUKS
unknown state
Low voltage dtection
minimum width
min.
max.
2.31V
2.21
2.31
2.41
2.81V
2.71
2.81
2.91
4.28V
4.18
4.28
4.38
2.31V
55
2.81V
60
4.28V
65
unit
V
mV
• See Fig. 8.
(Note 8-4)
TLVDW
typ.
0.7
0.95
V
• See Fig. 9.
0.2
ms
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.
No.A0886-20/29
LC87F7J32A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
Conditions
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
(Note 9-1)
IDDOP(1)
Specification
Pin/
Remarks
IDDOP(2)
• FmX’tal=32.768kHz crystal oscillation mode
min
typ
max
4.5 to 5.5
8.5
23
3.0 to 3.6
4.8
13
4.5 to 5.5
6.9
19
3.0 to 3.6
3.9
11
2.5 to 3.0
3.1
8.8
4.5 to 5.5
2.4
6.6
3.0 to 3.6
1.3
3.5
2.2 to 3.0
1.1
3.2
4.5 to 5.5
0.7
3.3
3.0 to 3.6
0.4
1.9
2.2 to 3.0
0.3
1.5
4.5 to 5.5
7.8
21
3.0 to 3.6
4.5
12
4.5 to 5.5
3.6
10
3.0 to 3.6
2.8
7.7
2.2 to 3.0
1.8
5.5
4.5 to 5.5
35
120
3.0 to 3.6
18
72
2.2 to 3.0
13
53
4.5 to 5.5
3.8
9.2
3.0 to 3.6
2.0
5.0
unit
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(4)
• System clock set to 8MHz side
• Internal RC oscillation stopped.
IDDOP(5)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(6)
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(7)
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDOP(8)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(9)
• FmCF=0Hz (oscillation stopped)
mA
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(10)
IDDOP(11)
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
IDDOP(13)
• System clock set to 10MHz wifh frequency
variable RC oscillation
• 1/1 frequency division ratio
IDDOP(14)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(15)
• Internal RC oscillation stopped.
• System clock set to 4MHz wifh frequency
IDDOP(16)
variable RC oscillation
• 1/1 frequency division ratio
IDDOP(17)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
IDDOP(19)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HALT mode
IDDHALT(1)
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• FmX’tal=32.768kHz crystal oscillation mode
(Note 9-1)
IDDHALT(2)
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(3)
mA
• HALT mode
• FmCF=8MHz ceramic oscillation mode
IDDHALT(4)
μA
4.5 to 5.5
2.8
7.7
3.0 to 3.6
1.4
3.9
2.5 to 3.0
1.1
3.1
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped.
IDDHALT(5)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0886-21/29
LC87F7J32A
Continued from preceding page.
Parameter
HALT mode
Symbol
Conditions
VDD[V]
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FmX’tal=32.768kHz crystal oscillation mode
(Note 9-1)
IDDHALT(6)
Specification
Pin/
Remarks
IDDHALT(7)
min
typ
max
unit
4.5 to 5.5
1.2
3.3
3.0 to 3.6
0.6
1.7
2.2 to 3.0
0.4
1.2
4.5 to 5.5
0.40
1.89
3.0 to 3.6
0.20
0.83
2.2 to 3.0
0.15
0.69
4.5 to 5.5
3.3
9.0
3.0 to 3.6
1.6
4.4
4.5 to 5.5
1.7
4.6
3.0 to 3.6
0.8
2.2
2.2 to 3.0
0.6
1.7
4.5 to 5.5
22
82
3.0 to 3.6
9
33
2.2 to 3.0
6
26
• HOLD mode
4.5 to 5.5
0.05
22
• CF1=VDD or open
3.0 to 3.6
0.03
13
2.2 to 3.0
0.02
9
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDHALT(8)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(9)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(10)
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
IDDHALT(11)
• 1/2 frequency division ratio
IDDHALT(12)
mA
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
IDDHALT(13)
• System clock set to 10MHz wifh frequency
variable RC oscillation
• 1/1 frequency division ratio
IDDHALT(14)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(15)
• Internal RC oscillation stopped.
• System clock set to 4MHz wifh frequency
IDDHALT(16)
variable RC oscillation
• 1/1 frequency division ratio
IDDHALT(17)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(18)
• System clock set to 32.768kHz side
μA
• Internal RC oscillation stopped.
IDDHALT(19)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
VDD1
(External clock mode)
IDDHOLD(3)
IDDHOLD(4)
• HOLD mode
4.5 to 5.5
3.5
25
IDDHOLD(5)
• CF1=VDD or open
3.0 to 3.6
2.2
15
2.2 to 3.0
2.0
10
(External clock mode)
IDDHOLD(6)
• LVD option selected
Timer HOLD
IDDHOLD(7)
mode
IDDHOLD(8)
consumption
current
VDD1
• Timer HOLD mode
4.5 to 5.5
19
65
• CF1=VDD or open
3.0 to 3.6
7.0
31
2.2 to 3.0
4.5
17
μA
(External clock mode)
IDDHOLD(9)
• FmX’tal=32.768kHz crystal oscillation mode
Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
programming
VDD1
min
typ
max
unit
• 128-byte programming
• Erasing current included
3.0 to 5.5
5
10
mA
20
30
ms
40
60
μs
current
Programming
time
tFW(1)
• Erasing time
3.0 to 5.5
• Programming time
No.A0886-22/29
LC87F7J32A
UART (Full Duplex) Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Transfer ate
UBR
UTX(S0),
2.2 to 5.5
URX(S1)
min
typ
max
16/3
unit
8192/3
tCYC
Data length: 7/8/9 bits (LSB first)
Stop bits:
1 bit (2-bit in continuous data transmission)
Parity bits: None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Stop bit
Start of
transmission
End of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit
Start bit
Start of
reception
End of
reception
Receive data (LSB first)
UBR
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
12MHz
8MHz
4MHz
MURATA
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
Remarks
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
CSTCE12M0G52-R0
(10)
(10)
Open
470
3.0 to 5.5
0.05
0.15
CSTCE8M00G52-R0
(10)
(10)
Open
2.2k
2.7 to 5.5
0.05
0.15
Internal
MURATA
Internal
C1, C2
CSTLS8M00G53-B0
(15)
(15)
Open
680
2.5 to 5.5
0.05
0.15
C1, C2
CSTCR4M00G53-R0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
C1, C2
MURATA
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
No.A0886-23/29
LC87F7J32A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor Name
Frequency
Name
Operating
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
18
18
Open
560
Voltage Range
[V]
Oscillation
Stabilization Time
typ
max
[s]
[s]
1.4
3.0
Remarks
Applicable
EPSON
32.768kHz
Circuit Constant
Oscillator
MC-306
TOYOKOMU
2.2 to 5.5
CL value=
12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as
possible because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
Rf1
Rf2
Rd1
C1
C2
XT2
Rd2
C3
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0886-24/29
LC87F7J32A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal
absent
HOLD release signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0886-25/29
LC87F7J32A
VDD
Note:
External circuits for reset may vary depending on the
usage of POR and LVD. Please refer to the user’s manual
for more information.
RRES
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0886-26/29
LC87F7J32A
VDD
SW : ON/OFF (programmable)
RLCD
RLCD
SW: ON (VLCD=VDD)
RLCD
RLCD
VLCD
RLCD
RLCD
2/3VLCD
RLCD
1/2VLCD
RLCD
1/3VLCD
RLCD
RLCD
GND
Figure 8 LCD Bias Resistors
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 9 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
No.A0886-27/29
LC87F7J32A
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
LVD reset voltage
(LVDET)
VDD
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES
Figure 10 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
VDD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
VSS
Figure 11 Low voltage detection minimum width
(Example of momentary power loss/Voltage variation waveform)
No.A0886-28/29
LC87F7J32A
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A0886-29/29
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