KLI 2104 D

KLI-2104
Linear CCD Image Sensor
Description
The KLI−2104 Image Sensor is a high dynamic range,
multi-spectral, linear solid-state image sensor designed for demanding
color scanning applications.
The KLI−2104 contains three parallel linear photodiode arrays, each
with 2098 active photosites for the detection of red, green, and blue
(R, G, B) signals. A fourth channel, comprised of 4,196 pixels,
provides high resolution luminance information. This combination
allows the KLI−2104 to provide high resolution scans with accurate
color reproduction.
The device offers high sensitivity, low noise, and negligible lag.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Quadri-Linear CCD
Total Number of Pixels
Chroma
Luma
3 × 2222
1 × 4244
Number of Active Pixels
Chroma
Luma
3 × 2098
1 × 4196
Pixel Size
Chroma
Luma
14 mm
7 mm
Inter-Array Spacing
G to R, R to B
B to L
84 mm
87.5 mm
Active Image Size
29.4 mm (Diagonal)
Chip Size
35.64 mm (H) × 1.06 mm (V)
Saturation Signal
Chroma
Luma
208,000 e−
140,000 e−
Output Sensitivity
12 mV/e−
Peak Quantum Efficiency
R; G; B; L
73%; 55%; 62%; 88%
Responsivity
R; G; B; L
Figure 1. KLI−2104 Linear CCD
Image Sensor
Features
• Quadri-Linear Color Array Design
•
•
•
•
•
(G, R, B, L) for High Resolution with
Accurate Color Reproduction
High Sensitivity Photosites
Low Noise Design with Negligible Image
Lag
Pixel-Summing Support for Extended
Sensitivity and Dynamic Range
5.0 V Clock Inputs with Two-Phase
Register Clocking
Choice of Multi-Layer Anti-Reflective
Coated (MAR) or Clear Coverglass
Applications
• Digitization
• Photography
33; 36; 56; 16 V/mJ/cm2
e−
Total Read Noise
30
Dark Current
Chroma
Luma
0.22 pA/Pixel
0.07 pA/Pixel
Dynamic Range
Chroma
Luma
80 dB
75 dB
Charge Transfer Efficiency
0.99999
Photoresponse Non-Uniformity
15% Peak-Peak
Operating Frequency
20 MHz per Output
Package
CERDIP
Cover Glass Options
MAR Coated, 2 Sides
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
KLI−2104/D
KLI−2104
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KLI−2104 IMAGE SENSOR
Part Number
Description
KLI−2104−DAA−EB−AA
Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass (No Coatings), Standard Grade
KLI−2104−DAA−EB−AE
Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass (No Coatings), Engineering Grade
KLI−2104−DAA−ED−AA
Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KLI−2104−DAA−ED−AE
Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
Marking Code
KLI−2104
Lot Number
Serial Number
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KLI−2104
DEVICE DESCRIPTION
Architecture
2 Blank 12 Dark
12 Dark 4 Blank
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
(ea.)
4196 Active Pixels Total
(ea.)
2 Blank 12 Dark
(ea.)
2098 Active Pixels
(ea.)
VidO
VidE
VidB
VidR
VidG
12 Dark 4 Blank
Figure 2. Block Diagram
Chroma Channel Schematic (Not Drawn to Scale)
fRC
RDC
12 Dark
2098 Active Pixels
12 Dark
VDDC
TG 1 C
IGC
TG 2 C
2 Blank
Cells
IDC
F.D.
4 Blank
Cells
f1 C
f2 C
Sub
VID
f2SC
Sub
fRL
RDL
Luma Channel Schematic (Not Drawn to Scale)
VDDL
f2L
f1L
Sub
2 Blank
Cells
IDL
F.D.
4 Blank
Cells
TGL
Sub
Sub
Sub
24 Dark
4196 Active Pixels
fRL
24 Dark
RDL
VDDL
IGL
Sub
2 Blank
Cells
4 Blank
Cells
f1L
f2L
F.D.
Sub
Figure 3. Single Channel Schematic, Chroma and Luma
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3
VIDO
Sub
First Active
Pixel
Last Active Pixel
(Center)
KLI−2104
Luma
Channel
(Edge)
6.25 Line Spacing (87.5 mm)
Blue
Channel
6 Line Spacing (84 mm)
Red
Channel
6 Line Spacing (84 mm)
Green
Channel
Figure 4. Active Pixel and Channel Alignment − KLI−2104
Imaging
then transferred to the output structures in a parallel format
at the falling edge of the f2 clock. Re-settable floating
diffusions are used for the charge-to-voltage conversion
while source followers provide buffering to external
connections. The potential change on the floating diffusion
is dependent on the amount of signal charge and is given by
DVFD = DQ/CFD, where DVFD is the change in potential on
the floating diffusion, DQ is the amount of charge, and CFD
is the capacitance of the floating diffusion node. Prior to
each pixel output, the floating diffusion is returned to the RD
level by the reset clock, fR.
During the integration period, an image is obtained by
gathering electrons generated by photons incident upon the
photodiodes. The charge collected in the photodiode array
is a linear function of the local exposure. The charge is stored
in the photodiode itself and is isolated from the CCD shift
registers during the integration period by the transfer gates
TG1 and TG2 for the chroma channels, which are held at
a barrier potential. (The luminance channel has only one
transfer gate, TG). At the end of the integration period,
the CCD register clocking is stopped with the f1 and f2
gates being held in a ‘high’ and ‘low’ state respectively.
Next, the TG gates are turned ‘on’ causing the charge to
drain from the photodiode into the TG1 storage region. As
TG1 is turned back ‘off’ charge is transferred through TG2
and into the f1 storage region. The TG2 gate is then turned
‘off’, isolating the shift registers from the accumulation
region once again. For the luminance channel, only one TG
transfer is required. Complementary clocking of the f1 and
f2 phases now resumes for readout of the current line of data
while the next line of data is integrated.
Pixel Summing (Chroma Channels Only)
Enabling the pixel − summing feature can vary the
effective resolution of the color channels of this sensor.
A separate pin is provided for the last shift register gate
labeled f2SC. This gate, when clocked appropriately, stores
the summation of signal from adjacent pixels. This
combined charge packet is then transferred onto the sense
node. As an example, the sensor can be operated in 2-pixel
summing mode (1,049 pixels), by supplying a clock to f2SC
which is a 75% duty cycle signal at 1/2 the frequency of the
f2C signal, and modifying the fRC clock as depicted in
Figure 25. Applications that require full resolution mode
(2,098 pixels), must tie the f2SC pin to the f2C pin. Refer
to Figure 24 for additional details.
The luma channel outputs are in an odd and even
configuration. The odd pixel value and the even pixel value
are available simultaneously during the f2 clock low phase.
In this manner, pixel summing is an option off-chip.
Charge Transport and Sensing
Readout of the signal charge is accomplished by
two-phase, complementary clocking of the f1 and f2 gates.
The register architecture has been designed for high speed
clocking with minimal transport and output signal
degradation, while still maintaining low (5 Vp-p min) clock
swings for reduced power dissipation, lower clock noise and
simpler driver design. The data in all registers is clocked
simultaneously toward the output structures. The signal is
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4
KLI−2104
Physical Description
Pin Description and Device Orientation
SUB
1
32
SUB
IGC
2
31
LS
IDC
3
30
IGL
TG2C
4
29
IDL
TG1C
5
28
TGL
f2C
6
27
f2L
f1C
7
26
f1L
N/C
8
25
N/C
f2SC
9
24
VIDO
SUBG
10
23
SUBL
VIDG
11
22
VIDE
SUBR
12
21
SUBB
VIDR
13
20
VIDB
VDDC
14
19
VDDL
fRC
15
18
fRL
RDC
16
17
RDL
Figure 5. Pinout Diagram
Table 3. PACKAGE PIN DESCRIPTION
Pin
Name
1
SUB
2
IGC
3
IDC
4
TG2C
5
TG1C
6
f2C
7
8
9
Description
Pin
Name
Substrate/Ground
17
RDL
Reset Drain, Luma
Test Input − Input Diode, Chroma
18
fRL
Reset Clock, Luma
Test Input − Input Diode, Chroma
19
VDDL
Amplifier Supply (Luma)
Transfer Gate 2 Clock, Chroma
20
VIDx
Output Video (R, G, B)
Transfer Gate 1 Clock, Chroma
21
SUBx
Ground Reference (R, G, B)
Phase 2 CCD Clock, Chroma
22
VIDE
Output Video (Luma Even Channel)
f1C
Phase 1 CCD Clock, Chroma
23
SUBL
Ground Reference (Luma)
N/C
No Connection (Ground)
24
VIDO
Output Video (Luma Odd Channel)
H2SC
Phase 2 Summing Gate, Chroma
25
N/C
No Connection (Ground)
10
SUBx
Ground Reference (R, G, B)
26
f1L
Phase 1 CCD Clock, Luma
11
VIDx
Output Video (R, G, B)
27
f2L
Phase 2 CCD Clock, Luma
12
SUBx
Ground Reference (R, G, B)
28
TGL
Transfer Gate Clock, Luma
13
VIDx
Output Video (R, G, B)
29
IDL
Test Input − Input Diode, Luma
14
VDDC
Amplifier Supply (Chroma)
30
IGL
Test Input − Input Gate, Luma
15
fRC
Reset Clock, Chroma
31
LS
Light Shield/Exposure Drain
16
RDC
Reset Drain, Chroma
32
SUB
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5
Description
Substrate/Ground
KLI−2104
IMAGING PERFORMANCE
Each limit identified as a maximum and/or a minimum is
tested and guaranteed for every device. Nominal values are
to be considered typical performance values that are design
and manufacturing targets. These values are not guaranteed.
Specifications given under nominally specified operating
conditions for the given mode of operation at 25°C,
fCLK = 1 MHz, 2.1 ms integration time, MAR cover glass,
color filters, and an active load as in the schematic shown in
Figure 23 of a typical output bias/buffer circuit, unless
otherwise specified. See notes on next page for further
descriptions.
Table 4. SPECIFICATIONS
Symbol
Min.
Nom.
Max.
Units
Notes
Verification
Plan15
Saturation Output Voltage,
Chroma
VSAT, Chroma
2.0
2.5
−
Vp-p
1, 9
Die
Saturation Output Voltage,
Luminance
VSAT, Luma
1.2
1.75
−
Vp-p
1, 9
Die
Output Sensitivity
DVOUT/DNe
−
12
−
mV/e−
Design
Design
Design
Description
Saturation Signal Charge,
Chroma
Ne,sat chroma
−
208,000
−
e−
Saturation Signal Charge,
Luminance
Ne,SAT Luma
−
146,000
−
e−
Responsivity
Quantum Efficiency
Blue Channel @ 460 nm
Green Channel @ 540 nm
Red Channel @ 650 nm
Luma Channel @ 550 nm
R, Chroma
2, 9, 10
QE, Chroma
QE, Luma
−
−
−
−
73
55
62
88
−
−
−
−
Dynamic Range
Chroma
Luma
DR, Chroma
DR, Luma
−
−
80
75
−
−
Dark Noise, Chroma and Luma
Noise, Dark
−
30
−
Dark Signal Non-Uniformity,
Chroma
Luma
DSNU, Chroma
DSNU, Luma
−
−
2
2
16
16
Dark Current
Chroma
Luma
IDARK, Chroma
IDARK, Luma
−
−
0.22
0.07
0.5
0.2
Charge Transfer Efficiency
Chroma
Luma
CTE, Chroma
CTE, Luma
0.999995
0.999995
0.999998
0.999998
1
1
L, Chroma
L, Luma
−
−
0.05
0.1
1
1
VODC
5
6.6
Photoresponse Non-Uniformity,
Low Frequency, Chroma
PRNUC, Low
−
Photoresponse Non-Uniformity,
Medium Frequency, Chroma
PRNUC, Med
Photoresponse Non-Uniformity,
High Frequency, Chroma
%
2, 9, 10
±10%
±10%
±10%
±10%
Design
dB
3
Design
e−
Design
mV p-p
14
Die
pA/Pixel
4
Die
−
5
Die
%
1st Field
Die
8
V
9
Die
6
20
% p-p
6
Die
−
6
20
% p-p
7
Die
PRNUC, High
−
3
15
%
8
Die
Photoresponse Non-Uniformity,
Low Frequency, Luma
PRNUL, Low
−
6
20
% p-p
6
Die
Photoresponse Non-Uniformity,
Medium Frequency, Luma
PRNUL, Med
−
6
20
% p-p
7
Die
Photoresponse Non-Uniformity,
High Frequency, Luma
PRNUL, High
−
3
15
%
8
Die
Dark Def
−
−
0
Allowed
12
Die
Lag
Chroma
Luma
DC Output Offset
Darkfield Defect, Brightpoint
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6
KLI−2104
Table 4. SPECIFICATIONS (continued)
Symbol
Min.
Nom.
Max.
Units
Notes
Verification
Plan15
Brightfield Defect, Dark or
Bright
Bfld Def
−
−
0
Allowed
13
Die
Smear, Photodiode to CCD
Crosstalk
Blue Channel @ 450 nm
Green Channel @ 550 nm
Red Channel @ 650 nm
Smear,
Chroma
Smear
Luma channel @ 550 nm
Smear, Luma
Description
Linearity, Maximum from Best
Fit Straight Line
Blue Channel
Green Channel
Red Channel
Luma Channel
DC Amplifier Gain
−
−
−
0.2
0.05
0.4
−
−
−
−
1.2
−
Linearity,
Chroma
Linearity, Luma
−
−
−
−
0.6
1.2
1
1
−
−
−
−
%
Design
%
Design
%
Design
Gain, DC
−
0.75
−
Amplifier Output Resistance
ROUT
−
220
−
W
Design
Design
Output Buffer Bandwidth
f−3dB
−
72
−
MHz
Design
1. Calculated under a flat field illumination. Defined as the maximum output level achievable before linearity or PRNU performance is degraded
beyond specification.
2. With color filter. Values specified at filter peaks. 50% bandwidth = ±30 nm. Color filter arrays become transparent after 710 nm. It is
recommended that a suitable IR cut filter be used to maintain spectral balance and optimal MTF. See quantum efficiency plots in Figure 7.
3. This device utilizes 2-phase clocking for cancellation of driver displacement currents. Symmetry between f1 and f2 phases must be
maintained to minimize clock noise.
4. Dark current doubles approximately every +7°C.
5. Measured per transfer, 2 phases per pixel. For the typical total line (Chroma): (0.99999)4256 = 0.9583. For the typical total line (Luma):
(0.99999)4256 = 0.9583. It should be noted that this parameter degrades with increasing horizontal clock frequency.
6. Low frequency response is measured across the entire array with a 1,000 pixel-moving window and a 5 pixel median filter evaluated under
a flat field illumination.
7. Medium frequency response is measured across the entire array with a 50 pixel-moving window and a 5 pixel median filter evaluated under
a flat field illumination.
8. High frequency response non-uniformity represents individual pixel defects evaluated under a flat field illumination. An individual pixel value
may deviate above or below the average response for the entire array by a certain threshold.
9. Increasing the current load (nominally 6 mA) to improve signal bandwidth will decrease these parameters.
10. If resistive loads are used to set current, the amplifier gain will be reduced, thereby reducing the output sensitivity and net responsivity.
11. Where defective pixels are allowed, they will be separated by at least one non-defective pixel within and across channels.
12. Pixels whose response is greater than the average response by the specified threshold, (16 mV). See Figure 6.
13. Pixels, whose response is greater or less than the average response by the specified threshold, contained in the high frequency PRNU
specification for that channel. See Figure 6.
14. Absolute difference between the maximum and minimum average signal level for an entire video channel.
15. A “die” parameter is measured on every sensor during production testing. A “design” parameter is quantified during design verification and
not guaranteed by specification.
Note 13: Bright
Field Bright Pixel
Average
Pixel
Signal Out
Note 12: Dark
Field Bright
Pixel
Note 13 Bright
Field Dark Pixel
Exposure
Figure 6. Defective Pixel Classification
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7
KLI−2104
TYPICAL PERFORMANCE MEASURES
KLI−2104 Responsivity − Color Channels
70
Responsivity (V/mJ/cm2)
60
50
40
30
20
10
0
350
400
450
500
550
600
650
700
750
800
850
900
850
900
Wavelength (nm)
Figure 7. KLI−2104 Responsivity − Color Channels
KLI−2104 Responsivity − Even/Odd Monochrome Channels
18
16
Responsivity (V/mJ/cm2)
14
12
10
8
6
4
2
0
350
400
450
500
550
600
650
700
750
Wavelength (nm)
Figure 8. Luminance Channel Responsivity
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8
800
KLI−2104
KLI−2104 Quantum Efficiency − Even/Odd Monochrome Channels
100
90
Quantum Efficiency (%)
80
70
60
50
40
30
20
10
0
350
400
450
500
550
600
650
700
750
800
850
900
Wavelength (nm)
Figure 9. KLI−2104 Quantum Efficiency − Even/Odd Monochrome Channels
KLI−2104 Quantum Efficiency − Color Channels
100
90
Quantum Efficiency (%)
80
70
60
50
40
30
20
10
0
350
400
450
500
550
600
650
700
750
800
Wavelength (nm)
Figure 10. KLI−2104 Quantum Efficiency − Color Channels
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9
850
900
KLI−2104
RED Channel Linearity, Typical Response − Red LED Illumination
3
2.5
VOUT (V)
2
1.5
1
0.5
0
1
0
2
3
4
5
Illumination Level
Figure 11. Red Channel Linearity
GREEN Channel Linearity, Typical Response − Green LED Illumination
3
2.5
VOUT (V)
2
1.5
1
0.5
0
0
1
2
3
4
5
6
Illumination Level
Figure 12. Green Channel Linearity
BLUE Channel Linearity, Typical Response − Blue LED Illumination
3
2.5
VOUT (V)
2
1.5
1
0.5
0
0
1
2
3
4
5
Illumination Level
Figure 13. Blue Channel Linearity
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10
6
KLI−2104
Dark Noise vs. Temperature
Typical Performance − 1 MHz Data Rate
50
RED
GREEN
BLUE
Even/Odd
45
Electrons
40
35
30
25
20
25
35
45
55
65
Temperature (5C)
Figure 14. Dark Noise vs. Temperature
Typical Modulation Transfer Function KLI−2104 Chroma Channels (MTF)
100
90
80
MTF (%)
70
60
50
450 nm
40
550 nm
30
650 nm
20
750 nm
10
0
0
5
10
15
20
25
Spatial Frequency (Cyc/mm)
Figure 15. Typical Modulation Transfer
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11
30
35
40
KLI−2104
KLI−2104 Smear (Photodiode-to-CCD Crosstalk)
@ 450−800 nm Typical Performance
1.8
BLUE CHANNEL Smear (%)
GREEN CHANNEL Smear (%)
1.6
RED CHANNEL Smear (%)
EVEN CHANNEL Smear (%)
1.4
ODD CHANNEL Smear (%)
Smear (%)
1.2
1.0
0.8
0.6
0.4
0.2
0
450
500
550
600
650
700
750
800
Wavelength (nm)
Figure 16. KLI−2104 Smear
CTE
KLI−2104 CTE vs. Frequency
1.000000
0.999998
0.999996
0.999994
0.999992
0.999990
0.999988
0.999986
0.999984
0.999982
0.999980
0.999978
0.999976
0.999974
0.999972
0.999970
Chroma
Luma
2.5
5
10
Frequency (MHz)
Figure 17. CTE vs. Frequency
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12
15
20
KLI−2104
Typical KLI−2104 Dark Noise vs. CCD Clock Frequency
1,000
BLUE Noise (e−)
GREEN Noise (e−)
RED Noise (e−)
Noise (e−)
EO Noise (e−)
100
10
1
10
fCCD
Figure 18. Typical KLI−2104 Dark Noise vs. CCD Clock Frequency
Typical KLI−2104 Dark Noise vs. CCD Clock Frequency
250
BLUE Noise (e−)
GREEN Noise (e−)
200
RED Noise (e−)
Noise (e−)
EO Noise (e−)
150
100
50
0
1
2
3
4
5
6
7
fCCD
Figure 19. Typical KLI−2104 Dark Noise vs. CCD Clock Frequency
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13
8
KLI−2104
Typical KLI−2104 Noise vs. Temperature
(1 MHz)
100
Chroma Average
Noise (e−)
Luma Average
10
0
10
20
30
40
50
60
70
Temperature (5C)
Figure 20. Noise vs. Temperature
Typical KLI−2104 Dark Voltage vs. Temperature
(1 MHz/tINT = 2.2 ms)
0.01
Blue
Green
Red
Dark Voltage (V)
E/O
0.001
35
40
45
50
55
Temperature (5C)
Figure 21. Dark Voltage vs. Temperature
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14
60
65
KLI−2104
OPERATION
Table 5. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Gate Pin Voltage
VGATE
0
16
V
1, 2
Pin-to-Pin Voltage
VPIN−PIN
−
16
V
1, 3
Diode Pin Voltages
VDIODE
−0.5
16
V
1, 4
Output Bias Current
IDD
−10
−1
mA
5
Output Load Capacitance
CVID,LOAD
−
10
pF
9
CCD Clocking Frequency
fCLK
−
20
MHz
6
Operating Temperature
TOP
0
70
°C
7
Storage Temperature
TST
−25
80
°C
8
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to substrate voltage.
2. Includes pins: H1n, H2n, TGx, fRx, OGx, IGx.
3. Voltage difference (either polarity) between any two pins.
4. Includes pins: VIDn, VSSn, RDx, VDDx, LS and IDx.
5. Care must be taken not to short output pins to ground during operation as this may cause permanent damage to the output structures.
6. Charge transfer efficiency will degrade at frequencies higher than the maximum clocking frequency. VIDn load resistor values may need to
be decreased as well.
7. Noise performance will degrade with increasing temperatures.
8. Long term storage at the maximum temperature will accelerate color filter degradation.
9. Exceeding the upper limit on output load capacitance will greatly reduce the output frequency response. Thus, direct probing of the output
pins with conventional oscilloscope probes is not recommended.
10. The absolute maximum ratings for the entire table indicate the limits of this device beyond which damage may occur. The Operating ratings
indicate the conditions that the device is functional. Operating at or near these ratings do not guarantee specific performance limits.
Guaranteed specifications and test conditions are contained in the Imaging Performance section.
Device Input ESD Protection Circuit (Schematic)
To Device
Function
I/O Pin
Vt = ~20 V
CAUTION:
To allow for maximum performance, this device was designed with limited input protection; thus, it is sensitive to electrostatic
induced damage. These devices should be installed in accordance with strict ESD handling procedures!
Figure 22. ESD Protection Circuit
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15
KLI−2104
DC Bias Operating Conditions
Table 6. DC BIAS OPERATING CONDITIONS
Symbol
Minimum
Nominal
Maximum
Units
Substrate
Description
VSUB C,L
−
0
−
V
Reset Drain Bias (Color)
VRD C,L
11.5
12.0
12.5
V
Output Buffer Supply
VDD C,L
11.5
12.0
12.5
V
Output Bias Current/Channel
IVIDPIN
−4.0
−6.0
−8.0
mA
VLS
11.5
12.0
12.5
V
Test Pin − Input Gate
VIG C,L
−
0
−
V
Test Pin − Input Diode
VID C,L
−
12.0
−
V
Light Shield/Drain Bias
Notes
1
1. A current sink must be supplied for each output. Load capacitance should be minimized so as not to limit bandwidth. The values of RX and
RL should be chosen to optimize for a given operating frequency, but. Rx should not be less than 75 W. The values shown in Figure 23 below
represent one possible solution.
Typical Output Bias/Buffer Circuit
VDD
To Device
Output Pin: VIDx
(Minimize Path Length)
BFR90
or Equiv.
Buffered Output
RX = 120 W
RL = 600 W*
Figure 23. Typical Output Bias/Buffer Circuit
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KLI−2104
AC Operating Conditions
Table 7. AC ELECTRICAL CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
1e = 1/fCLK
50
50
−
ns
1 e Count
tR
−
30
−
ns
Typical
1L = tINT
0.1064
2.128
−
ms
2128 e Counts
PD−CCD Transfer Period
tPD
1,000
−
−
ns
8 e Counts
Transfer Gate 1 Clear
tTG1
500
1,000
−
ns
1 e Count
Transfer Gate 2 Clear
tTG2
500
1,000
−
ns
1 e Count
Reset Pulse Duration
tRST
9
−
−
ns
1
Clamp to f2 Delay
tCD
5
−
−
ns
2
Sample to Reset Edge Delay
tSD
5
−
−
ns
2
LOG Gate Duration
tLOG1
1,000
−
−
ns
LOG Gate Clear
tLOG2
1,000
−
−
ns
CCD Element Duration
f1L, f1C, f2L, fC2, Rise Time
Line/Integration Period
1. Minimum values given are for 20 MHz CCD operation.
2. Recommended delays for Correlated Double Sampling (CDS) of output.
Table 8. CLOCK LEVELS
Description
Symbol
Minimum
Nominal
Maximum
Units
CCD Readout Clocks High
Vf1CH, Vf2CH, Vf1LH, Vf2LH
4.6
5.0
−
V
CCD Readout Clocks Low
Vf1CL, Vf2CL, Vf1LL, Vf2LL
−0.1
0.0
0.1
V
Transfer Clocks High
VTGLH, VTG1H, VTG2H
4.6
5.0
−
V
Transfer Clocks Low
VTGLL, VTG1L, VTG2L
−0.1
0.0
0.1
V
Reset Clock High
VfRCH, VfRLH
4.6
5.0
−
V
Reset Clock Low
VfRCL, VfRLL
−0.1
0.0
0.1
V
1. Care should be taken to insure that low rail overshoot does not exceed −0.5 VDC. Exceeding this value may result in non-photogenerated
charged being injected into the video signal.
2. Connect pin to ground potential for applications where exposure control is not required.
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17
KLI−2104
TIMING
Requirements and Characteristics
Table 9. CLOCK LINE CAPACITANCE
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
Phase 1 Clock Capacitance
Cf1C
−
758
−
pF
1
Phase 2 Clock Capacitance
Cf2C
−
558
−
pF
1
Transfer Gate 1 Capacitance
CTG1C
−
440
−
pF
Transfer Gate 2 Capacitance
CTG2C
−
222
−
pF
Reset Gate Capacitance
CfRC
−
6
−
pF
Phase 1 Clock Capacitance
Cf1L
−
397
−
pF
1
Phase 2 Clock Capacitance
Cf2L
−
302
−
pF
1
Transfer Gate Capacitance
CTGL
−
92
−
pF
Reset Gate Capacitance
CfRL
−
6
−
pF
CHROMA
LUMA
1. This is the total load capacitance per CCD phase. Since the CCDs are driven from both ends of the sensor, the effective load capacitance
per drive pin is approximately half the value listed.
Line Timing − Full Resolution Mode
f1C, f1L
f2C, f2L,
f2SC
4 Blank
Pixels*
12 Dark
Pixels*
2098 Active Pixels*
12 Dark 2 Blank
Pixels* Pixels*
tINT
TG1C, TGL
TG2C
* Pixel counts are per output.
Transfer Timing − Full Resolution Mode
f1C, f1L
First Dark Reference Pixel Data Valid
(5th H2 Falling Edge)
1 Pixel
f2C, f2L,
f2SC
TG1C, TGL
tTG1
tTG2
tPD
TG2C
Figure 24. Timing Diagram
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18
4 Blank
Pixels*
KLI−2104
Output Timing − Full Resolution Mode
f2C = f2SC
tR
1 Pixel
fRC, fRL
tCD
tRST
VIDn
VFEEDTHRU
VSAT
VDARK
tSD
Clamp*
Sample*
Output Timing − 2-Pixel Summing Mode
f2C, f2L
f2SC
fRC
VIDn
VPixel N + Pixel (N+1)
Clamp*
Sample*
* Required for Optional Off-Chip, Analog, Correlated Double Sampling (CDS) Signal Processing.
Figure 25. Output Timing
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19
KLI−2104
MECHANICAL DRAWINGS
Completed Assembly
Figure 26. Completed Assembly
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20
KLI−2104
COVER GLASS SPECIFICATION
Two-Sided Multi-Layer Anti-Reflective Cover Glass Specification (MAR)
This device is configured with a coverglass designed to reduce reflections and maximize transmission of the visible light.
The typical spectral characteristics of this glass is found below:
Maximum Reflectance Allowed (Two-Sided)
2.40
2.20
2.00
Reflectance (%)
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
Reflectance (Two-Sided)
0.20
0.00
400
450
500
550
600
Wavelength (nm)
Figure 27. Maximum Reflectance Allowed
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21
650
700
KLI−2104
REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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22
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
KLI−2104/D