Ordering number : ENA2005 LV8136V Bi-CMOS IC For Brushless Motor Drive http://onsemi.com Direct PWM Drive, Quiet Predriver IC Overview The LV8136V is a PWM system predriver IC designed for three-phase brushless motors. This IC reduces motor driving noise by using a high-efficiency, quiet PWM drive (150-degree drive system). It incorporates a full complement of protection circuits and, by combining it with a hybrid IC in the STK611 or STK5C4 series, the number of components used can be reduced and a high level of reliability can be achieved. Furthermore, its power-saving mode enables the power consumption in the standby mode to be reduced to zero. This IC is optimally suited for driving various large-size motors such as those used in air conditioners and hot-water heaters. Features • Three-phase bipolar drive • Quiet PWM drive (150-degree current-carrying) • Supports drive phase control (15-degree lead angle for 150-degree current-carrying drive. From this state, a lead angle from 0 to 28 degrees can be set in 16 steps) • Supports power saving mode(power saving mode at CTL pin voltage of 1.0V (typ) or less; ICC = 0mA, HB pin turned off) • Supports bootstrap (maximum duty limit) • Automatic recovery type constraint protection circuit • Forward/reverse switching circuit, Hall bias pin • Current limiter circuit, low-voltage protection circuit, and thermal shutdown protection circuit • FG1 and FG3 output (360-degree electrical angle/1 pulse and 3 pulses) Semiconductor Components Industries, LLC, 2013 May, 2013 20812 SY PC 20120119-S000021 No.A2005-1/19 LV8136V Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Supply voltage VCC max Output current IO max Allowable power dissipation Pd max1 Pd max2 Conditions Ratings Unit VCC pin 18 V 15 mA Independent IC 0.45 W Mounted on a specified circuit board.* 1.05 W CTL pin applied voltage VCTL max 18 V FG1,FG3 pin applied voltage VFG1 max 18 V Junction temperature VFG3 max Tj max 150 °C Operating temperature Topr -40 to +105 °C Storage temperature Tstg -55 to +150 °C * Specified circuit board : 114.3mm × 76.1mm × 1.6mm, glass epoxy Note 1) Absolute maximum ratings represent the values that cannot be exceeded for any length of time. Note 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for further details. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating range at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage range VCC 9.5 to 16.5 5V constant voltage output current IREG 10 mA V HB pin output current IHB 30 mA FG1,FG3 pin output current IFG1, IFG3 10 mA Electrical Characteristics at Ta = 25°C, VCC = 15V Parameter Symbol Ratings Conditions min Supply current 1 ICC1 Supply current 2 ICC2 At stop CTL ≤ 1.0V typ VHO IO = -10mA Unit typ max 5.0 8.0 mA 0 20 μA Output Block High level output voltage VREG-0.35 VREG-0.15 V Low level output voltage VLO IO = 10mA 0.15 0.3 V Lower output ON resistance RONL IO = 10mA 15 30 Ω Upper output ON resistance RONH IO = -10mA 15 Output leakage current IOleak Minimum output pulse width Tmin Output minimum dead time Tdt 35 Ω 10 μA 2.0 4.0 μs 2.0 4.0 μs 5V Constant Voltage Output Output voltage VREG IO = -5mA 5.3 V Voltage fluctuation ΔV (REG1) VCC = 9.5 to 16.5V, IO = -5mA 4.7 5.0 100 mV Load fluctuation ΔV (REG2) IO = -5 to -10mA 100 mV Hall Amplifier Input bias current IB (HA) Common-mode input voltage range 1 VICM1 Common-mode input voltage range 2 VICM2 -2 0 μA When a Hall element is used 0.3 VREG-1.7 V Single-sided input bias mode 0 VREG V (when a Hall IC is used) Hall input sensitivity VHIN Sine wave, 80 mVp-p Hall element offset = 0V Hysteresis width ΔVIN (HA) 9 20 40 mV Input voltage Low Æ High VSLH 5 11 19 mV Input voltage High Æ Low VSHL -19 -11 -5 mV Continued on next page. No.A2005-2/19 LV8136V Continued from preceding page. Parameter Symbol Ratings Conditions min Unit typ max CSD Oscillator Circuit High level output voltage VOH (CSD) Low level output voltage VOL (CSD) Amplitude V (CSD) External capacitor charging current ICHG1 (CSD) External capacitor discharging 2.7 3.0 3.3 V 0.8 1.0 1.2 V 1.75 2.0 2.25 Vp-p VCHG1 = 2.0V -17 -10 -4 μA ICHG2 (CSD) VCHG2 = 2.0V 4 10 17 μA f (CSD) C = 0.22μF (design target value) current Oscillation frequency 113.6 Hz PWM Oscillator (PWM pin) High level output voltage VOH (PWM) 3.3 3.5 3.8 Low level output voltage VOL (PWM) 1.3 1.5 1.7 V Amplitude V (PWM) 1.78 2.0 2.22 Vp-p Oscillation frequency f (PWM) C = 2200pF, R = 15kΩ 17 V kHz (design target value) Current Limiter Operation Limiter voltage VRF 0.225 0.25 0.275 V 150 175 °C 35 °C Thermal Shutdown Protection Operation Thermal shutdown protection TSD operating temperature Hysteresis width * Design target value (junction temperature) ΔTSD * Design target value (junction temperature) TH pin Protection start voltage VTH Hysteresis width ΔVTH 0.25 0.6 1.05 V 0.2 0.4 0.6 V HB pin Output ON resistance RON (HB) IHB = 10mA Output leakage current IL (HB) Power saving mode VCC = 15V 15 30 Ω 10 μA Low Voltage Protection Circuit (detecting VCC voltage) Operation voltage VSD Hysteresis width ΔVSD 7.0 8.0 9.0 V 0.25 0.5 0.75 V 40 60 Ω 10 μA VCC V FG1 FG3 Pin Output ON resistance RON (FG) IFG = 5mA Output leakage current IL (FG) VFG = 18V CTL Amplifier (drive mode) Input voltage range VIN (CTL) High level input voltage VIH (CTL) PWM ON duty 90% 5.1 0 5.4 5.7 V Middle level input voltage VIM (CTLI) PWM ON duty 0% 1.8 2.1 2.4 V Low level input voltage VIL1 (CTL) Power saving mode 1.0 1.5 V Hysteresis width ΔCTL 0.15 0.5 0.85 V Input current IIH (CTLI) 10 18 26 μA CTL Amplifier (power saving mode) CTL = 3.5V F/R Pin High level input voltage VIH (FR) 3.0 VREG V Low level input voltage VIL (FR) 0 0.7 V Input open voltage VIO (FR) Hysteresis width VIS (FR) High level input current IIH (FR) VF/R = VREG Low level input current IIL (FR) VF/R = 0V 0 0.3 V 0.21 0.31 0.41 V 10 50 100 μA -10 0 +10 μA Continued on next page. No.A2005-3/19 LV8136V Continued from preceding page. Parameter Symbol Ratings Conditions min Unit typ max FAULT Pin Drive stop voltage VFOF 0 Drive start voltage VFON 3.0 Input open voltage VIO (FLT) 4.6 High level input current IIH (FLT) VFLT=VREG Low level input current IIL (FLT) VFLT=0V Vadp01 ADP1 pin = 0V Maximum lead angle Vadp16 ADP1 pin = VREG 26 28 Current ratio with the ADP2 pin ADP CTL = 3.75V, IADP1/IADP2 1.45 2 2.55 A/A 1.95 2.5 3.05 V 0.51 V -250 0.35 V VREG V 0 10 μA -160 -70 μA 0 2 VREG V ADP1 Pin (drive phase adjustment) Minimum lead angle Deg Deg current ADP2 Pin (drive phase adjustment) High level output voltage VADP2H CTL = 5.4V Low level output voltage VADP2L CTL = 0V 0 DPL Pin (drive-phase-adjustment limit setting pin) Lead angle limit high level voltage VDPLH 3.3 3.5 3.8 V Lead angle limit low level voltage VDPLL 1.3 1.5 1.7 V * These are design target values and no measurements are made. No.A2005-4/19 LV8136V Package Dimensions unit : mm (typ) 3191C Pd max – Ta Allowable power dissipation, Pd max -- W 1.5 9.75 0.5 5.6 7.6 30 1 0.65 0.15 0.22 1.5 MAX (1.3) (0.33) Specified circuit board : 114.3 × 76.1 × 1.6mm3 glass epoxy Mounted on a specified circuit board. 1.0 0.5 Independent IC 0.38 0.16 0 --40 --20 0 20 40 60 80 100 120 0.1 Ambient temperature, Ta -- °C SANYO : SSOP30(275mil) HB HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT TH RF TGND VREG5 FR RPWM CPWM Pin Assignment 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 2 3 4 5 6 7 8 9 10 11 12 13 14 IN1- IN2+ IN2- IN3+ IN3- GND VCC CTL DPL FG3 FG1 ADP2 CSD 15 ADP1 1 IN1+ LV8136V Top view No.A2005-5/19 ADP1 ADP2 DPL FG3 Output FG1 Output FG3 FG1 VREG VREG VREG VREG CSD FG Rotate Detect Drive Phase Setting Drive Phase Revise CSD OSC CTL Input CTL CTL AMP F/R RESET TSD MOSC FAULT LVSD GND CURR LIM PRE DRIVER HB VREG VCC VREG F/R Input RPWM CPWM F/R PWM OSC PWM GENERATE CONTROL CIRCUIT HALL HYS AMP IN1+ IN1- IN2+ IN2- IN3+ IN3- RF TH LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 FAULT HB TGND + VCC Rf VREG VREG RCIN U-,V-,W- ITRIP TH2 TH1 LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 FAULT ENABLE VS3,WOUT VDD VSS VS2,VOUT VB3 VS1,UOUT VB2 VB1 VCC VS3,WOUT VS2,VOUT VS1,UOUT STK5C4-XXX + M VM LV8136V Sample Application Circuit 1 (Hall element, HIC) No.A2005-6/19 ADP1 ADP2 DPL FG3 Output FG1 Output FG3 FG1 VREG VREG VREG VREG CSD FG Rotate Detect Drive Phase Setting Drive Phase Revise CSD OSC Hall IC Input2 Hall IC Input3 CTL Input CTL CTL AMP F/R RESET TSD MOSC FAULT LVSD GND CURR LIM PRE DRIVER HB VREG VCC VREG F/R Input RPWM CPWM F/R PWM OSC PWM GENERATE CONTROL CIRCUIT HALL HYS AMP IN1+ IN1- IN2+ IN2- IN3+ IN3- Hall IC VREG Input1 RF TH LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 FAULT HB TGND + VCC VREG VREG RCIN U-,V-,W- ITRIP TH2 TH1 LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 FAULT ENABLE VS3,WOUT VDD VSS VS2,VOUT VB3 VS1,UOUT VB2 VB1 VCC VS3,WOUT VS2,VOUT VS1,UOUT STK5C4-XXX + M VM LV8136V Sample Application Circuit 2 (Hall IC, HIC) Note : The Hall IC to be used must be of open collector or open drain type (no internal pull-up resistor connected to the output). No.A2005-7/19 ADP1 ADP2 DPL FG3 Output FG1 Output FG3 FG1 VREG VREG VREG VREG CSD FG Rotate Detect Drive Phase Setting Drive Phase Revise CSD OSC CTL Input CTL CTL AMP F/R RESET TSD MOSC FAULT LVSD GND CURR LIM PRE DRIVER HB VREG VCC VREG F/R Input RPWM CPWM F/R PWM OSC PWM GENERATE CONTROL CIRCUIT HALL HYS AMP IN1+ IN1- IN2+ IN2- IN3+ IN3- VREG RF TH LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 VREG FAULT HB VCC TGND + VCC VB HIN HO LIN VS COM LO 8 7 6 5 VCC VB HIN HO LIN VS COM LO 8 7 6 5 1 2 3 4 VCC VB HIN HO LIN VS COM LO 8 7 6 5 TND525/NCP5106 MURA260T3 1 2 3 4 TND525/NCP5106 MURA260T3 1 2 3 4 TND525/NCP5106 MURA260T3 ATP613 ATP613 ATP613 ATP613 ATP613 ATP613 WOUT VOUT UOUT VM + M LV8136V Sample Application Circuit 3 (Hall element, FET) No.A2005-8/19 ADP1 ADP2 DPL FG3 Output FG1 Output FG3 FG1 VREG VREG VREG VREG CSD FG Rotate Detect Drive Phase Setting Drive Phase Revise CSD OSC Hall IC Input2 Hall IC Input3 CTL Input CTL CTL AMP F/R RESET TSD MOSC FAULT LVSD GND CURR LIM PRE DRIVER HB VREG VCC VREG F/R Input RPWM CPWM F/R PWM OSC PWM GENERATE CONTROL CIRCUIT HALL HYS AMP IN1+ IN1- IN2+ IN2- IN3+ IN3- Hall IC VREG Input1 VREG RF TH LIN3 LIN2 LIN1 HIN3 HIN2 HIN1 VREG FAULT HB VCC TGND + VCC VB HIN HO LIN VS COM LO 8 7 6 5 VCC VB HIN HO LIN VS COM LO 8 7 6 5 1 2 3 4 VCC VB HIN HO LIN VS COM LO 8 7 6 5 TND525/NCP5106 MURA260T3 1 2 3 4 TND525/NCP5106 MURA260T3 1 2 3 4 TND525/NCP5106 MURA260T3 ATP613 ATP613 ATP613 ATP613 ATP613 ATP613 WOUT VOUT UOUT VM + M LV8136V Sample Application Circuit 4 (Hall IC, FET) Note: The Hall IC to be used must be of open collector or open drain type (no internal pull-up resistor connected to the output). No.A2005-9/19 LV8136V Pin Functions Pin No. 1 2 3 4 5 6 Pin Name IN1+ IN1IN2+ IN2IN3+ IN3- Pin function Equivalent Circuit Hall signal input pins. VREG The high state is when IN+ is greater than IN-, and the low state is the reverse. An amplitude of at least 100mVp-p (differential) is desirable for the Hall signal inputs. If noise on the Hall signals is a problem, insert capacitors between IN+ and IN- pins. 1 3 5 500Ω 500Ω 2 4 6 If input is provided from a Hall IC, the common-mode input range can be expanded by biasing either + or -. 7 GND Ground pin of the control circuit block. 8 VCC Power supply pin for control. Insert a capacitor between this pin and ground to prevent the influence of noise, etc. 9 CTL Control input pin. When CTL pin voltage rises, the IC changes the output signal VREG VCC PWM duty to increase the torque output. 65kΩ 9 125kΩ 10 DPL Setting pin for drive phase adjustment limit. VREG This pin is used to limit the lead angle of the drive phase. The lead angle is limited to zero degrees when the voltage 500Ω is 1.5V or lower and the limit is released 10 when the voltage is 3.5V or higher. 11 FG3 FG3 : 3-Hall FG signal output pin. 12 FG1 8-pole motor outputs 12 FG pulses per VREG 11 12 one rotation. In power saving mode, high-level is output. 25Ω FG1 :1-Hall FG signal output pin. 8-pole motor outputs 4 pulses per one rotation. In power saving mode, high-level is output. Continued on next page. No.A2005-10/19 LV8136V Continued from preceding page. Pin No. 13 Pin Name ADP2 Pin function Equivalent Circuit Setting pin for phase drive correction. VCC This pin sets the amount of correction made to the lead angle according to the CTL input. Insert a resistor between this VREG pin and ground to adjust the amount of VREG correction. 500Ω 13 500Ω 14 CSD Pin to set the operating time of the motor constraint protection circuit. VREG Insert a capacitor between this pin and ground. This pin must be connected to ground if the constraint protection circuit is not used. 500Ω 14 500Ω 15 ADP1 Drive phase adjustment pin. The drive phase can be advanced from VCC VREG 0 to 28 degrees during 150-degree current carrying drive. The lead angle becomes 0 degrees when 0V is input and 28 degrees when 5V is input. AD 500Ω 15 500Ω 16 CPWM Triangle wave oscillation pin for PWM generation. VREG Insert a capacitor between this pin and ground and a resistor between this pin and RPWM for triangle wave oscillation. 200Ω 17 RPWM Oscillation pin for PWM generation. Insert a resistor between this pin and 16 VREG CPWM. 17 Continued on next page. No.A2005-11/19 LV8136V Continued from preceding page. Pin No. Pin Name Pin function 18 FR FR 20 TGND Forward/reverse rotation setting pin. Equivalent Circuit VREG A low-level specifies forward rotation and a high-level specifies reverse rotation. This pin is held low when open. 2kΩ 18 20 TGND Test pin. Connect this pin to ground. 100kΩ 19 VREG5 5V regulator output pin (control circuit power supply). VCC Insert a capacitor between this pin and 50Ω ground for power stabilization. 0.1μF or so is desirable. 19 21 RF Output current detection pin. This pin is used to detect the voltage VREG across the current detection resistor (Rf). The maximum output current is determined by the equation IOUT = 0.25V/Rf. 5kΩ 22 TH Thermistor connection pin. 21 VREG The thermistor detects heat generated from HIC and turns off the drive output when an overheat condition occurs. If the pin voltage is 0.6V or lower, the drive output is turned off. 500Ω 22 Continued on next page. No.A2005-12/19 LV8136V Continued from preceding page. Pin No. 23 Pin Name FAULT Pin function Equivalent Circuit HIC protection signal input pin. VREG This pin accepts an error mode detection signal generated by the HIC side. 30kΩ A low-level indicates that an error mode 500Ω is detected and turns off the drive 23 output. 24 LIN3 LIN1, LIN2, and LIN3 : 25 LIN2 L-side output pins. 26 LIN1 Generate 0 to VREG5 push-pull 27 HIN3 outputs. 28 HIN2 29 HIN1 VREG 25 27 29 HIN1, HIN2, and HIN3 : H-side output pins. 24 26 28 500Ω Generate 0 to VREG5 push-pull outputs. 30 HB Hall bias HIC power supply pin. Insert a capacitor between this pin and VCC ground. This pin is set to high-impedance state in power saving mode. By supplying Hall bias and HIC power using this pin, the power consumption by Hall bias and 30 HIC in power saving mode can be reduced to zero. No.A2005-13/19 LV8136V Timing Chart (IN = “H”indicates the state in which IN+ is greater than IN-.) (1) F/R pin = L Normal hall input LA=0 IN1+ IN1IN2+ IN2IN3+ IN3- IN1 IN2 IN3 H L H H H L H L L L H L L H H L L H H L H H L L H H L L H L L H H L L H F/R="L"120° energization HIN1 ON PWM UOUT OFF PWM LIN1 ON HIN2 ON PWM PWM VOUT OFF PWM LIN2 ON HIN3 ON PWM WOUT OFF LIN3 ON F/R="L"150° energization HIN1 ON PWM UOUT OFF LIN1 ON PWM ON ON PWM SOFF SOFF PWM PWM ON ON PWM SOFF SOFF HIN2 ON VOUT OFF ON PWM SOFF PWM PWM LIN2 ON ON ON PWM SOFF PWM PWM SOFF ON SOFF HIN3 ON PWM WOUT OFF LIN3 ON ON PWM SOFF SOFF PWM PWM ON ON PWM SOFF SOFF PWM ON SOFF F/R="H"120° energization in reverse rotate HIN1 ON UOUT OFF PWM PWM LIN1 ON HIN2 ON VOUT OFF PWM PWM LIN2 ON HIN3 ON WOUT OFF PWM PWM LIN3 ON 3 HALL FG 1 HALL FG The energization is switched to 120° when 3 Hall FG frequency is 6.1Hz (TYP) or lower A direction of rotation is detected from Hall signal according to F/R pin input If the motor rotates in reverse against F/R pin input, 120° energization is maintained forcibly. No.A2005-14/19 LV8136V (2) F/R pin = H Reverse hall input LA=0 IN1+ IN1IN2+ IN2IN3+ IN3- L L H IN1 IN2 IN3 L H H L H L H H L H L L H L H L L H L H H L H L H H L H L H H L L F/R="L"120° energization HIN1 ON PWM UOUT OFF PWM LIN1 ON HIN2 ON PWM VOUT OFF PWM LIN2 ON HIN3 ON PWM WOUT OFF PWM LIN3 ON F/R="L"150° energization HIN1 ON SOFF UOUT OFF PWM PWM LIN1 ON ON ON PWM SOFF SOFF PWM PWM ON ON PWM SOFF PWM ON SOFF HIN2 ON PWM VOUT OFF LIN2 ON ON ON PWM SOFF SOFF PWM PWM ON ON PWM SOFF SOFF HIN3 ON WOUT OFF PWM ON PWM SOFF PWM PWM LIN3 ON ON ON PWM SOFF SOFF PWM ON SOFF F/R="H"120° energization in reverse rotate HIN1 ON PWM UOUT OFF PWM LIN1 ON HIN2 ON VOUT OFF PWM PWM PWM LIN2 ON HIN3 ON WOUT OFF PWM PWM LIN3 ON 3 HALL FG 1 HALL FG The energization is switched to 120° when 3 Hall FG frequency is 6.1Hz (TYP) or lower A direction of rotation is detected from Hall signal according to F/R pin input If the motor rotates in reverse against F/R pin input, 120° energization is maintained forcibly. No.A2005-15/19 LV8136V Functional Description • Basic operation of 120-degree ⇔ 150-degree current-carrying switching At startup, this IC starts at 120-degree current-carrying. The current-carrying is switched to 150 degrees when the 3-Hall FG frequency is 6.1Hz (typ) or above and the rising edge of the IN2 signal has been detected twice in succession. the Hall signal input sequence ° Concerning This IC controls the motor rotation direction commands and Hall signal input sequence in order to set the lead angle. If the motor rotation direction commands and Hall signal input sequence do not conform to what is shown on the timing chart, the motor is driven by 120-degree current-carrying. Example 1 : When the Hall signal has been input with the following logic IN1 IN2 IN3 H L H → H L L → H H L → L H L → L H H → L L H → H L L When F/R pin input is high → 120-degree current-carrying When F/R pin input is low → 150-degree current-carrying Example 2 : When the Hall signal has been input with the following logic IN1 IN2 IN3 H L H → L L H → L H H → L H L → H H L When F/R pin input is high → 150-degree current-carrying When F/R pin input is low → 120-degree current-carrying • CTL pin input a) Power-saving mode VCTL < VIL (1.0V : typ) When the CTL pin voltage is lower than VIL (1.0V : typ), the IC enters the power-saving mode, and the following are set : • LIN1 to LIN3 and HIN1 to HIN3 outputs all set to low • ICC = 0, HB pin = OFF The power consumption of the IC can now be set to 0, and the power consumption of the Hall element connected to the HB pin and the output block can also be set to 0. b) Standby mode VIL < VCTL < VIM (2.1V : typ) When the CTL pin voltage is VIL < VCTL < VIM, the IC enters the standby mode. Low is output for the UIN1 to UIN3 outputs and bootstrap charge pulses (2μs pulse width: design target) are output to the LIN1 to LIN3 outputs to prepare for drive start. c) Drive mode VIM < VCTL < VIH (5.4V : typ) When the CTL pin voltage is VIM < VCTL < VIH, the IC enters the drive mode, and the motor is driven at the PWM duty ratio corresponding to VCTL. When VCTL is increased, the PWM duty ratio increases, and the maximum duty ratio (*90% : typ) is reached at VIH. * When the PWM oscillation frequency setting is 17kHz. d) Test mode 8V < VCTL < VCTL max (design target) When the CTL pin voltage is 8V or higher, the IC enters the test mode, and the motor is driven at the 120-degree current-carrying and maximum duty ratio. • The CTL pin is pulled down by 190kΩ : typ inside the IC. Caution is required when the control input voltage input is subjected to resistance division, for example. • Bootstrap capacitor initial charging mode When the mode is switched from the power-saving mode to the standby mode and then to the drive mode, the IC enters the bootstrap capacitor charging mode (UH, VH, WH pins = L UL, VL, WL pins = H 3.84ms typ) in order to charge the bootstrap capacitor. No.A2005-16/19 LV8136V • Drive phase adjustment During 150-degree current-carrying drive, current-carrying is started from the phase that is 15 degrees ahead of the 120-degree current-carrying. From this state, any lead angle from 0 to 28 degrees can be set using the ADP1 pin voltage (lead angle control). This setting can be adjusted in 16 steps (in 1.875-degree increments) from 0 to 28 degrees using the ADP1 pin voltage, and it is updated every Hall signal cycle (it is sampled at the rising edge of the IN3 input and updated at its falling edge). A number of lead angle adjustments proportionate to the CTL pin voltage can be undertaken by adjusting the resistance levels of resistors connected to the ADP1 pin, ADP2 pin and DPL pin. When these pins are not going to be used, reference must be made to section 4.5, and the pins must not be used in the open status. Furthermore, a resistance of 47kΩ or more must be used for the resistor (RADP2) that is connected to the ADP2 pin. 1. The slopes of VCTL and VADP1 can be adjusted by setting the resistance level of the resistor (RADP1) connected to ADP1 (pin 15). VREG Lead Angle[°] 16 steps RDPL1 33kΩ 2.5V 2.34V IADP2 ADP1 ADP1(RADP1=47kΩ) DPL 28° 5V ADP2 VADP1,VADP2[V] IADP1 47kΩ RADP2 ADP2 ADP1(RADP1=22kΩ) RADP1 VADP2=(VCTL-2.1)×(2.5/3.3) IADP2=VADP2/RADP2 IADP1=2×IADP2 VADP1=IADP1×RADP1 0° 0V 2.1V 5.4V VCTL[V] 2. The ADP2 pin rise can be halted (a limit on the lead angle adjustment can be set by means of the CTL voltage) by setting DPL (pin 10). Lead Angle[°] 16 steps RDPL1 33kΩ 2.5V ADP1(RADP1=47kΩ) 1.25V 1.17V ADP2 ADP1(RADP1=22kΩ) 0° 0V 2.1V 3.75V 5.4V VCTL[V] IADP2 ADP1 VREG DPL 28° 5V ADP2 VADP1,VADP2[V] IADP1 RDPL2 33kΩ 47kΩ RADP2 RADP1 VADP2=(VCTL-2.1)×(2.5/3.3) IADP2=VADP2/RADP2 IADP1=2×IADP2 VADP1=IADP1×RADP1 DPLLIM=VDPL×1.5 3. The offset and slope can be adjusted as desired by setting RADP1 and RADP12 of ADP1 (pin 15). (It is also possible to set a limit on the lead angle adjustment by means of the CTL voltage by setting DPL.) Lead Angle[°] 16 steps RDPL1 33kΩ 2.5V ADP2 2.1V 5.4V IADP1 47kΩ RADP2 0.88V 0° 0V IADP2 ADP1 4.25V DPL ADP1 (RADP1=47kΩ,RADP12=220kΩ) VREG ADP1 (RADP1=33kΩ,RADP12=33kΩ) 28° 5V ADP2 VADP1,VADP2[V] VCTL[V] VREG RDPL12 RADP1 VADP2=(VCTL-2.1)×(2.5/3.3) IADP2=VADP2/RADP2 IADP1=2×IADP2 VADP1=((RADP1×RADP12)/(RADP1+RADP12))×IADP1 +(RADP1/(RADP1+RADP12))×VREG 4. When the lead angle is not adjusted ADP1 pin: shorted to ground; ADP2 pin and DPL pin: pulled down to ground using the resistors 5. When the lead angle is not adjusted by means of the CTL pin voltage (for use with a fixed lead angle) ADP1 pin: lead angle setting by resistance division from VREG; ADP2 pin and DPL pin: pulled down to ground by the resistors No.A2005-17/19 LV8136V Description of LV8136V 1. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VRF/Rf (where VRF = 0.25V typ, Rf is the value of the current detection resistor). The current limiter operates by reducing the output on duty to suppress the current. The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the current limiting function does not malfunction, its operation has a delay of approx. 1μs. If the motor coils have a low resistance or a low inductance, current fluctuation at startup (when there is no back electromotive force in the motor) will be rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above the set current. Application must take this increase in the current due to the delay into account when the current limiter value is set. 2. Power Saving Circuit (CTL pin) This IC goes into the power saving mode that stops operation of all the circuits to reduce the power consumption. If the HB pin is used for the Hall element bias and the output block, the current consumption in the power-saving mode is zero. 3. Hall Input Signal Signals with an amplitude in excess of the hysteresis is required for the Hall inputs. However, considering the influence of noise and phase displacement, an amplitude of over 100mV is desirable. If noise disrupts the output waveform (at phase change), this must be prevented by inserting capacitors or other devices across the Hall inputs. The constraint protection circuit uses the Hall inputs to discriminate the motor constraint state. Although the circuit is designed to tolerate a certain amount of noise, care is required. If all three phases of the Hall input signal go to the same input state (HHH or LLL), the outputs are all set to the off state. If the outputs from a Hall IC are used, fixing one side of the inputs (either the + or –side) at a voltage within the common-mode input voltage range (0.3V to VREG-1.7V) allows the other input side to be used as an input over the 0V to VREG range. 4. Constraint Protection Circuit This IC goes into the power saving mode that stops operation of all the circuits to reduce the power consumption. If the HB pin is used for the Hall element bias and the output block, the current consumption in the power-saving mode is zero. This IC provides an on-chip constraint protection circuit to protect the IC itself and the motor when the motor is constrained. If the Hall input signals do not change for over a fixed period when the motor is in operation, this circuit operates. Also, the upper-side output transistor is turned off while the constraint protection circuit is operating. This time is determined by the capacitance of the capacitor connected to the CSD pin. Set time (in seconds) ≈ 90 × C (μF) If a 0.022μF capacitor is used, the protection time will be about 2.0 seconds. The set time must be selected to have an adequate margin with respect to the motor startup time Conditions to clear the constraint protection state : CTL pin when a low-level voltage is input → Release protection and reset count When TSD protection is detected → Stop count 5. Power Supply Stabilization Since this IC adopts a switching drive technique, the power-supply line level can be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the VCC pins and ground. If the electrolytic capacitors cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1μF must be connected near these pins. If diodes are inserted in the power-supply line to prevent destruction of the device when the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. No.A2005-18/19 LV8136V 6. VREG Stabilization A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply. The ground lead of that capacitor must be located as close as possible to the control system ground (SGND) of the IC. 7. Forward/Reverse Switching (F/R pin) Switching between forward rotation and reverse rotation must not be undertaken while the motor is running. 8. TH Pin The TH pin must normally be pulled up to the 5V regulator for use. When it has been set to low, the outputs of LIN1, LIN2 and LIN3 as well as HIN1, HIN2 and HIN3 are low. 9. FAULT Pin The FAULT pin must normally be pulled up to the 5V regulator for use. When it has been set to low, the outputs of LIN1, LIN2 and LIN3 as well as HIN1, HIN2 and HIN3 are low. 10. PWM Frequency Setting fCPWM ≈ 1/ (1.78CR) Components with good temperature characteristics must be used. An oscillation frequency of about 17kHz is obtained when a 2200pF capacitor and 15kΩ resistor are used. If the PWM frequency is too low, switching noise will be heard from the motor; conversely, if it is too high, the output power loss will increase. For this reason, a frequency between 15kHz and 30kHz or so is desirable. The capacitor ground must be connected as close as possible to the control system ground (SGND pin) of the IC to minimize the effects of the outputs. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A2005-19/19