ENA2089 D

Ordering number : ENA2089A
LC717A00AJ
CMOS LSI
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
http://onsemi.com
Overview
The LC717A00AJ is a high-performance, low-cost capacitance-digital-converter LSI for electrostatic capacitive touch
sensor, especially focused on usability. It has 8 channels capacitance-sensor input. The built-in logic circuit can detect
the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications.
The calibration function is automatically performed by the built-in logic circuit during power activation or whenever
there are environmental changes. In addition, since initial settings of parameters, such as gain, are configured,
LC717A00AJ can operate as stand-alone when the recommended switch pattern is applied.
Also, since LC717A00AJ has a serial interface compatible with I2C and SPI bus, parameters can be adjusted using
external devices whenever necessary. Moreover, outputs of the 8-input capacitance data can be detected and measured
as 8-bit data.
Features
• Detection system: Differential capacitance detection (Mutual capacitance type)
• Input capacitance resolution: Can detect capacitance changes in the femto Farad order
• Measurement interval (8 differential inputs): 18ms (Typ) (at initial configuration),
3ms (Typ) (at minimum interval configuration)
• External components for measurement: Not required
• Current consumption: 320μA (Typ) (VDD = 2.8V), 740μA (Typ) (VDD = 5.5V)
• Supply voltage: 2.6V to 5.5V
• Detection operations: Switch
• Packages: SSOP30
• Interface: I2C * compatible bus or SPI selectable.
* I2C Bus is a trademark of Philips Corporation.
Semiconductor Components Industries, LLC, 2013
August, 2013
Ver1.0.1
D1912HKPC 20121129-S00003/71112HK No.A2089-1/11
LC717A00AJ
Specifications
Absolute Maximum Ratings at Ta = +25°C
Parameter
Symbol
Supply voltage
VDD
Input voltage
Ratings (VSS = 0V)
Unit
-0.3 to +6.5
V
VIN
-0.3 to VDD+0.3
V
Output voltage
VOUT
-0.3 to VDD+0.3
V
Power dissipation
Pd max
Peak output current
IOP
Total output current
IOA
Storage temperature
Tstg
160
mW
±8
mA
±40
mA
-55 to +125
°C
Remarks
*1
*2
Ta = +105°C,
Mounted on a substrate *3
per terminal,
50% Duty ratio *2
Output total value of LSI,
25% Duty ratio
*1) Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN
*2) Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT
*3) Single-layer glass epoxy board (76.1×114.3×1.6t mm)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Operating supply voltage
VDD
Supply ripple + noise
Vpp
Operating temperature
Topr
Conditions
min
typ
max
2.6
-40
25
Unit
5.5
V
±20
mV
105
°C
Remarks
*1
*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1μF, and is mounted near the LSI.
Electrical Characteristics at VSS = 0V, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
* Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143kHz.
* Not tested at low temperature before shipment.
Parameter
Symbol
Capacitance detection resolution
N
Output noise RMS
NRMS
Input offset capacitance
CoffRANGE
Conditions
min
typ
minimum gain setting
±1.0
CoffRESO
adjustment resolution
Cin offset drift
CinDRIFT
minimum gain setting
Cin detection sensitivity
CinSENSE
minimum gain setting
Cin pin leak current
ICin
Cin = Hi-Z
Cin allowable parasitic input
CinSUB
Cin against VSS
fCDRV
Cdrv pin leak current
ICDRV
*1 *3
±8.0
pF
*1 *3
8
bit
LSB
*1
0.12
±8
LSB/fF
*2
±500
nA
30
pF
143
186
kHz
±25
±500
nA
0.04
±25
nRST minimum pulse width
tNRST
Power-on reset time
tPOR
Power-on reset operation
tPOROP
100
Cdrv = Hi-Z
1
20
10
condition: Hold time
Power-on reset operation
VPOROP
0.1
condition: Input voltage
Power-on reset operation
tVDD
0V to VDD
1
VIH
High input
0.8VDD
VIL
Low input
Remarks
bit
LSB
capacitance
Cdrv drive frequency
Unit
8
adjustment range
Input offset capacitance
max
*1 *3
μs
*1
ms
*1
ms
*1
V
*1
V/ms
*1
V
*1 *4
V
*5
condition: Power supply rise rate
Pin input voltage
Pin output voltage
VOH
High output
(IOH = +3mA)
VOL
Low output
(IOL = -3mA)
0.2VDD
0.8VDD
0.2VDD
Continued to the next page.
No.A2089-2/11
LC717A00AJ
Continued from the previous page.
Parameter
SDA pin leak current
Symbol
VOL I2C
Conditions
min
typ
SDA Low output
(IOL = -3mA)
Pin leak current
ILEAK
Current consumption
IDD
max
Unit
0.4
V
±1
μA
*6
μA
*1 *3
μA
*3
When stand-alone
configuration and
non-touch
320
390
VDD = 2.8V
when stand-alone
configuration and
non-touch
ISTBY
Remarks
VDD = 5.5V
During Sleep process
740
900
1
*1) Design-guaranteed values (not tested before shipment)
*2) Measurements conducted using the test mode in the LSI
*3) Ta = +25°C
*4) Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN
*5) Apply to Cdrv, Pout0 to 7, SO, ERROR, INTOUT
*6) Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN
No.A2089-3/11
LC717A00AJ
I2C Compatible Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
*Not tested at low temperature before shipment
Parameter
Symbol
Pin Name
SCL clock frequency
fSCL
SCL
START condition hold time
tHD;STA
SCL
Conditions
min
typ
max
Unit
400
SDA
kHz
0.6
μs
SCL clock low period
tLOW
SCL
1.3
μs
SCL clock high period
tHIGH
SCL
0.6
μs
Repeated START condition
tSU;STA
SCL
0.6
μs
setup time
SDA
Data hold time
tHD;DAT
SCL
0
SDA
Data setup time
tSU;DAT
SCL
100
SDA
SDA, SCL rise/fall time
tr / tf
0.9
SCL
300
SDA
STOP condition setup time
tSU;STO
SCL
SDA
STOP-to-START bus release
tBUF
time
SCL
SDA
Remarks
*1
μs
μs
*1
μs
*1
0.6
μs
1.3
μs
*1
Unit
Remarks
*1) Design-guaranteed values (not tested before shipment)
SPI Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
*Not tested at low temperature before shipment
Parameter
SCK clock frequency
Symbol
fSCK
Pin Name
Conditions
min
typ
SCK
max
5
MHz
SCK clock Low time
tLOW
SCK
90
ns
*1
SCK clock High time
tHIGH
SCK
90
ns
*1
Input signal rise/fall time
tr / tf
ns
*1
90
ns
*1
90
ns
*1
20
ns
*1
30
ns
*1
90
ns
*1
90
ns
*1
90
ns
*1
80
ns
*1
80
ns
*1
0
ns
*1
0
ns
*1
nCS
SCK
300
SI
nCS setup time
tSU;NCS
nCS
SCK
SCK clock setup time
tSU;SCK
nCS
SCK
Data setup time
tSU;SI
SCK
SI
Data hold time
tHD;SI
SCK
SI
nCS hold time
tHD;NCS
nCS
SCK
SCK clock hold time
tHD;SCK
nCS
SCK
nCS standby pulse width
tCPH
nCS
Output high impedance time
tCHZ
nCS
from nCS
Output data determination time
SO
tv
SCK
SO
Output data hold time
tHD;SO
SCK
SO
Output low impedance time
from SCK clock
tCLZ
SCK
SO
*1) Design-guaranteed values (not tested before shipment)
No.A2089-4/11
LC717A00AJ
Power-on Reset (POR)
When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on reset operation condition: Power supply rise rate tVDD must be at least 1V/ms.
Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset state, it is
possible to verify the tPOR externally.
During power-on reset state, Cin, Cref and Pout are unknown.
VDD
tVDD
VPOROP
tPOR
tPOR
tPOROP
POR
(LSI internal signal)
RESET
UNKNOWN
RELEASE
INTOUT
VALID
Cin,
Cref,
Pout
UNKNOWN
RESET
RELEASE
UNKNOWN
UNKNOWN
VALID
fig.1
I2C Compatible Bus Data Timing
90%
SDA
10%
90%
10%
tHD;DTA
tLOW
tSU;DTA
90% 90%
10%
tSU;STA
90%
SCL
tHD;STA
10%
tHIGH
tr
10%
tHD;STA
90%
10% 10%
90%
90%
90%
tBUF
10%
tSU;STO
90%
10%
tf
repeated START
condition
START
condition
STOP
condition
START
condition
fig.2
I2C Compatible Bus Communication Formats
• Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L ACK
Register Address (N)
Slave
ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave
Slave
Slave
fig.3
• Read format (data can be read from sequentially incremented addresses)
START
Slave Address
Write=L ACK
Slave
RESTART
Slave Address
Register Address (N)
ACK
Slave
Read=H ACK Data read from Register Address (N) ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Master
Master
Master
fig.4
No.A2089-5/11
LC717A00AJ
I2C Compatible Bus Slave Address
Selection of two kinds of addresses is possible through the SA terminal.
SA pin input
7bit Slave Address
Low
0x16
High
Binary Notation
0x17
8bit Slave Address
00101100b (Write)
0x2C
00101101b (Read)
0x2D
00101110b (Write)
0x2E
00101111b (Read)
0x2F
SPI Data Timing (SPI Mode 0 / Mode 3)
tCPH
nCS
tSU;SCK
tSU;NCS
tHIGH
tHD;NCS
tf
tr
tLOW
tHD;SCK
SCK
tSU;SI
tHD;SI
VALID
SI
tCLZ
SO
tHD;SO
tCHZ
VALID
Hi-Z
tV
fig.5
SPI Communication Formats (Example of Mode 0)
• Write format (data can be written into sequentially incremented addresses while holding nCS = L)
nCS
SCK
SI
SO
Write=L
7 6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data written to Register Address(N)
Register Address(N)
7
6
5
4
3
2
1
0
Data written to Register Address(N+1)
Hi-Z
fig.6
• Read format (data can be read from sequentially incremented addresses while holding nCS = L)
nCS
SCK
SI
Read=H
7 6 5
4
3
2
1
0
Register Address(N)
SO
Hi-Z
7
6
5
4
3
2
1
0
Data read from Register Address(N)
7
6
5
4
3
2
1
0
7
Data read from Register Address(N+1)
fig.7
No.A2089-6/11
LC717A00AJ
Package Dimensions
[LC717A00AJ]
unit : mm (typ)
3421
8.0
0.5
6.4
4.4
30
12
0.22
0.5
0.15
0.1
(1.5)
1.7 MAX
(0.5)
SANYO : SSOP30(225mil)
Pin Assignment
Pin No.
Pin Name
Pin No.
Pin Name
1
VDD
16
Cref
2
VSS
17
ERROR
3
Non Connect *1
18
Cdrv
4
Cin4
19
INTOUT
5
Cin5
20
GAIN
6
Cin6
21
SCL/SCK
7
Cin7
22
SDA/SI
8
Pout0
23
SA/SO
9
Pout1
24
nCS
10
Pout2
25
nRST
11
Pout3
26
Non Connect *1
12
Pout4
27
Cin0
13
Pout5
28
Cin1
14
Pout6
29
Cin2
15
Pout7
30
Cin3
*1) connect to GND when mounted
No.A2089-7/11
LC717A00AJ
Block Diagram
Pout0
Cref
Pout1
Cin0
Pout2
Cin1
Pout3
Cin2
Cin3
Cin4
1st
AMP
2nd
AMP
A/D
CONVERTER
MUX
Pout4
Pout5
Pout6
Cin5
Pout7
Cin6
Cdrv
Cin7
ERROR
CONTROL
LOGIC
nCS
SCL/SCK
SDA/SI
SA/SO
INTOUT
nRST
GAIN
I2C/SPI
POR
OSCILLATOR
VDD
VSS
LC717A00AJ is capacitance-digital-converter LSI capable of detecting changes in capacitance in the femto Farad order.
It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system when
the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects the changes in the
capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into digital
data, and a control logic that controls the entire chip. Also, it has an I2C compatible bus or SPI that enables serial
communication with external devices as necessary.
No.A2089-8/11
LC717A00AJ
Pin Functions
Pin Name
I/O
Pin Functions
Cin0
I/O
Capacitance sensor input
Cin1
I/O
Capacitance sensor input
Cin2
I/O
Capacitance sensor input
Cin3
I/O
Capacitance sensor input
Cin4
I/O
Capacitance sensor input
Cin5
I/O
Capacitance sensor input
Cin6
I/O
Capacitance sensor input
Cin7
I/O
Capacitance sensor input
Cref
I/O
Reference capacitance input
Pout0
O
Cin0 judgment result output
Pout1
O
Cin1 judgment result output
Pout2
O
Cin2 judgment result output
Pout3
O
Cin3 judgment result output
Pout4
O
Cin4 judgment result output
Pout5
O
Cin5 judgment result output
Pout6
O
Cin6 judgment result output
Pout7
O
Cin7 judgment result output
ERROR
O
Error occurrence status output
Cdrv
O
Output for capacitance sensors drive
INTOUT
O
Interrupt output
SCL/SCK
I
GAIN
I
nCS
I
nRST
I
Clock input (I2C)
/ Clock input (SPI)
Pin Type
VDD
AMP
R
VSS
Buffer
VDD
Buffer
VSS
VDD
Selection pin of the initial value of gain of the
R
2nd-amplifier
Interface selection
/ Chip select inverting input (SPI)
External reset signal inverting input
VSS
VDD
R
SDA/SI
I/O
Data input and output (I2C)
/ Data input (SPI)
VSS
VDD
SA/SO
I/O
R
Slave address selection (I2C)
/ Data output (SPI)
VSS
VDD
Power supply (2.6V to 5.5V) *1
VSS
Ground (Earth) *1 *2
Buffer
*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1μF, and is mounted near the LSI.
*2) When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
No.A2089-9/11
LC717A00AJ
Details of Pin Functions
●Cin0 to Cin7
These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern. Cin
and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively coupled.
Therefore, LSI can detect capacitance change near each pattern as 8bit digital data.
However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able
to detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cin0 to Cin7 are connected to the inverting input of the 1st amplifier.
During measurement process, channels other than the one being measured are all in “Low” condition.
Leave the unused terminals open.
●Cref
It is the reference-capacitance-input pin. It is used by connecting to the wire pattern like Cin pins or is used by
connecting any capacitance between this pin and Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cref is connected to the non-inverting input of the 1st amplifier.
Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one
generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin
accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change
accurately.
However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect
capacitance change in each Cin pin correctly.
●Pout0 to Pout7
These are the detection-result-output pins. The capacitance detection results of Cin0 to Cin7 are compared with the
threshold of the LSI. The pin outputs a “High” or a “Low” depending on the result.
●ERROR
It is the error-occurrence-status-output pin.
It outputs “Low” during normal operation. If there is a calibration error or a system error, it outputs “High” to indicate
that an error occurred.
●Cdrv
It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at
Cin0 to Cin7.
Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.
●INTOUT
It is the interrupt-output pin. It outputs “High” when a measurement process is completed.
Connect to a main microcomputer if necessary, and use as interrupt signal.
Leave the terminal open if not in used.
●SCL/SCK
Clock input (I2C) / Clock input (SPI)
It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
●GAIN
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. It is the selection pin of the initial value of gain of the 2nd amplifier.
Even if this LSI is used alone, gain setting can still be selected through this terminal. At initialization of the LSI, it is
set to 7-times higher than the minimum setting when GAIN pin is “Low”, and is set to 14-times higher than the
minimum setting when GAIN pin is “High”.
No.A2089-10/11
LC717A00AJ
●nCS
Interface selection / Chip-select-inverting input (SPI)
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is
automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To
switch to SPI mode after LSI initialization, change the nCS input “High” → “Low”. The nCS pin is used as the chipselect-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized.
If interface is not to be used, fix the pin to “High”.
●nRST
It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in the reset state.
Each pin (Cin0 to 7, Cref, Pout,0 to 7, ERROR) is “Hi-Z” during reset state.
●SDA/SI
Data input and output (I2C) / Data input (SPI)
It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of
operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
●SA/SO
Slave address selection (I2C) / Data output (SPI)
It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode
of operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
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performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A2089-11/11
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