ENA0964 D

Ordering number : ENA0964B
LC75818PT
CMOS IC
1/8 to 1/10 Duty Dot Matrix LCD Display
Controllers/Drivers with Key Input Function
http://onsemi.com
Overview
The LC75818PT is 1/8 to 1/10 duty dot matrix LCD display controllers/drivers that support the display of characters,
numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from
a microcontroller, the LC75818PT also provide on-chip character display ROM and RAM to allow display systems to
be implemented easily. These products also provide up to 4 general-purpose output ports and incorporate a key scan
circuit that accepts input from up to 30 keys to reduce printed circuit board wiring.
Features
• Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)
• Controls and drives a 5×7, 5×8, or 5×9 dot matrix LCD.
• Supports accessory display segment drive (up to 80 segments)
• Display technique: 1/8 duty 1/4 bias drive (5×7 dots)
1/9 duty 1/4 bias drive (5×8 dots)
1/10 duty 1/4 bias drive (5×9 dots)
• Display digits: 16 digits×1 line (5×7 dots, 5×8 dots, 5×9 dots)
• Display control memory
CGROM: 240 characters (5×7, 5×8, or 5×9 dots)
CGRAM: 16 characters (5×7, 5×8, or 5×9 dots)
ADRAM: 16×5 bits
DCRAM: 64×8 bits
• Instruction function
Display on/off control
Display shift function
• Sleep mode can be used to reduce current drain.
• Built-in display contrast adjustment circuit
• The frame frequency of the common and segment output waveforms can be controlled by instructions.
• Serial data I/O supports CCB format communication with the system controller.
• Independent LCD driver block power supply VLCD
• A voltage detection type reset circuit is provided to initialize the IC and prevent incorrect display.
• The INH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose
output ports to the low level.
• RC oscillator circuit
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
•
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
51612HKPC /31710HKIM 20100223-S00003,S00005,S00006/82008HKIM No.A0964-1/43
LC75818PT
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Symbol
Conditions
Ratings
VDD
-0.3 to +4.2
VLCD max
VLCD
-0.3 to +11.0
VIN1
CE, CL, DI, INH
Output current
Allowable power dissipation
V
-0.3 to +4.2
CE, CL, DI, INH
Output voltage
Unit
VDD max
VIN2
VDD=2.7 to 3.6V
OSC, KI1 to KI5, TEST
VIN3
VLCD1, VLCD2, VLCD3, VLCD4
-0.3 to +6.5
V
-0.3 to VDD +0.3
-0.3 to VLCD +0.3
VOUT1
DO
VOUT2
OSC, KS1 to KS6, P1 to P4
VOUT3
VLCD0, S1 to S80, COM1 to COM10
IOUT1
S1 to S80
IOUT2
COM1 to COM10
3
IOUT3
KS1 to KS6
1
-0.3 to +6.5
-0.3 to VDD +0.3
V
-0.3 to VLCD +0.3
300
IOUT4
P1 to P4
5
Pd max
Ta=85°C
200
μA
mA
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Range at Ta = -40°C to +85°C, VSS = 0V
Parameter
Supply voltage
Symbol
Conditions
VDD
VDD
VLCD
When the display contrast adjustment circuit is used.
VLCD
VLCD
When the display contrast adjustment circuit is not
Ratings
min
typ
max
2.7
3.6
7.0
10.0
unit
V
4.5
10.0
VLCD4
+4.5
VLCD
used.
Output voltage
VLCD0
VLCD0
Input voltage
VLCD1
VLCD1
3/4
(VLCD0VLCD4)
VLCD2
VLCD2
VLCD3
VLCD4
VLCD0
V
1/4
(VLCD0VLCD4)
VLCD4
VLCD0
2/4
(VLCD0VLCD4)
VLCD3
V
0
VLCD0
1.5
Continued on next page.
No.A0964-2/43
LC75818PT
Continued from preceding page.
Parameter
Symbol
Input high level voltage
Ratings
Conditions
min
CE, CL, DI, INH
VIH1
CE, CL, DI, INH
typ
0.8VDD
3.6
VDD=2.7 to 3.6V
OSC external clock operating mode
0.8VDD
5.5
0.8VDD
VDD
VIH3
KI1 to KI5
0.6VDD
VDD
VIL1
CE, CL, DI, INH, KI1 to KI5
0
0.2VDD
VIL2
OSC external clock operating mode
0
0.2VDD
0
5.5
VIH2
Input low level voltage
Output pull-up voltage
VOUP
DO
Recommended external
Rosc
OSC RC oscillator operating mode
Cosc
OSC RC oscillator operating mode
fosc
OSC RC oscillator operating mode
capacitor for RC oscillation
Guaranteed range of RC
oscillation
V
V
V
10
kΩ
470
pF
resistor for RC oscillation
Recommended external
unit
max
150
300
600
kHz
kHz
External clock operating frequency
fCK
OSC external clock operating mode
[Figure 4]
100
300
600
External clock duty cycle
DCK
OSC external clock operating mode
[Figure 4]
30
50
70
[Figure 2],[Figure 3]
160
ns
160
ns
CL, DI
%
Data setup time
tds
Data hold time
tdh
CL, DI
[Figure 2],[Figure 3]
CE wait time
tcp
CE, CL
[Figure 2],[Figure 3]
160
ns
CE setup time
tcs
CE, CL
[Figure 2],[Figure 3]
160
ns
CE hold time
tch
CE, CL
[Figure 2],[Figure 3]
160
ns
High level clock pulse width
tφH
CL
[Figure 2],[Figure 3]
160
ns
Low level clock pulse width
tφL
CL
[Figure 2],[Figure 3]
160
DO output delay time
tdc
DO RPU=4.7kΩ CL=10pF *1
[Figure 2],[Figure 3]
1.5
μs
DO rise time
tdr
DO RPU=4.7kΩ CL=10pF *1
[Figure 2],[Figure 3]
1.5
μs
ns
Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and
the load capacitance CL.
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Hysteresis
Symbol
VH
Pins
Conditions
Ratings
min
typ
CE, CL, DI, INH,
0.1VDD
KI1 to KI5
Power-down detection
VDET
2.0
voltage
Input high level current
IIH1
CE, CL, DI, INH
2.4
5.0
VI=5.5V
VDD=2.7 to 3.6V
5.0
OSC
VI=VDD external clock operating mode
IIL1
CE, CL, DI, INH
VI=0V
-5.0
IIL2
OSC
VI=0V external clock operating mode
-5.0
Input floating voltage
VIF
KI1 to KI5
Pull-down resistance
RPD
KI1 to KI5
VDD=3.3V
50
IOFFH
DO
VO=5.5V
Output high level voltage
VOH1
S1 to S80
IO=-20μA
VLCDO-0.6
VOH2
COM1 to COM10
IO=-100μA
VLCDO-0.6
VOH3
KS1 to KS6
IO=-250μA
VDD-0.8
VOH4
P1 to P4
IO=-1mA
VDD-0.9
VOL1
S1 to S80
IO=20μA
VOL2
COM1 to COM10
IO=100μA
VOL3
KS1 to KS6
IO=12.5μA
VOL4
P1 to P4
IO=1mA
VOL5
DO
IO=1mA
V
μA
5.0
Output off leakage current
Output low level voltage
2.2
unit
V
VI=3.6V
IIH2
Input low level current
max
μA
100
VDD-0.4
0.05VDD
V
250
kΩ
6.0
μA
VDD-0.1
V
VLCD4+0.6
VLCD4+0.6
0.1
0.4
1.2
V
0.9
0.1
0.3
Continued on next page.
No.A0964-3/43
LC75818PT
Continued from preceding page.
Parameter
Symbol
Output middle level
VMID1
Pins
Conditions
S1 to S80
IO=±20μA
voltage *2
VMID2
VMID3
Oscillator frequency
fosc
COM1 to COM10
COM1 to COM10
OSC
IO=±100μA
IO=±100μA
Rosc=10kΩ
IDD1
IDD2
VDD
VDD
min
typ
unit
max
2/4
2/4
(VLCD0
-VLCD4)
(VLCD0
-VLCD4)
-0.6
+0.6
3/4
3/4
(VLCD0
-VLCD4)
(VLCD0
-VLCD4)
-0.6
+0.6
1/4
1/4
(VLCD0
-VLCD4)
(VLCD0
-VLCD4)
-0.6
+0.6
210
Cosc=470pF
Current drain
Ratings
300
sleep mode
390
V
kHz
100
VDD=3.6V
output open
500
1000
fosc=300kHz
ILCD1
ILCD2
VLCD
VLCD
sleep mode
15
VLCD=10.0V
output open
fosc=300kHz
450
900
200
400
μA
When the display contrast
adjustment circuit is used.
ILCD3
VLCD
VLCD=10.0V
output open
fosc=300kHz
When the display contrast
adjustment circuit is not used.
Note: *2. Excluding the bias voltage generation divider resistor built into the VLCD0, VLCD1, VLCD2, VLCD3,
and VLCD4. (See Figure 1.)
VLCD
CONTRAST
ADJUSTER
VLCD0
VLCD1
To the common and segment drivers
VLCD2
VLCD3
VLCD4
Excluding these resistors
[Figure 1]
No.A0964-4/43
LC75818PT
(1) When CL is stopped at the low level
≈ ≈ ≈ ≈ ≈
≈ ≈
DI VIH1
VIL1
tcs
tcp
tdc
tdh
tds
VIL1
≈ ≈
tφL
tφH
VIH1
CL 50%
VIL1
≈
VIH1
CE
DO
tdr
D1
≈
D0
tch
[Figure 2]
≈
(2) When CL is stopped at the high level
VIH1
VIL1
≈
CE
≈
CL
VIH1
50%
VIL1
tcp
tcs
VIH1
DI
VIL1
tds
tdh
DO
D0
D1
tdc
tch
≈ ≈ ≈ ≈
tφH
≈ ≈ ≈ ≈ ≈
tφL
tdr
[Figure 3]
(3) OSC pin clock timing in external clock operating mode
OSC
VIH2
50%
VIL2
tCKH
tCKL
fCK=
1
tCKH + tCKL
DCK=
t
[kHz]
tCKH
×100[%]
CKH + tCKL
[Figure 4]
No.A0964-5/43
LC75818PT
Package Dimensions
unit : mm (typ)
3257A
14.0
16.0
0.5
16.0
14.0
120
1
0.15
0.4
0.125
0.1
1.2MAX
(1.0)
(1.2)
SANYO : TQFP120(14X14)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
Pin Assignments
61
90
60
LC75818PT
(TQFP120)
120
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
31
1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
KS1
KS2
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
P1
P2
P3
P4
VDD
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VSS
TEST
OSC
INH
DO
CE
CL
DI
91
30
Top view
No.A0964-6/43
LC75818PT
GENERAL
PORT
S1
S78
S79
S80
COM10
COM1
P4
P2
P3
P1
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER
LATCH
INSTRUCTION
DECODER
ADRAM
80
bits
INSTRUCTION
REGISTER
ADDRESS
COUNTER
VLCD
CONTRAST
ADJUSTER
VLCD0
CGRAM
5×9×16
bits
CGROM
5×9×240
bits
DCRAM
64×8
bits
VLCD1
ADDRESS
REGISTER
VLCD2
VLCD3
VLCD4
SHIFT REGISTER
CCB INTERFACE
VDD
VDET
KEY BUFFER
TIMING
GENERATOR
VSS
CLOCK
GENERATOR
KS1
KS2
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
CE
CL
DI
DO
KEY SCAN
INH
OSC
TEST
No.A0964-7/43
LC75818PT
Pin Functions
Pin
Pin No.
S1 to S80
1 to 80
Function
Handling
Active
I/O
-
O
OPEN
-
O
OPEN
-
O
OPEN
H
I
GND
-
O
OPEN
-
I/O
VDD
H
I
when unused
Segment driver outputs.
COM1 to COM10
90 to 81
Common driver outputs.
KS1 to KS6
91 to 96
Key scan outputs. Although normal key scan timing lines require
diodes to be inserted in the timing lines to prevent shorts, since
these outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs are
used to form a key matrix.
KI1 to KI5
97 to 101
Key scan inputs.
These pins have built-in pull-down resistors.
P1 to P4
102 to 105
General-purpose outputs. P4 can be used as a clock output port
with the "set key scan output port/general-purpose output port
state" instruction.
OSC
115
Oscillator connections. An oscillator circuit is formed by
connecting an external resistor and capacitor to this pin.
This pin can also be used as the external clock input pin with the
"set display technique" instruction.
CE
118
CL
119
DI
120
DO
117
INH
116
Serial data interface connections to the controller. Note that DO,
being an open-drain output, requires a pull-up resistor.
I
CE: Chip enable
CL: Synchronization clock
GND
-
I
-
O
OPEN
L
I
VDD
-
I
-
-
O
OPEN
-
I
OPEN
-
I
OPEN
DI: Transfer data
DO: Output data
Input that turns the display off, disables key scanning, and
forces the general-purpose output ports low.
• When INH is low (VSS):
• Display off
S1 to S80=”L” (VLCD4)
COM1 to COM10=”L” (VLCD4)
• General-purpose output ports P1 to P4=low (VSS)
• Key scanning disabled: KS1 to KS6=low (VSS)
• All the key data is reset to low.
• When INH is high (VDD):
• Display on
• The state of the pins as key scan output pins or
general-purpose output ports can be set with the
"set key scan output port/general-purpose output
port state" instruction.
• Key scanning is enabled.
However, serial data can be transferred when the INH pin is low.
TEST
114
This pin must be connected to ground.
VLCD0
108
LCD drive 4/4 bias voltage (high level) supply pin. The level on this
pin can be changed by the display contrast adjustment circuit.
However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V.
Also, external power must not be applied to this pin since the pin
circuit includes the display contrast adjustment circuit.
VLCD1
109
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 3/4 (VLCD0 - VLCD4) voltage level
externally.
VLCD2
110
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 2/4 (VLCD0 - VLCD4) voltage level
externally.
Continued on next page.
No.A0964-8/43
LC75818PT
Continued from preceding page.
Pin
Pin No.
VLCD3
111
Function
Handling
Active
I/O
-
I
OPEN
-
I
GND
-
-
-
-
-
-
-
-
-
when unused
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 1/4 (VLCD0 - VLCD4) voltage level
externally.
VLCD4
112
LCD drive 0/4 bias voltage (low level) supply pin. Fine
adjustment of the display contrast can be implemented by
connecting an external variable resistor to this pin.
However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V,
and VLCD4 must be in the range 0V to 1.5V, inclusive.
VDD
106
Logic block power supply connection. Provide a voltage of
between 2.7to 3.6V.
VLCD
107
LCD driver block power supply connection. Provide a voltage of
between 7.0 to 10.0V when the display contrast adjustment circuit
is used and provide a voltage of between 4.5 to 10.0V when the
circuit is not used.
VSS
Power supply connection. Connect to ground.
113
Block Functions
• AC (address counter)
AC is a counter that provides the addresses used for DCRAM and ADRAM.
The address is automatically modified internally, and the LCD display state is retained.
• DCRAM (data control RAM)
DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are
converted to 5×7, 5×8, or 5×9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of
64×8 bits, and can hold 64 characters. The table below lists the correspondence between the 6-bit DCRAM address
loaded into AC and the display position on the LCD panel.
• When the DCRAM address loaded into AC is 00H.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DCRAM address (hexadecimal)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DCRAM address (hexadecimal)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DCRAM address (hexadecimal)
3F
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
(shift left)
(shift right)
Note: *3. The DCRAM address is expressed in hexadecimal.
Most significant bit
↓
MSB
Least significant bit
↓
LSB
DCRAM address
DA0
DA1
DA2
DA3
Hexadecimal
DA4
DA5
Hexadecimal
Example: When the DCRAM address is 2EH.
DA0
DA1
DA2
DA3
DA4
DA5
0
1
1
1
0
1
No.A0964-9/43
LC75818PT
• ADRAM (Additional data RAM)
ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 16×5 bits, and the stored
display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence
between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.
• When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 16)
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADRAM address (hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADRAM address (hexadecimal)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADRAM address (hexadecimal)
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
(shift left)
(shift right)
Note: *4. The ADRAM address is expressed in hexadecimal.
Least significant bit
↓
LSB
ADRAM address
RA0
RA1
Most significant bit
↓
MSB
RA2
RA3
Hexadecimal
Example: When the ADRAM address is AH.
RA0
RA1
RA2
RA3
0
1
0
1
• CGROM (Character generator ROM)
CGROM is ROM that is used to generate the 240 kinds of 5×7, 5×8, or 5×9 dot matrix character patterns from the
8-bit character codes. CGROM has a capacity of 240×45 bits. When a character code is written to DCRAM, the
character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD
corresponding to the DCRAM address loaded into AC.
• CGRAM (Character generator RAM)
CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5×7, 5×8,
or 5×9 dot matrix character patterns can be stored. CGRAM has a capacity of 16×45 bits.
No.A0964-10/43
LC75818PT
Serial Data Input
(1) When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D0
D1 D2 D3 D4
D62 D63
Instruction data (Up to 64 bits)
DO
(2) When CL is stopped at the high level
CE
CL
DI
0
B0
1
B1
0
B2
0
B3
0
A0
0
A1
1
A2
0
A3
D0 D1 D2 D3 D4
D62 D63
Instruction data (Up to 64 bits)
DO
• B0 to B3, A0 to A3: CCB address 42H
• D0 to D63: Instruction data
The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When
transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set
of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.
No.A0964-11/43
D1... D39
CD1 CD2…CD40
D0
D41
D42
D43
D44
D45
D46
D47
AD2
AC1
AD3
AC2
AD4
AC3
X
X
AC5
AD5
AC4
CD41 CD42 CD43 CD44 CD45
AD1
AC0
X
X
AC6
X
X
AC7
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8
D40
D49
D50
D51
D52
D53
D54
D55
CT1
CA1
RA 1
DA1
DA1
C T2
CA2
R A2
DA2
DA2
C T3
CA3
RA 3
DA3
DA3
X
CA4
X
DA4
DA4
X
CA5
X
DA5
DA5
X
CA6
X
X
X
X
CA7
X
X
X
KC1 KC2 KC3 KC4 KC5 KC6 PC40 PC41
C T0
CA0
RA0
DA0
DA0
DG9 DG10 DG11 DG12 DG13 DG14 DG15 DG16
D48
A
M
R/L
SC
FC
X
SP
OC
PC1
C TC
X
IM
IM
PC2
X
X
X
X
PC3
X
X
X
X
X
X
X
X
X
RA0 RA1 RA2 RA3
A
M
DT1 DT2
D56 D57 D58 D59
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
D60 D61 D62 D63
Notes: *5. Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). Note that the execution time of this first
instruction is 108μs (fosc=300kHz, fCK=300kHz).
*6. The data format differs when the “DCRAM data write” instruction is executed in the increment mode (IM = 1).
(See detailed instruction descriptions .)
*7. The data format differs when the “ADRAM data write” instruction is executed in the increment mode (IM = 1).
(See detailed instruction descriptions.)
*8. The execution times listed here apply when fosc=300kHz, fCK=300kHz. The execution times differ when the oscillator frequency fosc or the external
clock frequency fCK differs.
Example: When fosc = 210kHz, fCK = 210kHz
300
300
27μs× 210 = 39μs, 108μs× 210 = 155μs
*9.When the sleep mode (SP = 1) is set, the execution time is 27μs (when fosc = 300kHz, fCK = 300kHz).
Set key scan output port/
general-purpose output
port state
contrast
Set display
CGRAM data write
*7
ADRAM data write
write *6
DCRAM data
Set AC address
Display shift
Display on/off
control
*5
Set display technique
Instruction
Instruction Table
X: don’t care
0μs
0μs
27μs
27μs
27μs
27μs
27μs
*9
0μs/27μs
*5
0μs/108μs
*8
Execution time
LC75818PT
No.A0964-12/43
LC75818PT
Detailed Instruction Descriptions
• Set display technique ... <Sets the display technique>
(Display technique)
Code
D56
D57
D58
D59 D60
DT1
DT2
FC
0C
D61
D62
D63
0
0
1
0
Note: Be sure to execute the "set display technique"
instruction first after power-on (VDET-based
system reset).
X: don’t care
DT1, DT2: Sets the display technique
DT1
DT2
Output pins
Display technique
COM9
COM10
0
0
1/8 duty, 1/4 bias drive
VLCD4 level
VLCD4 level
1
0
1/9 duty, 1/4 bias drive
COM9
VLCD4 level
0
1
1/10 duty, 1/4 bias drive
COM9
COM10
Note: *10. COMn (n=9,10): Common
output
FC: Sets the frame frequency of the common and segment output waveforms
Frame frequency
FC
1/10 duty, 1/4 bias drive
1/8 duty, 1/4 bias drive
1/9 duty, 1/4 bias drive
f8[Hz]
f9[Hz]
f10[Hz]
0
fosc/3072, fCK/3072
fosc/3456, fCK/3456
fosc/3840, fCK/3840
1
fosc/1536, fCK/1536
fosc/1728, fCK/1728
fosc/1920, fCK/1920
OC: Sets the RC oscillator operating mode and external clock operating mode.
OC
OSC pin function
0
RC oscillator operating mode
1
External clock operating mode
Note: *11. When selecting the RC oscillator operating mode, be sure to connect an external resistor Rosc and an
external capacitor Cosc to the OSC pin.
• Display on/off control ... <Turns the display on or off>
(Display ON/OFF control)
Code
D40 D41 D42 D43 D44 D45 D46 D47 D48 D49
D50
D51 D52
D53 D54
D55
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 DG14 DG15 DG16
D56
D57
D58
D59
M
A
SC
SP
D60 D61 D62 D63
0
0
1
0
X: don’t care
M, A: Specifies the data to be turned on or off
M
A
0
0
Display operating state
Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG16 data.)
0
1
Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG16 data are turned on.)
1
0
Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG16 data are turned on.)
1
1
Both MDATA and ADATA are turned on
(The MDATA and ADATA of display digits specified by the DG1 to DG16 data are turned on.)
Note: *12. MDATA, ADATA
5×7 dot matrix display
----- ADATA
--- MDATA
5×8 dot matrix display
----- ADATA
--- MDATA
5×9 dot matrix display
----- ADATA
--- MDATA
No.A0964-13/43
LC75818PT
DG1 to DG16: Specifies the display digit
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Display digit data
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
DG11
DG12
DG13
DG14
DG15
DG16
For example, if DG1 to DG7 are 1, and DG8 to DG16 are 0, then display digits 1 to 7 will be turned on, and display
digits 8 to 16 will be turned off (blanked).
SC: Controls the common and segment output pins
SC
Common and segment output pin states
0
Output of LCD drive waveforms
1
Fixed at the VLCD4 level (all segments off)
Note: *13. When SC is 1, the S1 to S80 and COM1 to COM10 output pins are set to the VLCD4 level,
regardless of the M, A, and DG1 to DG16 data.
SP: Controls the normal mode and sleep mode
SP
Mode
0
Normal mode
Sleep mode
The common and segment pins go to the VLCD4 level and the oscillator on the OSC pin is stopped (although it operates during
key scan operations) in RC oscillator operating mode (OC="0") and reception of the external clock is stopped (external clock is
received during key scan operations) in external clock operating mode (OC="1"), to reduce current drain.
1
Although the "display on/off control", "set display contrast" and "set key scan output port/general-purpose output port state"
(disallowed to set the clock output at the P4 pin) instructions can be executed in this mode, applications must return the IC to
normal mode to execute any of the other instruction setting. When the IC is in external clock operating mode, be sure to stop
the external clock input after the lapse of the instruction execution time (27μs: fCK=300kHz).
• Display shift ... <Shifts the display>
(Display shift)
Code
D56
D57
D58
D59
D60
D61
D62
D63
M
A
R/L
X
0
0
1
1
X: don’t care
M, A: Specifies the data to be shifted
M
A
0
0
Shift operating state
Neither MDATA nor ADATA is shifted
0
1
Only ADATA is shifted
1
0
Only MDATA is shifted
1
1
Both MDATA and ADATA are shifted
R/L: Specifies the shift direction
R/L
Shift direction
0
Shift left
1
Shift right
No.A0964-14/43
LC75818PT
• Set AC address... <Specifies the DCRAM and ADRAM address for AC>
(Set AC)
Code
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DA0
DA1
DA2
DA3
DA4
DA5
X
X
RA0
RA1
RA2
RA3
0
1
0
0
X: don’t care
DA0 to DA5: DCRAM address
DA0
DA1
DA2
DA3
DA4
LSB
↑
Least significant bit
DA5
MSB
↑
Most significant bit
RA0 to RA3: ADRAM address
RA0
RA1
RA2
LSB
↑
Least significant bit
RA3
MSB
↑
Most significant bit
This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC.
• DCRAM data write ... <Specifies the DCRAM address and stores data at that address>
(Write data to DCRAM)
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC7
DA0
DA1
DA2
DA3
DA4
DA5
X
X
IM
X
X
X
0
1
0
1
X: don’t care
DA0 to DA5: DCRAM address
DA0
DA1
DA2
DA3
LSB
↑
Least significant bit
DA4
DA5
MSB
↑
Most significant bit
AC0 to AC7: DCRAM data (character code)
AC0
AC1
AC2
AC3
AC4
AC5
AC6
LSB
↑
Least significant bit
AC7
MSB
↑
Most significant bit
This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a
5×7, 5× 8, or 5×9 dot matrix display data using CGROM or CGRAM.
IM: Sets the method of writing data to DCRAM
IM
DCRAM data write method
0
Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.)
1
Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.)
No.A0964-15/43
LC75818PT
Notes: *14.
• DCRAM data write method when IM = 0
CE
CCB address
CCB address
CCB address
CCB address
(1)
(1)
(1)
(1)
24 bit
24 bit
24 bit
24 bit
DI
DCRAM
Instruction
execution time
Instruction
execution time
DCRAM data
write finishes
Instruction
execution time
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
• DCRAM data write method when IM = 1
(Instructions other than the “DCRAM data write” instruction cannot be executed.)
CE
CCB address
CCB address
CCB address
CCB address
(1)
(2)
(2)
24 bit
8 bit
8 bit
DI
CCB address
(2)
8 bit
CCB address
(3)
(2)
8 bit
16 bit
DCRAM
Instruction
Instruction
Instruction
Instruction
Instruction
execution time
execution time
execution time
execution time
execution time
DCRAM data
DCRAM data
DCRAM data
DCRAM data
write finishes
write finishes
write finishes
write finishes
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
Instructions other than the “DCRAM data write” instruction
cannot be executed.
Data format at (1) (24 bits)
Code
D40 D41 D42 D43 D44 D45
D46 D47
D48
D49 D50 D51
D52 D53 D54
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
DA0
DA1 DA2 DA3
DA4 DA5
D55 D56
X
X
IM
D57
X
D58 D59
X
X
D60 D61 D62
0
1
0
D63
1
X: don’t care
Data format at (2) (8 bits)
Code
D56
D57 D58 D59 D60 D61 D62 D63
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
Data format at (3) (16 bits)
Code
D48 D49 D50 D51 D52 D53 D54 D55
D56
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
0
D57 D58 D59
X
X
D60 D61 D62
X
0
1
0
D63
1
X: don’t care
• ADRAM data write ... <Specifies the ADRAM address and stores data at that address>
(Write data to ADRAM)
Code
D40 D41 D42 D43 D44
AD1 AD2 AD3 AD4 AD5
D45 D46 D47 D48 D49
X
X
X
D50 D51
RA0 RA1 RA2 RA3
D52
D53
X
X
D54 D55
X
X
D56
D57
IM
X
D58 D59
X
X
D60
0
D61 D62
1
1
D63
0
X: don’t care
RA0 to RA3:ADRAM address
RA0
RA1
RA2
LSB
↑
Least significant bit
RA3
MSB
↑
Most significant bit
No.A0964-16/43
LC75818PT
AD1 to AD5: ADATA display data
In addition to the 5×7, 5×8, or 5×9 dot matrix display data (MDATA), this IC supports direct display of the five
accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM.
The figure below shows the correspondence between the data and the display. When ADn = 1(where n is an integer
between 1 and 5) the segment corresponding to that data will be turned on.
S5m+1
S5m+5 (m is an integer
between 0 and 15)
ADATA
Corresponding output pin
AD1
S5m+1 (m is an integer between 0 and 15)
AD2
S5m+2
AD3
S5m+3
AD4
S5m+4
AD5
S5m+5
IM: Sets the method of writing data to ADRAM
ADRAM data write method
IM
0
Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.)
1
Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.)
Notes: *15.
• ADRAM data write method when IM = 0
CE
CCB address
CCB address
DI
CCB address
CCB address
(4)
(4)
(4)
(4)
24 bit
24 bit
24 bit
24 bit
ADRAM
Instruction
execution time
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
• ADRAM data write method when IM = 1
(Instructions other than the “ADRAM data write” instruction cannot be executed.)
CE
CCB address
DI
CCB address
CCB address
CCB address
CCB address
CCB address
(4)
(5)
(5)
(5)
(5)
(6)
24 bit
8 bit
8 bit
8 bit
8 bit
16 bit
ADRAM
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
Instructions other than the “ADRAM data write” instruction
cannot be executed.
No.A0964-17/43
LC75818PT
Data format at (4) (24 bits)
Code
D40 D41 D42 D43
D44 D45
AD1 AD2 AD3 AD4 AD5
D46
X
D47 D48 D49
X
X
RA0 RA1
D50
D51 D52 D53
RA2 RA3
X
X
D54
D55
X
X
D56 D57
IM
D58 D59 D60
X
X
X
0
D61 D62
1
1
D63
0
X: don’t care
Data format at (5) (8 bits)
Code
D56 D57 D58 D59 D60
D61 D62 D63
AD1 AD2 AD3 AD4 AD5
X
X
X
X: don’t care
Data format at (6) (16 bits)
Code
D48 D49 D50 D51 D52 D53
AD1 AD2 AD3 AD4 AD5
D54 D55 D56
X
X
X
0
D57 D58 D59 D60 D61 D62 D63
X
X
X
0
1
1
0
X: don’t care
• CGRAM data write ... <Specifies the CGRAM address and stores data at that address>
(Write data to CGRAM)
Code
D0
D1
D2
D3
D4
D5
D6
D7
D8
CD1 CD2 CD3
CD4
CD5
CD6
CD7
CD8
CD9
D9
D10
D11
D12
D13
D14
D15
CD10 CD11 CD12 CD13 CD14 CD15 CD16
Code
D16
D17
D18
D19
D20
D21
D22
D23
CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24
D24
CD25
D25
D26
D27
D28
D29
D30
D31
CD26 CD27 CD28 CD29 CD30 CD31 CD32
Code
D32
D33
D34
D35
D36
D37
D38
D39
CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40
D40
CD41
D41
D42
D43
D44
CD42 CD43 CD44 CD45
D45
D46
D47
X
X
X
D62
D63
1
1
Code
D48
CA0
D49
D50
D51
D52
D53
D54
D55
D56
CA1 CA2 CA3
CA4
CA5
CA6
CA7
X
D57
X
D58
D59
D60
D61
X
X
0
1
X: don’t care
CA0 to CA7: CGRAM address
CA0
CA1
CA2
CA3
CA4
LSB
↑
Least significant bit
CA5
CA6
CA7
MSB
↑
Most significant bit
CD1 to CD45: CGRAM data (5×7, 5×8, or 5×9 dot matrix display data)
The bit CDn (where n is an integer between 1 and 45) corresponds to the 5×7, 5×8, or 5×9 dot matrix display data.
The figure below shows that correspondence. When CDn is 1 the dots which correspond to that data will be turned on.
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
Note: *16. CD1 to CD35: 5×7 dot matrix display data
CD1 to CD40: 5×8 dot matrix display data
CD1 to CD45: 5×9 dot matrix display data
No.A0964-18/43
LC75818PT
• Set display contrast… <Sets the display contrast>
(Set display contrast)
Code
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
CT0
CT1
CT2
CT3
X
X
X
X
CTC
X
X
X
1
0
0
0
X: don’t care
CT0 to CT3: Sets the display contrast (11 steps)
CT0
CT1
CT2
CT3
0
0
0
0
0.94VLCD=VLCD-(0.03VLCD×2)
LCD drive 4/4 bias voltage supply VLCD0 level
1
0
0
0
0.91VLCD=VLCD-(0.03VLCD×3)
0
1
0
0
0.88VLCD=VLCD-(0.03VLCD×4)
1
1
0
0
0.85VLCD=VLCD-(0.03VLCD×5)
0
0
1
0
0.82VLCD=VLCD-(0.03VLCD×6)
1
0
1
0
0.79VLCD=VLCD-(0.03VLCD×7)
0
1
1
0
0.76VLCD=VLCD-(0.03VLCD×8)
1
1
1
0
0.73VLCD=VLCD-(0.03VLCD×9)
0
0
0
1
0.70VLCD=VLCD-(0.03VLCD×10)
1
0
0
1
0.67VLCD=VLCD-(0.03VLCD×11)
0
1
0
1
0.64VLCD=VLCD-(0.03VLCD×12)
CTC: Sets the display contrast adjustment circuit state
CTC
Display contrast adjustment circuit state
0
The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level.
1
The display contrast adjustment circuit operates, and the display contrast is adjusted.
Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is
also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin and
modifying the VLCD4 pin voltage. However, the following conditions must be met: VLCD0-VLCD4≥ 4.5V, and
1.5V≥VLCD4 ≥ 0V.
• Set key scan output port/general-purpose output port state
... <Sets the key scan output port and general-purpose output port states>
(Key scan output port and General-purpose output port control)
Code
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
KC1
KC2
KC3
KC4
KC5
KC6
PC40 PC41
PC1
PC2
PC3
X
1
0
0
1
X:don’t care
KC1 to KC6: Sets the key scan output pin KS1 to KS6 state
Output pin
KS1
KS2
KS3
KS4
KS5
KS6
Key scan output state setting data
KC1
KC2
KC3
KC4
KC5
KC6
When KC1 to KC3 are set to 1 and KC4 to KC6 are set to 0, in the key scan standby state, the KS1 to KS3 output pins
will output the high level (VDD) and KS4 to KS6 will output the low level (VSS).
Note that key scan output signals are not output from output pins that are set to the low level.
PC1, PC2, PC3: Sets the general-purpose output port P1, P2, P3 state
Output pin
P1
P2
P3
General-purpose output port state setting
PC1
PC2
PC3
When PC1 is set to 1 and PC2 to PC3 are set to 0, P1 output pin will output the high levels (VDD) and P2 to P3 will
output the low levels (VSS).
No.A0964-19/43
LC75818PT
PC40, PC41: Sets the general-purpose output port P4 state
PC40
Output pin (P4) state
PC41
0
0
“L”(VSS)
1
0
“H”(VDD)
0
1
Clock signal output (fosc/2, fCK/2)
1
1
Clock signal output (fosc/8, fCK/8)
Serial Data Output
(1) When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
DO
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X: don’t care
(2) When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
DO
KD28 KD29 KD30 SA
X KD1 KD2 KD3
X
Output data
X: don’t care
• B0 to B3, A0 to A3: CCB address 43H
• KD1 to KD30: Key data
• SA: Sleep acknowledge data
Note: *17. If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep
acknowledge data(SA) will be invalid.
Output Data
(1) KD1 to KD30: Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1
KD1
KD2
KD3
KD4
KD5
KS2
KD6
KD7
KD8
KD9
KD10
KS3
KD11
KD12
KD13
KD14
KD15
KS4
KD16
KD17
KD18
KD19
KD20
KS5
KD21
KD22
KD23
KD24
KD25
KS6
KD26
KD27
KD28
KD29
KD30
(2) SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial
data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in
Sleep mode and 0 in normal mode.
No.A0964-20/43
LC75818PT
Key Scan Operation Functions
(1) Key scan timing
The key scan period is 2304T(s). To reliably determine the on/off state of the keys, the LC75818PT scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 4800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75818PT cannot detect a key press shorter than 4800T(s).
KS1
*18
KS2
*18
KS3
*18
KS4
*18
KS5
*18
KS6
*18
1
*18
1
2
*18
2
3
*18
3
4
*18
4
5
Key on
1
fosc
T=
1
fCK
*18
5
6
T=
6
*18
4608T[s]
Note: *18. Not that the high/low states of these pins are determined by the "set key scan output port/general-purpose
output port state" instruction, and that key scan output signals are not output from pins that are set to low.
(2) In normal mode
• The pins KS1 to KS6 are set to high or low with the "set key scan output port/general-purpose output port state"
instruction.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, a key scan is started
and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether
multiple key data bits are set.
• If a key is pressed for longer than 4800T(s) (Where T=1/fosc, T=1/fCK) the LC75818PT outputs a key data
read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75818PT
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between
1kΩ and 10kΩ).
Key input 1
Key input 2
Key scan
4800T[s]
4800T[s]
4800T[s]
CE
Serial data transfer Serial data transfer Key address
(43H)
Serial data transfer
Key address
Key address
DI
DO
Key data read
Key data read request
Key data read
Key data read request
Key data read
Key data read request
T=
1
fosc
T=
1
fCK
No.A0964-21/43
LC75818PT
(3) In sleep mode
• The pins KS1 to KS6 are set to high or low with the "set key scan output port/general-purpose output port state"
instruction.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed in the RC oscillator
operating mode, the oscillator on the OSC pin is started (the IC starts receiving the external clock in external clock
operating mode) and a key scan is performed . Keys are scanned until all keys released. Multiple key presses are
recognized by determining whether multiple key data bits are set.
• If a key is pressed for longer than 4800T(s) (Where T=1/fosc, T=1/fCK) the LC75818PT outputs a key data
read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75818PT
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1kΩ and 10kΩ).
• Sleep mode key scan example
Example: When a "display on/off control (SP=1)" instruction and a "set key scan output port/general-purpose
output port state (KC1 to KC5= 0, KC6=1)" instruction are executed. (i.e. sleep mode with only KS6 high.)
“L” KS1
“L” KS2
“L” KS3
When any one of these keys is pressed in RC
oscillator operating mode, the oscillator on the OSC
pin is started (the IC starts receiving the external
clock in external clock operating mode) and the keys
are scanned.
“L” KS4
“L” KS5
“H” KS6
*19
KI1
KI2
KI3
KI4
KI5
Note: *19. These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state
with only KS6 high, as in the above example.
That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal
when keys on the KS1 to KS5 lines are pressed at the same time.
Key input
(KS6 line)
Key scan
4800T[s]
4800T[s]
CE
Serial data transfer
Serial data transfer Key address Serial data transfer Key address
(43H)
DI
T=
1
fosc
T=
1
fCK
DO
Key data read
Key data read request
Key data read
Key data read request
Multiple Key Presses
Although the LC75818PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed.
Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of
three or more keys should check the key data for three or more 1 bits and ignore such data.
No.A0964-22/43
LC75818PT
1/8 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
COM1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
COM2
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
COM8
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when all
LCD segments
corresponding to COM1 to
COM8 are turned off
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
VLCD1
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
VLCD1
VLCD2
VLCD3
LCD driver output when all
LCD segments
corresponding to COM1 to
COM8 are turned on
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD4
VLCD0
VLCD2
VLCD3
VLCD4
T8
8
T8
T8=
1
f8
f
When a "set display technique" instruction with FC = 0 is executed: f8 = fosc , f8 = CK
3072
3072
fCK
fosc
When a "set display technique" instruction with FC = 1 is executed: f8 =
, f8 =
1536
1536
No.A0964-23/43
LC75818PT
1/9 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
COM1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
COM2
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM9
VLCD3
VLCD4
VLCD0
LCD driver output when all
LCD segments
corresponding to COM1 to
COM9 are turned off
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when all
LCD segments
corresponding to COM1 to
COM9 are turned on
VLCD1
VLCD2
VLCD3
VLCD4
T9
9
T9
T9=
1
f9
f9 = fosc , f9 =
3456
fosc
When a "set display technique" instruction with FC = 1 is executed: f9 =
,f9 =
1728
When a "set display technique" instruction with FC = 0 is executed:
fCK
3456
fCK
1728
No.A0964-24/43
LC75818PT
1/10 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
COM1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
COM2
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
COM10
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when all
LCD segments
corresponding to COM1 to
COM10 are turned off
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when all
LCD segments
corresponding to COM1 to
COM10 are turned on
VLCD1
VLCD2
VLCD3
VLCD4
T10
10
T10
T10=
1
f10
f
When a "set display technique" instruction with FC = 0 is executed: f10 = fosc , f10 = CK
3840
3840
fCK
fosc
When a "set display technique" instruction with FC = 1 is executed: f10 =
, f10 =
1920
1920
No.A0964-25/43
LC75818PT
Clock Signal Output Waveform
P4
Tc/2
Tc=
1
fc
Tc
"Set Key Scan Output Port/
General-purpose Port State"
Instruction Data
General-purpose port P4
clock signal frequency
fc (1/Tc) [Hz]
PC40
PC41
0
1
Clock signal output (fosc/2, fCK/2)
1
1
Clock signal output (fosc/8, fCK/8)
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the
voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection
voltage VDET,which is 2.2V, typical. To assure that this function operates reliably, a capacitor must be added to the
logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power
is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1ms.
(See Figure 5.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 5.)
• Power on: Logic block power supply(VDD) on → LCD driver block power supply (VLCD) on
• Power off: LCD driver block power supply(VLCD) off → Logic block power supply (VDD) off
When 5V signal is applied to the CE, CL, DI, and INH pins which are to be connected to the controller and if the
logic block power supply (VDD) is off, set the input voltage at the CE, CL, DI, and INH pins to 0V and apply the 5V
signal to these pins after turning on the logic block power supply (VDD).
System Reset
1. Reset function
The LC75818PT performs a system reset with the VDET. When a system reset is applied, the display is turned off,
key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level
(VSS).
These states that are created as a result of the system reset can be cleared by executing the instruction described below.
(See Figure 5.)
• Clearing the display off state
Display operation can be enabled by executing a “display on/off control” instruction. However, since the contents of
the DCRAM, ADRAM, and CGRAM are undefined, applications must set the contents of these memories before
turning on display with the “display on/off control” instruction. That is, applications must execute the following
instructions.
• Set display technique (The "set display technique" instruction must be executed first.)
• DCRAM data write
• ADRAM data write (If the ADRAM is used.)
• CGRAM data write (If the CGRAM is used.)
• Set AC address
• Set display contrast (If the display contrast adjustment circuit is used.)
After executing the above instructions, applications must turn on the display with a “display on/off control”
instruction.
Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off
control” instruction or the INH pin.
No.A0964-26/43
LC75818PT
• Clearing the key scan disable and key data reset states
By executing the following instructions not only create a state in which key scanning can be performed, but also clear
the key data reset.
• "Set display technique" (The "set display technique" instruction must be executed first.)
• "Set key scan output port / general-purpose output port state"
• Clearing the general-purpose output ports locked at the low level (VSS) state
By executing the following instructions clear the general-purpose output ports locked at the low level (VSS) state and
set the states of the general-purpose output ports.
• "Set display technique" (The "set display technique" instruction must be executed first.)
• "Set key scan output port / general-purpose output port state"
t3 t4
t1 t2
VDD
VDET
VDET
VLCD
Instruction
execution
Key scan
Initial state settings
Disabled
General-purpose
Fixed at the low level (VSS)
output ports
Display state
Execution enabled
Can be set to such states as high (VDD), or low (VSS) level
Display off
"Set display technique" and
“Set key scan output port/
general-purpose output port
state” instruction execution
Display on
“Display on/off control”
instruction execution
(Turning the display on)
Display off
”Display on/off control“
instruction execution
(Turning the display off)
• t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
• t2 ≥ 0
• t3 ≥ 0
• t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
• Initial state settings
Set display technique (The "set display technique" instruction must be executed first.)
DCRAM data write
ADRAM data write (If the ADRAM is used.)
CGRAM data write (If the CGRAM is used.)
Set AC address
Set display contrast (If the display contrast adjustment circuit is used.)
[Figure 5]
No.A0964-27/43
LC75818PT
2. Block states during a system reset
(1) CLOCK GENERATOR,TIMING GENERATOR
When a reset is applied, these circuits are forcibly initialized internally. Then, when the "set display technique"
instruction is executed, oscillation of the OSC pin starts in RC oscillator operating mode (the IC starts receiving
the external clock in external clock operating mode), execution of the instruction is enabled.
(2) INSTRUCTION REGISTER, INSTRUCTION DECODER
When a reset is applied, these circuits are forcibly initialized internally. Then, when instruction execution starts,
the IC operates according to those instructions.
(3) ADDRESS REGISTER, ADDRESS COUNTER
When a reset is applied, these circuits are forcibly initialized internally. Then, the DCRAM and the ADRAM
addresses are set when “Set AC address” instruction is executed.
(4) DCRAM, ADRAM, CGRAM
Since the contents of the DCRAM, ADRAM, and CGRAM become undefined during a reset, applications must
execute “DCRAM data write”, “ADRAM data write (If the ADRAM is used.)”, and “CGRAM data write (If the
CGRAM is used.)” instructions before executing a “display on/off control” instruction.
(5) CGROM
Character patterns are stored in this ROM.
(6) LATCH
Although the value of the data in the latch is undefined during a reset, the ADRAM, CGROM, and CGRAM data
is stored by executing a “display on/off control” instruction.
(7) COMMON DRIVER, SEGMENT DRIVER
These circuits are forced to the display off state when a reset is applied.
(8) CONTRAST ADJUSTER
Display contrast adjustment circuit operation is disabled when a reset is applied. After that, the display contrast
can be set by executing a “set display contrast” instruction.
(9) KEY SCAN, KEY BUFFER
When a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also,
the key data is all set to 0. After that, key scanning can be performed by executing a "set key scan output
port/general-purpose output port state" instruction.
(10) GENERAL PORT
When a reset is applied, the general-purpose output port state is locked at the low level (VSS).
(11) CCB INTERFACE, SHIFT REGISTER
These circuits go to the serial data input wait state.
No.A0964-28/43
GENERAL
PORT
S1
S78
S79
S80
COM10
COM1
P4
P2
P3
P1
LC75818PT
COMMON
DRIVER
SEGMENT DRIVER
LATCH
INSTRUCTION
DECODER
ADRAM
80
bits
INSTRUCTION
REGISTER
ADDRESS
COUNTER
VLCD
CONTRAST
ADJUSTER
VLCD0
CGRAM
5×9×16
bits
CGROM
5×9×240
bits
DCRAM
64×8
bits
VLCD1
ADDRESS
REGISTER
VLCD2
VLCD3
VLCD4
SHIFT REGISTER
CCB INTERFACE
VDD
KEY BUFFER
TIMING
GENERATOR
VDET
VSS
CLOCK
GENERATOR
KS1
KS3
KS2
KS4
KS5
KS6
KI3
KI2
KI1
KI4
KI5
CE
CL
DI
DO
KEY SCAN
INH
OSC
TEST
Blocks that are reset
(3) Output pin states during the reset period
Output pin
State during reset
S1 to S80
L (VLCD4)
COM1 to COM10
KS1 to KS6
L (VLCD4)
L (VSS)
P1 to P4
L (VSS)
D0
H
*20
Note: *20. Since this output pin is an open-drain output, a pull-up resistor (between 1kΩ and 10kΩ) is required. This
pin is held at the high level even if a key data read operation is performed before executing the "set display
technique" or "set key scan output port/general-purpose output port state" instruction.
No.A0964-29/43
LC75818PT
OSC Pin Peripheral Circuit
(1) RC oscillator operating mode (when the "set display technique (OC=0)" instruction is executed)
When RC oscillator operating mode is selected, an external resistor Rosc and an external capacitor Cosc must be
connected between the OSC pin and GND.
OSC
Rosc
Cosc
(2) External clock operating mode (when the "set display technique (OC=1)" instruction is executed)
When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to
the maximum allowable current value at the external clock output pin. Also make sure that the waveform of the
external clock is not heavily distorted.
External clock output pin
Rg
OSC
External oscillator
Note: *21. Allowable current value at external clock output pin >
VDD
Rg
Note when applying a 5V signal to the CE, CL, DI, and INH pins
When applying a 5V signal to the CE, CL, DI, and INH pins which are to be connected to the controller, set the input
voltage to the CE, CL, DI, and INH pins to 0V if the logic block power supply (VDD) is off, and apply the 5V signal to
those pins after turning on the logic block power supply (VDD).
No.A0964-30/43
LC75818PT
Sample Application Circuit 1
1/8 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
VDD
+3.3V
COM1
*22
COM2
COM3
COM4
COM5
COM6
COM7
COM8
TEST
VSS
VLCD
+8V
OPEN
VLCD0
VLCD1
VLCD2
C
C
C
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
VLCD4 *23
C≥0.047μF
OSC *24
*27
From the
controller
To the controller
To the controller
power supply
*26
INH *25
CE
CL
DI
DO
KKKKK
I I I I I
5 4 3 2 1
S76
S77
S78
S79
S80
KKKKKK
SSSSSS
6 5 4 3 2 1
P1
P2
P3
P4
General-purpose output ports
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise
time when power is applied and the logic block power supply voltage VDD fall time when power drops are
both at least 1 ms, as the LC75818PT is reset by the VDET.
*23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
*24. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be
connected between the OSC pin and ground. When selecting the external clock operating mode, connect a
current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external
oscillator). (See the “OSC Pin Peripheral Circuit” section.)
*25. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*27 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block
power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power
supply (VDD).
No.A0964-31/43
LC75818PT
Sample Application Circuit 2
1/8 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
VDD
+3.3V
COM1
*22
TEST
VSS
COM2
COM3
COM4
COM5
COM6
COM7
COM8
VLCD
+8V
R
R
R
C
C
C
R
C≥0.047μF
10kΩ≥R≥2.2kΩ
VLCD0
VLCD1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD2
VLCD3
VLCD4 *23
OSC *24
*27
From the controller
To the controller
To the controller
power supply
*26
INH *25
CE
CL
DI
DO
KK K KK
I I I I I
54 3 21
S76
S77
S78
S79
S80
General-purpose output ports
KKKKKK
SSSSSS
6 5 4 3 2 1
P1
P2
P3
P4
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise
time when power is applied and the logic block power supply voltage VDD fall time when power drops are
both at least 1 ms, as the LC75818PT is reset by the VDET.
*23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
*24. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be
connected between the OSC pin and ground. When selecting the external clock operating mode, connect a
current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external
oscillator). (See the “OSC Pin Peripheral Circuit” section.)
*25. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*27 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block
power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power
supply (VDD).
No.A0964-32/43
LC75818PT
Sample Application Circuit 3
1/9 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
VDD
+3.3V
*22
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
TEST
VSS
VLCD
+8V
OPEN
VLCD0
VLCD1
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
C
C
C
VLCD4 *23
C≥0.047μF
OSC *24
*27
From the controller
To the controller
To the controller
power supply
*26
INH *25
CE
CL
DI
DO
KKK KK
I I I I I
5 4 3 21
S76
S77
S78
S79
S80
K KKK KK
S SSS SS
6 5 4 3 21
P1
P2
P3
P4
General-purpose output ports
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise
time when power is applied and the logic block power supply voltage VDD fall time when power drops are
both at least 1 ms, as the LC75818PT is reset by the VDET.
*23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
*24. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be
connected between the OSC pin and ground. When selecting the external clock operating mode, connect a
current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external
oscillator). (See the “OSC Pin Peripheral Circuit” section.)
*25. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*27 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block
power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power
supply (VDD).
No.A0964-33/43
LC75818PT
Sample Application Circuit 4
1/9 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
VDD
+3.3V
*22
COM1
TEST
VSS
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
VLCD
+8V
VLCD0
R
R
R
C
C
C
R
C≥0.047μF
10kΩ≥R≥2.2kΩ
VLCD1
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
VLCD4 *23
OSC *24
*27
From the controller
To the controller
To the controller
power supply
*26
INH *25
CE
CL
DI
DO
KKKKK
I I I I I
5 4 3 21
S76
S77
S78
S79
S80
KKK KKK
SSS SSS
6 5 4 3 2 1
P1
P2
P3
P4
General-purpose output ports
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise
time when power is applied and the logic block power supply voltage VDD fall time when power drops are
both at least 1 ms, as the LC75818PT is reset by the VDET.
*23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
*24. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be
connected between the OSC pin and ground. When selecting the external clock operating mode, connect a
current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external
oscillator). (See the “OSC Pin Peripheral Circuit” section.)
*25. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*27 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block
power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power
supply (VDD).
No.A0964-34/43
LC75818PT
Sample Application Circuit 5
1/10 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
VDD
+3.3V
COM1
*22
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
VSS
VLCD
+8V
OPEN
VLCD0
VLCD1
VLCD2
C
C
VLCD3
C
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD4 *23
C≥0.047μF
OSC *24
*27
From the controller
To the controller
To the controller
power supply
*26
INH *25
CE
CL
DI
DO
K K KKK
I I I I I
5 4 3 21
S76
S77
S78
S79
S80
KKK KKK
SSS SSS
6 5 4 3 21
P1
P2
P3
P4
General-purpose output ports
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise
time when power is applied and the logic block power supply voltage VDD fall time when power drops are
both at least 1 ms, as the LC75818PT is reset by the VDET.
*23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
*24. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be
connected between the OSC pin and ground. When selecting the external clock operating mode, connect a
current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external
oscillator). (See the “OSC Pin Peripheral Circuit” section.)
*25. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*27 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block
power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power
supply (VDD).
No.A0964-35/43
LC75818PT
Sample Application Circuit 6
1/10 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
VDD
+3.3V
COM1
*22
TEST
VSS
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
VLCD
+8V
VLCD0
R
R
R
C
C
C
R
C≥0.047μF
10kΩ≥R≥2.2kΩ
VLCD1
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
VLCD4 *23
OSC *24
*27
From the controller
To the controller
To the controller
power supply
*26
INH *25
CE
CL
DI
DO
KK K KK
I I I I I
5 4 3 21
S76
S77
S78
S79
S80
K KK K KK
S SS S SS
6 54 3 21
P1
P2
P3
P4
General-purpose output ports
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Note *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise
time when power is applied and the logic block power supply voltage VDD fall time when power drops are
both at least 1 ms, as the LC75818PT is reset by the VDET.
*23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
*24. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be
connected between the OSC pin and ground. When selecting the external clock operating mode, connect a
current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external
oscillator). (See the “OSC Pin Peripheral Circuit” section.)
*25. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*26. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and
10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
*27 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block
power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power
supply (VDD).
No.A0964-36/43
LC75818PT
Sample Correspondence between Instructions and the Display (When the LC75818PT-8560 is used)
LSB
No.
Instruction (hexadecimal)
D44 to
D48 to
D52 to
D56 to
D60 to
D43
D47
D51
D55
D59
D63
Power application
(Initialization with the VDET)
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Sets to 1/8 duty 1/4 bias display drive
8
DCRAM data write (increment mode)
2
0
0
1
3
4
2
0
address 10H
Writes the display data “8” to DCRAM
3
DCRAM data write (increment mode)
2
address 0FH
Writes the display data “1” to DCRAM
3
DCRAM data write (increment mode)
8
address 0EH
Writes the display data “8” to DCRAM
3
DCRAM data write (increment mode)
1
address 0DH
Writes the display data “5” to DCRAM
3
DCRAM data write (increment mode)
8
address 0CH
Writes the display data “7” to DCRAM
3
DCRAM data write (increment mode)
5
address 0BH
Writes the display data “C” to DCRAM
4
DCRAM data write (increment mode)
7
address 0AH
Writes the display data “L” to DCRAM
4
DCRAM data write (increment mode)
3
address 09H
Writes the display data “ ” to DCRAM
DCRAM data write (increment mode)
C
address 08H
Writes the display data “I” to DCRAM
4
DCRAM data write (increment mode)
0
address 07H
Writes the display data “S” to DCRAM
5
DCRAM data write (increment mode)
9
address 06H
Writes the display data “L” to DCRAM
4
DCRAM data write (increment mode)
3
address 05H
Writes the display data “ ” to DCRAM
2
DCRAM data write (increment mode)
C
address 04H
Writes the display data “O” to DCRAM
4
DCRAM data write (increment mode)
0
address 03H
Writes the display data “Y” to DCRAM
5
DCRAM data write (increment mode)
F
address 02H
Writes the display data “N” to DCRAM
4
DCRAM data write (increment mode)
9
address 01H
Writes the display data “A” to DCRAM
DCRAM data write (increment mode)
E
address 00H
Writes the display data “S” to DCRAM
5
DCRAM data write (increment mode)
1
technique
Writes the display data “ ” to DCRAM
A
DCRAM data write (increment mode)
0
Operation
The display is in the off state.
0
0
Display
Initializes the IC.
Set display technique
2
3
MSB
D40 to
address 11H
Writes the display data “ ” to DCRAM
A
address 12H
Continued on next page.
No.A0964-37/43
LC75818PT
Continued from preceding page.
LSB
No.
Instruction (hexadecimal)
D44 to
D48 to
D52 to
D56 to
D60 to
D43
D47
D51
D55
D59
D63
0
2
1
4
1
C
1
C
1
C
1
C
1
C
1
C
8
4
1
4
0
2
0
F
F
Display shift
Display shift
26
Display shift
27
Display shift
28
Display shift
29
32
F
ADRAM address 0H into AC
SANYO LSI LC758
Turns on the LCD for all digits (16 digits) in
SANYO LSI LC7581
Shifts the display (MDATA only) to the left
ANYO LSI LC75818
Shifts the display (MDATA only) to the left
NYO LSI LC75818
Shifts the display (MDATA only) to the left
YO LSI LC75818
Shifts the display (MDATA only) to the left
O LSI LC75818
Shifts the display (MDATA only) to the left
LSI LC75818
Shifts the display (MDATA only) to the left
Display on/off control
0
0
F
F
0
0
F
Set AC address
0
0
MDATA
Set to sleep mode, turns off the LCD for all
Display on/off control
F
Operation
Loads the DCRAM address 00H and the
Display shift
25
31
0
Display on/off control
F
24
30
Display
Set AC address
22
23
MSB
D40 to
digits
LSI LC75818
Turns on the LCD for all digits (16 digits) in
SANYO LSI LC758
Loads the DCRAM address 00H and the
MDATA
ADRAM address 0H into AC
Note: *28. This sample above assumes the use of 16 digits 5×7 dot matrix LCD. CGRAM and ADRAM are not used.
No.A0964-38/43
LC75818PT
Notes on the controller key data read techniques
1. Timer based key data acquisition
• Flowchart
CE=”L”
NO
DO=”L”
YES
Key data read
processing
• Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
DI
t8
Key
address
t7
t8
Key data read
t8
t7
t7
DO
Key data read request
t9
Controller
determination
(Key on)
t9
Controller
determination
(Key on)
t9
Controller
determination
(Key off)
t9
Controller
determination
(Key on)
Controller
Determination
(Key off)
t5: Key scan execution time when the key data agreed for two key scans. (4800T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was
executed again. (9600T(s))
1
1
t7: Key address (43H) transfer time
T=
T=
fCK
fosc
t8: Key data read time
• Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller
must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a
key has been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No.A0964-39/43
LC75818PT
2. Interrupt based key data acquisition
• Flowchart
CE=”L”
NO
DO=”L”
YES
Key data read
processing
Wait for at least t10
CE=”L”
NO
DO=”H”
YES
Key OFF
• Timing chart
Key on
Key on
Key input
Key scan
t5
t5
CE
DI
t8
t8
Key
address
t7
t5
t6
Key data read
t8
t7
t8
t7
t7
DO
Key data read request
t10
Controller
determination
(Key on)
Controller
determination
(Key off)
t10
Controller
determination
(Key on)
Controller
determination
(Key on)
t10
Controller
determination
(Key on)
t10
Controller
determination
(Key off)
t5: Key scan execution time when the key data agreed for two key scans. (4800T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was
executed again. (9600T(s))
1
1
t7: Key address (43H) transfer time
T=
T=
fCK
fosc
t8: Key data read time
No.A0964-40/43
LC75818PT
• Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10
has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique
must satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No.A0964-41/43
Upper
4BIT
=
>
(9)
(10)
(11)
(12)
(13)
(14)
(15)
1000
1001
1010
1011
1100
1101
1110
(16)
<
'
(8)
0111
1111
;
&
(7)
0110
/
.
,
*
7
%
(6)
0101
)
6
$
(5)
0100
(
3
#
(4)
0011
?
:
9
8
5
4
2
1
0
0011
(3)
!
0010
0010
0001
(2)
MSB
0000
CG
RAM(1)
0001
0000
LSB
Lower
4BIT
LC75818PT-8560 Character Font (Standard)
Ù
Ú
Ò
Ó
Ì
Í
È
É
À
Á
1110
O
_
o
IJ
ij
i
e
£
n
n
I
n
N
o
å
õ
ã
Ü
Û
Ö
Ô
Ï
Î
Ë
Ê
Ä
Â
1111
a
G
m
M
g
Å
s
S
l
K
L
]
1101
Ã
1100
ñ
1011
Õ
Ñ
1010
ç
z
ü
ù
y
i
j
û
ö
ô
ï
ú
ò
ó
ì
î
í
ê
é
ë
ä
à
è
â
1001
á
1000
x
w
v
u
t
s
r
q
p
0111
h
g
f
e
d
c
b
a
0110
Ç
[
Z
Y
X
W
V
U
T
S
R
Q
P
0101
k
J
I
H
G
F
E
D
C
B
A
@
0100
LC75818PT
No.A0964-42/43
LC75818PT
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.A0964-43/43
Similar pages