NCP81255 D

NCP81255
Single‐Phase Voltage
Regulator with Intel
Proprietary Interface for
Computing Applications
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The NCP81255 is a high-performance, low-bias current,
single-phase regulator with integrated power MOSFETs intended to
support a wide range of computing applications. The device is able to
deliver up to 14 A TDC output current on an adjustable output with
Intel proprietary interface interface. Operating in high switching
frequency up to 1.2 MHz allows employing small size inductor and
capacitors. The controller makes use of ON Semiconductor’s patented
high performance RPM operation. RPM control maximizes transient
response while allowing for smooth transitions between
discontinuous-frequency-scaling operation and continuous-mode
full-power operation. The NCP81255 has an ultra-low offset current
monitor amplifier with programmable offset compensation for
high-accuracy current monitoring.
1 40
QFN40
CASE 485DY
MARKING DIAGRAM
1
NCP81255
FAWLYYWW
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Auto DCM Operation in High Current Power States
High Performance RPM Control System
IMVP8 Intel proprietary interface Support
Ultra Low Offset IOUT Monitor
Dynamic VID Feed-Forward
Programmable Droop Gain
Zero Droop Capable
Supports IMVP8 Intel proprietary interface Addresses
PSYS Input Monitor
Thermal Monitor
UltraSonic Operation
Digitally Controlled Operating Frequency
QFN40 5 mm × 5 mm Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
NCP81255
F
A
WL
YY
WW
G
= Specific Device Code
= Wafer Fab
= Assembly Location
= Lot ID
= Year
= Work Week
= Pb-Free Package
ORDERING INFORMATION
Device
NCP81255MNTXG
Package
Shipping†
QFN40 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• IMVP8 Rail1, Rail3, and Rail4
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 1
1
Publication Order Number:
NCP81255/D
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2
CFF
RFF
RCS
VSP
CCS
−gm
Intel
proprietary
interface
Control
GND
DAC
VSN
R_OFFSET_ADJ
CS_SENSE
SWN
ALERT#
SCLK
SDIO
VR_HOT#
VR_RDY
VSS_SENSE
Rdroop_adj
CSN
NTC
CSP
−gm
COMP
OFFSET
Bias Current
Generator
VSP
TSENSE
PSYS
ICCMAX
ADDR
VBOOT
OCP
VREF
Ilimit_adj
Iout_adj
IOUT
ADC
RPM Trigger & PWM
Control Functions
VCC
PVCC
DOSC
VCC_SENSE
Comp
Clamp
EN
RPM
Generator
UVLO
Gate
Driver
PWM
OVP
UVP
Monitor
−
Figure 1. Block Diagram
+
C_Fit
VFF
(Input Voltage Feed-Forward)
ZCD Comparator
for PS2 Operation
PGND
BG
SWN
TG
VBST
PVCC
VIN
CS_SENSE
NCP81255
NCP81255
+5 V
+5 V
VCC
SKT_SNS+
VSP
GND
SKT_SNS−
VSN
PVCC
COMP
VIN
EN
VIN
ILIM
IOUT
BST
HG
TSENSE
VCC_Rail4
VPU
NTC
SW
LG
PGND
NTC
VRHOT
VPU
VPU
CSP
CSN
SDIO
ALERT
ROSC
SCLK
Batt chrgr
PSYS
IMAX
ADDR
VIN
VRRDY
SLEW
VRMP
VBOOT
NCP81255
Figure 2. Simplified Application Schematic
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3
EN
VCC
IOUT
CSP
CSN
ILIM
COMP
VSN
VSP
PSYS
39
38
37
36
35
34
33
32
31
20
10
PGND
SW
19
9
43
PGND
PGND
GH
42
VIN
18
8
PGND
BST
17
7
PGND
VIN
44
GL
16
6
PGND
VR_RDY
15
5
PGND
PGND
NCP81255
14
4
VIN
SCLK
13
3
VIN
ALERT
41 GND
12
2
VIN
SDIO
11
1
VIN
VR_HOT#
49
NCP81255
30
DOSC/ADDR/VBOOT
29
TSENSE
28
IMAC
27
PVCC
26
PGND
25
GL
24
GL
23
SW
22
SW
21
SW
Figure 3. Pin Configuration
Table 1. NCP81255 PIN DESCRIPTIONS
Pin No.
Symbol
1
VR_HOT#
2
SDIO
3
ALERT#
Description
Thermal Logic Output for Over-Temperature Condition on either TSENSE
Serial VID Data Interface
Serial VID ALERT#
4
SCLK
Serial VID Clock
5
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
6
VR_RDY
7
VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
8
BST
Provides Bootstrap Voltage for the HS Gate Driver. A Cap is Required from this Pin to SW
9
GH
Gate of HS FET
10
SW
Switching Node. Provides a Return Path for the Integrated HS Driver. Internally Connected to the
Source of the HS FET
11
VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
12
VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
13
VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
14
VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
15
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
16
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
17
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
18
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
VR_RDY Indicates the Controller is Ready to Accept Intel proprietary interface Commands
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4
NCP81255
Table 1. NCP81255 PIN DESCRIPTIONS (continued)
Pin No.
Symbol
Description
19
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
20
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
21
SW
Switch Node. Pins to be Connected to an External Inductor. These Pins are Interconnection
between Internal HS and LS FETs
22
SW
Switch Node. Pins to be Connected to an External Inductor. These Pins are Interconnection
between Internal HS and LS FETs
23
SW
Switch Node. Pins to be Connected to an External Inductor. These Pins are Interconnection
between Internal HS and LS FETs
24
GL
Gate of LS FET
25
GL
Gate of LS FET
26
PGND
Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
27
PVCC
Voltage Supply of Gate Drivers. A 4.7 mF or Larger Ceramic Capacitor Bypasses this Input to GND,
Placed as Close to the Pin as Possible
28
IMAX
ICCMAX Register Program
29
TSENSE
30
DOSC/ADDR/
VBOOT
External Temperature Sense Network is Connected to this Pin
31
PSYS
32
VSP
Differential Output Voltage Sense Positive
33
VSN
Differential Output Voltage Sense Negative
34
COMP
Programming for FSW, Intel proprietary interface Address, and VBOOT. A Resistor to GND Programs
these Values during Start-up, per Look-up Table
System Power Signal Input. A Resistor to Ground Scales this Signal
Compensation
35
ILIM
Current-Limit Program
36
CSN
Differential Current Sense Negative
37
CSP
Differential Current Sense Positive
38
IOUT
IOUT Gain Program
39
VCC
Power Supply Input Pin of Control Circuits. A 1 mF or Larger Ceramic Capacitor Bypasses this Input
to Ground, Placed Close to the Controller
40
EN
41
GND
Flag. Analog Ground. Ground of Internal Control Circuits
42
VIN
Flag. Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to
Power Ground. Place Close to Pins
43
PGND
44
GL
Enable
Flag. Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET.
Flag. Gate of LS FET
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NCP81255
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Power Supply Voltage to PGND
VVIN
−
30
V
Switch Node to PGND
VSW
−
30
V
Analog Supply Voltage to GND
VCC, VCCP
−0.3
6.5
V
BST_PGND
−0.3
33
38 (< 50 ns)
V
BST to SW
BST_SW
−0.3
6.5
V
GH to SW
GH
−0.3
−2 (< 200 ns)
BST + 0.3
V
GL to GND
GL
−0.3
−2 (< 200 ns)
VCCP + 0.3
V
VSN
−0.3
0.3
V
IOUT
IOUT
−0.3
2.5
V
PGND to GND
PGND
−0.3
0.3
V
−0.3
VCC + 0.3
BST to PGND
VSN to GND
Other Pins
Latch Up Current: (Note 1)
All Pins, Except Digital Pins
Digital Pins
ILU
Operating Junction Temperature Range
Operating Ambient Temperature Range
V
mA
−100
−10
100
10
TJ
−40
125
°C
TA
−40
100
°C
Storage Temperature Range
TSTG
−40
Thermal Resistance Junction to Board (Note 2)
RqJB
8.2
°C/W
Thermal Resistance Junction to Ambient (Note 2)
RqJA
21.8
°C/W
PD
4.59
W
Moisture Sensitivity Level (Note 4)
MSL
3
−
ESD Human Body Model
HBM
2,000
V
ESD Machine Model
MM
200
V
CDM
1,000
V
Power Dissipation at TA = 25°C (Note 3)
ESD Charged Device Model
150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latch up Current per JEDEC standard: JESD78 Class II.
2. The thermal resistance values are dependent on the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4-layer FR−4 PCB board, which as two, 1-ounce copper internal power and ground planes and 2-ounce
copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors, etc.)
3. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on TJMAX = 125°C and RqJA = 21.8°C/W.
4. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC Standard: J−STD−020D.1.
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NCP81255
Table 3. ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Test Conditions
Min
Typ
Max
Unit
EN = High
−
10
12
mA
EN = Low
−
20
40
mA
PS3
−
−
10
mA
PS4
−
−
200
mA
VCC Rising
−
−
4.5
V
VCC Falling
4
−
−
V
Parameter
BIAS SUPPLY
VCC Quiescent Current
VCC UVLO Threshold
VCC UVLO Hysteresis
VIN UVLO Threshold
−
275
−
mV
VIN Rising
−
−
4.25
V
VIN Falling
3
−
−
V
−
680
−
mV
VIN UVLO Hysteresis
ENABLE INPUT
Enable High Input Leakage Current
Enable = 0
−1.0
0
1.0
mA
Upper Threshold
VUPPER
0.8
−
−
V
Lower Threshold
VLOWER
−
−
0.3
V
−
300
−
mV
−
−
2.5
ms
Soft Start Slew Rate
−
1/2 SR Fast
−
mv/ms
Slew Rate Slow
−
1/2 SR Fast
−
mv/ms
Slew Rate Fast
−
30
−
mv/ms
600
−
1,200
KHz
−10
−
10
%
Voltage Range
0
−
2
V
Total Unadjusted Error (TUE)
−1
−
+1
%
−
−
1
LSB
Power Supply Sensitivity
−
±1
−
%
Conversion Time
−
6
−
ms
Round Robin
−
55
−
ms
−
−
0.3
V
−1.0
−
1.0
mA
Alert# Assert Threshold
−
491
−
mV
Alert# De-Assert Threshold
−
513
−
mV
VRHOT Assert Threshold
−
472
−
mV
−
494
−
mV
116
120
124
mA
Enable Hysteresis
Enable Delay Time
Measure Time from Enable Transitioning
HI to VR_RDY High
DAC SLEW RATE
OSCILLATOR
Switching Frequency Range
Switching Frequency Accuracy
600 KHz < FSW < 1.2 MHz
ADC
Differential Non-Linearity (DNL)
8-Bit
VR_HOT#
Output Low Voltage
Output Leakage Current
High Impedance State
TSENSE
VRHOT Rising Threshold
TSENSE Bias Current
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NCP81255
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
VR_RDY_OUTPUT
Output Low Saturation Voltage
IVR_RDY = 4 mA,
−
−
0.3
V
Rise Time
External Pull-Up of 1 kW to 3.3 V,
CTOT = 45 pF, DVo = 10% to 90%
−
−
150
ns
Fall Time
External Pull-Up of 1 kW to 3.3 V,
CTOT = 45 pF, DVo = 90% to 10%
−
−
150
ns
Output Voltage at Power-Up
VRRDY Pulled Up to 5 V via 2 kW
−
−
1.2
V
Output Leakage Current When High
VRRDY = 5.0 V
−1.0
−
1.0
mA
VRRDY Delay (Falling)
From OCP
−
0
−
ms
VRRDY Delay (Falling)
From OVP
−
0.3
−
ms
−1
−
1
mA
−0.3
−
3.0
V
DIFFERENTIAL VOLTAGE SENSE AMPLIFIER
Input Bias Current
VSP Input Voltage Range
VSN Input Voltage Range
−0.3
−
0.3
V
1.33
1.6
1.86
mS
Load = 1 nF in Series with 1 kW in Parallel
with 10 pF to Ground
70
73
−
dB
Source Current
Input Differential −200 mV
−
280
−
mA
Sink Current
Input Differential 200 mV
−
280
−
mA
−3dB Bandwidth
Load = 1 nF in Series with 1 kW in Parallel
with 10 pF to Ground
−
15
−
MHz
gm
VSP = 1.2 V
Open loop Gain
IOUT
Analog Gain Accuracy
−3
−
+3
%
gm
0.95
1.0
1.05
mS
IOUT Output Accuracy
−140
−
140
nA
0
−
2.0
V
−
−
1
LSB
360
−
440
mV
−
2
−
V
ADC Voltage Range
ADC Differential Nonlinearity (DNL)
Highest 8-Bits
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold
VSP−VSN−VID Setting
Over Voltage Max Capability
Over Voltage Delay
VSP Rising to PWMx Low
−
400
−
ns
Over Voltage VR_RDY Delay
VSP Rising to VR_RDY Low
−
400
−
ns
Under Voltage Threshold
VSP−VSN Falling
225
290
375
mV
Under-Voltage Hysteresis
VSP−VSN Falling/Rising
−
25
−
mV
Under-Voltage Blanking Delay
VSP−VSN Falling to VR_RDY Falling
−
5
−
ms
0.95
1.0
1.05
mS
−1
−
1
mA
−
80
−
dB
1.275
1.3
1.325
V
−
500
−
ns
−
1.0
−
mS
−1.85
−
1.85
mV
DROOP
gm
Offset Accuracy
Common Mode Rejection
CS1 Input Referred from 0.5 V to 1.2 V
OVERCURRENT PROTECTION
ILIMIT Threshold
ILIMIT Delay
ILIMIT Gain
IILIMIT/(CSP−CSN), CSP−CSN = 20 mV
CSP-CSN ZCD COMPARATOR
Offset Accuracy
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NCP81255
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Typ
Max
Unit
−1.5
−
1.5
mV
VGS = 4.5 V, ID = 10 A, RON_H
−
8.0
−
mW
VGS = 4.5 V, ID = 10 A, RON_L
−
4.0
−
mW
Pull-High Drive On Resistance
VBST – VSW = 5 V, RDRV_HH
−
1.2
2.5
W
Pull-Low Drive On Resistance
VBST – VSW = 5 V, RDRV_HL
−
0.8
2.0
W
GH Propagation Delay Time
From GL Falling to GH Rising, TGH_d
15
23
30
ns
GH Rise Time
TGH_R
−
9
15
ns
GH Fall Time
TGH_F
4
9
15
ns
GH Pull-Down Resistance
VBST – VSW = 0 V
−
292
−
kW
Pull-High Drive On Resistance
VCCP – VPGND = 5 V, RDRV_LH
−
0.9
2.5
W
Pull-Low Drive On Resistance
VCCP – VPGND = 5 V, RDRV_LL
−
0.4
1.25
W
GL Propagation Delay Time
From GH Falling to GL Rising, TGL_d
−
11
30
ns
GL Rise Time
TGL_R
6
9
15
ns
GL Fall Time
TGL_F
−
11
15
ns
RSW (Note 1)
−
2
−
kW
EN = L or EN = H and DRVL = H, Ron_BST
5
13
21
W
SWN ZCD COMPARATOR
Offset Accuracy
HIGH-SIDE MOSFET
Drain-to-Source On Resistance
LOW-SIDE MOSFET
Drain-to-Source On Resistance
HIGH-SIDE GATE DRIVE
LOW-SIDE GATE DRIVE
SW TO PGND RESISTANCE
SW to PGND Pull-Down Resistance
BOOTSTRAP RECTIFIER SWITCH
Output Low Resistance
1. Guaranteed by design, not tested in production.
2. TJ = 25°C
TGL_f
TGL_r
GL
TGH_d
GH to SW
TGH_r
TGH_f
VTH
VTH
TGL_d
SW
1V
NOTE: Timing is referenced to the 10% and the 90% points, unless otherwise stated.
Figure 4. Driver Timing Diagram
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NCP81255
Table 4. STATE TRUTH TABLE
State
VR_RDY Pin
Error AMP
Comp Pin
OVP & UVP
POR
0 < VCC < UVLO
N/A
N/A
N/A
Disabled
EN < Threshold
UVLO > Threshold
Low
Low
Disabled
Start-Up Delay & Calibration
EN > Threshold
UVLO > Threshold
Low
Low
Disabled
Soft Start
EN > Threshold
UVLO > Threshold
Low
Operational
Active/No Latch
Normal Operation
EN > Threshold
UVLO > Threshold
High
Operational
Active/Latching
Over Voltage
Low
N/A
DAC + 150 mV
Over Current
Low
Operational
Last DAC Code
Vout = 0 V
Low: if Reg34h: bit 0 = 0;
High: if Reg34h: bit 0 = 1;
Clamped at 0.9 V
Disabled
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10
Method
of Reset
N/A
NCP81255
GENERAL
Switching Frequency, Intel proprietary interface
Address, and Boot Voltage Programming
The NCP81255 is a single phase IMVP8 Intel proprietary
interface controller with a built in gate driver. The controller
makes use of a digitally enhanced high performance current
mode RPM control method that provides excellent transient
response while minimizing transient aliasing. The average
operating frequency is digitally stabilized to remove
frequency drift under all continuous mode operating
conditions. At light load the NCP81255 automatically
transitions into DCM operation to save power.
FSW, address, and VBOOT are during power up on
a single pin. A 10 mA current is sourced from the pin and the
resulting voltage is measured. This is compared with the
thresholds and the corresponding values for FSW, VBOOT,
and Intel proprietary interface address are configured. These
values are programmed on power up and cannot be changed
after the initial power up sequence is complete.
Serial VID Interface (Intel proprietary interface)
For Intel proprietary interface communication details
please contact Intel®, Inc.
Table 5. SWITCHING FREQUENCY
Resistor
FSW
Address
VBOOT
1
10 kW
1.2 MHz
0
0V
2
13 kW
1.1 MHz
0
0V
3
16 kW
1.0 MHz
0
0V
4
19.2 kW
900 kHz
0
0V
5
22.5 kW
800 kHz
0
0V
6
26 kW
700 kHz
0
0V
7
29.6 kW
600 kHz
0
0V
8
33.5 kW
1.2 MHz
1
0V
9
37.4 kW
1.1 MHz
1
0V
10
41.5 kW
1.0 MHz
1
0V
11
45.8 kW
900 kHz
1
0V
12
50.2 kW
800 kHz
1
0V
13
54.8 kW
700 kHz
1
0V
14
59.5 kW
600 kHz
1
0V
15
64.5 kW
1.2 MHz
2
1.05 V
16
69.6 kW
1.1 MHz
2
1.05 V
17
75 kW
1.0 MHz
2
1.05 V
18
80.6 kW
900 kHz
2
1.05 V
19
86.5 kW
800 kHz
2
1.05 V
92.6 kW
700 kHz
2
1.05 V
20
21
99 kW
600 kHz
2
1.05 V
22
105.5 kW
1.2 MHz
3
0V
23
112.5 kW
1.1 MHz
3
0V
24
119.6 kW
1.0 MHz
3
0V
25
127 kW
900 kHz
3
0V
26
134.8 kW
800 kHz
3
0V
27
143 kW
700 kHz
3
0V
28
151.4 kW
600 kHz
3
0V
29
160.3 kW
700kHz
0
1.05 V
30
169.5 kW
700kHz
1
1.05 V
31
180 kW
700 kHz
2
0V
32
210 kW
700 kHz
3
1.05 V
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NCP81255
I COMP + gm @ ǒV DAC * ǒV VSP * V VSNǓǓ
Remote Sense Error Amplifier
A high performance, high input impedance, true
differential transconductance amplifier is provided to
accurately sense the regulator output voltage and provide
high bandwidth transient performance. The VSP and VSN
inputs should be connected to the regulator’s output voltage
sense points through filter networks describe in the Droop
Compensation and DAC Feed-Forward Compensation
sections. The remote sense error amplifier outputs a current
proportional to the difference between the output voltage
and the DAC voltage:
This current is applied to a standard Type II compensation
network.
Single-Phase Rail Voltage Compensation
The Remote Sense Amplifier outputs a current that is
applied to a Type II compensation network formed by
external tuning components CLF, RZ and CHF
DAC
gm
(eq. 1)
+
+
S
VSN
VSN
VSP
VSP
−
COMP
RZ
CHF
CLF
Figure 5.
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12
NCP81255
Differential Current Feedback Amplifier
based on the effect of temperature on both the thermistor and
inductor. The CSP and CSN pins are high impedance inputs,
but it is recommended that the low-pass filter resistance not
exceed 10 kW in order to avoid offset due to leakage current.
It is also recommended that the voltage sense element
(inductor DCR) be no less than 0.5 mW for sufficient current
accuracy. Recommended values for the external filter
components are:
The NCP81255 controller has a low offset, differential
amplifier to sense output inductor current. An external
low-pass filter can be used to superimpose a reconstruction
of the AC inductor current onto the DC current signal sensed
across the inductor. The low-pass filter time constant should
match the inductor L/DCR time constant by setting the filter
pole frequency equal to the zero of the output inductor. This
makes the filter AC output mimic the product of AC inductor
current and DCR, with the same gain as the filter DC output.
It is best to perform fine tuning of the filter pole during
transient testing.
FZ +
FP +
[email protected]@
ǒ
DCR @ 25°C
Ǔ
@ C CSSP
V CURR +
R TH ) R CSSP
R PHSP ) R TH ) R CSSP
+
AV = 1
(eq. 4)
@ DCR
Current
Sense AMP
CSN
(eq. 5)
RCSSP
−
CCSSP
COMP
@ I OUT @ DCR
RPHSP
CSP
RAMP
R [email protected]ǒR TH)R CSSPǓ
Using 2 parallel capacitors in the low-pass filter allows
fine tuning of the pole frequency using commonly available
capacitor values.
The DC gain equation for the current sense amplifier
output is:
(eq. 3)
Forming the low-pass filter with an NTC thermistor (RTH)
placed near the output inductor, compensates both the DC
gain and the filter time constant for the inductor DCR change
with temperature. The values of RPHSP and RCSSP are set
PWM
Generator
L PHASE
R PHSP)R TH)R CSSP
R [email protected]ǒR TH)R CSSPǓ
R PHSP)R TH)R CSSP
= 7.68 kW
= 14.3 kW
= 100 kW, Beta = 4300
C CSSP +
(eq. 2)
[email protected]@L
1
RPHSP
RCSSP
RTH
t
RTH
To Inductor
CURR
PWM
Figure 6.
PSYS
The amplifier output signal is combined with the COMP
and RAMP signals at the PWM comparator inputs to
produce the Ramp Pulse Modulation (RPM) PWM signal.
The PSYS pin is an analog input to the NCP81255. It is
a system input power monitor that facilitates the monitoring
of the total platform system power. For more details about
PSYS please contact Intel, Inc.
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13
NCP81255
Load-line Programming (DROOP)
An output load-line is a power supply characteristic
wherein the regulated (DC) output voltage decreases by
a voltage VDROOP, proportional to load current. This
characteristic can reduce the output capacitance required to
maintain output voltage within limits during load transients
faster than those to which the regulation loop can respond.
+
+
VSN
VSN
VSP
VSP
In the NCP81255, a load-line is produced by adding a signal
proportional to output load current (VDROOP) to the output
voltage feedback signal – thereby satisfying the voltage
regulator at an output voltage reduced proportional to load
current. VDROOP is developed across a resistance between
the VSP pin and the output voltage sense point.
CSNSSP
S
−
RDRPSP
To VCC_SENSE
gm
RDRPSP
CDRPSP
RPHSP
CSP
+
AV = 1
Current
Sense AMP
CSN
RCSSP
−
CCSSP
t
RTH
To Inductor
Figure 7.
V DROOP + R DRPSP @ gm @
R TH ) R CSSP
R PHSP ) R TH ) R CSSP
Loadline
gm @ DCR
@
R PHSP ) R TH ) R CSSP
R TH ) R CSSP
(eq. 6)
ICC Max
The loadl-ine is programmed by choosing RDRPSP such
that the ratio of voltage produced across RDRPSP to output
current is equal to the desired load-line.
R DRPSP +
@ I OUT @ DCR
A resistor to ground on the IMAX pin programs these
registers at the time the part is enabled. 10 mA is sourced
from these pins to generate a voltage on the program resistor.
The resistor value should be no less than 10 kW.
(eq. 7)
ICC_MAX 21h +
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14
R @ 10 mA @ 255 A
2V
(eq. 8)
NCP81255
Programming IOUT
scaled with an external resistor to ground such that a load
equal to ICC_MAX generates a 2 V signal on IOUT.
A pull-up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
RPHSP
CSP
+
AV = 1
Current
Sense AMP
CSN
RCSSP
−
CCSSP
To Inductor
t
RTH
gm
IOUT
Current
Monitor
RIOUTSP
IOUT
Figure 8.
2V
R IOUTSP +
gm @
(eq. 9)
R TH)R CSSP
R PHSP)R TH)R CSSP
@ IccMax @ DCR
Programming the DAC Feed-Forward Filter
in order to compensate for the response of the Droop
function to the inductor current flowing into the charging
output capacitors. RFFSP sets the gain of the DAC
feed-forward and CFFSP provides the time constant to
cancel the time constant of the system per the following
equations. COUT is the total output capacitance of the
system.
The NCP81255 outputs a pulse of current from the VSN
pin upon each increment of the internal DAC following
a DVID UP command. A parallel RC network inserted into
the path from VSN to the output voltage return sense point,
VSS_SENSE, causes these current pulses to temporarily
decrease the voltage between VSP and VSN. This causes the
output voltage during DVID to be regulated slightly higher,
DAC Feed-Forward Current
DAC
Feed-Forward
From Intel
proprietary
interface
Interface
DAC
DAC
CFFSP
+
+
gm
S
VSN
VSN
VSP
VSP
RFFSP
−
To VCC_SENSE
CSNSSP
Figure 9.
R FFSP +
Loadline @ C OUT
1.35 @
10 *9
C FFSP +
(W)
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15
200
R FFSP
(nF)
(eq. 10)
NCP81255
Programming the Current Limit
The current limit threshold is programmed with a resistor
(RILIM) from the ILIM pin to ground. The current limit
latches the single-phase rail off immediately if the ILIM pin
voltage exceeds the ILIM Threshold. Set the value of the
current limit resistor based on the equation shown below.
A capacitor can be placed in parallel with the programming
resistor to slightly delay activation of the latch if some
tolerance of short over-current events is desired.
RPHSP
CSP
+
AV = 1
Current
Sense AMP
CSN
RCSSP
−
CCSSP
gm
Over-Current
Programming
To Inductor
ILIM
RILIMSP
Over-Current
Comparators
OCP
t
RTH
OCP REF
Figure 10.
1.3 V
R ILIMSP +
gm @
(eq. 11)
R TH)R CSSP
R PHSP)R TH)R CSSP
TSENSE
@ I OUT
LIMIT
@ DCR
sense input is sampled by the internal A/D converter.
A 100k NTC similar to the VISHAY ERT−J1VS104JA
should be used. See the specification table for the thermal
sensing voltage thresholds and source current.
A temperature sense input is provided. A precision current
is sourced out the TSENSE pin to generate voltage on the
temperature sense network. The voltage on the temperature
TSENSE
RCOMP1
0.0 W
CFILTER
0.1 mF
RCOMP2
8.2 kW
AGND
RTNC
100 kW
AGND
Figure 11.
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16
NCP81255
• Switching Node: SW node should be a copper pour, but
Ultrasonic Mode
The switching frequency of a rail in DCM will decrease
at very light loads. Ultrasonic Mode forces the switching
frequency to stay above the audible range.
•
Input Under-Voltage Protection
The controller is protected against under-voltage on the
VCC, VCCP, and VFF pins.
•
Under-Voltage Protection
Under-voltage protection will shut off the output similar
to OCP to protect against short circuits. The threshold is
specified in the parametric spec tables and is not adjustable.
•
Over-Current Protection (OCP)
•
A programmable current limit is programmed with
a resistor between the ILIM pin and ground. to this resistor
is compared to the ILIM Threshold Voltage (VCL). If the
ILIM pin voltage exceeds the lower Threshold Voltage, an
internal latch-off timer starts. When the timer expires, the
controller shuts down if the fault is not removed. If the
voltage at the ILIM pin exceeds the higher Threshold
Voltage, the controller shuts down immediately. To recover
from an OCP fault, the EN pin or VCC voltage must be
cycled low.
•
Layout Notes
The NCP81255 has differential voltage and current
monitoring. This improves signal integrity and reduces
noise issues related to layout for easy design use. To insure
proper function there are some general rules to follow.
Always place the inductor current sense RC filters as close
to the CSN and CSP pins on the controller as possible. Place
the VCC decoupling caps as close as possible to the
controller VCC pin.
compact because it is also a noise source.
Bootstrap: The bootstrap cap and an optional resistor
need to be very close and directly connected between
BST and SW pins. No need to externally connect pin 10
to SW node because it has been internally connected to
other SW pins.
Ground: It would be good to have separated ground
planes for PGND and GND and connect the two planes
at one point. Directly connect GND pin to the exposed
panda then connect to GND ground plane through vias.
Voltage Sense: Use Kelvin sense pair and arrange
a “quiet” path for the differential output voltage sense.
Current sense: Careful layout for current sensing is
critical for jitter minimization, accurate current
limiting, and IOUT reporting. The temperature
compensating thermistor should be placed as close as
possible to the inductor. The wiring path should be kept
as short as possible and well away from the switch
node.
Intel proprietary interface Bus: The Serial VID bus is a
high-speed data bus and the bus routing should be done
to limit noise coupling from the switching node. The
signals should be routed with the Alert# line in between
the Intel proprietary interface clock and Intel
proprietary interface data lines. The Intel proprietary
interface lines must be ground referenced and each
line’s width and spacing should be such that they have
nominal 50 W impedance with the board stack-up.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from
a small package with reduced temperature rise. Thermal
layout guidelines are:
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Power Paths: Use wide and short traces for power
paths (such as VIN, VOUT, SW, and PGND) to reduce
parasitic inductance and high-frequency loop area. It is
also good for efficiency improvement.
• Power Supply Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be a small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low-ESL MLCC is placed very close
to VIN and PGND pins.
• VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC and VCCP pins.
The filter resistor at VCC pin should be not higher than
2.2 W to prevent large voltage drop.
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17
NCP81255
PACKAGE DIMENSIONS
QFN40 5x5, 0.4P
CASE 485DY
ISSUE O
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18
NCP81255
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NCP81255/D