ENA2355 D

Ordering number : EN*A2355
STK541UC62K-E
Advance Information
http://onsemi.com
Inverter IPM
for 3-phase Motor Drive
Overview
This “Inverter IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase
outputs in a single SIP module (Single-In line Package). Output stage uses IGBT/FRD technology and implements
Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal
Boost diodes are provided for high side gate boost drive.
Function
 Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit
 All control input and status output are at low voltage levels directly compatible with microcontrollers
 Built-in cross conduction prevention
 Externally accessible embedded thermistor for substrate temperature measurement
 The level of the over-current protection current is adjustable with the external resistor, “RSD”
Certification
 UL1557 (File Number : E339285).
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Conditions
Unit
450
V
VCC
P to N, surge<500V
Collector-emitter voltage
VCE
P to U,V,W or U,V,W to N
600
V
P, N, U,V,W terminal current
±10
A
P, N, U,V,W terminal current at Tc=100C
±5
A
P, N, U,V,W terminal current for a Pulse width of 1ms.
±20
A
20
V
Output current
Io
Output peak current
Iop
Pre-driver voltage
Input signal voltage
FLTEN terminal voltage
Maximum power dissipation
VD1,2,3,4
VIN
VFLTEN
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
FLTEN terminal
IGBT per channel
Junction temperature
Tj
IGBT,FRD
Storage temperature
Tstg
0 to 7
V
0.3 to VDD
V
22
W
150
C
40 to +125
C
40 to +100
C
Tc
IPM case temperature
Case mounting screws
*3
0.9
Nm
Vis
50Hz sine wave AC 1 minute
*4
2000
VRMS
Tightening torque
Withstand voltage
*2
HIN1, 2, 3, LIN1, 2, 3
Pd
Operating substrate temperature
*1
Ratings
Supply voltage
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1: Surge voltage developed by the switching operation due to the wiring inductance between “P” and “N” terminal.
*2: Terminal voltage: VD1=VB1U, VD2=VB2V, VD3=VB3W, VD4=VDDVSS
*3: Flatness of the heat-sink should be 0.15mm and below.
*4: Test conditions : AC2500V, 1 second.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet.
Semiconductor Components Industries, LLC, 2014
August, 2014
81914HK No.A2355-1/17
STK541UC62K-E
Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15V
Parameter
Symbol
Conditions
Test
circuit
min
typ
max
Unit
-
-
0.1
mA
mA
Power output section
Collector-emitter cut-off current
ICE
VCE = 600V
Bootstrap diode reverse current
IR(BD)
VR(BD)
Collector to emitter
saturation voltage
Diode forward voltage
VCE(SAT)
VF
Fig.1
-
-
0.1
-
1.4
2.3
Ic=10A
Upper side
Tj=25C
Lower side *1
Ic=5A
Upper side
Tj=100C
Lower side *1
IF=10A
Upper side
-
1.3
2.2
Tj=25C
Lower side *1
-
1.6
2.5
IF=5A
Upper side
-
1.2
-
Tj=100C
Lower side *1
Fig.2
Fig.3
-
1.7
2.6
-
1.3
-
-
1.6
-
V
V
-
1.5
-
Junction to case
θj-c(T)
IGBT
-
-
5.5
thermal resistance
θj-c(D)
FRD
-
-
6.5
-
0.08
0.4
-
1.6
4.0
-
-
0.8
C/W
Control (Pre-driver) section
Pre-driver current consumption
ID
VD1, 2, 3=15V
VD4=15V
High level Input voltage
Vin H
Low level Input voltage
Vin L
Input threshold voltage hysteresis*1
Vinth(hys)
Logic 0 input leakage current
IIN+
Logic 1 input leakage current
IIN
FLTEN terminal input electric current
IoSD
FAULT : ON/VFLTEN=0.1V
FAULT clearance delay time
FLTCLR
Fault output latch time
VCC and VS undervoltage upper
threshold
VCCUV+
VSUV+
VCC and VS undervoltage lower
threshold
VSUV
VCC and VS undervoltage hysteresis
Fig.4
HIN1, HIN2, HIN3,
mA
V
2.5
-
-
V
0.5
0.8
-
V
VIN=+3.3V
76
118
160
uA
VIN=0V
97
150
203
uA
-
2
-
mA
6
9
12
ms
10.5
11.1
11.7
V
10.3
10.9
11.5
V
0.14
0.2
-
A
10
-
17
A
0.30
0.33
0.36
V
LIN1, LIN2, LIN3 to VSS
VCCUV
VCCUVH
VSUVH
Over current protection level
ISD
PW=100μs
Output level for current monitor
ISO
Io=10A
Fig.5
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1: The lower side’s VCE(SAT) and VF include a loss by the shunt resistance
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2355-2/17
STK541UC62K-E
Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15V, VCC = 300V, L = 3.9mH
Parameter
Symbol
Conditions
Test
circuit
min
typ
max
Unit
0.2
0.4
1.1
-
0.5
1.2
-
200
-
J
Switching Character
tON
Io=10A
tOFF
Inductive load
Eon
Ic=5A, P=300V,
Turn-off switching loss
Eoff
VDD=15V, L=3.9mH
-
130
-
J
Total switching loss
Etot
Tc=25C
-
330
-
J
Turn-on switching loss
Eon
Ic=5A, P=300V,
-
240
-
J
Turn-off switching loss
Eoff
VDD=15V, L=3.9mH
-
160
-
J
Total switching loss
Etot
Tc=100C
-
400
-
J
Diode reverse recovery energy
Erec
IF=5A, P=400V, VDD=15V,
-
17
-
J
Diode reverse recovery time
Trr
L=0.5mH, Tc=100C
62
-
ns
Reverse bias safe operating area
RBSOA
Io=20A, VCE=450V
Switching time
Turn-on switching loss
Short circuit safe operating area
SCSOA
VCE=400V, Tc=100C
Allowable offset voltage slew rate
dv/dt
Between U, V, W to N
Fig.6
Fig.6
Fig.6
Fig.7
s
Full square
4
50
-
-
s
50
V/ns
Reference voltage is “VSS” terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes:
1. When the internal protection circuit operates, a Fault signal is turned ON (When the Fault terminal is low level, Fault signal is ON
state : output form is open DRAIN) but the Fault signal does not latch.After protection operation ends,it returns automatically within
about 6ms to 12ms and resumes operation beginning condition. So, after Fault signal detection, set all input signals to OFF (Low)
at once.However, the operation of pre-drive power supply low voltage protection (UVLO:with hysteresis about 0.2V) is as follows.
Upper side:
The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the
input signal will turn ‘low’.
Lower side:
The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage.
2. When assembling the IPM on the heat sink with M3 type screw, tightening torque range is 0.6 Nm to 0.9 Nm.
3. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an operating
malfunction.
No.A2355-3/17
STK541UC62K-E
Equivalent Block Diagram
VB1(7)
U(8)
VB2(4)
V(5)
VB3(1)
W(2)
P(10)
U.V.
U.V.
U.V.
Shunt Resistor
N(12)
Thermistor
VTH (13)
Level
Level
Level
Shifter
Shifter
Shifter
HIN1(15)
HIN2(16)
HIN3(17)
LIN1(18)
Logic
Logic
Logic
LIN2(19)
LIN3(20)
FLTEN(21)
ISO(22)
VDD(14)
VSS(23)
Latch
Latch Time About 9ms
( Automatic Reset )
Over-Current
VDD-Under Voltage
No.A2355-4/17
STK541UC62K-E
Module Pin-Out Description
Pin
Name
Description
1
VB3
High Side Floating Supply Voltage 3
2
W, VS3
Output 3 - High Side Floating Supply Offset Voltage
3
NA
None
4
VB2
High Side Floating Supply voltage 2
5
V,VS2
Output 2 - High Side Floating Supply Offset Voltage
6
NA
None
7
VB1
High Side Floating Supply voltage 1
8
U,VS1
Output 1 - High Side Floating Supply Offset Voltage
9
NA
None
10
P
Positive Bus Input Voltage
11
NA
None
12
N
Negative Bus Input Voltage
13
VTH
Temperature Feedback
14
VDD
+15V Main Supply
15
HIN1
Logic Input High Side Gate Driver - Phase U
16
HIN2
Logic Input High Side Gate Driver - Phase V
17
HIN3
Logic Input High Side Gate Driver - Phase W
18
LIN1
Logic Input Low Side Gate Driver - Phase U
19
LIN2
Logic Input Low Side Gate Driver - Phase V
20
LIN3
Logic Input Low Side Gate Driver - Phase W
21
FLTEN
Fault output and Enable
22
ISO
Current monitor output
23
VSS
Negative Main Supply
No.A2355-5/17
STK541UC62K-E
Test Circuit
The tested phase U+ shows the upper side of the U phase and U shows the lower side of the U phase.
■ICE / IR(BD)
ICE
U+
V+
W+
U-
V-
W-
M
10
10
10
8
5
2
N
8
5
2
12
12
12
1
M
A
VD3=15V
2
4
VD2=15V
5
VCE
7
U(BD)
V(BD)
W(BD)
M
7
4
1
N
23
23
23
VD1=15V
8
14
VD4=15V
23
N
Fig.1
1
■VCE(SAT) (test by pulse)
M
VD3=15V
2
U+
V+
W+
U-
V-
W-
M
10
10
10
8
5
2
N
8
5
2
12
12
12
m
15
16
17
18
19
20
4
VD2=15V
5
V
Ic
7
VD1=15V
VCE(SAT)
8
14
VD4=15V
m
23
N
Fig.2
■VF (test by pulse)
M
U+
V+
W+
U-
V-
W-
M
10
10
10
8
5
2
N
8
5
2
12
12
12
V
VF
IF
N
Fig.3
■ID
VD1
VD2
VD3
VD4
M
7
4
1
14
N
8
5
2
23
ID
A
M
VD*
N
Fig.4
No.A2355-6/17
STK541UC62K-E
■ISD
1
8
VD3=15V
2
4
VD2=15V
Input signal
(0 to 5V)
5
Io
7
VD1=15V
Io
SD
8
14
VD4=15V
Input signal
100μS
18
23
12
Fig.5
■Switching time (The circuit is a representative example of the lower side U phase.)
1
10
VD1=15V
Input signal
(0 to 5V)
2
4
VD2=15V
5
90%
8
7
Vcc
CS
VD3=15V
Io
10%
tOFF
8
14
VD4=15V
Input signal
Io
18
23
12
Fig.6
 RB-SOA (The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5V)
1
10
VD1=15V
2
4
VD2=15V
5
Io
8
7
Vcc
CS
VD3=15V
8
14
VD4=15V
Input signal
Io
18
23
12
Fig.7
No.A2355-7/17
STK541UC62K-E
Input / Output Timing Diagram
VBS undervoltage protection reset signal
OFF
HIN1,2,3
ON
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
-terminal
(BUS line)
Current
FLTEN terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(typ.9ms)
Fig.8
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When VDD rises the operation will
resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gate voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 6 to
12ms after the over current condition is removed.
No.A2355-8/17
STK541UC62K-E
Logic level table
P
INPUT
Ho
HIN1,2,3
(15,16,17)
IC
Driver
U,V,W
(8,5,2)
LIN1,2,3
(18,19,20)
OUTPUT
HIN
LIN
OCP
Ho
Lo
U,V,W
FLTEN
H
L
OFF
L
H
N
OFF
L
H
OFF
H
L
P
OFF
L
L
OFF
L
L
High
Impedance
OFF
H
H
OFF
L
L
High
Impedance
OFF
X
X
ON
L
L
High
Impedance
ON
Lo
N
Fig. 9
No.A2355-9/17
STK541UC62K-E
Sample Application Circuit
CB
7 8
CB
VTH
VSS
VDD
ISO
FLTEN
LIN3
LIN2
LIN1
HIN3
HIN2
HIN1
N
U
VB1
V
4 5
P
1 2
VB2
W
VB3
STK541UC62K-E
10
12 15 16 17 18 19 20 21 22 14 23 13
CB
CS
RP
VP
Control Logic
Vcc
CD
VDD=15V
CI
Recommended Operating Conditions at Tc = 25C
Item
Supply voltage
Symbol
Conditions
VCC
P to N
VD1,2,3
VB1 to U, VB2 to V, VB3 to W
VD4
VDD to VSS
ON-state input voltage
VIN(ON)
OFF-state input voltage
VIN(OFF)
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
PWM frequency
fPWM
Dead time
DT
Allowable input pulse width
Tightening torque
Pre-driver supply voltage
*1
min
typ
max
Unit
V
0
280
450
12.5
15
17.5
13.5
15
16.5
V
0
-
0.3
3.0
-
5.0
-
1
-
20
kHz
Turn-off to turn-on
2
-
-
μs
PWIN
ON and OFF
1
-
-
μs
-
‘M3’ type screw
0.6
-
0.9
Nm
V
*1 Pre-drive power supply (VD4=15±1.5V) must be have the capacity of Io=20mA(DC), 0.5A(Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precaution
1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated;
each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF, however this
value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about
20Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of
surge voltages. Recommended value of “CS” is in the range of 0.1 to 10μF.
3. “ISO” (pin22) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6kΩ
4. “FLTEN” (pin21) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 5.6kΩ.
5. Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and VTH
terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used.
The temperature monitor example application is as follows, please refer the Fig.10 and below.
6. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended for
safety.
7. When “N” and “VSS” terminal are short-circuited on the outside, level that over-current protection (ISD) might be changed from
designed value as IPM. Please check it in your set (“N” terminal and “VSS” terminal are connected in IPM).
8. When input pulse width is less than 1.0μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
No.A2355-10/17
STK541UC62K-E
The characteristic of thermistor
Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Resistance
R25
Tc=25C
99
100
101
kΩ
Resistance
R100
Tc=100C
B
B-Constant (25 to 50C)
Temperature Range
5.12
5.38
5.66
kΩ
4165
4250
4335
K
40
-
+125
C
Case Temperature(Tc) - Thermal resistance(RTH)
10000
Thermistor Resistanse, RTH-Kohm
min
typ
1000
max
100
10
1
-40
-30
-20
-10
0
10
20 30 40 50 60 70
Case temperature, Tc-degC
80
90
100 110 120 130
Fig.10 Variation of thermistor resistance with temperature
Case Temperature(Tc) - TH terminal voltage(VTH)
6.0
Thermistor Pin Read-Out Voltage, VTH-V
min
typ
5.0
max
4.0
3.0
2.0
1.0
0.0
-40
-30
-20
-10
0
10
20 30 40 50 60 70
Case temperature, Tc-degC
80
90
100 110 120 130
Fig.11 Variation of thermistor terminal voltage with temperature
(47k pull-up resistor, 5V)
No.A2355-11/17
STK541UC62K-E
The characteristic of PWM switching frequency
Maximum RMS Output Current / Phase
(A)
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
PWM Switching Frequency (kHz)
Fig. 12 Maximum sinusoidal phase current as function of switching frequency
at Tc=100℃, VCC=400V
No.A2355-12/17
STK541UC62K-E
Switching waveform
450
14
13
12
Current
11
Voltage
400
350
10
Current[A]
250
8
7
200
6
150
5
4
Voltage[V]
300
9
100
3
50
2
1
0
0
-50
-1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time[us]
Fig. 13 IGBT Turn-on. Typical turn-on waveform at Tc=100C, VCC=400V
450
14
13
400
12
350
10
Current
9
Voltage
300
250
8
7
200
6
150
5
4
Voltage[V]
Current[A]
11
100
3
50
2
1
0
0
-50
-1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time[us]
Fig. 14 IGBT Turn-off. Typical turn-off waveform at Tc=100C, VCC=400V
No.A2355-13/17
STK541UC62K-E
CB capacitor value calculation for bootstrap circuit
Calculate conditions
Value
Unit
Upper side power supply.
Parameter
VBS
Symbol
15
V
Total gate charge of output power IGBT at 15V.
QG
89
nC
Upper limit power supply low voltage protection.
UVLO
12
V
Upper side power dissipation.
IDMAX
400
μA
ON time required for CB voltage to fall from 15V to UVLO
TONMAX
-
s
Capacitance calculation formula
Thus, the following formula are true
VBS x CB - QG - IDMAX * TONMAX = UVLO * CB
therefore,
CB = (QG + IDMAX * TONMAX) / (VBS - UVLO)
The relationship between TONMAX and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated
above. The recommended value of CB is in the range of 1 to 47μF, however, this value needs to be verified prior to production.
CB vs Tonmax
Bootstrap Capacitance CB [uF]
100
10
1
0.1
0.01
0.1
1
10
100
1000
Tonmax [ms]
Fig. 15 Tonmax - CB characteristic
No.A2355-14/17
STK541UC62K-E
VCE
Ic
90% Ic
50%
HIN/LIN
HIN/LIN
10% Ic
tr
tON
Fig. 16a Input to output propagation turn-on delay time
Ic
VCE
90% Ic
HIN/LIN
50%
HIN/LIN
10% Ic
tf
tOFF
Fig. 16b Input to output propagation turn-off delay time
IF
VCE
HIN/LIN
Irr
trr
Fig. 16c Diode reverse recovery
No.A2355-15/17
STK541UC62K-E
Package Dimensions
(unit : mm)
The tolerances of length are +/- 0.5mm unless otherwise specified.
missing pin ; 3, 6, 9, 11
56.0
note3
2.0
9.0
23
1
0.6+0.2
-0.05
0.5+0.2
-0.05
2.0
22.0
4.3
note1
(10.9)
STK541UC62K
21.8
4DB00
0.5
R1.
7
1
3.4
note2
5.0
22X2.0=44.0
3.2
46.2
2.0
5.0
3
2
50.0
62.0
note1: Mark for No.1 pin identification.
note2: The form of a character in this
drawing differs from that of HIC.
note3: This indicates the date code.
The form of a character in this
drawing differs from that of HIC.
No.A2355-16/17
STK541UC62K-E
ORDERING INFORMATION
Device
STK541UC62K-E
Package
Shipping (Qty / Packing)
SIP23 56x21.8
(Pb-Free)
8 / Tube
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
PS No.A2355-17/17
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