EN7257 D

Ordering number : EN7257B
LB11872H
Monolithic Digital IC
For Polygonal Mirror Motors
http://onsemi.com
Three-Phase Brushless Motor Driver
Overview
The LB11872H is a three-phase brushless motor driver developed for driving the motors used for the polygonal mirror
in laser printers and similar applications. It can implement, with a single IC chip, all the circuits required for polygonal
mirror drive, including speed control and driver functions. The LB11872H can implement motor drive within minimal
drive noise due to its use of current linear drive.
Features
• Three-phase bipolar current linear drive + midpoint control circuit.
• PLL speed control circuit.
• Speed is controlled by an external clock signal.
• Supports Hall FG operation.
• Built-in output saturation prevention circuit.
• Phase lock detection output (with masking function).
• Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip.
• On-chip output diodes.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Supply voltage
VCC max
Output current
IO max
T ≤ 500ms
Allowable power dissipation
Pd max1
Pd max2
Ratings
Unit
30
V
1.2
A
Independent IC
0.8
W
*With specified substrate
2.0
W
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
∗ When mounted on the specified printed circuit board : 114.3mm × 76.1mm × 1.6mm, glass epoxy
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
82708 MS PC/91002AS (OT) No.7257-1/11
LB11872H
Allowable Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
10 to 28
V
6.3 V regulator-voltage output current
IREG
0 to -20
mA
LD pin applied voltage
VLD
0 to 28
V
LD pin output current
ILD
0 to 15
mA
FGS pin applied voltage
VFG
0 to 28
V
FGS pin output current
IFG
0 to 10
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Supply current 1
ICC1
Stop mode
5
7
mA
Supply current 2
ICC2
Start mode
17
22
mA
Output saturation voltages VAGC = 3.5V
SOURCE (1)
VSAT1-1
IO = 0.5A, RF = 0Ω
1.7
2.2
V
SOURCE (2)
VSAT1-2
IO = 1.0A, RF = 0Ω
2.0
2.7
V
SINK (1)
VSAT2-1
IO = 0.5A, RF = 0Ω
0.4
0.9
V
SINK (2)
VSAT2-2
IO = 1.0A, RF = 0Ω
1.0
1.7
V
Output leakage current
IO (LEAK)
VCC = 28V
100
μA
6.3V Regulator-voltage output
Output voltage
VREG
6.25
6.60
V
Voltage regulation
ΔVREG1
VCC = 9.5 to 28V
5.90
50
100
mV
Load regulation
ΔVREG2
Iload = -5 to -20mA
10
60
mV
Temperature coefficient
ΔVREG3
Design target
Input bias current
IB (HA)
Differential input : 50mVp-p
Differential input voltage range
VHIN
SIN wave input
50
*600
Common-phase input voltage range
VICM
Differential input : 50mVp-p
2.0
VCC-2.5
Input offset voltage
VIOH
Design target value*1
-20
20
value*1
0
mV/°C
Hall amplifier block
2
10
μA
mVp-p
V
mV
FG amplifier and schmitt block (IN1)
Input amplifier gain
GFG
5
Times
Input hysteresis (high to low)
VSHL
0
mV
Input hysteresis (low to high)
VSLH
Hysteresis width
VFGL
-10
Input conversion
mV
4
7
12
mV
Low-voltage protection circuit
Operating voltage
VSD
8.4
8.8
9.2
V
Hysteresis width
ΔVSD
0.2
0.4
0.6
V
150
180
°C
40
°C
Thermal protection circuit
Thermal shutdown operating
TSD
Design target value*1 (junction temperature)
ΔTSD
Design target value*1 (junction temperature)
temperature
Hysteresis width
Current limiter operation
Acceleration limit voltage
VRF1
0.53
0.59
0.65
V
Deceleration limit voltage
VRF2
0.32
0.37
0.42
V
Error amplifier
Design target value*1
Input offset voltage
VIO (ER)
Input bias current
IB (ER)
High-level output voltage
VOH (ER)
IOH = -500μA
Low-level output voltage
VOL (ER)
IOL = 500μA
DC bias level
VB (ER)
-10
10
mV
-1
1
μA
VREG-1.2
VREG-0.9
V
0.9
1.2
V
-5%
1/2VREG
5%
V
Note* : Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input. amplitudes should be held to under 350mVp-p.
*1 : This parameter is a design target value and is not measured.
Continued on next page.
No.7257-2/11
LB11872H
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
VREG-0.2
VREG-0.1
Unit
max
Phase comparator output
High-level output voltage
VPDH
IOH = -100μA
Low-level output voltage
VPDL
IOL = 100μA
Output source current
IPD+
VPD = VREG/2
Output sink current
IPD-
VPD = VREG/2
Output saturation voltage
VLD (SAT)
ILD = 10mA
Output leakage current
ILD (LEAK)
VLD = 28V
Output saturation voltage
VFG (SAT)
IFG = 5mA
Output leakage current
IFG (LEAK)
VFG = 28V
Dead zone width
VDZ
With the phase is locked
50
Output idling voltage
VID
Forward gain 1
GDF+1
With phase locked
Forward gain 2
GDF+2
With phase unlocked
Reverse gain 1
GDF-1
Reverse gain 2
GDF-2
Acceleration command voltage
VSTA
Deceleration command voltage
VSTO
0.2
V
0.3
V
-500
μA
1.5
mA
Lock detection output
0.15
0.5
V
10
μA
0.5
V
10
μA
100
300
mV
0.4
0.5
0.6
Times
0.8
1.0
1.2
Times
With phase locked
-0.6
-0.5
-0.4
Times
With phase unlocked
-0.8
-1.0
-1.2
Times
5.0
5.6
0.8
1.5
V
FG output
0.15
Drive block
6
mV
V
Forward limiter voltage
VL1
Rf = 22Ω
0.53
0.59
0.65
V
Reverse limiter voltage
VL2
Rf = 22Ω
0.32
0.37
0.42
V
Oscillation frequency
fOSC
C = 0.022μF
High-level pin voltage
VCSDH
4.3
4.8
5.3
V
Low-level pin voltage
VCSDL
0.75
1.15
1.55
V
External capacitor charge and
ICHG
3
5
7
μA
0.80
V
400
10000
Hz
2.0
VREG
V
1.0
V
CSD oscillator circuit
31
Hz
discharge current
Lock detection delay count
CSDCT1
7
Clock cutoff protection operating
CSDCT2
2
Lock protection count
CSDCT3
31
Initial reset voltage
VRES
count
0.60
Clock input block
External input frequency
fCLK
High-level input voltage
VIH (CLK)
Design target value*1
Low-level input voltage
VIL (CLK)
value*1
Input open voltage
VIO (CLK)
Hysteresis width
VIS (CLK)
Design target value*1
High-level input current
IIH (CLK)
V (CLK) = VREG
Low-level input current
IIL (CLK)
V (CLK) = 0V
Design target
0
2.7
3.0
3.3
V
0.1
0.2
0.3
V
140
185
μA
-185
-140
μA
S/S pin
*1
High-level input voltage
VIH (S/S)
2.0
VREG
V
Low-level input voltage
VIL (S/S)
0
1.0
V
Input open voltage
VIO (S/S)
2.7
3.3
V
Hysteresis width
VIS (S/S)
High-level input current
IIH (S/S)
V (S/S) = VREG
Low-level input current
IIL (S/S)
V (S/S) = 0V
0.1
-185
3.0
0.2
0.3
V
140
185
μA
-140
μA
: This parameter is a design target value and is not measured.
No.7257-3/11
LB11872H
Package Dimensions
unit : mm (typ)
3233B
Pd max – Ta
Allowable power dissipation, Pd max – W
2.4
HEAT SPREADER
15.2
(6.2)
0.65
7.9
10.5
15
(4.9)
28
1
14
0.8
0.25
2.0
0.1
(2.25)
0.3
2.7
2.45max
(0.8)
Specified board : 114.3×76.1×1.6mm3
glass epoxy
2.0
1.6
1.2
1.12
0.8
Independent IC
0.45
0.4
0
– 20
0
20
40
60
80
100
Ambient temperature, Ta – °C
SANYO : HSOP28H(375mil)
LD
CLK
S/S
20
19
18
17
16
15
8
9
10
11
12
13
14
CSD
NC
FG
HSOP28H
PD
21
NC
22
EI
VREG
23
NC
VCC
24
EO
SUB
25
MN
RF
26
FC
OUT1
27
AGC
OUT2
28
GND
OUT3
Pin Assignment
2
3
4
5
6
7
IN2+
IN2-
IN1+
IN1-
IN3+
IN3-
GND
1
NC
LB11872H
Top view
Truth Table
OUT1 to OUT3 (H : Source, L : Sink)
IN1
IN2
IN3
OUT1
OUT2
OUT3
H
L
H
L
H
M
H
L
L
L
M
H
H
H
L
M
L
H
L
H
L
H
L
M
L
H
H
H
M
L
L
L
H
M
H
L
For IN1 to IN3, “H” means that IN+ is greater than IN-, and “L” means IN- is greater than IN+.
For OUT1 to OUT3, “H” means the output is a source, and “L” means that it is a sink.
No.7257-4/11
FG
LD
MN 9
FG 14
LD 17
CSD 12
Vreg 22
+
+
-
RESET
OSC
×5
6.3VREG
+
-
4
LD
PD
IN1
5
2
IN2
3
6
EI
19
PLL
PD
18
IN3
7
HALL AMP & MATRIX
FILTER
FG
RESTRICT DET
LOCK DET
CLOCK DET
16
CLK
CLK
+
-
AGC
8
AGC
V-AMP
EO
20
SUB
24
FRAME
GND
OUTPUT
OCL
LVSD
TSD
28 OUT3
27 OUT2
26 OUT1
25 RF
21 FC
15 S/S
23 VCC
+
S/S
VCC
LB11872H
Block Diagram
No.7257-5/11
LB11872H
Pin Functions
Pin No.
2
3
4
Pin name
IN2+
IN2IN1+
6
IN1IN3+
7
IN3-
5
Function
Equivalent circuit
Hall effect sensor signal inputs.
These inputs are high when IN+ is greater than
VCC
IN- and low when IN- is greater than IN+.
Insert capacitors between the IN+ and IN– pins to
reduce noise.
An amplitude of over 50mVp-p and under
350mVp-p is desirable for the Hall input signals.
Kickback can occur in the output waveform if the
Hall input amplitude is over 350mVp-p.
8
AGC
AGC amplifier frequency characteristics
correction.
3
5
300Ω
7
300Ω
2
4
6
VREG
Insert a capacitor (about 0.022μF) between this
pin and ground.
300Ω
8
9
MN
Monitor pin.
12
CSD
Used for both initial reset pulse generation and as
This pin should be left open in normal operation.
the reference time for constraint protection
VREG
circuits.
Insert a capacitor between this pin and ground.
300Ω
14
FG
FG pulse output.
This is an open-collector output.
12
VREG
14
15
S/S
Start/stop control.
Low : Start 0 to 1.0V
VREG
High : Stop 2.0V to VREG
This pin goes to the high level when open.
33kΩ
5kΩ
15
30kΩ
Continued on next page.
No.7257-6/11
LB11872H
Continued from preceding page.
Pin No.
Pin name
16
CLK
Function
Equivalent circuit
Clock input.
VREG
Low : 0 to 1.0V
High : 2.0V to VREG
This pin goes to the high level when open.
33kΩ
5kΩ
16
30kΩ
17
LD
Phase locked state detection output.
VREG
This output goes to the on state when the PLL
locked state is detected.
17
This is an open-collector output.
18
PD
Phase comparator output (PLL output).
VREG
This pin output the phase error as a pulse signal
with varying duty.The output current increases as
the duty becomes smaller.
18
19
EI
Error amplifier in put pin.
VREG
300Ω
19
20
EO
Error amplifier output pin.
VREG
The output current increases when this output is
high.
300Ω
20
40kΩ
Continued on next page.
No.7257-7/11
LB11872H
Continued from preceding page.
Pin No.
Pin name
21
FC
Function
Equivalent circuit
Control amplifier frequency correction.
VREG
Inserting a capacitor (about 5600pF) between this
pin and ground will stop closed loop oscillation in
the current control system. The output current
response characteristics will be degraded if the
capacitor is too large.
22
VREG
21
Stabilized power supply (6.3V)
VCC
Insert a capacitor (about 0.1μF) between this pin
and ground for stabilization.
22
23
VCC
Power supply.
24
SUB
SUB pin.
25
RF
Connect this pin to ground.
Output current detection.
VCC
Insert low-valued resistors (Rf) between these
pins and ground. The output current will be limited
to the value set by the equation IOUT = VL/Rf.
26
OUT1
Motor drive outputs.
27
OUT2
If the output oscillates, insert a capacitor (about
28
OUT3
0.1μF) between this pin and ground.
VREG
26 27 28
300Ω
25
1
NC
No connection (NC) pins.
These pins may be used for wiring connections.
10
11
13
FRAME
GND
Ground.
No.7257-8/11
LB11872H
LB11920 Description
1. Speed Control Circuit
This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges
(low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed.
During this control operation, the FG servo frequency will be the same as the CLK frequency.
fFG (servo) = fCLK
2. Output Drive Circuit
To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint
control technique to prevent ASO destruction of the output transistors.
Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the
drive is cut and the motor is left in the free-running state.
Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1μF) must be inserted
between the OUT pins and ground.
3. Hall Input Signals
This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input
amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the
individual phases, discrepancies in the output phase switching timing may occur.
An amplitude (differential) of at least 50mVp-p is required in the Hall input signals. However, if the input amplitude
exceeds 350mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output.
If Hall signal input frequencies in excess of 1kHz (the frequency in a single Hall input phase) are used, internal IC
heating during startup and certain other times (that is, when the output transistors are saturated) may increase.
Reducing the number of magnetic poles can be effective in dealing with problem.
The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a
problem, a capacitor must be inserted across this input. However, since this could result in differences between the
signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases.
Although VCC can be used as the Hall element bias power supply, using VREG can reduce the chances of problems
occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned
with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only on
the low side.
4. Power Saving Circuit
This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is
implemented by removing the bias current from most of the circuits in the IC. However, the 6.3V regulator output is
provided in the power saving state.
5. Reference Clock
Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although
the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor.
This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the formula
below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode.
f (Hz) ≈ 0.64 ÷ CCSD
CCSD (μF) : The capacitor inserted between the CSD pin and ground.
When a capacitor of 0.022μF is used, the frequency will be about 29Hz.
If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat and
then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will not be
restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied before the
rotor constraint protection time elapses.
No.7257-9/11
LB11872H
6. Rotor Constraint Protection Circuit
This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained
physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the IN1 signal)
does not switch within a fixed time, output drive will be turned off. The time constant is determined by the capacitor
connected to the CSD pin.
< time constant (in seconds) > ≈ 30.5 × 1.57 × CCSD (μF)
If a 0.02μF capacitor is used, the protection time will be about 1.05 seconds.
To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and
reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection circuit
may not operate normally.
7. Phase Lock Signal
(1) Phase lock range
Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in
the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the
changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor,
the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states
where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup
and when unlocked due to switching clock frequencies.
(2) Masking function for the phase lock state signal
A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pull-in.
However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CSD pin and ground.
< masking time (seconds) > ≈ 6.5 × 1.57 × CCSD (μF)
When a 0.022μF capacitor is used, the masking time will be about 225ms. In cases where complete masking is required,
a masking time with fully adequate margin must be used.
8. Initial Reset
To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero
until it reaches 0.63V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good
approximation using the following formula.
< reset time (seconds) > ≈ 0.13 × CCSD (μF)
A reset time of over 100μs is required.
9. Current Limiter Circuit
The current limit value is determined by the resistor Rf inserted between the RF pin and ground.
ILIM = VL/Rf VL = 0.59V (typical) (during acceleration) and 0.37V (typical) (during deceleration)
10. Power Supply Stabilization
An adequately large capacitor must be inserted between the VCC pin and ground for power supply stabilization. If
diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with
reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be
used.
If high-frequency noise is a problem, a ceramic capacitor of about 0.1μF must also be inserted in parallel.
11. VREG Stabilization
A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply.
The capacitor must be connected as close as possible to the pins.
12. Error Amplifier External Component Values
To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as
possible.
No.7257-10/11
LB11872H
13. FRAME Pin and Heat sink Area
The FRAME pin and the heat sink area function as the control circuit ground terminal. It is desirable that this ground
line and the Rf resistor ground line be grounded at a single point at the ground for the electrolytic capacitor.
Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package
to the PCB with, for example, a solder with good thermal conductivity.
14. CSD Pin
The capacitor connected to the CSD pin influences several operational aspects of this IC, including the rotor constraint
protection time and the phase lock signal mask time. The following are possible ways of determining the value of this
capacitor.
(1) If removing chattering from the phase lock state signal is most important :
Select a capacitance that can assure an adequate mask time.
(2) If startup time is more important than chattering :
Select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that
there are no problems with the clock cutoff protection circuit and initial reset time.
Operation of the rotor constraint protection circuit may hinder the study of motor characteristics in the uncontrolled
state. It is possible to only operate the initial reset function and not operate the rotor constraint protection circuit by
inserting a resistor (about 390kΩ) in parallel with the capacitor between the CSD pin and ground.
15. FC Pin
The capacitor connected to the FC pin is required for current limiter loop phase compensation. If the value is too low,
the output will oscillate. If the value is too large, it will be easier for currents in excess of the limit value to flow during
the current limit time (time before the circuit operates) in states where the output is saturated. (This is because the
control response characteristics become worse.)
16. AGC Pin
A capacitance that allows a certain amount of smoothing of the AGC pin voltage in the motor speed range used must be
selected for the capacitor connected to the AGC pin. It is also desirable to use a capacitance that allows the AGC
voltage to reach an essentially stabilized voltage before the initial reset is cleared. (If the capacitance is too large, the
rate of change of the AGC voltage will become slower.)
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PS No.7257-11/11
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