EN8317 D

Ordering number : EN8317
LB11876
Monolithic Digital IC
For Polygonal Mirror Motors
http://onsemi.com
Three-Phase Brushless Motor Driver
Overview
The LB11876 is a 3-phase brushless motor driver developed for driving the polygonal mirror motor in plain-paper
copiers and similar products. It can support any motor voltage and motor current required by the use of appropriate
external components.
The LB11876 adopts direct PWM drive to achieve drive with minimal power loss.
Functions
• This is a version of the LB11875 with a modified constraint protection function.
• Three-phase bipolar drive (direct PWM)
• PLL speed control circuit
• Dedicated external clock
• Clock divider switching function
• Hall sensor FG support
• Short-circuit braking function
• Built-in current limiter, thermal protection, constraint protection, and undervoltage protection circuits
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Symbol
Conditions
VCC max
Unit
18
Input current
I13 max
V13 pin
Output current
IO max
UL pin, VL pin, WL pin, UH pin, VH pin, and WH pin
LVSD pin apply voltage
Ratings
LVSD max
Allowable power dissipation 1
Pd max1
Independent IC
Allowable power dissipation 2
Pd max2
When mounted on a circuit board *1
V
5
mA
30
mA
18
V
0.62
W
1.36
W
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
*1 Specified circuit board : 114.3 × 76.1 × 1.6mm3, glass epoxy.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
41807 TI PC B8-8869 No.8317-1/15
LB11876
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Supply voltage range 1
VCC1
Supply voltage range 2
VCC2
Conditions
Ratings
With VCC shorted to VREG
Input current range
I13
V13 pin
Output current
IO
UL pin, VL pin, WL pin, UH pin, VH pin, and WH pin
Unit
8 to 17
V
4.5 to 5.5
V
0.5 to 4
mA
20
mA
mA
5V constant voltage output
IREG
0 to -30
LD pin apply voltage
VLD
0 to 17
V
LD pin output current
ILD
0 to 15
mA
FGS pin apply voltage
VFGS
0 to 17
V
FGS pin output current
IFGS
0 to 10
mA
Electrical Characteristics at Ta = 25°C, VCC = 12V
Parameter
Symbol
Ratings
Conditions
min
Supply current 1
ICC1
Supply current 2
ICC2
Unit
typ
Stop mode
max
15
25
mA
3
5
mA
5V constant voltage output (VREG pin)
Output voltage
VREG
5.0
5.35
V
Line regulation
ΔVREG1
VCC = 8 to 13.5V
4.65
40
100
mV
Load regulation
ΔVREG2
IO = 0 to -15mA
20
100
Temperature coefficient
ΔVREG3
Design target
0
mV
mV/°C
13V constant voltage output (V13 pin)
Output voltage
V13
IO = 2mA
12.5
13.5
14.5
V
0.2
0.5
V
0.9
1.2
V
10
μA
Output Block
Output saturation voltage 1-1
VO sat1-1
Output saturation voltage 1-2
Low level, IO = 400μA
VO sat1-2
Low level, IO = 10mA
Output saturation voltage 2
VO sat2
High level, IO = -20mA
Output leakage current
IO leak
VCC – 1.2
VCC – 0.9
V
Hall Sensor Amplifier Block
Input bias current
Common-mode input voltage
IHB (HA)
VICM1 (HA)
-2
When a Hall sensor is used
μA
-0.5
0.5
VCC – 2.0
V
0
VCC
V
range1
Common-mode input voltage
VICM2 (HA)
When a single-sided input bias is used
range2
(using a Hall sensor IC)
Input sensitivity
Sine wave
80
mVp-p
Hysteresis
ΔVIN (HA)
Input current low → high
VSLH (HA)
12
mV
Input current high → low
VSHL (HA)
-12
mV
15
24
42
mV
FG Schmitt Trigger Block
Input bias current
Common-mode input voltage
IB (FGS)
VICM1 (FGS)
-2
When a Hall sensor is used
μA
-0.5
0.5
VCC – 2.0
V
0
VCC
V
range1
Common-mode input voltage
VICM2 (FGS)
range2
Input sensitivity
When a single-sided input bias is used
(using a Hall sensor IC)
Sine wave
80
Hysteresis
ΔVIN (FGS)
VIN (FGS)
Design target
15
mVp-p
Input current low → high
VSLH (FGS)
Design target
12
Input current high → low
VSHL (FGS)
Design target
-12
24
42
mV
mV
mV
Continued on next page.
No.8317-2/15
LB11876
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
FGS Output
Output saturation voltage
Output leakage current
VOL (FGS)
ILD = 7mA
IL (FGS)
VO = VCC
0.15
0.5
V
10
μA
V
PWM Oscillator
High-level output voltage
VOH (PWM)
2.6
2.9
3.2
Low-level output voltage
VOL (PWM)
1.4
1.7
2.0
V
External capacitor charge
ICHG
-65
-50
-35
μA
VPWM = 2.0V
current
Oscillator frequency
f (PWM)
C = 620pF
50
kHz
Amplitude
V (PWM)
1.0
1.2
1.4
Vp-p
High-level output voltage
VOH (CSD)
3.2
3.5
3.8
V
Low-level output voltage
VOL (CSD)
0.9
1.1
1.3
V
External capacitor charge
ICHG1
-13
-10
-7
μA
ICHG2
7
10
13
μA
CSD Oscillator Circuit
current
External capacitor discharge
current
Oscillator frequency
f (CSD)
Amplitude
V (CSD)
C = 0.068μF
30
2.2
2.4
VREG - 0.2
VREG - 0.1
Hz
2.6
Vp-p
Phase Comparator Output
High-level input voltage
VPDH
IOH = -100μA
Low-level input voltage
VPDL
IOH = 100μA
Input source current
IPD+
VPD = VREG/2
Input sink current
IPD-
VPD = VREG/2
0.2
V
0.3
V
-0.6
mA
1.5
mA
Phase Lock Detection Output
Output saturation voltage
Output leakage current
VOL( LD)
IL (LD)
ILD = 10mA
0.15
0.4
V
10
μA
-10
10
mV
-0.4
0.4
μA
VO = VCC
Error Amplifier Block
Input offset voltage
Input bias current
VIO (ER)
Design target value
IB (ER)
High-level output voltage
VOH (ER)
IEI = -0.1mA, no load
3.7
V
Low-level output voltage
VOL (ER)
IEI = 0.1mA, no load
1.3
V
VB (ER)
Design target value
DC bias level
-5%
VREG/2
5%
V
0.225
0.25
0.275
V
Current Llimiter Circuit
Llimiter voltage
VRF
Low Voltage Protection Circuit
Operating voltage
VSDL
3.5
3.7
3.9
V
Release voltage
VSDH
4.0
4.2
4.4
V
Hysteresis
ΔVSD
0.35
0.5
0.65
V
150
180
°C
30
°C
Thermal shutdown circuit
Thermal shutdown operating
TSD
temperature
Thermal shutdown temperature
Design target value (junction
temperature)
ΔTSD
hysteresis
Design target value (junction
temperature)
CLD Circuit
External capacitor discharge
ICLD
-5
-4
3.25
3.5
-3
μA
3.75
V
current
Operating voltage
VH (CLD)
Continued on next page.
No.8317-3/15
LB11876
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
CLKIN pin
External input frequency
fI (CKIN)
0.1
10
kHz
High-level input voltage
VIH (CKIN)
2.0
VREG
V
Low-level input voltage
VIL (CKIN)
0
1.0
V
Input open voltage
VIO (CKIN)
VREG –
VREG
V
0.5
Hysteresis
VIS (CKIN)
High-level input current
IIH (CKIN)
VCKIN = VREG
Low-level input current
IIL (CKIN)
VCKIN = 0V
0.13
0.21
0.29
V
-10
0
10
μA
-130
-90
μA
S/S pin
High-level input voltage
VIH (SS)
2.0
VREG
V
Low-level input voltage
VIL (SS)
0
1.0
V
Input open voltage
VIO (SS)
VREG –
VREG
V
0.5
Hysteresis
VIS (SS)
High-level input current
IIH (SS)
VS/S = VREG
Low-level input current
IIL (SS)
VS/S = 0V
0.13
0.21
0.29
V
-10
0
10
μA
-130
-90
μA
F/R pin
High-level input voltage
VIH (FR)
2.0
VREG
V
Low-level input voltage
VIL (FR)
0
1.0
V
Input open voltage
VIO (FR)
VREG –
VREG
V
0.5
Hysteresis
VIS (FR)
High-level input current
IIH (FR)
VF/R = VREG
Low-level input current
IIL (FR)
VF/R = 0V
0.13
0.21
0.29
V
-10
0
10
μA
-130
-90
μA
BRSEL pin
High-level input voltage
VIH (BSEL)
2.0
VREG
V
Low-level input voltage
VIL (BSEL)
0
1.0
V
Input open voltage
VIO (BSEL)
VREG –
VREG
V
0.5
Hysteresis
VIS (BSEL)
High-level input current
IIH (BSEL)
VBSEL = VREG
Low-level input current
IIL (BSEL)
VBSEL = 0V
0.13
0.21
0.29
V
-10
0
10
μA
-130
-90
μA
CLKSEL pin
High-level input voltage
VIH (CSEL)
2.0
VREG
V
Low-level input voltage
VIL (CSEL)
0
1.0
V
Input open voltage
VIO (CSEL)
VREG –
VREG
V
0.5
Hysteresis
VIS (CSEL)
High-level input current
IIH (CSEL)
VCSEL = VREG
Low-level input current
IIL (CSEL)
VCSEL = 0V
0.13
0.21
0.29
V
-10
0
10
μA
-130
-90
μA
No.8317-4/15
LB11876
Package Dimensions
unit : mm (typ)
3247A
Pd max – Ta
7.6
19
0.5
5.6
36
Allowable power dissipation, Pd max – W
2.0
1
18
0.2
(1.5)
1.7max
0.3
15.0
Specified circuit board : 114.3×76.1×1.6mm3
glass epoxy board
1.5
1.36W
1.0
0.62W
0.5
0.347W
0
– 20
(0.7)
0
20
40
60
80
100
Ambient temperature, Ta – °C
0.1
0.8
0.761W
Independent IC
SANYO : SSOP36(275mil)
Three-Phase Logic Truth Table (The input "H" state is the state where IN+ > IN-)
F/R= "L"
F/R ="H"
Output
IN1
IN2
IN3
IN1
IN2
IN3
Source
1
H
L
H
L
H
L
VH
UL
2
H
L
L
L
H
H
WH
UL
3
H
H
L
L
L
H
WH
VL
4
L
H
L
H
L
H
UH
VL
5
L
H
H
H
L
L
UH
WL
6
L
L
H
H
H
L
VH
WL
S/S pin
Sink
BRSEL pin
Input state
State
Input state
High or open
Stop
High or open
During deceleration
Free running
Low
Start
Low
Short-circuit braking
CLKSEL pin
Input state
Clock divisor
High or open
1
Low
2
fFG = fCLK ÷ divisor
No.8317-5/15
LB11876
FGIN+
FGIN-
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
UL
UH
VL
VH
WL
WH
RF
RFGND
GND
VCC
Pin Assignment
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
FGS
LD
S/S
CLKSEL
BRSEL
F/R
PD
EI
EO
TOC
NC
PWM
CLD
CSD
VREG
V13
LVSD
LB11876
Top view
Pin Functions
Pin No.
Pin
1
CLK
Description
Equivalent Circuit
External clock signal input
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
This pin goes to the high level when open.
50kΩ
Hysteresis : about 0.21V
f = 10kHz (maximum)
5kΩ
1
2
FGS
FG Schmitt trigger output
This is an open-collector output.
VREG
2
3
LD
Phase lock detection output
This output goes to the on state (low-level output) in
VREG
the phase locked state.
This is an open-collector output.
3
Continued on next page.
No.8317-6/15
LB11876
Continued from preceding page.
Pin No.
Pin
4
S/S
Description
Equivalent Circuit
Start/stop control
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
This pin goes to the high level when open.
50kΩ
A low level specifies the start state.
Hysteresis : about 0.21V
5kΩ
4
5
CLK
Clock divisor selection
SEL
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
This pin goes to the high level when open.
50kΩ
A low level specifies a divisor of two, and a high level
specifies a divisor of 1.
5kΩ
Hysteresis : about 0.21V
6
BR
Deceleration (braking) control selection
SEL
Low : 0V to 1.0V
5
VREG
High : 2.0V to VREG
This pin goes to the high level when open.
50kΩ
A low level specifies short-circuit braking, and a high
level or open specifies free running operation.
5kΩ
Hysteresis : about 0.21V
7
F/R
6
Forward/reverse selection
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
This pin goes to the high level when open.
A low level specifies forward operation.
Hysteresis : about 0.21V
50kΩ
5kΩ
7
Continued on next page.
No.8317-7/15
LB11876
Continued from preceding page.
Pin No.
Pin
8
PD
Description
Equivalent Circuit
Phase comparator output
VREG
The phase error is converted to a pulse duty and
output from this pin.
8
9
EI
Error amplifier input
VREG
300Ω
9
10
EO
Error amplifier output
VREG
10
40kΩ
11
TOC
Torque command input
VREG
This pin is normally connected to the EO pin.
When the TOC voltage falls, the UH, VH, and WH on
duty is increased.
200Ω
11
12
NC
Since this pin is not connected to any internal circuits,
it may be used as a connection point.
Continued on next page.
No.8317-8/15
LB11876
Continued from preceding page.
Pin No.
Pin
13
PWM
Description
Equivalent Circuit
Sets the PWM oscillator frequency.
Connect a capacitor between this pin and ground.
VREG
A 620pF capacitor sets the oscillator frequency to be
about 50kHz.
200Ω
13
1kΩ
14
CLD
Phase lock signal mask time setting
A mask time of about 90ms can be set up by
VREG
connected a capacitor (about 0.1μF) between this pin
and ground.Leave this pin open if there is no need to
mask the phase lock signal.
300Ω
14
15
CSD
Constraint protection circuit operating time setting and
initialization pulse setting
VREG
Reset circuit
A protection circuit operating time of about 1 seconds
can be set up by connecting a capacitor (about
0.068μF) between this pin and ground. Connect both a
capacitor and a resistor (about 220kΩ and 4700pF) in
300Ω
parallel between this pin and ground if this protection
15
circuit is not used.
16
VREG
Stabilized power supply output (5V output)
VREG
Connect a capacitor between this pin and ground for
power supply stabilization.
(About 0.1μF)
16
Continued on next page.
No.8317-9/15
LB11876
Continued from preceding page.
Pin No.
Pin
17
V13
18
LVSD
Description
Equivalent Circuit
13V shunt regulator output
17
Undervoltage protection detection
VCC
If a power supply voltage of 5V or over is to be
detected, connect a Zener diode in series to set the
detection voltage.
19
VCC
18
Power supply. Connect a capacitor between this pin
and ground for power supply stabilization.
20
GND
21
RF
GND
Ground
Output current detection reference
VREG
The external resistor Rf is connected to ground.
21
22
RF
Output current detection
A resistor is connected between RF and ground.
VREG
The maximum output current IOUT is determined by
the equation IOUT = 0.25/Rf.
22
Continued on next page.
No.8317-10/15
LB11876
Continued from preceding page.
Pin No.
Pin
23
WH
Outputs (that drive external transistors)
24
WL
Duty control is applied to the UH, VH, and WH outputs.
25
VH
26
VL
27
UH
28
UL
Description
Equivalent Circuit
VCC
23 24 25
50kΩ
29
IN3-
Hall sensor inputs
30
IN3+
"H" is the state where IN+ > IN-, and "L" is the reverse
31
IN2-
state.
32
IN2+
If noise on the Hall sensor signals is a problem,
33
IN1-
connect capacitors between the IN+ and IN- inputs.
34
IN1+
26 27 28
VCC
500Ω
500Ω
29 31 33
30 32 34
35
FGIN-
FG input
36
FGIN+
If noise on the FG signal is a problem, the input signal
VCC
can be filtered with a capacitor or a capacitor plus
resistor.
500Ω
35
500Ω
36
No.8317-11/15
LB11876
Internal Equivalent Circuit Block Diagram and External Reference Circuit
(Application example)
Hall sensor, FET output
24V single supply
VREG
CLD
LD
PD
EI
LD
mask
LD
FGIN-
VREG
FGIN+
FG
filter
+
-
EO
+
FGS
FGS
TOC
CLKSEL
CLK
SEL
24V
PLL
LVSD
1/2
DEV
LVSD
TSD
CLK
CLK
COMP
V13
V13
PWM
VCC
PWM
OSC
VREG
VREG
S/S
S/S
UL
F/R
F/R
UH
PRI
BRSEL
CSD
BR
SEL
CSD
OSC
VL
Logic
driver
VH
Hall sensor
logic
WL
WH
CURR
LIM
Hall sensor hysteresis amplifier
IN1+ IN1- IN2+ IN2- IN3+ IN3-
GND
RF
RFGND
VCC
No.8317-12/15
LB11876
LB11876 Overview
1. Speed control circuit
Since the LB11876 adopts PLL speed control, it provides precise, low-jitter, and stable motor operation. This PLL
circuit compares the falling edge of the CLK signal with the FG signal (the falling edges of the FGIN+ or FGS output)
and controls motor operation based on the difference.
The FG servo frequency during this control operation is controlled by the frequency given by the following formula
which is based on the divisor selected by the clock input frequency (fCLK) and the CLKSEL pin.
fFG (servo) = fCLK ÷ <divisor>
2. Output drive circuit
To minimize the power loss in the output, the LB11876 adopts direct PWM drive. The output transistors, which are
external, are always saturated when on and the motor drive power is adjusted by changing the duty with which the
output is on.
The PWM switching is performed with the UH, VH, and WH outputs. Either high side or low side switching can be
selected by the way the output transistors are connected.
3. Current limiter circuit
The current limiter circuit limits the drive current to a current determined by the equation I = VRF/RF, where VRF =
0.25V (typical) and Rf is the current detection resistor. The limiting operation works by reducing other output on duty
to suppress the drive current.
Detection with excellent precision can be acquired by connecting the RF and RFGND pin lines to points as close as
possible to the ends of the current detection resistor (Rf).
4. Reference clock
Care must be taken to assure that no noise due to chattering or other problems appears on the externally input clock
signal. While the input circuit is designed with hysteresis, noise must be rejected by, for example, inserting capacitors
in the clock line if noise problems occur.
If the application is to be started in the state where there is no reference clock input signal, the motor will turn
somewhat and then drive will be turned off.
5. PWM frequency
The PWM frequency is determined by the capacitance of the capacitor (C) connected to the PWM pin.
fPWM ≈ 1/(30000 × C)
If a 620pF capacitor is used, the circuit will oscillate at about 50kHz. If the PWM frequency is too low the motor will
emit switching noise, and if it is too high the power loss in the output will increase. A frequency in the range 30kHz to
100kHz is desirable. This capacitor must be connected between this pin and the GND pin by lines that are as short as
possible to make this circuit immune to noise.
6. Hall sensor input signals
To prevent noise problems, the Hall sensor input signals should have an amplitude of at least 100mV. If the output
waveforms (during phase switching) are disrupted by noise, this must be prevented by connecting capacitors across the
inputs.
If the outputs from a Hall sensor IC are input, holding one side of the inputs (either the + or - side) at a voltage within
the common-mode input range for direct Hall sensor signal input will allow the other side to be used as 0V to VCC
input.
7. FG input signal
Normally, one of the Hall sensor signals is used as the FG input signal. if noise is a problem, the input signal must be
filtered with a capacitor or a capacitor plus resistor.
No.8317-13/15
LB11876
8. Constraint protection circuit
The LB11876 includes a built-in constraint protection circuit to protect the IC and the motor if the motor is physically
constrained from turning. If one Hall sensor input signals do not switch states for a period in excess of a certain fixed
time in the start state, the PWM drive side output is turned off. The time is set by the capacitor connected to the CSD
pin.
Set time (seconds) ≈ 15.4 × C (μF)
If a 0.068µF capacitor is used, the protection time will be about 1.05 seconds. (If one Hall sensor input signal period
becomes longer than this time, the PWM drive side output is turned off.) This set time must have a certain amount of
margin with respect to the motor startup time. This protection circuit will not operate during deceleration due to
switching the clock frequency. The constraint protection state can be cleared by either switching to the stop state or
turning the power off and then on again.
Since the CSD pin also functions as the initial reset pulse generation pin, connecting this pin to ground will reset the
logic circuits and make speed control operation impossible. Therefore, if the constraint protection circuit is not used,
this pin must be connected to ground by a resistor of about 220kΩ and a capacitor of about 4700pF connected in
parallel.
9. Undervoltage protection circuit
The LB11876 includes a undervoltage protection circuit to prevent incorrect operation when power is first applied or
when the power supply voltage falls. The LVSD pin turns the PWM drive side output off at voltages under about 3.7V
(typical), and clears the protection state when the voltage rises above about 4.2V (typical). An arbitrary operating
voltage can be set by adding an external Zener diode.
Note that the maximum applied voltage for the LVSD pin is 18V.
10. Phase lock signal
(1) Phase lock range
: Since this IC does not have a speed system counter, the speed error range in the
phase locked state cannot be determined by the IC characteristics alone. (This is because the range is affected by the
acceleration with changes in the FG frequency.) If it is necessary to stipulate this in conjunction with a motor, it will
be necessary to measure the range with the actual motor state. Since speed errors occur easily in states where the FG
acceleration is large, it is thought that the lock pull-in time at startup and the unlock time due to clock switching will
be the cases where the speed error is the largest.
(2) Phase lock signal mask function : It is possible to assure that the lock signal is output in stable states by masking the
short-term low levels due to hunting during lock pull-in. Note, however, that the lock signal output will be delayed
by the amount of the mask time. The mask time is set by the capacitor connected between the CLD pin and ground.
Mask time (seconds) ≈ 0.9 × C (μF)
When a 0.1µF capacitor is used, the mask time will be about 90ms. If full masking is required, the mask time must
be set with an adequate margin. Leave the CLD pin open if masking is not required.
11. Power supply stabilization
(1) VCC
: Since this IC is used in switching drive applications with large output currents,
the power supply line is easily disrupted.
Therefore it is necessary to connect an adequately large capacitor between the VCC pin and ground. The capacitor
ground side should be located as close to the IC GND pin as possible.
Since the power supply line is most easily disrupted during lock pull-in at high speeds, designers must analyze this
case carefully and select an adequately large capacitor.
Since the power supply line is particularly susceptible to disruption if a diode is inserted in the power supply line to
prevent destruction of the IC by reverse connection, an even larger capacitor must be selected in this case.
(2) 13V regulator
: When implementing a motor driver circuit with single-voltage power supply
specifications and a voltage that is outside the power supply voltage range of this IC, the supply voltage required by
this IC (approx. 13V) can be created using the V13 pin. The V13 pin circuit is a shunt regulator and can generate a
13V level by supplying current through an external resistor. A stabilized voltage is generating by setting the current
to a level in the range 0.5mA to 4mA. An external transistor with a current capacity of over 80mA (ICC + Hall
sensor bias current + output source current) and a voltage handling capacity higher than the motor supply voltage
must be selected. Since heat generation in the transistor may become a problem, heat dissipation must be provided
by the package.
(3) 5V regulator
: Connect a capacitor with a value over 0.1µF to stabilize the VREG voltage,
which is the IC's control circuit power supply. That capacitor's ground side must be connected as close as possible
to the IC ground.
No.8317-14/15
LB11876
12. Power saving circuit
This IC goes into a power saving state in which current drain is reduced when set to the stop state. This power saving
state is implemented by cutting the bias current to most of the circuits in the IC. The 5V regulator output, however, is
still output when the IC is in the power saving state.
13. Error amplifier system components
The external components for the error amplifier block must be located as close as possible to the IC to minimize the
influence of noise. These components must also be located as far from the motor as possible.
14. Forward/reverse switching
In principle, forward/reverse switching must be performed with the motor in the stopped state.
This IC does provide circuit workarounds for handling the through currents that occur during switching if the direction
is switched while the motor is turning. However, care is required with respect to lifting of the motor supply voltage
during this switching, since the motor current will return to the power supply during brief instants. If this becomes a
problem, the size of the capacitor connected between the power supply line and ground must be increased.
If the motor current after switching exceeds the current limit value, the PWM drive side output will be turned off.
However, the opposite side output will go to the short-circuit braking state and a current determined by the motor
induced voltage and the coil resistance. This current must be held under the current rating of the output transistors used.
(This aspect requires more care the faster the motor speed at which forward/reverse switching occurs.)
15. Brake switching
Either free running or short-circuit braking can be selected with the BRSEL pin.
The short-circuit braking mode adopts a form in which all phases of the PWM drive side output transistors are turned
on (all phases of the reverse side transistors are turned off). Care is required, since the current limiter function does not
operate during braking. During braking, the output circuits go to a shorted state with 100% duty. The current that flows
in the output transistors during braking is determined by the motor induced voltage and the coil resistance. This current
must be held under the current rating of the output transistors used. (This aspect requires more care the faster the motor
speed at which braking occurs.)
16. NC pins
Since the NC pins are electrically open, they can be used for intermediate wiring connections without problem.
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.8317-15/15
Similar pages