CAT24AA16 D

CAT24AA16
16-Kb I2C CMOS Serial
EEPROM
Description
The CAT24AA16 is a 16−Kb CMOS Serial EEPROM device
internally organized as 2048x8 bits.
The device features a 16−byte page write buffer and supports
100 kHz, 400 kHz and 1 MHz I2C protocols.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
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SOIC−8
W SUFFIX
CASE 751BD
TSOT−23
TB SUFFIX
CASE 419AE
Features
•
•
•
•
•
•
•
•
•
•
•
Standard and Fast I2C Protocol Compatible
Supports 1 MHz Clock Frequency
1.7 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
This Device is Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
PIN CONFIGURATIONS
SOIC
NC
1
8
VCC
NC
2
7
WP
NC
3
6
SCL
VSS
4
5
SDA
(Top View)
TSOT−23
SCL
1
VSS
2
SDA
3
5
WP
4
VCC
(Top View)
SCL
CAT24AA16
PIN FUNCTION
SDA
Pin Name
WP
VSS
Figure 1. Functional Symbol
Function
SDA
Serial Data Input/Output
SCL
Clock Input
WP
Write Protect
VCC
Power Supply
VSS
Ground
NC
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 1
1
Publication Order Number:
CAT24AA16/D
CAT24AA16
Table 1. ABSOLUTE MAXIMUM RATINGS
Ratings
Units
Storage Temperature
Parameters
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. REABILITY CHARACTERISTICS (Note 2)
Symbol
NEND (Note 3)
TDR
Parameter
Endurance
Min
Units
1,000,000
Program/Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. DC OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
0.5
mA
ICCW
Write Current
Write, fSCL = 400 kHz
1
mA
ISB
Standby Current
All I/O Pins at GND or VCC
1
mA
IL
I/O Pin Leakage
Pin at GND or VCC
1
mA
−0.5
VCC x 0.3
V
VCC x 0.7
VIL
Input Low Voltage
VIH
Input High Voltage
VCC + 0.5
V
VOL1
Output Low Voltage
VCC w 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 4)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 4)
Input Capacitance (Other Pins)
VIN = 0 V
6
pF
IWP (Note 5)
WP Input Current
VIN < 0.5 x VCC, VCC = 5.5 V
200
mA
VIN < 0.5 x VCC, VCC = 3.3 V
150
VIN < 0.5 x VCC, VCC = 1.8 V
100
VIN > 0.5 x VCC
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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CAT24AA16
Table 5. AC CHARACTERISTICS (Note 6) (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Standard
VCC = 1.7 V − 5.5 V
Symbol
FSCL
tHD:STA
Max
Clock Frequency
Min
100
START Condition Hold Time
Max
1 MHz
VCC = 2.5 V − 5.5 V
Min
400
Max
Units
1000
kHz
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.4
ms
tHIGH
High Period of SCL Clock
4
0.6
0.4
ms
4.7
0.6
0.25
ms
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
0
ns
tSU:DAT
Data In Setup Time
250
100
100
ns
tR (Note 7)
SDA and SCL Rise Time
tF (Note 7)
SDA and SCL Fall Time
tSU:STO
1000
Bus Free Time Between STOP and
START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
300
300
STOP Condition Setup Time
tBUF
Ti (Note 7)
300
300
ns
100
ns
4
0.6
0.25
ms
4.7
1.3
0.5
ms
3.5
100
0.9
50
Noise Pulse Filtered at SCL and SDA
Inputs
100
0.4
50
100
ms
ns
100
ns
tSU:WP
WP Setup Time
0
0
0
ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR
tPU
(Notes 7, 8)
6.
7.
8.
Min
Parameter
Fast
VCC = 1.7 V − 5.5 V
Write Cycle Time
5
5
5
ms
Power−up to Ready Mode
1
1
1
ms
Test conditions according to “AC Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
v 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC w 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT24AA16
I2C Bus Protocol
Power−On Reset (POR)
Each CAT24AA16 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pullup resistors. The Master
provides the clock to the SCL line, and the Master and Slaves
drive the SDA line. A ‘0’ is transmitted by pulling a line
LOW and a ‘1’ by releasing it HIGH. Data transfer may be
initiated only when the bus is not busy (see AC
Characteristics). During data transfer, SDA must remain
stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). A START is generated by a
HIGH to LOW transition, while a STOP is generated by a
LOW to HIGH transition. The START acts like a wake−up
call. Absent a START, no Slave will respond to the Master.
The STOP completes all commands.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and delivered on the negative
edge of SCL.
WP: When the Write Protect input pin is forced HIGH by an
external source, all write operations are inhibited. When the
pin is not driven by an external source, it is pulled LOW
internally.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The four most significant bits of the Slave
address are 1010 (Ah). The next three bits are internal
address bits, a10, a9, a8. The last bit, R/W, instructs the Slave
to either provide (1) or accept (0) data, i.e. it specifies a Read
(1) or a Write (0) operation.
Functional Description
The CAT24AA16 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24AA16
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
Acknowledge
During the 9th clock cycle following every byte sent onto
the bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
a10
a9
Figure 3. Slave Address Bits
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4
a8
R/W
CAT24AA16
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
BUS RELEASE DELAY
(RECEIVER)
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (w tSU:DAT)
ACK DELAY (v tAA)
Figure 4. Acknowledge Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 6). The STOP
starts the internal Write cycle, and while this operation is in
progress (tWR), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 7).
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24AA16 initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24AA16 is still busy
with the write operation, NoACK will be returned. If the
CAT24AA16 device has completed the internal write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24AA16 is shipped erased, i.e., all bytes are FFh.
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CAT24AA16
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a7 B a0
d7 B d0
S
T
O
P
P
S
A
C
K
SLAVE
A
C
K
A
C
K
Figure 6. Byte Write Sequence
SCL
8th Bit
SDA
ACK
Byte n
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
DATA
BYTE
n
ADDRESS
BYTE
SLAVE
ADDRESS
DATA
BYTE
n+1
S
T
O
P
DATA
BYTE
n+x
S
P
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
n=1
x v 15
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
9
a7
a0
1
8
SCL
SDA
d7
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
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6
d0
A
C
K
CAT24AA16
READ OPERATIONS
Immediate Read
sequence by sending data, the Master then creates a START
condition and broadcasts a Slave address with the R/W bit
set to ‘1’. The Slave responds with ACK after every byte sent
by the Master and then sends out data residing at the selected
address. After receiving the data, the Master responds with
NoACK and then terminates the session by creating a STOP
condition on the bus (Figure 11).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends an address
byte to the Slave. Rather than completing the Byte Write
BUS ACTIVITY:
MASTER
N
O
S
T
A
R
T
S
A T
CO
K P
SLAVE
ADDRESS
P
S
SLAVE
A
C
K
SCL
8
9
SDA
8th Bit
DATA
BYTE
NO ACK
DATA OUT
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
SLAVE
ADDRESS
N
O
S
T
A
R
T
S
A T
CO
K P
SLAVE
ADDRESS
S
S
A
C
K
SLAVE
P
A
C
K
A
C
K
DATA
BYTE
Figure 11. Selective Read Sequence
N
O
BUS ACTIVITY:
MASTER
A
C
K
SLAVE
ADDRESS
A
C
K
S
AT
CO
KP
A
C
K
P
SLAVE
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
Figure 12. Sequential Read Sequence
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7
DATA
BYTE
n+x
CAT24AA16
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
E1
E
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT24AA16
PACKAGE DIMENSIONS
TSOT−23, 5 LEAD
CASE 419AE−01
ISSUE O
SYMBOL
D
MIN
NOM
A
e
E1
MAX
1.00
A1
0.01
0.05
0.10
A2
0.80
0.87
0.90
b
0.30
c
0.12
0.45
0.15
D
2.90 BSC
E
2.80 BSC
E1
1.60 BSC
e
0.95 TYP
E
L
0.30
L1
0.40
0.20
0.50
0.60 REF
L2
0.25 BSC
0º
θ
8º
TOP VIEW
A2 A
b
q
L
A1
c
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
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L2
CAT24AA16
Example of Ordering Information
Prefix
Device #
CAT
24AA16
Suffix
TD
I
−G
Temperature Range
Company ID
I = Industrial (−40°C to +85°C)
Product Number
24AA16
T3
Lead Finish
G: NiPdAu
Blank: Matte−Tin
Tape & Reel
T: Tape & Reel
3: 3,000 Units / Reel
10: 10,000 Units / Reel
(Note 12)
Package
TD: TSOT−23 5−Lead
W: SOIC 8−Lead
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10. The standard lead finish is NiPdAu.
11. The device used in the above example is a CAT24AA16TDI−GT3 (TSOT−23 5−Lead, Industrial Temperature, NiPdAu, Tape & Reel,
3,000/Reel).
12. The 10,000/Reel option is only available for the TSOT−23 5−Lead package.
13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
14. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
CAT24AA16/D