CAT24AA01 D

CAT24AA01, CAT24AA02
1-Kb and 2-Kb I2C CMOS
Serial EEPROM
Description
The CAT24AA01/24AA02 are 1−Kb and 2−Kb CMOS Serial
EEPROM devices internally organized as 128x8/256x8 bits.
They feature a 16−byte page write buffer and support the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocols.
In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02
have no external address pins, and are therefore suitable in
applications that require a single CAT24AA01/02 on the I 2C bus.
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TSOT−23
TD SUFFIX
CASE 419AE
Features
•
•
•
•
•
•
•
•
•
•
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATIONS
TSOT−23
SCL
1
VSS
2
SDA
3
5
WP
4
VCC
(Top View)
MARKING DIAGRAM
VCC
RSYM
SCL
CAT24AA01
CAT24AA02
SDA
RS = Device Code
Y
= Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
WP
VSS
PIN FUNCTION
Figure 1. Functional Symbol
Pin Name
Function
SDA
Serial Data/Address
SCL
Clock Input
WP
Write Protect
VCC
Power Supply
VSS
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 5
1
Publication Order Number:
CAT24AA01/D
CAT24AA01, CAT24AA02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. REABILITY CHARACTERISTICS (Note 2)
Symbol
NEND (Note 3)
TDR
Parameter
Endurance
Data Retention
Min
Units
1,000,000
Program/Erase Cycles
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
ICCR
Read Current
Read, fSCL = 400 kHz
ICCW
Min
Max
Units
0.5
mA
Write Current
Write
1
mA
ISB
Standby Current
All I/O Pins at GND or VCC
1
mA
IL
I/O Pin Leakage
Pin at GND or VCC
1
mA
VIL
Input Low Voltage
−0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 2)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 2)
Input Capacitance (other pins)
VIN = 0 V
6
pF
IWP (Note 4)
WP Input Current
VIN < VIH
100
mA
VIN > VIH
1
4. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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2
CAT24AA01, CAT24AA02
Table 5. A.C. CHARACTERISTICS (Note 5) (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
FSCL
tHD:STA
Fast
1 MHz
VCC = 1.7 V – 5.5 V
VCC = 2.5 V – 5.5 V
Min
Parameter
Symbol
Standard
VCC = 1.7 V – 5.5 V
Clock Frequency
Max
Min
100
START Condition Hold Time
Max
Min
400
Max
Units
1000
kHz
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.5
ms
tHIGH
High Period of SCL Clock
4
0.6
0.5
ms
4.7
0.6
0.25
ms
0
0
ns
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
tSU:DAT
Data In Setup Time
250
tR
(Note 6)
SDA and SCL Rise Time
1000
300
300
ns
tF
(Note 6)
SDA and SCL Fall Time
300
300
100
ns
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between
STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti
(Note 6)
ns
0.6
0.25
ms
4.7
1.3
0.5
ms
3.5
100
Noise Pulse Filtered at
SCL and SDA Inputs
0.9
50
100
WP Setup Time
0
tHD:WP
WP Hold Time
2.5
tPU
(Notes 6, 7)
100
4
tSU:WP
tWR
100
0.4
50
100
0
ns
100
ns
ms
0
2.5
ms
ms
1
Write Cycle Time
5
5
5
ms
Power−up to Ready Mode
1
1
1
ms
5. Test conditions according to “A.C. Test Conditions” table.
6. Tested initially and after a design or process change that affects this parameter.
7. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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3
CAT24AA01, CAT24AA02
I2C BUS PROTOCOL
Power−On Reset (POR)
Each CAT24AA01/02 incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and the Master
and Slaves drive the SDA line. A ‘0’ is transmitted by
pulling a line LOW and a ‘1’ by releasing it HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). A START is generated by a
HIGH to LOW transition, while a STOP is generated by a
LOW to HIGH transition. The START acts like a wake−up
call. Absent a START, no Slave will respond to the Master.
The STOP completes all commands.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and delivered on the negative
edge of SCL.
WP: When the Write Protect input pin is forced HIGH by an
external source, all write operations are inhibited. When the
pin is not driven by an external source, it is pulled LOW
internally.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The four most significant bits of the Slave
address are 1010 (Ah).
For the CAT24AA01/02 the next three bits must be 000.
The last bit, R/W, instructs the Slave to either provide (1)
or accept (0) data, i.e. it signals a Read (1) or a Write (0)
request.
Functional Description
The CAT24AA01/02 supports the Inter−Integrated
Circuit (I2C) Bus protocol. The protocol relies on the use of
a Master device, which provides the clock and directs bus
traffic, and Slave devices which execute requests. The
CAT24AA01/02 operates as a Slave device. Both Master
and Slave can transmit or receive, but only the Master can
assign those roles.
Acknowledge
During the 9th clock cycle following every byte sent onto
the bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
0
0
0
R/W
Figure 3. Slave Address Bits
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4
CAT24AA01, CAT24AA02
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
BUS RELEASE DELAY (RECEIVER)
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tHD:DAT
tSU:STA
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 5). The STOP
starts the internal Write cycle, and while this operation is in
progress (tWR), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 6).
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 8). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 7). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Delivery State
The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh.
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5
CAT24AA01, CAT24AA02
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a7 ÷ a 0
d7 ÷ d0
S
T
O
P
P
S
A
C
K
SLAVE
A
C
K
A
C
K
Figure 6. Byte Write Sequence
SCL
8th Bit
Byte n
SDA
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
BUS ACTIVITY: S
T
A
MASTER R
T
DATA
BYTE
n
ADDRESS
BYTE
SLAVE
ADDRESS
DATA
BYTE
n+1
DATA
BYTE
n+x
S
T
O
P
S
P
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
n =1
x v15
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
a7
a0
9
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
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6
A
C
K
CAT24AA01, CAT24AA02
READ OPERATIONS
Immediate Read
condition and broadcasts a Slave address with the R/W bit
set to ‘1’. The Slave responds with ACK after every byte sent
by the Master and then sends out data residing at the selected
address. After receiving the data, the Master responds with
NoACK and then terminates the session by creating a STOP
condition on the bus (Figure 11).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory. For the CAT24AA01, the internal address
counter will not wrap around at the end of the 128 byte
memory space.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends an address
byte to the Slave. Rather than completing the Byte Write
sequence by sending data, the Master then creates a START
BUS ACTIVITY:
MASTER
N
O
S
T
A
R
T
S
AT
CO
KP
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
8
SCL
DATA
BYTE
9
8th Bit
SDA
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
S
T
A
MASTER R
T
S
T
A
R
T
BUS ACTIVITY:
ADDRESS
BYTE
SLAVE
ADDRESS
S
N
O
S
AT
CO
KP
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
A
C
K
A
C
K
DATA
BYTE
Figure 11. Selective Read Sequence
N
O
BUS ACTIVITY:
MASTER
A
C
K
SLAVE
ADDRESS
A
C
K
S
A T
CO
K P
A
C
K
P
SLAVE
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATE
BYTA
n+2
Figure 12. Sequential Read Sequence
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7
DATA
BYTE
n+x
CAT24AA01, CAT24AA02
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
MAX
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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8
CAT24AA01, CAT24AA02
PACKAGE DIMENSIONS
TSOT−23, 5 LEAD
CASE 419AE−01
ISSUE O
SYMBOL
D
MIN
NOM
A
e
E1
MAX
1.00
A1
0.01
0.05
0.10
A2
0.80
0.87
0.90
b
0.30
c
0.12
E
0.45
0.15
D
2.90 BSC
E
2.80 BSC
E1
1.60 BSC
e
0.95 TYP
L
0.30
L1
0.40
0.20
0.50
0.60 REF
L2
0.25 BSC
0º
θ
8º
TOP VIEW
A2 A
b
q
L
A1
c
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
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9
L2
CAT24AA01, CAT24AA02
Ordering Information
Device Order Number
Specific
Device
Marking
Package
Type
CAT24AA01TDI−GT3
RS
SOT−23−5
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24AA02TDI−GT3
RS
SOT−23−5
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
Temperature Range
Lead
Finish
Shipping
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10. For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
CAT24AA01/D