CM1641 D

CM1641
4-Channel Low
Capacitance Dual-Voltage
ESD Protection Array
Features
• Three Channels of Low Voltage ESD Protection
• One Channel of High Voltage ESD Protection
• Provides ESD Protection to IEC61000−4−2 Level 4:
•
•
•
•
•
•
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±8 kV Contact Discharge (Pins 1−3)
±15 kV Contact Discharge (Pin 4)
Low Channel Input Capacitance
Minimal Capacitance Change with Temperature and Voltage
High Voltage Zener Diode Protects Supply Rail
No Need for External Bypass Capacitors
Each I/O Pin can Withstand over 1000 ESD Strikes*
These Devices are Pb−Free and are RoHS Compliant
♦
♦
UDFN8
D4 SUFFIX
CASE 517BC
ELECTRICAL SCHEMATIC
VP (Internal)
CH1
TYPICAL APPLICATION
CH2
VCC
High−Speed
Data Lines
CH3
CH1 (1)
VN (8)
CH2 (2)
VN (7)
CH3 (3)
VCC (4)
DAP*
VN (6)
GND (5)
VCC
Pin 4
Pin 1
Pin 2
LV
Pin 3
HV
Pin 5
GND
Pins 6 − 8
VN
Note: Pins 5 and 6 to 8 are connected
to a common substrate.
MARKING DIAGRAM
* Die Attach Pad
on Back of Package
(Connect to Ground)
1
P41
M
G
Note: All grounds must be connected.
P41 MG
G
= CM1641−04D4
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
CM1641−04D4
UDFN−8
0.4 mm
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2011
April, 2011 − Rev. 5
1
Publication Order Number:
CM1641/D
CM1641
Table 1. PIN DESCRIPTIONS
PACKAGE / PINOUT DIAGRAMS
4−Channel, 8−Lead, UDFN−8 Package
Top View
(Pins Down View)
Pin
Name
Type
Description
1
CH1
I/O
LV Low−capacitance ESD Channel
2
CH2
I/O
LV Low−capacitance ESD Channel
3
CH3
I/O
LV Low−capacitance ESD Channel
4
VCC
HV VDD
5
GND
−
Ground
6
VN
−
Negative Voltage Supply Rail
7
VN
−
Negative Voltage Supply Rail
8
VN
−
Negative Voltage Supply Rail
DAP
GND
−
Die Attach Pad (Ground)
Pin 1
Marking
HV ESD Channel
Bottom View
(Pins Up View)
8 7 6 5
1 2 3 4
P41
DAP
1 2 3 4
8 7 6 5
CM1641−04D4
8−Lead UDFN Package
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Units
DC Voltage on Low−Voltage Pins
Parameter
6.0
V
DC Voltage on High−Voltage Pins (VCCpin)
14.5
V
−65 to +150
°C
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Rating
Units
–40 to +85
°C
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Conditions
Min
Typ
Max
Units
LV Diode Reverse Voltage (Positive Voltage)
IF = 10 mA, TA = 25°C
6.8
8.2
9.2
V
LV Diode Forward Voltage (Negative Voltage)
IF = 10 mA, TA = 25°C
−1.05
−0.90
−0.60
LV Channel Leakage Current
TA = −30°C to 65°C, VIN = 3.3 V
VN = 0 V
LV Channel Input Capacitance
At 1 MHz, VN = 0 V, VIN = 1.65 V
1.2
LV Channel Input Capacitance Matching
At 1 MHz, VN = 0 V, VIN = 1.65 V
0.02
HV Channel Leakage Current
TA = 25°C, VCC = 11 V, VN = 0 V
0.1
CIN_HV
HV Channel Input Capacitance
At 1 MHz, VN = 0 V, VIN = 2.5 V
53
VF_HV
HV Diode Breakdown Voltage
Positive Voltage
IF = 10 mA, TA = 25°C
VESD
ESD Protection
Peak Discharge Voltage at any channel
input, in system
Contact Discharge per
IEC 61000−4−2 Standard
VF
ILEAK
CIN
DCIN
ILEAK_HV
Parameter
14.6
100
nA
1.5
pF
1.0
mA
pF
pF
17.7
V
kV
TA = 25°C
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2
±8 (Pin 1−3)
±15 (Pin 4)
CM1641
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
VCL
RDYN
Parameter
Conditions
LV Channel Clamp Voltage (Pin 1−3)
Positive Transients
Negative Transients
Dynamic Resistance
LV Channel Positive Transients
LV Channel Negative Transients
HV Channel Positive Transients
HV Channel Negative Transients
TA = 25°C, IPP = 1 A,
tP = 8/20 mS
IPP = 1 A, tP = 8/20 mS
Any I/O Pin to Ground
1. All parameters specified at TA = –40°C to +85°C unless otherwise noted.
PERFORMANCE INFORMATION
Input Capacitance (pF)
Input Channel Capacitance Performance Curves for Low Voltage Pins
Input Voltage (V)
Input Capacitance (pF)
Figure 1. Typical Variation of CIN vs. VIN
(Low Voltage Inputs, f = 1 MHz, VN = 0 V )
Temperature (°C)
Figure 2. Typical Variation of CIN vs. Temperature
(Low Voltage Inputs, f = 1 MHz, VN = 0 V )
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3
Min
Typ
+9.64
−1.75
0.72
0.59
1.20
0.36
Max
Units
V
W
CM1641
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance for Low Voltage Pins
Nominal conditions unless specified otherwise, 50 W Environment.
0 dB
−1 dB
−2 dB
INSERTION LOSS
−3 dB
−4 dB
−5 dB
−6 dB
−7 dB
−8 dB
−9 dB
−10 dB
3
10
100
1000
2000
6000
FREQUENCY (MHz)
Figure 3. Channel 1 vs. All GND Pins (0 V DC Bias)
0 dB
−1 dB
−2 dB
INSERTION LOSS
−3 dB
−4 dB
−5 dB
−6 dB
−7 dB
−8 dB
−9 dB
−10 dB
3
10
100
1000
2000
FREQUENCY (MHz)
Figure 4. Channel 2 vs. All GND Pins (0 V DC Bias)
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4
6000
CM1641
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance for Low Voltage Pins
Nominal conditions unless specified otherwise, 50 W Environment.
0 dB
−1 dB
−2 dB
INSERTION LOSS
−3 dB
−4 dB
−5 dB
−6 dB
−7 dB
−8 dB
−9 dB
−10 dB
3
10
100
1000
FREQUENCY (MHz)
Figure 5. Channel 3 vs. All GND Pins (0 V DC Bias)
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5
2000
6000
CM1641
PACKAGE DIMENSIONS
UDFN8, 1.7x1.35, 0.4P
CASE 517BC−01
ISSUE O
A
B
D
2X
0.10 C
PIN ONE
REFERENCE
2X
0.10 C
ÉÉ
ÉÉ
ÇÇ
ÉÉ
MOLD CMPD
EXPOSED Cu
A1
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.25 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A3
DETAIL B
ALTERNATE
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
TOP VIEW
A
DETAIL B
0.05 C
8X
L
L1
DETAIL A
0.05 C
NOTE 4
SIDE VIEW
DETAIL A
8X
L
(A3)
L
A1
C
SEATING
PLANE
ALTERNATE TERMINAL
CONSTRUCTIONS
D2
1
RECOMMENDED
SOLDERING FOOTPRINT*
E2
1.40
8X
8
K
e
e/2
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
1.70 BSC
1.10
1.30
1.35 BSC
0.30
0.50
0.40 BSC
0.15
−−−
0.20
0.30
−−−
0.05
8X
0.40
8X b
0.10 C A B
0.05 C
NOTE 3
PACKAGE
OUTLINE
BOTTOM VIEW
1.55
0.50
8X
1
0.25
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
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For additional information, please contact your local
Sales Representative
CM1641/D
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