ESD7104 D

ESD7104
Transient Voltage
Suppressors
Low Capacitance ESD Protection for
High Speed Data
The ESD7104 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0 and HDMI.
Features
• Low Capacitance (0.3 pF Typical, I/O to GND)
• Low ESD Clamping Voltage
• Protection for the Following IEC Standards:
•
•
MARKING
DIAGRAM
UDFN10
CASE 517BB
7M MG
G
7M
= Specific Device Code (tbd)
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
IEC 61000−4−2 (Level 4)
UL Flammability Rating of 94 V−0
This is a Pb−Free Device
N/C N/C
Typical Applications
•
•
•
•
•
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USB 3.0
eSATA 3.0
Thunderbolt (Light Peak)
HDMI 1.3/1.4
Display Port
GND N/C N/C
10
9
8
7
6
1
2
3
4
5
I/O
I/O
GND
I/O
I/O
I/O
I/O
Pin 1 Pin 2
I/O
I/O
Pin 4 Pin 5
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
GND
Pin 3
=
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device
ESD7104MUTAG
April, 2012 − Rev. 2
Shipping
UDFN10 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2012
Package
1
Publication Order Number:
ESD7104/D
ESD7104
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
Conditions
VRWM
Breakdown Voltage
Min
Typ
Max
Unit
5.0
V
I/O Pin to GND
VBR
IT = 1 mA, I/O Pin to GND
5.5
V
Reverse Leakage Current
IR
VRWM = 5 V, I/O Pin to GND
1.0
mA
Clamping Voltage (Note 1)
VC
IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)
10
V
Clamping Voltage (Note 2)
VC
IEC61000−4−2, ±8 KV Contact
Clamping Voltage (Note 3)
VC
Junction Capacitance
Junction Capacitance
See Figures 1 and 2
V
IPP = ±8 A
IPP = ±16 A
14.1
19.5
V
CJ
VR = 0 V, f = 1 MHz between I/O Pins
0.2
0.3
pF
CJ
VR = 0 V, f = 1 MHz between I/O Pins and GND
0.3
0.35
pF
80
10
70
0
60
−10
50
−20
VOLTAGE (V)
VOLTAGE (V)
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − 2008 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
40
30
20
−30
−40
−50
10
−60
0
−70
−10
−20
0
20
40
60
80
100
120
−80
−20
140
0
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 1. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
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2
140
ESD7104
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 5. 8 X 20 ms Pulse Waveform
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3
80
22
−22
20
−20
18
−18
16
−16
CURRENT (A)
CURRENT (A)
ESD7104
14
12
10
8
−14
−12
−10
−8
6
−6
4
−4
2
−2
0
0
2
4
6
8
10
12
14 16
18
20
0
22 24
0
−2
−4 −6
−8 −10 −12 −14 −16 −18 −20 −22 −24
VOLTAGE (V)
VOLTAGE (V)
Figure 6. Positive TLP I−V Curve
Figure 7. Negative TLP I−V Curve
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7104
Without ESD
With ESD7104
Figure 10. USB3.0 Eye Diagram with and without ESD7104. 5.0 Gb/s, 400 mVPP
Without ESD
With ESD7104
Figure 11. HDMI1.4 Eye Diagram with and without ESD7104. 3.4 Gb/s, 400 mVPP
Without ESD
With ESD7104
Figure 12. ESATA3.0 Eye Diagram with and without ESD7104. 6 Gb/s, 400 mVPP
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5
ESD7104
S21 INSERTION LOSS (dB)
4
ESD7104 IO−GND
2
0
−2
−4
−6
−8
−10
1.E+06
1.E+07
1.E+08
1.E+09
FREQUENCY (Hz)
Figure 13. ESD7104 Insertion Loss
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6
1.E+10
ESD7104
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
ESD7104
D−
ESD7L5.0
GND_DRAIN
D+
StdA_SSRX+
GND
StdA_SSRX−
Figure 14. USB3.0 Standard A Connector Layout Diagram
USB 3.0 Micro B
Connector
ESD7104
Vbus
D−
D+
ID
GND
ESD7104
MicB_SSTX−
MicB_SSTX+
GND_DRAIN
MicB_SSRX−
MicB_SSRX+
Figure 15. USB3.0 Micro B Connector Layout Diagram
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7
ESD7104
HDMI
Type A Connector
ESD7104
D2+
GND
D2−
D1+
GND
D1−
ESD7104
D0+
GND
D0−
CLK+
GND
CLK−
CEC
N/C (or HEC_DAT – HDMI1.4)
SCL
SDA
GND
5V
HPD (and HEC_DAT – HDMI1.4)
NUP4114
Figure 16. HDMI Layout Diagram
e S ATA
Connector
GND
A+
ESD7104
A−
GND
B−
B+
GND
Figure 17. eSATA Layout Diagram
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8
ESD7104
PACKAGE DIMENSIONS
UDFN10 2.5x1, 0.5P
CASE 517BB
ISSUE O
L
D
ÍÍÍ
ÍÍÍ
PIN ONE
REFERENCE
0.10 C
2X
2X
0.10 C
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
TOP VIEW
DETAIL B
A3
A
A1
0.08 C
A1
C
SIDE VIEW
2X
DETAIL A
b2
1
10
MOLD CMPD
EXPOSED Cu
0.10 C
10X
L
A B
10X
ÇÇÇ
ÉÉÉ
ÉÉÉ
A3
DETAIL B
DIM
A
A1
A3
b
b2
D
E
e
L
L1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
0.35
0.45
2.50 BSC
1.00 BSC
0.50 BSC
0.30
0.40
--0.05
OPTIONAL
CONSTRUCTION
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
10X
5
2X
0.50
6
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
0.45
1.30
8X
b
0.10 C A
BOTTOM VIEW
0.05 C
PACKAGE
OUTLINE
B
NOTE 3
0.50
PITCH
8X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ESD7104/D
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