ESD7504 D

ESD7504
Transient Voltage
Suppressors
Low Capacitance ESD Protection Diode
for High Speed Data Line
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The ESD7504 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0.
UDFN10
CASE 517BB
• Low Capacitance (0.55 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATION
AND SCHEMATIC
N/C N/C
Typical Applications
10
USB 3.0
eSATA 1.0/2.0/3.0
HDMI 1.3/1.4
Display Port
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
GND N/C N/C
9
8
7
6
1
2
3
4
5
I/O
I/O
GND
I/O
I/O
I/O
Pin 1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
4E MG
G
4E
= Specific Device Code (tbd)
M
= Date Code
G
= Pb−Free Package
(*Note: Microdot may be in either location)
Features
•
•
•
•
MARKING
DIAGRAM
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
Pins 3, 8
Note: Common GND − Only Minimum of 1 GND connection required
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
=
ORDERING INFORMATION
Device
ESD7504MUTAG
March, 2014 − Rev. 0
Shipping
UDFN10
(Pb−Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2014
Package
1
Publication Order Number:
ESD7504/D
ESD7504
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
IPP
Parameter
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
RDYN
Working Peak Reverse Voltage
IR
VCL VBR VRWM
VBR
Breakdown Voltage @ IT
IT
VCL
RDYN
Test Current
RDYN
V
IR
IT
Maximum Reverse Leakage Current @ VRWM
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
IPP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
VRWM
Breakdown Voltage
VBR
Conditions
IT = 1 mA, I/O Pin to GND
IR
VRWM = 3.3 V, I/O Pin to GND
Clamping Voltage
(Note 1)
VC
IEC61000−4−2, ±8 kV Contact
Clamping Voltage
TLP (Note 2)
See Figures 5 through 6
VC
IPP = 8 A
IPP = −8 A
IPP = 16 A
IPP = −16 A
CJ
Typ
4.0
5.0
Max
Unit
3.3
V
I/O Pin to GND
Reverse Leakage Current
Junction Capacitance
Min
V
1.0
mA
See Figures 1 and 2
V
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
10.2
−4.5
V
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
13.7
−8.1
VR = 0 V, f = 1 MHz between I/O Pins and GND
0.55
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 3 and 4 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
10
80
0
70
−10
60
−20
VOLTAGE (V)
VOLTAGE (V)
90
50
40
30
20
−30
−40
−50
−60
10
−70
0
−80
−10
−20
0
20
40
60
80
100
120
−90
−20
140
0
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 1. IEC61000−4−2 +8 kV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 kV Contact
Clamping Voltage
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2
140
ESD7504
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
ESD7504
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 5. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 6 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 5. Simplified Schematic of a Typical TLP
System
Figure 6. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7504
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
ESD7504
D−
ESD7L5.0
GND_DRAIN
D+
StdA_SSRX+
GND
StdA_SSRX−
Black = Top layer
Red = Other layer
Figure 7. USB3.0 Layout Diagram
• Make sure to use differential design methodology and
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
♦ In USB 3.0 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes as shown in Figure 8.
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
Figure 8. USB 3.0 Connection Diagram
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5
ESD7504
PACKAGE DIMENSIONS
UDFN10 2.5x1, 0.5P
CASE 517BB
ISSUE O
L
D
ÍÍÍ
ÍÍÍ
PIN ONE
REFERENCE
0.10 C
2X
2X
0.10 C
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
TOP VIEW
DETAIL B
A3
A
A1
0.08 C
A1
C
SIDE VIEW
2X
DETAIL A
b2
1
10
MOLD CMPD
EXPOSED Cu
0.10 C
10X
L
A B
10X
ÇÇÇ
ÉÉÉ
ÉÉÉ
A3
DETAIL B
DIM
A
A1
A3
b
b2
D
E
e
L
L1
MILLIMETERS
MIN
MAX
0.55
0.45
0.05
0.00
0.13 REF
0.25
0.15
0.45
0.35
2.50 BSC
1.00 BSC
0.50 BSC
0.30
0.40
--0.05
OPTIONAL
CONSTRUCTION
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
10X
5
2X
0.50
6
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
0.45
1.30
8X
b
0.10 C A
BOTTOM VIEW
0.05 C
PACKAGE
OUTLINE
B
NOTE 3
0.50
PITCH
8X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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6
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
ESD7504/D
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