MC10E137 D

MC10E137, MC100E137
5 VECL 8-Bit Ripple Counter
Description
The MC10E/100E137 is a very high speed binary ripple counter. The
two least significant bits were designed with very fast edge rates while
the more significant bits maintain standard ECLinPS™ output edge
rates. This allows the counter to operate at very high frequencies while
maintaining a moderate power dissipation level.
The device is ideally suited for multiple frequency clock generation
as well as a counter in a high performance ATE time measurement
board.
Both asynchronous and synchronous enables are available to
maximize the device’s flexibility for various applications. The
asynchronous enable input, A_Start, when asserted enables the counter
while overriding any synchronous enable signals. The E137 features
XORed enable inputs, EN1 and EN2, which are synchronous to the
CLK input. When only one synchronous enable is asserted the counter
becomes disabled on the next CLK transition; all outputs remain in the
previous state poised for the other synchronous enable or A_Start to be
asserted to re-enable the counter. Asserting both synchronous enables
causes the counter to become enabled on the next transition of the CLK.
If EN1 (or EN2) and CLK edges are coincident, sufficient delay has
been inserted in the CLK path (to compensate for the XOR gate delay
and the internal D-flip flop setup time) to insure that the synchronous
enable signal is clocked correctly, hence, the counter is disabled.
All input pins left open will be pulled LOW via an input pulldown
resistor. Therefore, do not leave the differential CLK inputs open.
Doing so causes the current source transistor of the input clock gate to
become saturated, thus upsetting the internal bias regulators and
jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to an all zero state
upon assertion.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE137FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Features
•
•
•
•
•
•
•
•
• ESD Protection: Human Body Model: > 2 kV,
Differential Clock Input and Data Output Pins
VBB Output for Single-Ended Use
Synchronous and Asynchronous Enable Pins
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pull−down Resistors
Transistor Count = 330 devices
•
•
•
•
Machine Model: > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC10E137/D
MC10E137, MC100E137
Q7
Q6
Q6
VCCO
Q5
Q5
25
24
23
22
21
20
19
Table 1. PIN DESCRIPTION
18
Q4
27
17
Q4
28
16
VCC
A_Start
26
EN1
EN2
VEE
Q7
Pinout: 28-Lead PLCC
(Top View)
1
Q3
15
CLK
2
14
Q3
CLK
3
13
Q2
4
12
Q2
VBB
5
6
MR VCCO
7
8
9
10
11
Q0
Q0
Q1
Q1
VCCO
PIN
FUNCTION
CLK, CLK
ECL Differential Clock Inputs
Q0-Q7, Q0-Q7
ECL Differential Q Outputs
A_Start
ECL Asynchronous Enable Input
EN1, EN2
ECL Synchronous Enable Inputs
MR
Asynchronous Master Reset
VBB
Reference Voltage Output
VCC, VCCO
Positive Supply
VEE
Negative Supply
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 28−Lead Pinout
A_Start
EN1
EN2
D
CLK
CLK
CLK
CLK
VBB
R
Q0
Q0
Q1 Q1
Q7 Q7
Q
Q
Q
Q
CLK
CLK
D
R
MR
Figure 2. Logic Diagram
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2
CLK
CLK
D
Q
Q
R
CLK
CLK
D
Q
Q
R
MC10E137, MC100E137
Table 2. SEQUENTIAL TRUTH TABLE
EN1
EN2
A_Start
MR
CLK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Reset
Function
X
X
X
H
X
L
L
L
L
L
L
L
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
Stop
H
H
L
L
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Asynch Start
H
H
L
L
L
L
H
H
H
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
L
H
L
H
Stop
L
L
H
H
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
Synch Start
H
H
H
H
H
H
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
L
L
H
L
Stop
H
H
L
L
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
Reset
X
X
X
H
X
L
L
L
L
L
L
L
L
Z = Low to High Transition
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
Tsol
Wave Solder
265
265
°C
Pb
Pb−Free
VI v VCC
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E137, MC100E137
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
121
145
121
145
121
145
mA
VOH
Output HIGH Voltage (Note 2)
3980
40
70
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage (Single−Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single−Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.73
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.3
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
121
145
121
145
121
145
mA
VOH
Output HIGH Voltage (Note 5)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 5)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage (Single−Ended)
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage (Single−Ended)
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.35
−1.25
−1.31
−1.19
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
−2.8
−0.4
−2.8
−0.4
−2.8
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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4
MC10E137, MC100E137
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)
0°C
Symbol
Min
Characteristic
25°C
Typ
Max
121
145
Min
85°C
Typ
Max
121
145
Min
Typ
Max
Unit
139
167
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 8)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage (Single−Ended)
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
VBB
Output Voltage Reference
3.62
3.73
3.62
3.74
3.62
3.74
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
121
145
Min
85°C
Typ
Max
121
145
Min
Typ
Max
Unit
139
167
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 11)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common
Mode Range (Differential Configuration) (Note 12)
−3.8
−0.4
−3.8
−0.4
−3.8
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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5
MC10E137, MC100E137
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 13)
0°C
Characteristic
Min
Typ
fCOUNT
Maximum Count Frequency
1800
2200
tPLH
tPHL
Propagation Delay to Output
1300
1600
1950
2275
2625
2950
3250
3575
950
700
1700
2025
2425
2750
3125
3450
3775
4075
1325
1000
ts
Setup Time (EN1, EN2)
0
th
Hold Time (EN1, EN2)
tRR
Reset Recovery Time
25°C
Min
Typ
1800
2200
1300
1600
1950
2275
2625
2950
3250
3575
950
700
1700
2050
2450
2775
3150
3475
3800
4125
1325
1000
−150
0
300
150
MR, A_Start
400
200
tPW
Minimum Pulse Width
CLK, MR, A_Start
400
VPP
Input Voltage Swing
CLK/CLK
(Differential Configuration) (Note 14)
tJITTER
Random Clock Jitter (RMS)
tr
tf
Rise/Fall Times (20%−80%)
Symbol
CLK to Q0
CLK to Q1
CLK to Q2
CLK to Q3
CLK to Q4
CLK to Q5
CLK to Q6
CLK to Q7
A_Start to Q0
MR to Q0
Max
2150
2500
2925
3350
3750
4150
4450
4800
1700
1300
Min
Typ
1800
2200
1350
1650
2025
2350
2700
3050
3375
3700
950
700
1750
2100
2500
2850
3225
3550
3925
4250
1325
1000
−150
0
−150
ps
300
150
300
150
ps
400
200
400
200
2150
2500
2925
3350
3750
4150
4450
4800
1700
1300
400
0.25
1.0
150
275
1.0
150
275
2200
2550
3000
3425
3825
4250
4600
4950
1700
1300
150
275
ps
ps
1.0
<1
400
600
Unit
MHz
ps
0.25
<1
400
600
Max
400
0.25
<1
Q0,Q1
Q2 to Q7
85°C
Max
V
ps
400
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
14. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50 mV input swings.
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6
MC10E137, MC100E137
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E137FN
PLCC−28
37 Units / Rail
MC10E137FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E137FNR2
PLCC−28
500 / Tape & Reel
MC10E137FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E137FN
PLCC−28
37 Units / Rail
MC100E137FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E137FNR2
PLCC−28
500 / Tape & Reel
MC100E137FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10E137, MC100E137
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
http://onsemi.com
8
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E137, MC100E137
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC10E137/D