EMI4193 D

EMI4193
Common Mode Filter with
ESD Protection
Functional Description
The EMI4193 is an integrated common mode filter providing both
ESD protection and EMI filtering for high speed digital serial
interfaces such as HDMI or MIPI D−PHY.
The EMI4193 provides protection for two differential data line pairs
in a small RoHS−compliant WDFN16 package.
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MARKING
DIAGRAM
Features
6TMG
G
• Highly Integrated Common Mode Filter (CMF) with ESD Protection
•
•
•
•
•
•
provides protection and EMI reduction for systems using High Speed
Serial Data Lines with cost and space savings over discrete solutions
Large Differential Mode Bandwidth with Cutoff Frequency > 2 GHz
High Common Mode Stop Band Attenuation
Provides ESD Protection to IEC61000−4−2 Level 4, ±15 kV Contact
Discharge
Low Channel Input Capacitance Provides Superior Impedance
Matching Performance
Low Profile Package with Small Footprint in WDFN16 2 x 4 mm
Pb−Free Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
WDFN16
CASE 511BL
6T
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
In_1+
1
16
Out_1+
In_1−
2
15
Out_1−
GND
3
14
GND
In_2+
4
13
Out_2+
In_2−
5
12
Out_2−
GND
6
11
GND
In_3+
7
10
Out_3+
In_3−
8
9
Out_3−
Applications
• MIPI D−PHY (CSI−2, DSI, etc) in Mobile Phones and Digital Still
Cameras
1
16
2
15
4
External
(Connector) 5
13
7
10
8
9
12
Internal
(ASIC)
3, 14
ORDERING INFORMATION
Device
Package
Shipping†
EMI4193MTTAG
WDFN16
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
6, 11
Figure 1. EMI4193 Electrical Schematic
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 1
1
Publication Order Number:
EMI4193/D
EMI4193
PIN FUNCTION DESCRIPTION
Pin Name
Pin No.
Type
In_1+
1
I/O
CMF Channel 1+ to Connector (External)
Description
In_1−
2
I/O
CMF Channel 1− to Connector (External)
Out_1+
16
I/O
CMF Channel 1+ to ASIC (Internal)
Out_1−
15
I/O
CMF Channel 1− to ASIC (Internal)
In_2+
4
I/O
CMF Channel 2+ to Connector (External)
In_2−
5
I/O
CMF Channel 2− to Connector (External)
Out_2+
13
I/O
CMF Channel 2+ to ASIC (Internal)
Out_2−
12
I/O
CMF Channel 2− to ASIC (Internal)
In_3+
7
I/O
CMF Channel 3+ to Connector (External)
In_3−
8
I/O
CMF Channel 3− to Connector (External)
Out_3+
10
I/O
CMF Channel 3+ to ASIC (Internal)
CMF Channel 3− to ASIC (Internal)
Out_3−
9
I/O
GND
3, 14
GND
Ground
GND
6, 11
GND
Ground
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Operating Temperature Range
TOP
−40 to +85
°C
Storage Temperature Range
TSTG
−65 to +150
°C
ESD Discharge IEC61000−4−2 Contact Discharge
VPP
±15
kV
TL
260
°C
ILINE
100
mA
Maximum Lead Temperature for Soldering Purposes
(1/8” from Case for 10 seconds)
DC Current per Line
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
EMI4193
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Test Conditions
ILEAK
Channel Leakage Current
TA = 25°C, VIN = 5 V, GND = 0 V
Min
Typ
Unit
1.0
mA
VF
Channel Negative Voltage
TA = 25°C, IF = 10 mA
CIN
Channel Input Capacitance to Ground
(Pins 1,2,4,5,7,8 to Pins 3,6,11,14)
TA = 25°C, At 1 MHz, GND = 0 V,
VIN = 1.65 V
RCH
Channel Resistance
(Pins 1−16, 2−15, 4−13, 5−12, 7−10 & 8−9)
f3dB
Differential Mode Cut−off Frequency
50 W Source and Load Termination
Common Mode Stop Band Attenuation
@ 900 MHz
16
dB
Common Mode Impedance
@ 100 MHz
32
W
In−system ESD Withstand Voltage
a) Contact discharge per IEC 61000−4−2
standard, Level 4 (External Pins)
b) Contact discharge per IEC 61000−4−2
standard, Level 1 (Internal Pins)
(Notes 1 and 2)
TLP Clamping Voltage
(See Figure 9)
Forward IPP = 8 A
Forward IPP = 16 A
Forward IPP = −8 A
Forward IPP = −16 A
12
18
−6
−12
Dynamic Resistance
Positive Transients
Negative Transients
TA = 25°C, IPP = 1 A, tP = 8/20 ms
Any I/O pin to Ground;
Notes 1 and 3
1.36
0.6
Reverse Working Voltage
(Note 3)
Breakdown Voltage
IT = 1 mA; (Note 4)
Fatten
ZC
VESD
VCL
RDYN
VRWM
VBR
0.1
Max
1.5
V
0.8
1.3
pF
3.5
5.0
W
4.0
GHz
kV
±15
±2
5.6
V
V
V
V
5.0
V
9.0
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Standard IEC61000−4−2 with CDischarge = 150 pF, RDischarge = 330, GND grounded.
2. These measurements performed with no external capacitor.
3. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC
or continuous peak operating voltage level.
4. VBR is measured at pulse test current IT.
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3
EMI4193
TYPICAL CHARACTERISTICS
0
0
−1
−5
−2
−10
−15
−4
dB
dB
−3
−5
−20
−25
−6
−7
−30
−8
−35
−9
1E6
−40
1E7
1E8
FREQUENCY (Hz)
1E9
1E6
1E10
Figure 2. Differential Mode Attenuation vs.
Frequency
1E7
1E8
1E9
FREQUENCY (Hz)
Figure 3. Common Mode Attenuation vs.
Frequency
MIPI DSI (D−PHY)
Host
MIPI DSI (D−PHY)
Client
EMI4192
Evaluation
Board
Figure 4. MIPI D−PHY LP Mode Test Setup
Figure 5. EMI4193 MIPI D−PHY LP Mode Measured Results
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4
1E10
EMI4193
EMI4193
HDMI
source
HDMI
To
SMA
N5380A
Probe
Head
TVdd
Figure 6. EMI4193 Eye Diagram Test Setup
Figure 7. EMI4193 Measured Eye Diagram
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5
1169A
Probe
Agilent
DSO81204A
scope
EMI4193
Transmission Line Pulse (TLP) Measurements
Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a
100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in
Figure 8. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10 s
of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 9 where an 8 kV
IEC61000−4−2 current waveform is compared with TLP current pulses at 8 and 16 A. A TLP curve shows the voltage at which
the device turns on as well as how well the device clamps voltage over a range of current levels. Typical TLP I−V curves for
the EMI4193 are shown in Figure 10.
Attenuator
L
SW
50 W Coax
Cable
50 W Coax Cable
÷
IM
VM
10 MW
VC
DUT
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP System
Figure 9. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms
Figure 10. Positive and Negative TLP Waveforms
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6
EMI4193
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low
a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per
the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones
or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor
has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD
pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor
Application Notes AND8307/D and AND8308/D.
IEC61000−4−2 Waveform
IEC61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Oscilloscope
TVS
50 W
Cable
50 W
Figure 11. Diagram of ESD Test Setup
100
% OF PEAK PULSE CURRENT
ESD Gun
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 12. 8 x 20 ms Pulse Waveform
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7
80
EMI4193
Figure 13. ESD Clamping Voltage +8 kV per IEC6100−4−2 (external to internal pin)
Figure 14. ESD Clamping Voltage −8 kV per IEC6100−4−2 (external to internal pin)
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8
EMI4193
PACKAGE DIMENSIONS
WDFN16 4x2, 0.5P
CASE 511BL
ISSUE O
0.10 C
2X
PIN 1
REFERENCE
0.10 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
ÇÇÇÇ
ÇÇÇÇ
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
(A3)
DETAIL B
A
ÉÉ
ÉÉ
ÇÇ
A3
ÉÉ
ÇÇ
ÇÇ
EXPOSED Cu
TOP VIEW
0.05 C
L
L
A B
D
MOLD CMPD
A1
DIM
A
A1
A3
b
D
E
e
L
L1
DETAIL B
0.05 C
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
RECOMMENDED
MOUNTING FOOTPRINT*
DETAIL A
1
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.15
0.25
4.00 BSC
2.00 BSC
0.50 BSC
0.70
0.90
0.05
0.15
8
13X
12X
12X
0.30
1.07
L
PACKAGE
OUTLINE
0.10
MIN
2.30
9
16
e
14X
e/2
BOTTOM VIEW
1
b
0.10
M
C A B
0.05
M
C
0.45
NOTE 3
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
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Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
EMI4193/D
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