TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM HT67F488 HT67F489 Revision: V1.50 Date: ��������������� August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description.......................................................................................... 7 Selection Table.................................................................................................. 8 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 9 Pin Description............................................................................................... 10 Absolute Maximum Ratings........................................................................... 13 D.C. Characteristics........................................................................................ 13 A.C. Characteristics........................................................................................ 16 A/D Converter Electrical Characteristics...................................................... 16 LVD & LVR Electrical Characteristics........................................................... 17 Power on Reset Characteristics.................................................................... 17 System Architecture....................................................................................... 18 Clocking and Pipelining.......................................................................................................... 18 Program Counter.................................................................................................................... 19 Stack...................................................................................................................................... 20 Arithmetic and Logic Unit – ALU............................................................................................ 20 Flash Program Memory.................................................................................. 21 Structure................................................................................................................................. 21 Special Vectors...................................................................................................................... 21 Look-up Table......................................................................................................................... 22 Table Program Example......................................................................................................... 22 In Circuit Programming – ICP................................................................................................ 23 On-Chip Debug Support – OCDS.......................................................................................... 24 RAM Data Memory.......................................................................................... 25 Structure................................................................................................................................. 25 General Purpose Data Memory ............................................................................................ 25 Special Purpose Data Memory ............................................................................................. 26 Special Function Register Description......................................................... 27 Indirect Addressing Register – IAR0, IAR1, IAR2.................................................................. 27 Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H.......................................................... 27 Accumulator – ACC................................................................................................................ 28 Program Counter Low Register – PCL .................................................................................. 28 Look-up Table Registers – TBLP, TBHP, TBLH ..................................................................... 29 Status Register – STATUS .................................................................................................... 29 Rev. 1.50 2 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM EEPROM Data Memory................................................................................... 31 EEPROM Data Memory Structure......................................................................................... 31 EEPROM Registers............................................................................................................... 31 Reading Data from the EEPROM.......................................................................................... 33 Writing Data to the EEPROM................................................................................................. 33 Write Protection...................................................................................................................... 33 EEPROM Interrupt................................................................................................................. 33 Programming Considerations................................................................................................. 34 Programming Examples......................................................................................................... 34 Oscillator......................................................................................................... 35 Oscillator Overview ............................................................................................................... 35 System Clock Configurations ................................................................................................ 35 External Crystal/Ceramic Oscillator – HXT............................................................................ 36 Internal RC Oscillator – HIRC ............................................................................................... 36 External 32.768kHz Crystal Oscillator – LXT......................................................................... 37 LXT Oscillator Low Power Function ...................................................................................... 38 Internal 32kHz Oscillator – LIRC ........................................................................................... 38 Operating Modes and System Clocks ......................................................... 39 System Clocks ...................................................................................................................... 39 System Operation Modes ...................................................................................................... 40 Control Register..................................................................................................................... 41 Operating Mode Switching .................................................................................................... 43 Standby Current Considerations ........................................................................................... 47 Wake-up ................................................................................................................................ 47 Watchdog Timer.............................................................................................. 48 Watchdog Timer Clock Source............................................................................................... 48 Watchdog Timer Control Register.......................................................................................... 48 Watchdog Timer Operation.................................................................................................... 49 Reset and Initialisation................................................................................... 50 Reset Functions .................................................................................................................... 50 Reset Initial Conditions ......................................................................................................... 53 Input/Output Ports ......................................................................................... 56 Pull-high Resistors................................................................................................................. 57 Port A Wake-up...................................................................................................................... 57 I/O Port Control Registers...................................................................................................... 57 Pin-shared Functions............................................................................................................. 57 I/O Pin Structures................................................................................................................... 58 Programming Considerations ................................................................................................ 59 Rev. 1.50 3 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Timer Modules – TM....................................................................................... 60 Introduction............................................................................................................................ 60 TM Operation......................................................................................................................... 60 TM Clock Source.................................................................................................................... 61 TM Interrupts.......................................................................................................................... 61 TM External Pins ................................................................................................................... 61 TM Input/Output Pin Control Registers.................................................................................. 61 Programming Considerations................................................................................................. 63 Periodic Type TM – PTM................................................................................. 64 Periodic TM Operation........................................................................................................... 64 Periodic Type TM Register Description.................................................................................. 65 Periodic Type TM Operating Modes....................................................................................... 70 Compact Type TM – CTM............................................................................... 79 Compact TM Operation ......................................................................................................... 79 Compact Type TM Register Description................................................................................ 80 Compact Type TM Operating Modes..................................................................................... 84 Analog to Digital Converter – ADC................................................................ 90 A/D Overview......................................................................................................................... 90 A/D Converter Register Description....................................................................................... 90 A/D Converter Data Registers – ADRL, ADRH...................................................................... 91 A/D Converter Control Registers – ADCR0, ADCR1, ACERL, ACERH................................. 91 A/D Operation ....................................................................................................................... 95 A/D Input Pins........................................................................................................................ 96 Summary of A/D Conversion Steps ....................................................................................... 97 Programming Considerations................................................................................................. 98 A/D Transfer Function............................................................................................................ 98 A/D Programming Example.................................................................................................... 99 LCD Display Memory.................................................................................... 101 LCD Driver Output................................................................................................................ 101 LCD Control Register........................................................................................................... 102 LCD Waveform..................................................................................................................... 106 LED Driver..................................................................................................... 109 LED Driver Operation........................................................................................................... 109 LED Driver Register............................................................................................................. 109 UART Interface...............................................................................................110 UART External Pin Interfacing..............................................................................................110 UART Data Transfer Scheme...............................................................................................111 UART Status and Control Registers.....................................................................................111 Baud Rate Generator............................................................................................................117 UART Setup and Control......................................................................................................118 UART Transmitter................................................................................................................ 120 UART Receiver.................................................................................................................... 121 Managing Receiver Errors................................................................................................... 123 Rev. 1.50 4 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM UART Module Interrupt Structure......................................................................................... 124 Address Detect Mode........................................................................................................... 125 UART Module Power Down and Wake-up........................................................................... 125 Interrupts....................................................................................................... 127 Interrupt Registers................................................................................................................ 127 Interrupt Operation............................................................................................................... 135 External Interrupt.................................................................................................................. 137 Multi-function Interrupt......................................................................................................... 137 A/D Converter Interrupt........................................................................................................ 137 UART Interrupt..................................................................................................................... 138 Time Base Interrupt.............................................................................................................. 138 EEPROM Interrupt............................................................................................................... 139 LVD Interrupt........................................................................................................................ 140 TM Interrupts ....................................................................................................................... 140 Interrupt Wake-up Function.................................................................................................. 140 Programming Considerations............................................................................................... 141 Low Voltage Detector – LVD........................................................................ 142 LVD Register........................................................................................................................ 142 LVD Operation...................................................................................................................... 143 Configuration Options.................................................................................. 144 Application Circuits...................................................................................... 144 Instruction Set............................................................................................... 145 Instruction............................................................................................................................. 145 Instruction Timing................................................................................................................. 145 Moving and Transferring Data.............................................................................................. 145 Arithmetic Operations........................................................................................................... 145 Logical and Rotate Operations............................................................................................. 146 Branches and Control Transfer............................................................................................ 146 Bit Operations...................................................................................................................... 146 Table Read Operations........................................................................................................ 146 Other Operations.................................................................................................................. 146 Instruction Set Summary............................................................................. 147 Table Conventions................................................................................................................ 147 Instruction Definition.................................................................................... 149 Package Information.................................................................................... 159 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions............................................ 160 Rev. 1.50 5 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Features CPU Features • Operating Voltage ♦♦ fSYS = 8MHz: 2.2V~5.5V ♦♦ fSYS = 12MHz: 2.7V~5.5V • Power down and wake-up functions to reduce power consumption • Oscillators ♦♦ Internal RC – HIRC ♦♦ External Crystal - HXT ♦♦ Internal 32kHz RC – LIRC ♦♦ External 32.768kHz Crystal – LXT • Fully integrated internal 8MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Bit manipulation instruction • 16-bit Table Read Function • 63 powerful instructions • Support dual words instructions for RAM access • 8-level subroutine nesting Peripheral Features • Flash Program Memory: 4K×16 ~ 8K×16 • RAM Data Memory: 256×8 • EEPROM Memory: 64×8 (only for HT67F489) • Watchdog Timer function • 42 bidirectional I/O lines ♦♦ Inlcude LCD/LED driving output • 4 pin-shared external interrupts • Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output functions • Dual Time-Base functions for generation of fixed time interrupt signals • 10-channel 12-bit resolution A/D converter • LCD display ♦♦ 20SEG × 4COM & 20SEG × 8COM ♦♦ 1/3 or 1/4 bias • LED display: 8SEG × 8COM • Low Voltage Reset function • Low Voltage Detect function • Package type: 44-pin LQFP Rev. 1.50 6 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM General Description The HT67F488/HT67F489 series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontrollers, designed especially for applications that interface directly to analog signals, such as those from sensors. Offering users the convenience of Flash Memory multiprogramming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory (only for HT67F489) for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter function. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HIRC, HXT, LXT and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. The UART module is contained in these devices. It can support the applications such as data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery operated device communication, etc. The inclusion of both LCD and LED driver functions allows for easy and cost effective solutions in applications that require interface to these display types. The inclusion of flexible I/O programming features, Time-Base functions along with many other features enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, chargers, motor driving, industrial control, consumer products, subsystem controllers, etc. Rev. 1.50 7 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Selection Table Most features are common to all devices, the main feature distinguishing them are Memory capacity and whether EEPROM or not. The following table summarises the main features of each device. Part No. Program Memory Data Memory Data EEPROM I/O Ext. Interrupt A/D LCD Driver HT67F488 4K×16 256×8 — 42 4 12-bit×10 20×4, 20×8 HT67F489 8K×16 256×8 64×8 42 4 12-bit×10 20×4, 20×8 Part No. LED Driver Timer Module Time Base UART Stack Package HT67F488 8x8 10-bit CTM×3 10-bit PTM×1 2 √ 8 44LQFP HT67F489 8x8 10-bit CTM×3 10-bit PTM×1 2 √ 8 44LQFP Block Diagram Rev. 1.50 8 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Pin Assignment P P P P C P C P C P C P C P C P F 4 /S P F 5 /S D 7 /S C 0 /S C 1 /S 2 /S E 3 /S E 4 /S E 5 /S E 6 /S E 7 /S E E G 1 E G 1 E G E G E G G 1 G 1 G 1 G 1 G 1 G 1 6 /R 7 /T X X 0 1 2 3 4 5 6 /S E G 1 8 /IN T 1 9 /IN T 1 /T P 0 _ 2 /T C K 0 /IC P D /T P 0 _ 0 /IC P C V D D & A V D V S S & A V S P A 1 /O S C P A 3 /O S C P A P A 4 /X T P A 5 /X T 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 D 0 K A 7 8 9 P F P F 7 /S E G P A 0 /IN T P A 2 /IN T 3 1 1 2 3 2 3 3 1 4 3 0 5 S 7 2 6 1 2 2 9 6 1 P D P D P D P D P D P D P D P E P E P E P E 3 3 2 8 2 7 8 2 6 9 2 5 1 0 1 1 2 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 6 /S 5 /S 4 /S 3 /S 2 /S 1 /S 0 /S 0 /C 1 /C 2 /C 3 /C E G 6 E G 5 E G 4 E G 3 E G 2 E G 1 E G 0 O M 0 O M 1 O M 2 O M 3 P B 0 P B 1 P B 2 P B 3 P E 4 P E 5 P E 6 P B 4 P E 7 P B 5 P A 7 /A /A /A /A /A /A /A /A /A /A N 0 N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 /T /T /T /T /C /C /C /V /C C K P 3 P 2 P 1 O M O M O M R E O M 3 F 4 /T C K 1 5 /T C K 2 6 7 P P P P C P C P C P C P C P C P F 4 /S P F 5 /S D 7 /S C 0 /S C 1 /S 2 /S E 3 /S E 4 /S E 5 /S E 6 /S E 7 /S E E G 1 E G 1 E G E G E G G 1 G 1 G 1 G 1 G 1 G 1 6 /R 7 /T X X 0 1 2 3 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 0 A D 7 8 9 P F 6 /S E G 1 8 /IN T P F 7 /S E G 1 9 /IN T 1 /T P 0 _ P A 0 /IN T 2 /T C K 0 /O C D S D A /IC P D P A 2 /IN T 3 /T P 0 _ 0 /O C D S C K /IC P C V D D & A V D V S S & A V S P A 1 /O S C P A 3 /O S C P A P A 4 /X T P A 5 /X T 1 1 2 3 2 3 3 1 K 4 3 0 5 S 6 1 1 2 2 9 6 2 3 3 7 2 8 2 7 8 2 6 9 1 0 1 1 2 5 2 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 P D P D P D P D P D P D P D P E P E P E P E 6 /S 5 /S 4 /S 3 /S 2 /S 1 /S 0 /S 0 /C 1 /C 2 /C 3 /C E G E G E G E G E G E G E G 6 5 4 3 2 1 0 O M 0 O M 1 O M 2 O M 3 P B 0 P B 1 P B 2 P B 3 P E 4 P E 5 P E 6 P B 4 P E 7 P B 5 P A 7 /A /A /A /A /A /A /A /A /A /A N 0 N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 /T /T /T /T /C /C /C /V /C C K P 3 P 2 P 1 O M O M O M R E O M 3 F 9 4 /T C K 1 5 /T C K 2 6 7 Rev. 1.50 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Pin Description Pin Name PA0/INT2/TCK0/ OCDSDA/ICPDA PA1/OSC2 PA3/OSC1 PA6, PA7 PA2/INT3/TP0_0/ OCDSCK/ICPCK PA4/XT1 PA5/XT2 PB0/AN0/TCK3 PB1/AN1/TP3 PB2/AN2/TP2 PB3/AN3/TP1 PB4/AN7/VREF PB5/AN9 PC0/SEG8 PC1/SEG9 Rev. 1.50 Function OPT I/T O/T Description PA0 PAPU PAWU ST CMOS INT2 — ST — External Interrupt 2 TCK0 — ST — TM0 input OCDSDA — ST CMOS OCDS Address/Data, for EV chip only. General purpose I/O. Register enabled pull-high and wake-up. ICPDA — ST CMOS ICP Address/Data PA1, PA3, PA6, PA7 PAPU PAWU ST CMOS OSC1 OSC HXT — High frequency crystal pin OSC2 OSC HXT — High frequency crystal pin PA2 PAPU PAWU ST CMOS — General purpose I/O. Register enabled pull-high and wake-up. General purpose I/O. Register enabled pull-high and wake-up. INT3 — ST TP0_0 TMPC ST External Interrupt 3 OCDSCK — ST — OCDS Clock pin, for EV chip only. ICPCK — ST — ICP Clock pin PA4 PAPU PAWU ST CMOS XT1 FSUBC LXT — PA5 PAPU PAWU ST CMOS XT2 FSUBC — LXT CMOS TM0 I/O General purpose I/O. Register enabled pull-high and wake-up. Low frequency crystal pin General purpose I/O. Register enabled pull-high and wake-up. Low frequency crystal pin PB0 PBPU ST AN0 ACERL AN — A/D channel 0 TCK3 — ST — TM3 input PB1 PBPU ST AN1 ACERL AN CMOS General purpose I/O. Register enabled pull-high. CMOS General purpose I/O. Register enabled pull-high. — A/D channel 1 TP3 TMPC ST CMOS TM3 I/O PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-high. AN2 ACERL AN TP2 TMPC ST CMOS TM2 I/O CMOS General purpose I/O. Register enabled pull-high. PB3 PBPU ST AN3 ACERL AN — A/D channel 2 — A/D channel 3 TP1 TMPC ST CMOS TM1 I/O PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-high. AN7 ACERL AN VREF ADCR1 AN PB5 PBPU ST AN9 ACERH AN PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG8 SEGCR1 — CMOS LCD segment output PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG9 SEGCR1 — CMOS LCD segment output — A/D channel 7 — ADC reference voltage input pin CMOS General purpose I/O. Register enabled pull-high. — A/D channel 9 10 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Pin Name PC2/SEG10 PC3/SEG11 PC4/SEG12 PC5/SEG13 PC6/SEG14 PC7/SEG15 PD0/SEG0 PD1/SEG1 PD2/SEG2 PD3/SEG3 PD4/SEG4 PD5/SEG5 PD6/SEG6 PD7/SEG7 PE0/COM0 PE1/COM1 PE2/COM2 PE3/COM3 PE4/AN4/COM4/ TCK1 Rev. 1.50 Function OPT I/T O/T Description PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG10 SEGCR1 — CMOS LCD segment output PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG11 SEGCR1 — CMOS LCD segment output PC4 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG12 SEGCR1 — CMOS LCD segment output PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG13 SEGCR1 — CMOS LCD segment output PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG14 SEGCR1 — CMOS LCD segment output PC7 PCPU ST CMOS General purpose I/O. Register enabled pull-high. SEG15 SEGCR1 — CMOS LCD segment output PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG0 SEGCR0 — CMOS LCD segment output PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG1 SEGCR0 — CMOS LCD segment output PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG2 SEGCR0 — CMOS LCD segment output PD3 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG3 SEGCR0 — CMOS LCD segment output PD4 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG4 SEGCR0 — CMOS LCD segment output PD5 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG5 SEGCR0 — CMOS LCD segment output PD6 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG6 SEGCR0 — CMOS LCD segment output PD7 PDPU ST CMOS General purpose I/O. Register enabled pull-high. SEG7 SEGCR0 — CMOS LCD segment output PE0 PEPU ST CMOS General purpose I/O. Register enabled pull-high. COM0 LCDC0 — CMOS LCD common output PE1 PEPU ST CMOS General purpose I/O. Register enabled pull-high. COM1 LCDC0 — CMOS LCD common output PE2 PEPU ST CMOS General purpose I/O. Register enabled pull-high. COM2 LCDC0 — CMOS LCD common output PE3 PEPU ST CMOS General purpose I/O. Register enabled pull-high. COM3 LCDC0 — CMOS LCD common output PE4 PEPU ST CMOS General purpose I/O. Register enabled pull-high. AN4 ACERL AN COM4 LCDC0 — TCK1 — ST — A/D channel 4 CMOS LCD common output — TM1 input 11 August 13, 2014 TinyPower TM Pin Name PE5/AN5/COM5/ TCK2 PE6/AN6/COM6 PE7/AN8/COM7 PF4/SEG16/RX PF5/SEG17/TX PF6/SEG18/INT0 PF7/SEG19/ INT1/TP0_1 Function OPT I/T PE5 PEPU ST AN5 ACERL AN COM5 LCDC0 — TCK2 — ST HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM O/T Description CMOS General purpose I/O. Register enabled pull-high. — A/D channel 5 CMOS LCD common output — TM2 input PE6 PEPU ST AN6 ACERL AN CMOS General purpose I/O. Register enabled pull-high. COM6 LCDC0 — CMOS LCD common output PE7 PEPU ST CMOS General purpose I/O. Register enabled pull-high. AN8 ACERH AN COM7 LCDC0 — CMOS LCD common output — A/D channel 6 — A/D channel 8 PF4 PFPU ST CMOS General purpose I/O. Register enabled pull-high. SEG16 SEGCR2 — CMOS LCD segment output RX — ST PF5 PFPU ST CMOS General purpose I/O. Register enabled pull-high. SEG17 SEGCR2 — CMOS LCD segment output — External UART RX serial data input pin TX — — CMOS External UART TX serial data output pin PF6 PFPU ST CMOS General purpose I/O. Register enabled pull-high. SEG18 SEGCR2 — CMOS LCD segment output INT0 — ST PF7 PFPU ST CMOS General purpose I/O. Register enabled pull-high. SEG19 SEGCR2 — CMOS LCD segment output — External Interrupt 0 INT1 — ST TP0_1 TMPC ST AVDD — PWR — ADC Power Supply VDD VDD — PWR — Power Supply AVSS AVSS — PWR — ADC Ground VSS VSS — PWR — Ground AVDD Note: I/T: Input type; OP: Optional by register option PWR: Power; CMOS: CMOS output; LXT: Low frequency crystal oscillator Rev. 1.50 — External Interrupt 1 CMOS TM0 I/O O/T: Output type ST: Schmitt Trigger input AN: Analog input pin 12 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOH Total.....................................................................................................................................-80mA IOL Total...................................................................................................................................... 80mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. D.C. Characteristics Ta=25°C Symbol VDD IDD1 Parameter Operating Voltage (HXT) Operating Current, Normal Mode, fSYS=fH, fSUB=fLXT or fLIRC Test Conditions ─ 3V 5V 3V 5V 3V 5V 3V IDD2 Operating Current, Normal Mode, fH=8MHz 5V 3V 5V 3V 5V 3V 5V 3V 5V IDD3 Operating Current, Slow Mode, fSYS= fSUB (LXT, LIRC) 3V 5V 3V 5V Rev. 1.50 Min. Typ. fSYS=4MHz 2.2 ─ 5.5 V fSYS=8MHz 2.2 ─ 5.5 V fSYS=12MHz 2.7 ─ 5.5 V fSYS=16MHz 4.5 ─ 5.5 V — 1.6 2.4 mA — 3.3 5.0 mA No load, fSYS=fH/2, ADC off, WDT enable — 0.9 1.5 mA — 2.5 3.75 mA No load, fSYS=fH/4, ADC off, WDT enable — 0.7 1.0 mA — 2.0 3.0 mA No load, fSYS=fH/8, ADC off, WDT enable — 0.6 0.9 mA — 1.6 2.4 mA No load, fSYS=fH/16, ADC off, WDT enable — 0.5 0.75 mA — 1.5 2.25 mA No load, fSYS=fH/32, ADC off, WDT enable — 0.49 0.74 mA — 1.45 2.18 mA No load, fSYS=fH/64, ADC off, WDT enable — 0.47 0.71 mA — 1.4 2.1 mA No load, fSYS=LXT, ADC off, WDT enable, LXTLP=0, LVR enable — 45 75 μA — 90 140 μA No load, fSYS=LXT, ADC off, WDT enable, LXTLP=1, LVR enable — 40 70 μA — 85 135 μA No load, fSYS=LIRC, ADC off, WDT enable, LVR enable — 40 65 μA — 80 130 μA VDD Conditions No load, fH=8MHz, ADC off, WDT enable 13 Max. Unit August 13, 2014 TinyPower TM Symbol Parameter HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Test Conditions 3V IIDLE01 IDLE0 Mode Stanby Current (LXT On) 5V 3V 5V IIDLE02 IDLE0 Mode Stanby Current (LIRC On) 3V 5V 3V IIDLE03 IDLE0 Mode Stanby Current (LXT On) 5V 3V IIDLE04 IDLE0 Mode Stanby Current (LXT On) 5V 3V IIDLE05 IDLE0 Mode Stanby Current (LXT On) 5V 3V IIDLE06 Min. Typ. No load, ADC off, WDT enable, LXTLP=0 — 2 4 μA — 4 8 μA No load, ADC off, WDT enable, LXTLP=1 — 1.5 3.0 μA — 3.0 6.0 μA No load, ADC off, WDT enable — 1.5 3.0 μA — 3.0 6.0 μA No load, ADC off, WDT enable, LXTLP=1, LCD enable (RT=1170kΩ without quick charge, VLCD=VDD) — 3 6 μA — 6 12 μA No load, ADC off, WDT enable, LXTLP=1, LCD enable (RT=225kΩ without quick charge, VLCD=VDD) — 14 28 μA — 24 48 μA — 5 10 μA — 9 18 μA — 11 22 μA — 18 36 μA — 0.5 3.0 mA — 1.0 6.0 mA No load, ADC off, WDT disable — 0.2 1 μA — 0.4 2 μA No load, ADC off, WDT enable — 1.5 3.0 μA — 2.5 5.0 μA VDD IDLE0 Mode Stanby Current (LXT On) 5V 3V Conditions No load, ADC off, WDT enable, LXTLP=1, LCD enable (RT=1170kΩ with quick charge, QCT[2:0]=0, VLCD=VDD) No load, ADC off, WDT enable, LXTLP=1, LCD enable (RT=1170kΩ with quick charge, QCT[2:0]=7, VLCD=VDD) IIDLE1 IDLE1 Mode Stanby Current (LIRC On) ISLEEP0 SLEEP0 Mode Stanby Current (LXT or LIRC Off) 3V ISLEEP1 SLEEP1 Mode Stanby Current (LXT or LIRC On) 3V VIL Input Low Voltage for I/O Ports or Input Pins — — 0 — 0.3VDD V VIH Input High Voltage for I/O Ports or Input Pins — — 0.7VDD — VDD V Rev. 1.50 5V 5V 5V No load, ADC off, WDT enable, fSYS=8MHz on Max. Unit 14 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit GPIO (except for PD0~PD7 & PE0~PE7) IOL IOH I/O Port Sink Current I/O Port Source Current 3V VOL=0.1VDD 4 8 — mA 5V VOL=0.1VDD 10 20 — mA 3V VOH=0.9VDD -2 -4 — mA 5V VOH=0.9VDD -5 -10 — mA 3V VOL=0.1VDD 8 16 — mA 5V VOL=0.1VDD 20 40 — mA 3V VOH=0.9VDD -2 -4 — mA 5V VOH=0.9VDD -5 -10 — mA High Sink I/O for LED driver (PE0~PE7) IOL IOH I/O Port Sink Current I/O Port Source Current Adjustable source I/O for LED driver (PD0~PD7) IOL I/O Port Sink Current 3V VOL=0.1VDD 4 8 — mA 5V VOL=0.1VDD 10 20 — mA VOH= 0.9VDD (IOHSn[1:0]=00B, n=0~7) -2 -4 — mA VOH= 0.9VDD (IOHSn[1:0]=01B, n=0~7) -0.67 -1.33 — mA VOH= 0.9VDD (IOHSn[1:0]=10B, n=0~7) -0.5 -1 — mA VOH= 0.9VDD (IOHSn[1:0]=11B, n=0~7) -0.33 -0.66 — mA VOH= 0.9VDD (IOHSn[1:0]=00B, n=0~7) -5 -10 — mA VOH= 0.9VDD (IOHSn[1:0]=01B, n=0~7) -1.67 -3.33 — mA VOH= 0.9VDD (IOHSn[1:0]=10B, n=0~7) -1.25 -2.5 — mA VOH= 0.9VDD (IOHSn[1:0]=11B, n=0~7) -0.83 -1.67 — mA 3V IOH I/O Port Source Current 5V 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ 3V/5V — -30 RT +30 % Total I/O Port Sink Current 5V — 80 — — mA Total I/O Port Source Current 5V — -80 — — mA RPH Pull-high Resistance for I/O Ports RT LCD total bias resister ITOL ITOH Rev. 1.50 15 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM A.C. Characteristics Ta=25°C Symbol fCPU Parameter Operating Clock Test Conditions Min. Typ. Max. Unit 2.2~5.5 DC ─ 4 MHz 2.2~5.5V DC ─ 8 MHz 2.7~5.5V DC ─ 12 MHz 4.5~5.5V DC ─ 16 MHz — 8 — MHz Ta=0°C to 70°C -2% 8 +2% MHz Ta=25°C -10% 32 +10% kHz μs VDD Conditions — fSYS System Clock (HIRC) 2.2V~5.5V fHIRC System Clock (HIRC) 4.5V~5.5V fLIRC System Clock (LIRC) 5V tTIMER TCKn Input Pulse Width — — 0.3 — — tINT Interrupt Pulse Width — — 10 — — μs tEERD EEPROM Read Time 5V — — 2 4 tSYS tEEWR EEPROM Write Time 5V — — 2 4 ms — — 25 50 100 ms tRSTD System Reset Delay Time (Power On Reset, LVR Reset, WDTC/LVRC S/W Reset) System Reset Delay Time (WDT Time-out Reset) — — 8.3 16.7 33.3 ms tSST System Start-up Timer Period (Wake-up from HALT) — — fSYS=LXT/HXT — 1024 — — fSYS=HIRC — 16 — — fSYS=LIRC — 2 — tSYS Note: tSYS=1/fSYS A/D Converter Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit AVDD A/D Converter Operating Voltage — — 2.7 — 5.5 V VADI A/D Converter Input Voltage — — 0 — AVDD/VREF V VREF A/D Converter Reference Voltage — — 2 — AVDD V VBG Reference with buffer voltage — — +3% V -4 — +4 LSB -3% 1.09 DNL Differential Non-linearity 5V VREF=AVDD=VDD tADCK=0.5μs INL Integral Non-linearity 5V VREF=AVDD=VDD tADCK=0.5μs -7 — +7 LSB IADC Additional Power Consumption if A/D Converter is used 3V No load (tADCK=0.5μs) — 0.9 1.35 mA 5V No load (tADCK=0.5μs) — 1.2 1.8 mA IBG Additional Power Consumption if VBG Reference with Buffer is Used — — — 200 300 μA tADCK A/D Converter Clock Period — — 0.5 — 10 μs tADC A/D Conversion Time (Include Sample and Hold Time) — — 16 — tADCK tADS A/D Converter Sampling Time — — — 4 — tADCK tON2ST A/D Converter On-to-Start Time — — 2 — — μs tBGS VBG Turn on Stable Time — — — — 200 μs Rev. 1.50 12-bit ADC 16 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM LVD & LVR Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VLVR1 LVR Enable, 2.10V option -5% 2.10 +5% V VLVR2 LVR Enable, 2.55V option -5% 2.55 +5% V LVR Enable, 3.15V option -5% 3.15 +5% V VLVR4 LVR Enable, 3.80V option -5% 3.80 +5% V VLVD1 LVDEN=1, VLVD=2.0V -5% 2.0 +5% V VLVD2 LVDEN=1, VLVD=2.2V -5% 2.2 +5% V VLVD3 LVDEN=1, VLVD=2.4V -5% 2.4 +5% V LVDEN=1, VLVD=2.7V -5% 2.7 +5% V LVDEN=1, VLVD=3.0V -5% 3.0 +5% V VLVD6 LVDEN=1, VLVD=3.3V -5% 3.3 +5% V VLVD7 LVDEN=1, VLVD=3.6V -5% 3.6 +5% V LVDEN=1, VLVD=4.0V -5% 4.0 +5% V — 30 45 μA VLVR3 VLVD4 VLVD5 Low Voltage Reset Voltage — Low Voltage Detector Voltage — VLVD8 ILVD Additional Power Consumption if LVD is used 3V LVD disable → LVD enable 5V (LVR enable) — 60 90 μA tLVR Low Voltage Width to Reset — — 120 240 480 μs tLVD Low Voltage Width to Interrupt — — 20 45 90 μs tLVDS LVDO stable time — tSRESET Software Reset Width to Reset — For LVR enable, LVD off→on — — — 15 μs 45 90 120 μs Power on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Rev. 1.50 17 August 13, 2014 HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM TinyPower TM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the devices suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC, HXT, LXT or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clocking and Pipelining Rev. 1.50 18 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is ex ecuted except for instructions, such as “JMP” or “CALL” that demands a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High Byte PCL Register HT67F488 PC11~PC8 PCL7~PCL0 HT67F489 PC12~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly. However, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.50 19 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation, RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement, INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.50 20 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits to 8K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device Capacity HT67F488 4K×16 HT67F489 8K×16 Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Program Memory Structure Rev. 1.50 21 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions respectively when the memory [m] is located in current page. If the memory [m] is located in other pages, the table data can be retrieved from the Program Memory using the “LTABRD [m]” or “LTABRDL [m]” instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “F00H” which refers to the start address of the last page within the 4K Program Memory of the HT67F488 device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “F06H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRD [m]” or “LTABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” or “LTABRD [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.50 22 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Table Read Program Example tempreg1 db ? ; temporary register #1 in current page tempreg2 db ? ; temporary register #2 in current page : : mov a,06h ; initialise low table pointer - note that this address is ; referenced to the last page or present page mov tblp,a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; Data at program memory address “F06H” transferred to tempreg1 ; and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; Data at program memory address “F05H” transferred to tempreg2 ; and TBLH ; in this example the data “1AH” is transferred to tempreg1 and ; data “0FH” to register tempreg2 while the value “00H” will be ; transferred the high byte register TBLH : : org F00h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pins MCU Programming Pins ICPDA PA0 Programming Serial Data/Address Pin Description ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data Memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Rev. 1.50 23 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D IC P D A P A 0 IC P C K P A 2 W r ite r _ V S S V S S * P r o g r a m m in g P in s * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named HT67V489 which is used to emulate the HT67F488/HT67F489 series of devices. The HT67V489 device also provides the “On-Chip Debug” function to debug the HT67F488/HT67F489 series of devices during development process. The devices, HT67F488/ HT67F489 and HT67V489, are almost functional compatible except the “On-Chip Debug” function and package types. Users can use the HT67V489 device to emulate the HT67F488/HT67F489 series of devices behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HTIDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the HT67V489 EV chip for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the HT67F488/ HT67F489 series of devices will have no effect in the HT67V489 EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Rev. 1.50 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-chip Debug Support Data/Address input/output Pin Description OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground 24 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM RAM Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory is divided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the Special Purpose Data Memory for all devices is the address 00H while the start address of the General Purpose Data Memory is the address 80H. The Special Purpose Data Memory registers are accessible in all sectors, with the exception of the EEC register at address 40H, which is only accessible in Sector 1. Device HT67F488 HT67F489 Capacity Sectors General Purpose: 256×8 0: 80H~FFH 1: 80H~93H (For LCD) 2: 80H~FFH Data Memory Structure General Purpose Data Memory There are 256 bytes of general purpose memory which are arranged in 80H~FFH of Sector 0, Sector 2 separately. And another 20 bytes of LCD memory are mapped in 80H~93H of Sector 1. All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. The general purpose data memory is fully accessible by the user program for both read and writing operations. By using the "SET [m].i" and "CLR [m].i" instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Rev. 1.50 25 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. They are overlapped in any sector. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused before 80H, any read instruction to these addresses will return the value "00H". Special Purpose Data Memory Rev. 1.50 26 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections, however several registers require a separate description in this section. Indirect Addressing Register – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. The following example shows how to clear a sector of four Data Memory locations already defined as locations adres1 to adres4. Rev. 1.50 27 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Indirect Addressing Program Example data.section ‘data’ adres1 db? adres2 db? adres3 db? adres4 db? block db? code.section at 0 code org 00h start: mov a, 04h; mov block, a mov a, offset adres1 ; mov mp0, a ; loop: clr IAR0 ; inc mp0; sdz block ; jmploop continue: setup size of block Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP0 increment memory pointer check if last memory location has been cleared The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Rev. 1.50 28 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the SC flag, CZ flag, zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • SC is the result of the “XOR” operation which is performed by the OV flag and the MSB of the current instruction operation result. • CZ is the operational result of different flags for different instuctions. Refer to register definitions for more details. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.50 29 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R/W R/W R R R/W R/W R/W R/W POR x x 0 0 x x x x “x” unknown Bit 7SC: The result of the “XOR” operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6CZ: The the operational result of different flags for different instructions. For SUB/SUBM instructions, the CZ flag is equal to the Z flag. For SBC/SBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.50 30 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM EEPROM Data Memory The HT67F489 device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Sector 0 and a single control register in Sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Sector 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Sector1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1L/ MP1H Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Sector 1, the MP1L Memory Pointer low byte must first be set to the value 40H and the MP1H Memory Pointer high byte set to the value 01H before any operations on the EEC register are executed. EEPROM Register List Name Bit 7 6 5 4 3 2 1 0 EEA — — D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEA Register Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5~0D5~D0: Data EEPROM address Data EEPROM address bit 5 ~ bit 0 Rev. 1.50 31 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The WR and RD can not be set to “1” at the same time. Rev. 1.50 32 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on MP1L/MP1H and MP2L/MP2H will be reset to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register is located in Sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.50 33 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte, MP1H or MP2H, could be normally cleared to zero as this would inhibit access to Sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR MP1H MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 set WREN bit SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.50 ; user defined address ; user defined data ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set WREN bit, enable write operations ; start Write Cycle - set WR bit – executed immediately after ; check for write cycle end ; disable EEPROM read/write 34 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Pins HIRC 8MHz — External High speed Crystal HXT 400kHz~16MHz OSC1/OSC2 Internal Low Speed RC LIRC 32kHz — External Low Speed Crystal LXT 32.768kHz XT1/XT2 Internal High Speed RC Oscillator Types System Clock Configurations There are three methods of generating the system clock, one high speed oscillator and two low speed oscillators. The high speed oscillator is the internal 8MHz RC oscillator - HIRC. The two low speed oscillators are the internal 32kHz RC oscillator - LIRC and the external 32.768kHz crystal oscillator - LXT. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. System Clock Configurations Rev. 1.50 35 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. An additional configuration option must be setup to configure the device according to whether the oscillator frequency is high, defined as equal to or above 1MHz, or low, which is defined as below 1MHz. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible. Crystal/Resonator Oscillator – HXT Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0pF 0pF 8MHz 0pF 0pF 4MHz 0pF 0pF 1MHz 100pF 100pF 455kHz (see Note2) 100pF 100pF Note: 1. C1 and C2 values are for guidance only. 2. XTAL mode configuration option: 455kHz. Crystal Recommended Capacitor Values Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins are free for use as normal I/O pins. Rev. 1.50 36 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via the FSUBC register. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification. The external parallel feedback resistor, RP, is required. The FSUBC register determines if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible. External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5M~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values Rev. 1.50 37 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the FSUBC register. FSUBC Register Bit 7 6 5 4 3 2 1 0 Name LXTLP FSUB6 FSUB5 FSUB4 FSUB3 FSUB2 FSUB1 FSUB0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 1 0 1 0 Bit 7LXTLP: LXT Low Power Control 0: Quick Start Mode 1: Low Power Mode Bit 6~0 FSUB6~FSUB0: fSUB clock source selection 0101010: LIRC 1010101: LXT Others: MCU reset After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Lowpower mode. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via the FSUBC register. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Rev. 1.50 38 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency fH or low frequency fSUB source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from the HIRC/HXT oscillator. The low speed system clock source can be sourced from internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillator, selected by the FSUB6~FSUB0 bits in the FSUBC register. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. System Clock Configuration Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 1.50 39 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operating Mode Description CPU fSYS fSUB fTBC NORMAL Mode On fH~fH/64 On On SLOW Mode On fSUB On On IDLE0 Mode Off Off On On IDLE1 Mode Off On On On SLEEP0 Mode Off Off Off Off SLEEP1 Mode Off Off On Off NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator HIRC/HXT. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from one of the low speed oscillators, either the LXT or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB clock will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to “0”. If the LVDEN is set to “1”, it won’t enter the SLEEP0 Mode. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB clock will continue to operate if the LVDEN is “1” or the Watchdog Timer function is enabled. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU, the system oscillator will be stopped, the low frequency clock fSUB will be on. Rev. 1.50 40 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the low frequency clock fSUB will be on. Note: If LVDEN=1 and the SLEEP or IDLE mode is entered, the LVD and bandgap functions will not be disabled, and the fSUB clock will be forced to be enabled. In sleep mode, other peripheral will disable except WDT, LVD if enable in SLEEP 1. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0” 000: fSUB (fLXT or fLIRC) 001: fSUB (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as “0” Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wakeup has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC/HXT oscillator is used. Rev. 1.50 41 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: System clock selection 0: fH/2 ~ fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — FSUBF LVRF LRF WRF R/W R/W — — — R/W R/W R/W R/W POR 0 — — — 0 x 0 0 “x” unknown Bit 7FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6~4 Unimplemented, read as “0” Bit 3FSUBF: FSUBC Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the FSUB6~FSUB0 bits in the FSUBC register contains any undefined values. This bit can only be cleared to 0 by the application program. Bit 2LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1LRF: LVR Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Rev. 1.50 42 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes. Rev. 1.50 43 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.50 44 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Rev. 1.50 45 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the Time Base clock fTBC and fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock, Time Base clock fTBC and fSUB clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. Rev. 1.50 46 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if enabled the LXT or LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.50 47 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fSUB, the fSUB clock is sourced from LIRC or LXT oscillator selected by the FSUBC register. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function software control 10101: Disable 01010: Enable Others: Reset MCU When these bits are changed by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB Rev. 1.50 48 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — FSUBF R/W R/W — — — R/W LVRF LRF WRF R/W R/W POR 0 — — — 0 R/W x 0 0 “x” unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere. Bit 6~4 Unimplemented, read as “0” Bit 3FSUBF: FSUBC Control register software reset flag Described elsewhere. Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR Control register software reset flag Described elsewhere. Bit 0WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other values by the environmental noise or software setting, except 01010B and 10101B, it will reset the device after 2~3 fSUB clock cycles. After power on these bits will have the value of 01010B. WE4 ~ WE0 Bits 10101B WDT Function Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. Rev. 1.50 49 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC Register Reset MCU WE4~WE0 bits CLR “HALT”Instruction “CLR WDT”Instruction M U X LXT LIRC fSUB FSUBC FSUB6~FSUB0 bits 8-stage Divider fSUB/28 WDT Prescaler WS2~WS0 (fSUB/28 ~ fSUB/218) 8-to-1 MUX WDT Time-out (28/fSUB ~ 218/fSUB) Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are four ways in which a reset can occur, through events occurring both internally and externally: • Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Power-on Reset tRSTD SST Time-out Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart Rev. 1.50 50 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM • Low Voltage Reset — LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Any other value: Generates MCU reset -- LVRC register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 fSUB clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fSUB clock cycles. However in this situation the register contents will be reset to the POR value. Rev. 1.50 51 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — FSUBF R/W R/W — — — R/W LVRF LRF WRF R/W R/W POR 0 — — — 0 R/W x 0 0 “x” unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere. Bit 6~4 Unimplemented, read as “0” Bit 3FSUBF: FSUBC Control register software reset flag Described elsewhere. Bit 2LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit can be clear to “0”, but can not set to “1”. Bit 1LRF: LVR Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0WRF: WDT Control register software reset flag Described elsewhere. • Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as LVR reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart • Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC/HXT. The tSST is 1024 clock for LXT. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during Sleep or IDLE Timing Chart Rev. 1.50 52 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF Reset Conditions 0 0 Power-on reset u u LVR reset during Normal or SLOW Mode operation 1 u WDT time-out reset during Normal or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs and AN0~AN9 as A/D input pins Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) IAR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu IAR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu IAR2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---x xxxx ---u uuuu ---u uuuu ---u uuuu STATUS xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu SMOD 000- 0011 000- 0011 000- 0011 uuu- uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu LVRC 0101 0101 0101 0101 0101 0101 uuuu uuuu Register CTRL 0--- 0x00 0--- uuuu 0--- uuuu 0--- uuuu INTEG 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev. 1.50 53 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) WDTC 0101 0011 0101 0011 0101 0011 uuuu uuuu TBC 0011 -111 0011 -111 0011 -111 uuuu -uuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI0 --00 --00 --00 --00 --00 --00 --uu --uu MFI1 --00 --00 --00 --00 --00 --00 --uu --uu MFI2 --00 --00 --00 --00 --00 --00 --uu --uu MFI3 --00 --00 --00 --00 --00 --00 --uu --uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU --00 0000 --00 0000 --00 0000 --uu uuuu PB --11 1111 --11 1111 --11 1111 --uu uuuu PBC --11 1111 --11 1111 --11 1111 --uu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu Register PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU 0000 ---- 0000 ---- 0000 ---- uuuu ---- PF 1111 ---- 1111 ---- 1111 ---- uuuu ---- PFC 1111 ---- 1111 ---- 1111 ---- uuuu ---- TMPC ---0 0000 ---0 0000 ---0 0000 ---u uuuu IOHR0 0000 0000 0000 0000 0000 0000 uuuu uuuu IOHR1 0000 0000 0000 0000 0000 0000 uuuu uuuu ADRL (ADRFS=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRL (ADRFS=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH (ADRFS=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH (ADRFS=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu 0110 0000 0110 0000 0110 0000 uuuu uuuu ADCR0 ADCR1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu ACERL 1111 1111 1111 1111 1111 1111 uuuu uuuu ACERH ---- --11 ---- --11 ---- --11 ---- --uu Rev. 1.50 54 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Register Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) TM0C0 0000 0--- 0000 0--- 0000 0--- uuuu u--- TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 ---- --uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 ---- --uu TM0RPL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0RPH ---- --00 ---- --00 ---- --00 ---- --uu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 ---- --uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 ---- --uu TM2C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH ---- --00 ---- --00 ---- --00 ---- --uu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH ---- --00 ---- --00 ---- --00 ---- --uu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH ---- --00 ---- --00 ---- --00 ---- --uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH ---- --00 ---- --00 ---- --00 ---- --uu FSUBC 0010 1010 0010 1010 0010 1010 uuuu uuuu LCDC0 0000 -000 0000 -000 0000 -000 uuuu -uuu LCDC1 000- 0000 000- 0000 000- 0000 uuu- uuuu SEGCR0 0000 0000 0000 0000 0000 0000 uuuu uuuu SEGCR1 0000 0000 0000 0000 0000 0000 uuuu uuuu SEGCR2 ---- 0000 ---- 0000 ---- 0000 ---- uuuu EEA --00 0000 --00 0000 --00 0000 --uu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 ---- uuuu USR 0000 1011 0000 1011 0000 1011 uuuu uuuu UCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Note: “u” stands for unchanged “x” stands for unknown “-” stands for unimplemented Rev. 1.50 55 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PF. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PBPU — — PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PB — — PB5 PB4 PB3 PB2 PB1 PB0 PBC — — PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PFPU PFPU7 PFPU6 PFPU5 PFPU4 — — — — PF PF7 PF6 PF5 PF4 — — — — PFC PFC7 PFC6 PFC5 PFC4 — — — — “—”: Unimplemented, read as “0” PAWUn: PA wake-up function control 0: Disable 1: Enable PAn/PBn/PCn/PDn/PEn/PFn: I/O Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O type selection 0: Output 1: Input PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: Pull-high function control 0: Disable 1: Enable Rev. 1.50 56 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PFPU, and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAWU7~PAWU0: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PFC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the chosen function of the multi-function I/O pins is selected by a series of registers via the application program control. Rev. 1.50 57 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure A/D Input/Output Structure Rev. 1.50 58 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PFC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PF, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.50 59 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Periodic TM sections. Introduction These devices contain four TMs having a reference name of TM0, TM1, TM2 and TM3. Each individual TM can be categorised as a certain type, namely Compact Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Periodic TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. Function CTM PTM Timer/Counter √ √ I/P Capture — √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty — 1 Edge Edge Duty or Period Duty or Period TM Function Summary This chip contains a specific number of either Compact Type and Periodic Type TM units which are shown in the table together with their individual reference names, TM0~TM3. TM0 TM1 TM2 TM3 10-bit PTM 10-bit CTM 10-bit CTM 10-bit CTM TM Name/Type Reference TM Operation The two different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.50 60 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact Type and Periodic Type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or two output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type is different, the details are provided in the accompanying table. Periodic Type TM output pin names have a “_n” suffix. Pin names that include a “_0” or “_1” suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. TM0 TM1 TM2 TM3 TP0_0, TP0_1 TP1 TP2 TP3 TM Output Pins TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output if reset to zero the pin will retain its original other functions. Rev. 1.50 61 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM TM0 Function Pin Control Block Diagram TM1 Function Pin Control Block Diagram TM2 Function Pin Control Block Diagram TM3 Function Pin Control Block Diagram Rev. 1.50 62 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TMPC Register Bit 7 6 5 4 3 2 1 0 Name — — — T3CP T2CP T1CP T0CP1 T0CP0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as “0” Bit 4T3CP: TP3 pin control 0: Disable 1: Enable Bit 3T2CP: TP2 pin control 0: Disable 1: Enable Bit 2T1CP: TP1 pin control 0: Disable 1: Enable Bit 1T0CP1: TP0_1 pin control 0: Disable 1: Enable Bit 0T0CP0: TP0_0 pin control 0: Disable 1: Enable Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named TMxAL and TMxRPL, using the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. TM Co�nter Re�ister (Read only) TMxDL TMxDH 8-bit B�ffer TMx�L TMx�H TM CCR� Re�ister (Read/Write) TMxRPL TMxRPH TM CCRP Re�ister (Read/Write) Data B�s Rev. 1.50 63 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte TMxAL or TMxRPL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH or TMxRPH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP ♦♦ Step 1. Read data from the High Byte TMxDH, TMxAH or TMxRPH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxRPL ––This step reads data from the 8-bit buffer. Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with an external input pin and can drive two external output pin. Name TM No. TM Input Pin TM Output Pin 10-bit PTM 0 TCK0 TP0_0, TP0_1 Periodic TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with the CCRA and CCRP registers. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.50 64 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Periodic Type TM Block Diagram (n=0) Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON — — — TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 TMnRPL D7 D6 D5 D4 D3 D2 D1 D0 TMnRPH — — — — — — D9 D8 10-bit Periodic TM Register List (n=0) Rev. 1.50 65 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM TMnC0 Register Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fH 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TM Output control bit, when the bit changes from low to high. Bit 2~0 Rev. 1.50 Unimplemented, read as “0” 66 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TMnC1 Register Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operation Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TPn_0, TPn_1, TCKn 01: Input capture at falling edge of TPn_0, TPn_1, TCKn 10: Input capture at falling/rising edge of TPn_0, TPn_1, TCKn 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When these bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Rev. 1.50 67 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Bit 3TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0, TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1TnCAPTS: TMn capture trigger source select 0: From TPn_0, TPn_1 pin 1: From TCKn pin Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TMnDH: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 Rev. 1.50 68 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TMnAH: TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 TMnRPL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TMnRPL: TMn CCRP Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRP bit 7 ~ bit 0 TMnRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0TMnRPH: TMn CCRP High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRP bit 9 ~ bit 8 Rev. 1.50 69 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be all cleared to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator Aand Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1, TnIO0 bits are zero then no pin change will take place. Rev. 1.50 70 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Co�nter Val�e Co�nter overflow CCRP=0 0x�FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nter cleared by CCRP val�e CCRP > 0 Co�nter Restart Res�me CCRP Pa�se CCR� Stop Time TnON TnP�U TnPOL CCRP Int. Fla� TnPF CCR� Int. Fla� Tn�F TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit O�tp�t To��le with Tn�F fla� Here TnIO [1:0] = 11 To��le O�tp�t select Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t select O�tp�t Inverts when TnPOL is hi�h O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode – TnCCLR = 0 (n=0) Note: 1. With TnCCLR = 0 – a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to initial state by a TnON bit rising edge Rev. 1.50 71 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 Co�nter overflow CCR� > 0 Co�nter cleared by CCR� val�e 0x�FF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U TnPOL No Tn�F fla� �enerated on CCR� overflow CCR� Int. Fla� Tn�F CCRP Int. Fla� TnPF TnPF not �enerated O�tp�t does not chan�e TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit O�tp�t To��le with Tn�F fla� Here TnIO [1:0] = 11 To��le O�tp�t select Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t select O�tp�t Inverts when TnPOL is hi�h O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode – TnCCLR = 1 (n=0) Note: 1. With TnCCLR = 1 – a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to initial state by a TnON rising edge 4. The TnPF flag is not generated when TnCCLR = 1 Rev. 1.50 72 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should all be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTM, PWM Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS = 8MHz, TM clock source select fSYS/4, CCRP = 512 and CCRA = 128, The PTM PWM output frequency = (fSYS/4) / (2×256) = fSYS/2048 =3.90625kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.50 73 August 13, 2014 TinyPower TM Counter Value HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM TnM [1:0] = 10 Counter cleared by CCRP Counter Reset when TnON returns high CCRP Pause Resume CCRA Counter Stop if TnON bit low Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode (n=0) Note: 1. Here Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO[1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.50 74 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Single Pulse Output Mode To select this mode, the required bit pairs, TnM1 and TnM0 should be set to 10 respectively and also the corresponding TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Single Pulse Generation (n=0) Rev. 1.50 75 August 13, 2014 TinyPower TM Co�nter Val�e HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM TnM [1:0] = 10 ; TnIO [1:0] = 11 Co�nter stopped by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Pa�se Co�nter Stops by software Res�me CCRP Time TnON Software Tri��er ��to. set by TCKn pin Cleared by CCR� match TCKn pin Software Tri��er Software Software Tri��er Clear Software Tri��er TCKn pin Tri��er TnP�U TnPOL No CCRP Interr�pts �enerated CCRP Int. Fla� TnPF CCR� Int. Fla� Tn�F TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) O�tp�t Inverts when TnPOL = 1 P�lse Width set by CCR� Single Pulse Mode (n=0) Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed. Rev. 1.50 76 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0, TPn_1 or TCKn pin, selected by the TnCAPTS bit in the TMnC0 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0, TPn_1 or TCKn pin the present value in the counter will be latched into the CCRA register and a TM interrupt generated. Irrespective of what events occur on the TPn_0, TPn_1 or TCKn pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0, TPn_1 or TCKn pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0, TPn_1 or TCKn pin, however it must be noted that the counter will continue to run. As the TPn_0, TPn_1 or TCKn pin is pin shared with other functions, care must be taken if the TMn is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnOC and TnPOL bits are not used in this Mode. Rev. 1.50 77 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Counter Value TnM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time TnON TnPAU TM capture pin TPn_x or TCKn Active edge Active edge Active edge CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode (n=0) Note: 1. TnM[1:0] = 01 and active edge set by the TnIO[1:0] bits 2. A TM Capture input pin active edge transfers counter value to CCRA 3. The TnCCLR bit is not used 4. No output function – TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 1.50 78 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one external output pin. Name TM No. TM Input Pin TM Output Pin 10-bit CTM 1, 2, 3 TCK1, TCK2, TCK3 TP1, TP2, TP3 Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Block Digram (n=1~3) Rev. 1.50 79 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 Compact TM Register List (n=1~3) TMnC0 Register Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fH 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Rev. 1.50 80 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Bit 2~0TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register Rev. 1.50 Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 TnM1, TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 TnIO1, TnIO0: Select TPn output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. 81 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Bit 3TnOC: TPn Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Rev. 1.50 82 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0D9~D8: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 TMnAL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0D7~D0: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0D9~D8: TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 Rev. 1.50 83 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.50 84 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Co�nter Val�e Co�nter overflow CCRP=0 0x�FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nter cleared by CCRP val�e CCRP > 0 Co�nter Restart Res�me CCRP Pa�se CCR� Stop Time TnON TnP�U TnPOL CCRP Int. Fla� TnPF CCR� Int. Fla� Tn�F TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit O�tp�t To��le with Tn�F fla� Here TnIO [1:0] = 11 To��le O�tp�t select Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t select O�tp�t Inverts when TnPOL is hi�h O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode - TnCCLR = 0 (n=1~3) Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.50 85 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 Co�nter overflow CCR� > 0 Co�nter cleared by CCR� val�e 0x�FF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U TnPOL No Tn�F fla� �enerated on CCR� overflow CCR� Int. Fla� Tn�F CCRP Int. Fla� TnPF TnPF not �enerated O�tp�t does not chan�e TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit O�tp�t To��le with Tn�F fla� Here TnIO [1:0] = 11 To��le O�tp�t select Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t select O�tp�t Inverts when TnPOL is hi�h O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode - TnCCLR = 1 (n=1~3) Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.50 86 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. • CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 8MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128, The CTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 3.90625kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 128 256 384 512 Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.50 87 August 13, 2014 TinyPower TM Co�nter Val�e HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns hi�h CCRP Pa�se Res�me CCR� Co�nter Stop if TnON bit low Time TnON TnP�U TnPOL CCR� Int. Fla� Tn�F CCRP Int. Fla� TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�ty Cycle set by CCR� PWM Period set by CCRP PWM res�mes operation O�tp�t controlled by O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode - TnDPX = 0 (n=1~3) Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.50 88 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Pa�se Res�me CCRP Co�nter Stop if TnON bit low Time TnON TnP�U TnPOL CCRP Int. Fla� TnPF CCR� Int. Fla� Tn�F TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�ty Cycle set by CCRP PWM Period set by CCR� PWM res�mes operation O�tp�t controlled by O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode - TnDPX = 1 (n=1~3) Note: 1. Here TnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.50 89 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Analog to Digital Converter – ADC The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. Input Channels A/D Channel Select Bits Input Pins 10 ACS4, ACS3~ACS0 AN0~AN9 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Structure A/D Converter Register Description Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the ADC data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Rev. 1.50 90 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Bit Register Name 7 6 5 4 ADRL(ADRFS=0) D3 D2 D1 D0 — — — — ADRL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRH(ADRFS=1) — — — — D11 D10 D9 D8 ADCR0 START EOCB ADOFF ADRFS ACS3 ACS2 ACS1 ACS0 ADCR1 ACS4 VBGEN — VREFS — ADCK2 ADCK1 ADCK0 ACERL ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 ACERH — — — — — — ACE9 ACE8 3 2 1 0 A/D Converter Register List A/D Converter Data Registers – ADRL, ADRH The devices, which have an internal 12-bit A/D converter, require two data registers, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS 0 1 ADRH 7 6 D11 D10 0 0 ADRL 5 4 3 2 1 0 7 6 5 4 3 2 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Data Registers A/D Converter Control Registers – ADCR0, ADCR1, ACERL, ACERH To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1, ACERL and ACERH are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS3~ACS0 bits in the ADCR0 register and the ACS4 bit in the ADCR1 register define the ADC input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS4~ACS0 bits to determine which analog channel input pin or internal VBG is actually connected to the internal A/D converter. The ACERH and ACERL control registers contain the ACE9~ACE0 bits which determine which pins on PB and PE Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. Rev. 1.50 91 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM ADCR0 Register Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS ACS3 ACS2 ACS1 ACS0 R/W R/W R R/W R/W R/W R/W R/W R/W POR 0 1 1 0 0 0 0 0 Bit 7START: Start the A/D conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running, the bit will be high. Bit 5ADOFF: ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. It is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module. Bit 4ADRFS: A/D data format control bit 0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3~0ACS3~ACS0: Select A/D channel (when ACS4 is “0”) 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001~1111: AN9 These are the A/D channel select control bits. As there is only one internal hardware A/ D converter each of the ten A/D inputs must be routed to the internal converter using these bits. If the ACS4 bit is set high, then the internal Bandgap VBG will be routed to the A/D Converter. Rev. 1.50 92 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM ADCR1 Register Bit 7 6 5 4 3 2 1 0 Name ACS4 VBGEN — VREFS — ADCK2 ADCK1 ADCK0 R/W R/W R/W — R/W — R/W R/W R/W POR 0 0 — 0 — 0 0 0 Bit 7ACS4: Select internal VBG as ADC input control 0: Disable 1: Enable This bit enables VBG to be connected to the A/D converter. The VBGEN bit must first have been set to enable the bandgap circuit VBG voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap VBG voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 6VBGEN: Internal VBG control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage VBG can be used by the A/D converter. If VBG is not used by the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When VBG is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion. Bit 5 Unimplemented, read as “0” Bit 4VREFS: Selecte ADC reference voltage 0: Internal ADC power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the internal reference is used which is taken from the power supply pin VDD. When the A/D converter reference voltage is supplied on the external VREF pin which is pin-shared with other functions, all of the pin-shared functions except VREF on this pin are disabled. Bit 3 Unimplemented, read as “0” Bit 2~0ADCK2~ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter. Rev. 1.50 93 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Bandgap reference voltage on/off true table: ACS4 VBGEN LVR/LVD VBG Bandgap Reference Voltage x x 0 Enable Off to GND On 0 Disable Off to GND x Off 1 x On On x: Don’t care ACERL Register Bit 7 6 5 4 3 2 1 0 Name ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7ACE7: Define PB4 is A/D input or not 0: Not A/D input 1: A/D input, AN7 Bit 6ACE6: Define PE6 is A/D input or not 0: Not A/D input 1: A/D input, AN6 Bit 5ACE5: Define PE5 is A/D input or not 0: Not A/D input 1: A/D input, AN5 Bit 4ACE4: Define PE4 is A/D input or not 0: Not A/D input 1: A/D input, AN4 Bit 3ACE3: Define PB3 is A/D input or not 0: Not A/D input 1: A/D input, AN3 Bit 2ACE2: Define PB2 is A/D input or not 0: Not A/D input 1: A/D input, AN2 Bit 1ACE1: Define PB1 is A/D input or not 0: Not A/D input 1: A/D input, AN1 Bit 0ACE0: Define PB0 is A/D input or not 0: Not A/D input 1: A/D input, AN0 Rev. 1.50 94 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM ACERH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — ACE9 ACE8 R/W — — — — — — R/W R/W POR — — — — — — 1 1 Bit 7~2 Unimplemented, read as “0” Bit 1ACE9: Define PB5 is A/D input or not 0: Not A/D input 1: A/D input, AN9 Bit 0ACE8: Define PE7 is A/D input or not 0: Not A/D input 1: A/D input, AN8 A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to “0” by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the A/D clock source speed range that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be taken for selected system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. Rev. 1.50 95 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM A/D Clock Period (tADCK) ADCK2, ADCK1, ADCK0 =000 (fSYS) ADCK2, ADCK1, ADCK0 =001 (fSYS/2) ADCK2, ADCK1, ADCK0 =010 (fSYS/4) ADCK2, ADCK1, ADCK0 =011 (fSYS/8) ADCK2, ADCK1, ADCK0 =100 (fSYS/16) ADCK2, ADCK1, ADCK0 =101 (fSYS/32) ADCK2, ADCK1, ADCK0 =110 (fSYS/64) ADCK2, ADCK1, ADCK0 =111 1MHz 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* Undefined 2MHz 500ns 1μs 2μs 4μs 8μs 16μs* 32μs* Undefined 4MHz 250ns* 500ns 1μs 2μs 4μs 8μs 16μs* Undefined 8MHz 125ns* 250ns* 500ns 1μs 2μs 4μs 8μs Undefined fSYS A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE9~ACE0 bits in the ACERH and ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be disabled automatically. A/D Input Pins All of the A/D analog input pins are pin-shared with the PB and PE I/O pins as well as other functions. The ACE9~ACE0 bits in the ACERH and ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE9~ACE0 bits for its corresponding pin is set high then the pins will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PBC or PEC port control register to enable the A/D input as when the ACE9~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF. Rev. 1.50 96 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM A/D Input Structure Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4~ACS0 bits which are also contained in the ADCR1 and ADCR0 registers. • Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE9~ACE0 bits in the ACERH and ACERL registers. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tADCK where tADCK is equal to the A/D clock period. Rev. 1.50 97 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM �DOFF tON�ST �DC mod�le ON off on off �/D samplin� time �/D samplin� time t�DCS ST�RT on t�DCS EOCB �CS�~�CS0 00011B Power-on Reset 00010B 00000B Reset �/D conversion 1. Define port confi��ration �. Select analo� channel Start of �/D conversion Reset �/D conversion Start of �/D conversion End of �/D conversion t�DC �/D conversion time 00001B Start of �/D conversion Reset �/D conversion End of �/D conversion t�DC �/D conversion time A/D Conversion Timing Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog input value of VDD or VREF divided by 4096. 1 LSB = (VDD or VREF) ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × (VDD or VREF) ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level. Rev. 1.50 98 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Ideal A/D Transfer Function A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE; mov a, 03H mov ADCR1, a ; clr ADOFF mov a, 0Fh ; mov ACERL, a mova,00h mov ACERH,a mov a, 00h mov ADCR0, a ; : Start_conversion: clr START set START ; clr START ; Polling_EOC: sz EOCB ; ; jmp polling_EOC ; mov a, ADRL ; mov adrl_buffer, a ; mov a, ADRH ; mov adrh_buffer, a ; : jmp start_conversion ; Rev. 1.50 disable ADC interrupt select fSYS/8 as A/D clock and switch off VBG setup ACERL to configure pins AN0~AN3 enable and connect AN0 channel to A/D converter reset A/D start A/D poll the ADCR0 register EOCB bit to detect end of A/D conversion continue polling read low byte conversion result value save result to user defined register read high byte conversion result value save result to user defined register start next A/D conversion 99 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Example: using the interrupt method to detect the end of conversion clr ADE; mov a, 03H mov ADCR1, a ; clr ADOFF mov a, 0Fh ; mov ACERL, a mova,00h mov ACERH,a mov a, 00h mov ADCR0, a ; : : Start_conversion: clr START set START ; clr START ; clr ADF ; set ADE; set EMI ; : : ; ADC_: mov acc_stack, a ; mov a, STATUS mov status_stack, a ; : : mov a, ADRL ; mov adrl_buffer, a ; mov a, ADRH ; mov adrh_buffer, a ; : : EXIT_ISR: mov a, status_stack mov STATUS, a ; mov a, acc_stack ; clr ADF ; reti Rev. 1.50 disable ADC interrupt select fSYS/8 as A/D clock and switch off VBG setup ACERL to configure pins AN0~AN3 enable and connect AN0 channel to A/D converter reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable global interrupt ADC interrupt service routine save ACC to user defined memory save STATUS to user defined memory read save read save low byte conversion result value result to user defined register high byte conversion result value result to user defined register restore STATUS from user defined memory restore ACC from user defined memory clear ADC interrupt flag 100 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM LCD Display Memory The devices provide an area of embedded data memory for LCD display. This area is located from 80H to 93H of the RAM at Sector 1. The Memory Pointer MP1H is the switch between the RAM and the LCD display memory. When the MP1H = 01H, data written into 80H~93H will affect the LCD display. When the MP1H is written other than 01H, any data written into 80H~93H is meant to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1L and MP1H. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a “1” or a “0” is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. b7 b6 b5 b4 b3 b2 b1 b0 180H SEG1 181H SEG2 192H SEG18 193H SEG19 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCD Driver Output The output number of the device LCD driver can be 20×4 or 20×8. The LCD driver is “R” type only. The LCD clock source is from fSUB, which can be either the LXT or LIRC oscillator. Rev. 1.50 101 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM LCD Control Register LCDC0 Register Bit 7 6 5 4 3 2 1 0 Name LCDEN TYPE DTYC BIAS — RSEL2 RSEL1 RSEL0 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 0 0 — 0 0 0 Bit 7LCDEN: LCD enable/disable control 0: Disable 1: Enable Note that the LCD driver and A/D converter should not be enabled simultaneously when the LCD output and A/D channel are shared with the same pin. Bit 6TYPE: LCD Waveform Type selection 0: Type A 1: Type B Bit 5DTYC: Define LCD Duty 0: 1/4 Duty ( LCD COM: COM0~COM3) 1: 1/8 Duty (LCD COM: COM0~COM7) Note: If DTYC=1, then COM4~COM7 pins will be configured as LCD COM. If DTYC=0, then COM4~COM7 pins will be configured as I/O. Bit 4BIAS: Define LCD Bias 0: 1/3 Bias 1: 1/4 Bias Bit 3 Unimplemented, read as “0” Bit 2~0RSEL2~RSEL0: Total Bias Resistor RT selection 000: 1170K 001: 225K 010: 60K 011: Quick Charging Mode, switch between 60K and 1170K. 1xx: Quick Charging Mode, switch between 60K and 225K. Note: The bias resistor for 1/3 bias is RT/3, 1/4 bias is RT/4. The devices provide low power quick charging mode for LCD display. In quick charging mode, the LCD will provide LCD bias current by RT=60K, at beginning of LCD display refreshes (i.e the moment on LCD COM changes). After quick charging time, the bias resistor will change to 225K/1170K. Rev. 1.50 102 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM LCDC1 Register Bit 7 6 5 4 3 2 1 0 Name QCT2 QCT1 QCT0 — VLCD3 VLCD2 VLCD1 VLCD0 R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7QCT2~QCT0: Quick charging time selection 000: 1×tSUB 001: 2×tSUB 010: 3×tSUB 011: 4×tSUB 100: 5×tSUB 101: 6×tSUB 110: 7×tSUB 111: 8×tSUB tSUB = 1/fSUB Bit 6 ~ 4 Unimplemented, read as "0" Bit 3 ~ 0VLCD3~VLCD0: VLCD selection 0000: 8/16×VDD 0001: 9/16×VDD 0010: 10/16×VDD 0011: 11/16×VDD 0100: 12/16×VDD 0101: 13/16×VDD 0110: 14/16×VDD 0111: 15/16×VDD 1000~1111: 16/16×VDD Rev. 1.50 103 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM SEGCR0 Register Bit 7 6 5 4 3 2 1 0 Name SEG7C SEG6C SEG5C SEG4C SEG3C SEG2C SEG1C SEG0C R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7SEG7C: Select SEG7 or PD7 0: SEG7 1: PD7 Bit 6SEG6C: Select SEG6 or PD6 0: SEG6 1: PD6 Bit 5SEG5C: Select SEG5 or PD5 0: SEG5 1: PD5 Bit 4SEG4C: Select SEG4 or PD4 0: SEG4 1: PD4 Bit 3SEG3C: Select SEG3 or PD3 0: SEG3 1: PD3 Bit 2SEG2C: Select SEG2 or PD2 0: SEG2 1: PD2 Bit 1SEG1C: Select SEG1 or PD1 0: SEG1 1: PD1 Bit 0SEG0C: Select SEG0 or PD0 0: SEG0 1: PD0 Rev. 1.50 104 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM SEGCR1 Register Bit 7 6 5 4 3 2 1 0 Name SEG15C SEG14C SEG13C SEG12C SEG11C SEG10C SEG9C SEG8C R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7SEG15C: Select SEG15 or PC7 0: SEG15 1: PC7 Bit 6SEG14C: Select SEG14 or PC6 0: SEG14 1: PC6 Bit 5SEG13C: Select SEG13 or PC5 0: SEG13 1: PC5 Bit 4SEG12C: Select SEG12 or PC4 0: SEG12 1: PC4 Bit 3SEG11C: Select SEG11 or PC3 0: SEG11 1: PC3 Bit 2SEG10C: Select SEG10 or PC2 0: SEG10 1: PC2 Bit 1SEG9C: Select SEG9 or PC1 0: SEG9 1: PC1 Bit 0SEG8C: Select SEG8 or PC0 0: SEG8 1: PC0 SEGCR2 Register Bit 7 6 5 4 3 2 1 0 Name — — — — SEG19C SEG18C SEG17C SEG16C R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3SEG19C: Select SEG19 or PF7 0: SEG19 1: PF7 Bit 2SEG18C: Select SEG18 or PF6 0: SEG18 1: PF6 Bit 1SEG17C: Select SEG17 or PF5 0: SEG17 1: PF5 Bit 0SEG16C: Select SEG16 or PF4 0: SEG16 1: PF4 Rev. 1.50 105 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM LCD Waveform LCD Display Off Mode COM0 ~ COM� V� VB VC VSS �ll sen�ment o�tp�ts V� VB VC VSS Normal Operation Mode 1 Frame COM0 V� VB VC VSS COM1 V� VB VC VSS COM� V� VB VC VSS COM� V� VB VC VSS �ll se�ments are OFF V� VB VC VSS COM0 side se�ments are ON V� VB VC VSS COM1 side se�ments are ON V� VB VC VSS COM� side se�ments are ON V� VB VC VSS COM� side se�ments are ON V� VB VC VSS COM0�1 side se�ments are ON V� VB VC VSS COM0�� side se�ments are ON V� VB VC VSS COM0�� side se�ments are ON V� VB VC VSS (other combinations are omitted) V� VB VC VSS �ll sen�ments are ON LCD Driver Output – Type A - 1/4 Duty, 1/3 Bias Note: VA=VLCD, VB=VLCD×2/3 and VC=VLCD×1/3. Rev. 1.50 106 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM LCD Display Off Mode COM0 ~ COM� V� VB VC VSS �ll sen�ment o�tp�ts V� VB VC VSS Normal Operation Mode 1 Frame COM0 V� VB VC VSS COM1 V� VB VC VSS COM� V� VB VC VSS COM� V� VB VC VSS �ll se�ments are OFF V� VB VC VSS COM0 side se�ments are ON V� VB VC VSS COM1 side se�ments are ON V� VB VC VSS COM� side se�ments are ON V� VB VC VSS COM� side se�ments are ON V� VB VC VSS COM0�1 side se�ments are ON V� VB VC VSS COM0�� side se�ments are ON V� VB VC VSS COM0�� side se�ments are ON V� VB VC VSS (other combinations are omitted) V� VB VC VSS �ll sen�ments are ON LCD Driver Output – Type B - 1/4 Duty, 1/3 Bias Note: VA=VLCD, VB=VLCD×2/3 and VC=VLCD×1/3. Rev. 1.50 107 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM tLCD LCD Se�ment LCD Se�ment VLCD VLCD VLCD x �/� VLCD x �/� COM0 VLCD x �/� COM0 VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM1 VLCD x �/� COM1 VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM� VLCD x �/� COM� VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM� VLCD x �/� COM� VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM� VLCD x �/� COM� VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM5 VLCD x �/� COM5 VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM6 VLCD x �/� COM6 VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� COM7 VLCD x �/� COM7 VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� SEG n VLCD x �/� SEG n VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� SEG n+1 VLCD x �/� SEG n+1 VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� SEG n+� VLCD x �/� SEG n+� VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS VLCD VLCD VLCD x �/� VLCD x �/� SEG n+� VLCD x �/� SEG n+� VLCD x �/� VLCD x 1/� VLCD x 1/� VSS VSS State1 State1 (on) (on) State� State� (off) (off) LCD Driver Output – Type A - 1/8 Duty, 1/4 Bias Rev. 1.50 108 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM LED Driver The devices contain an LED driver function offering high current output drive capability which can be used to drive external LEDs. LED Driver Operation The various I/O pins of devices have a capability of providing LED high current drive outputs, as shown in the accompanying table. Device LED Drive Pins HT67F488 HT67F489 PD0~PD7 (high source current) PE0~PE7 (high sink current) LED Driver Register IOHR0 Register Bit 7 6 5 4 3 2 1 0 Name IOHS31 IOHS30 IOHS21 IOHS20 IOHS11 IOHS10 IOHS01 IOHS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 IOHR1 Register Bit 7 6 5 4 3 2 1 0 Name IOHS71 IOHS70 IOHS61 IOHS60 IOHS51 IOHS50 IOHS41 IOHS40 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 IOHSn[1:0]: IOH capacity selection for PDn (n=0~7) 00: Fullly source driving capacity of GPIO 01: 1/3 source driving capacity of GPIO 10: 1/4 source driving capacity of GPIO 11: 1/6 source driving capacity of GPIO Rev. 1.50 109 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM UART Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Transmitter and receiver enabled independently • 2-byte Deep FIFO Receive Data Buffer • Transmit and Receive Multiple Interrupt Generation Sources: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect T r a n s m itte r S h ift R e g is te r M S B R e c e iv e r S h ift R e g is te r L S B T X P in M S B R X P in C L K L S B C L K T X R R e g is te r B a u d R a te G e n e ra to r M C U R X R R e g is te r B u ffe r D a ta B u s UART External Pin Interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O or other pin-shared functional pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O or other pin-shared functional pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin. If the TX and RX pins are shared with the LCD outputs and the UART interface and LCD driver both are enabled simultaneously, the LCD driver has the priority to use the corresponding pins as LCD outputs. Rev. 1.50 110 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM UART Data Transfer Scheme The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/ RXR data registers. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXIF USR PERR NF FERR OERR RIDLE RXIF TIDLE UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR2 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR/RXR TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 BRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 UART Register List Rev. 1.50 111 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a parity error has not been detected. When the flag is “1”, it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is “0”, it indicates that there is no framing error. When the flag is “1”, it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is “0”, it indicates that there is no overrun error. When the flag is “1”, it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1” indicating that the UART receiver is idle and the RX pin stays in logic high condition. Rev. 1.50 112 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is “0”, it indicates that the RXR read data register is empty. When the flag is “1”, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1” when the TXIF flag is “1” and when there is no transmit data or break character being transmitted. When TIDLE is equal to “1”, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is “0”, it indicates that the character is not transferred to the transmitter shift register. When the flag is “1”, it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. Rev. 1.50 113 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM UCR1 Register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 “x” unknown Bit 7UARTEN: UART function enable control 0: Disable UART. TX and RX pins are as I/O or other pin-shared functional pins 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. If the TX and RX pins are shared with the LCD outputs and the UART interface and LCD driver are both enabled simultaneously, the LCD driver will have the priority to use the corresponding pins as LCD outputs. When this bit is equal to “0”, the UART will be disabled and the RX pin as well as the TX pin will be as General Purpose I/O or other pin-shared functional pins. When the bit is equal to “1”, the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to “1”, the parity function will be enabled. If the bit is equal to “0”, then the parity function will be disabled. Replace the most significant bit position with a parity bit. Bit 4PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to “1”, odd parity type will be selected. If the bit is equal to “0”, then even parity type will be selected. Bit 3STOPS: Number of Stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to “1”, two stop bits are used. If this bit is equal to “0”, then only one stop bit is used. Rev. 1.50 114 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Bit 2TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is “0”, there are no break characters and the TX pin operates normally. When the bit is “1”, there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to “1”, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE R/W R/W R/W R/W R/W R/W RIE TIIE TEIE R/W R/W POR 0 0 0 0 0 0 R/W 0 0 Bit 7TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to “1” and the UARTEN bit is also equal to “1”, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be used as an I/O or other pin-shared functional pin. Bit 6RXEN: UART Receiver enabled control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to “0”, the receiver will be disabled with any pending data receptions being aborted. In addition the receive buffers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to “1” and the UARTEN bit is also equal to “1”, the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be used as an I/O or other pin-shared functional pin. Rev. 1.50 115 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to “1”, the high speed mode is selected. If the bit is equal to “0”, the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detect function is disabled 1: Address detect function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to “1”, the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of “1”, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is “0” with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to “1” and the MCU is in the SLEEP mode, a falling edge on the RX input pin will wakeup the device. Please reference the UART RX pin wake-up functions in different operating mode for the detail. If this bit is equal to “0” and the MCU is in the SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to “1” and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to “1” and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to “1” and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the TXIF flag. Rev. 1.50 116 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TXR/RXR Register Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bit 7 ~ bit 0 BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown Bit 7~0BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Note: Baud rate= fSYS/[64×(N+1)] if BRGH=0. Baud rate= fSYS/[16×(N+1)] if BRGH=1. Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS / [64 (N+1)] fSYS / [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Rev. 1.50 117 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Calculating the Register and Error Values For a clock frequency of 4MHz, and with BRGH set to “0” determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = fSYS / [64 (N+1)] Re-arranging this equation gives N = [fSYS / (BR×64)] - 1 Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208 To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR = 4000000 / [64×(12 + 1)] = 4808 Therefore the error is equal to (4808 - 4800) / 4800 = 0.16% The following table shows actual values of baud rate and error values for the two values of BRGH. fSYS=8MHz Baud Rate K/BPS Baud Rates for BRGH=0 BRG Kbaud Baud Rates for BRGH=1 Error (%) BRG Kbaud Error (%) — 0.3 — — — — — 1.2 103 1.202 0.16 — — — 2.4 51 2.404 0.16 207 2.404 0.16 4.8 25 4.808 0.16 103 4.808 0.16 9.6 12 9.615 0.16 51 9.615 0.16 19.2 6 17.8857 -6.99 25 19.231 0.16 38.4 2 41.667 8.51 12 38.462 0.16 57.6 1 62.500 8.51 8 55.556 -3.55 115.2 0 125 8.51 3 125 8.51 250 — — — 1 250 0 Baud Rates and Error Values UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Rev. 1.50 118 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Enabling/Disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. Rev. 1.50 119 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O or other pin-shared function. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. • This sequence of events can now be repeated to send additional data. • It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: ♦♦ A USR register access ♦♦ A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. Rev. 1.50 120 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: • A USR register access • A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmit Break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin. Rev. 1.50 121 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: • The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read. • When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. • If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: • A USR register access • An RXR register read execution Receive Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Rev. 1.50 122 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR Flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Noise Error – NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error – PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. Rev. 1.50 123 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. USR Register UCR2 Register Transmitter Empty Flag TXIF TEIE Transmitter Idle Flag TIDLE TIIE 0 1 RIE 0 1 Receiver Overrun Flag OERR OR Receiver Data Available RXIF RX Pin Wake-up WAKE ADDEN 0 1 UCR2 Register 0 1 UART Interrupt Request Flag UARF INTC2 Register UARE INTC0 Register EMI 0 1 0 1 RX7 if BNO=0 RX8 if BNO=1 UART Interrupt Scheme Rev. 1.50 124 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Address Detect Mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the MFE, URE and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. ADDEN 0 1 Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function UART Module Power Down and Wake-up When the MCU is in the Power Down Mode, the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be paused. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the Power Down mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake up the MCU from the Power Down Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Below table illustrates the UART RX wake-up functions in different operating mode. Rev. 1.50 125 August 13, 2014 TinyPower TM Operation Mode IDLE0 Mode IDLE1 Mode Description RX wake-up function CPU fSYS fH fSUB Off Off Off On When the CPU enters the IDLE0 mode, a falling edge on the RX pin will not turn on the fSYS clock and not wake up the CPU even if UCR2.2(RIE)=1 and UCR2.3(WAKE)=1. On When the UCR2.2(RIE)=1, UCR2.3(WAKE)=1 and the CPU is entered in IDLE1 mode: 1. If the UART is not transfer and a falling edge occurred on the RX pin, this will turn on fSYS and CPU is still off. If the UART transmission is on going, CPU will be woken up in the end of transfer. 2. If the UART transmission is on going, the CPU will be woken up in the end of transfer. Note: If RIE=0, WAKE=1 and the UART transmission is on going, the CPU will not be woken up in the end of receive. Off When the UCR2.2(RIE)=1, UCR2.3(WAKE)=1 and the CPU is entered in IDLE1 mode: 1. If the UART is not transfer and a falling edge occurred on the RX pin, this will turn on fSYS and CPU is still off. If the UART transmission is on going, CPU will be woken up in the end of transfer. 2. If the UART transmission is on going, the CPU will be woken up in the end of transfer. Note: If RIE=0, WAKE=1 and the UART transmission is on going, the CPU will not be woken up in the end of receive. Off IDLE1 Mode Off SLEEP0/1 Mode Off Rev. 1.50 HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM On On On On (fSYS=fH~fH/64) Off When the UCR2.2(RIE)=1, UCR2.3(WAKE)=1 and the CPU Off On/Off is entered in SLEEP mode, a falling edge on the RX pin will turn on fSYS and wake-up CPU. 126 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INT0~INT3 pins, while the internal interrupts are generated by various internal functions such as TMs, Time Base, LVD, EEPROM, UART and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI4 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/ disable bit or “F” for request flag. Function Global INTn Pin Enable Bit Request Flag EMI — Notes — INTnE INTnF n=0~3 A/D Converter ADE ADF — Multi-function MFnE MFnF n=0~4 Time Base TBnE TBnF n=0 or 1 LVD LVE LVF — EEPROM DEE DEF — UARE UARF — TnPE TnPF n=0~3 TnAE TnAF n=0~3 UART TM Interrupt Register Bit Naming Conventions Note: The EEPROM Interrupt is only for the HT67F489. Interrupt Register Contents Bit Register Name 7 6 5 4 3 2 1 0 INTEG INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF0F INT1F INT0F MF0E INT1E INT0E EMI INTC1 ADF MF3F MF2F MF1F ADE MF3E MF2E MF1E INTC2 MF4F INT3F INT2F UARF MF4E INT3E INT2E UARE MFI0 — — T0AF T0PF — — T0AE T0PE MFI1 — — T1AF T1PF — — T1AE T1PE MFI2 — — T2AF T2PF — — T2AE T2PE MFI3 — — T3AF T3PF — — T3AE T3PE MFI4 TB1F TB0F DEF LVF TB1E TB0E DEE LVE Note: The EEPROM Interrupt is only for the HT67F489. Rev. 1.50 127 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM INTEG Register Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6INT3S1~INT3S0: Interrupt edge control for INT3 pin 00: Disable 01: Rising edge 10: Falling edge 11: Both rising and falling edges Bit 5~4INT2S1~INT2S0: Interrupt edge control for INT2 pin 00: Disable 01: Rising edge 10: Falling edge 11: Both rising and falling edges Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Both rising and falling edges Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Both rising and falling edges Rev. 1.50 128 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM INTC0 Register Bit 7 6 5 4 3 2 1 Name — MF0F INT1F INT0F MF0E INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 0 Unimplemented, read as “0” Bit 6MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3MF0E: Multi-function 0 Interrupt Control 0: Disable 1: Enable Bit 2INT1E: INT1 Interrupt Control 0: Disable 1: Enable Bit 1INT0E: INT0 Interrupt Control 0: Disable 1: Enable Bit 0EMI: Global Interrupt Control 0: Disable 1: Enable Rev. 1.50 129 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM INTC1 Register Bit 7 6 5 4 3 2 1 0 Name ADF MF3F MF2F MF1F ADE MF3E MF2E MF1E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request Bit 6MF3F: Multi-function Interrupt 3 Request Flag 0: No request 1: Interrupt request Bit 5MF2F: Multi-function Interrupt 2 Request Flag 0: No request 1: Interrupt request Bit 4MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 3ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Bit 2MF3E: Multi-function 3 Interrupt Control 0: Disable 1: Enable Bit 1MF2E: Multi-function 2 Interrupt Control 0: Disable 1: Enable Bit 0MF1E: Multi-function 1 Interrupt Control 0: Disable 1: Enable Rev. 1.50 130 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM INTC2 Register Bit 7 6 5 4 3 2 1 0 Name MF4F INT3F INT2F UARF MF4E INT3E INT2E UARE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MF4F: Multi-function Interrupt 4 Request Flag 0: No request 1: Interrupt request Bit 6INT3F: INT3 pin interrupt request flag 0: No request 1: Interrupt request Bit 5INT2F: INT2 pin interrupt request flag 0: No request 1: Interrupt request Bit 4UARF: UART interrupt request flag 0: No request 1: Interrupt request Bit 3MF4E: Multi-function 4 Interrupt Control 0: Disable 1: Enable Bit 2INT3E: INT3 pin interrupt control 0: Disable 1: Enable Bit 1INT2E: INT2 pin interrupt control 0: Disable 1: Enable Bit 0UARE: UART interrupt control 0: Disable 1: Enable Rev. 1.50 131 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — T0AF T0PF — — T0AE T0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T0AF: TM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T0PF: TM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T0AE: TM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T0PE: TM0 Comparator P match interrupt control 0: Disable 1: Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name — — T1AF T1PF — — T1AE T1PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T1PF: TM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T1AE: TM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T1PE: TM1 Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.50 132 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM MFI2 Register Bit 7 6 5 4 3 2 1 0 Name — — T2AF T2PF — — T2AE T2PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T2AF: TM2 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T2PF: TM2 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T2AE: TM2 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T2PE: TM2 Comparator P match interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name — — T3AF T3PF — — T3AE T3PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T3AF: TM3 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T3PF: TM3 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T3AE: TM3 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T3PE: TM3 Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.50 133 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM MFI4 Register Bit 7 6 5 4 3 2 1 Name TB1F TB0F R/W R/W R/W POR 0 0 0 DEF LVF TB1E TB0E DEE LVE R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 7TB1F: Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 6TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 4LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3TB1E: Time Base 1 Interrupt Control 0: Disable 1: Enable Bit 2TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Bit 1DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 0LVE: LVD Interrupt Control 0: Disable 1: Enable Note: The EEPROM Interrupt is only for the HT67F489. Rev. 1.50 134 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector, if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the Accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.50 135 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Legend xxF Request Flag – no auto reset in ISR EMI auto disabled in ISR xxF Request Flag – auto reset in ISR Interrupt Request Name Flags xxE Enable Bit Interrupt Name INT0 Pin INT0F Enable Bits Master Enable Vector INT0E EMI 04H EMI 08H Request Flags Enable Bits INT1 Pin INT1F TM0 P T0PF T0PE M. Funct. 0 MF0F MF0E EMI 0CH TM0 A T0AF T0AE TM1 P T1PF T1PE M. Funct. 1 MF1F MF1E EMI 10H TM1 A T1AF T1AE TM2 P T2PF T2PE M. Funct. 2 MF2F MF2E EMI 14H TM2 A T2AF T2AE TM3 P T3PF T3PE M. Funct. 3 MF3F MF3E EMI 18H TM3 A T3AF T3AE A/D ADF ADE EMI 1CH UART UARF UARE EMI 20H INT2 Pin INT2F EMI 24H INT3 Pin INT3F INT3E EMI 28H M. Funct. 4 MF4F MF4E EMI 2CH LVD LVF LVE EEPROM DEF DEE Time Base 1 TB1F TB1E Time Base 0 TB0F TB0E Interrupts contained within Multi-Function Interrupts INT1E INT2E Priority High Low HT67F489 only Interrupt Structure Rev. 1.50 136 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM External Interrupt The external interrupt is controlled by signal transitions on the INTn pins. An external interrupt request will take place when the external interrupt request flag, INTnF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTnE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector will take place. When the interrupt is serviced, the external interrupt request flag, INTnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Multi-function Interrupt Within these devices there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, LVD interrupt, EEPROM interrupt and Time Base interrupt. A Multi-function interrupt request will take place the Multi-function interrupt request flag, MFnF is set. The Multi-function interrupt flag will be set when any of its included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to the Multi-function interrupt vector will take place. When the interrupt is serviced, the related Multi-Function request flag, MFnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, LVD interrupt, EEPROM interrupt and Time Base interrupt, will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Rev. 1.50 137 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM UART Interrupt Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, and UART interrupt enable bit, UARE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the UART Interrupt vector will take place. When the interrupt is serviced, the UART Interrupt flag, UARF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. However, the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section. Time Base Interrupt The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to the Multi-function Interrupt vector will take place. When the Time Base Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the TB0F or TB1F flag will not be automatically cleared, it has to be cleared by the application program. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. Rev. 1.50 138 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 — TB02 TB01 TB00 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 1 1 — 1 1 1 Bit 7TBON: TB0 and TB1 Control 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4 TB11, TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3 Unimplemented, read as “0” Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB Time Base Interrupt EEPROM Interrupt The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.50 139 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact and Periodic Type TMs have two interrupts each. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Periodic Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.50 140 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.50 141 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as “0” Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.50 142 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt function to avoid mistake action. Rev. 1.50 143 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. 1 Options High Speed System Oscillator Selection fH – HXT or HIRC Application Circuits V D D 0 .0 1 F * * V D D A N 0 ~ A N 9 P A 0 ~ P A 7 P B 0 ~ P B 5 0 .1 F P C 0 ~ P C 7 P D 0 ~ P D 7 P E 0 ~ P E 7 V S S P F 4 ~ P F 7 S E G 0 ~ S E G 1 9 X T 1 O S C C ir c u it X T 2 C O M 0 ~ C O M 7 T X R X Rev. 1.50 144 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Instruction Set Instruction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtekmicrocontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.50 145 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.50 146 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory section 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract immediate data from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,x SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.50 147 August 13, 2014 TinyPower TM Mnemonic HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None 2Note 2Note 2Note None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] Read table to TBLH and Data Memory TABRDL [m] Read table (last page) to TBLH and Data Memory ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and ITABRDL [m] Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.50 148 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.50 149 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.50 150 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.50 151 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.50 152 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.50 153 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ SBC A, x Description Operation Affected flag(s) Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Rev. 1.50 154 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Rev. 1.50 155 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM SNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Rev. 1.50 156 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None TABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRD [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Rev. 1.50 157 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.50 158 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.50 159 August 13, 2014 TinyPower TM HT67F488/HT67F489 A/D 8-Bit Flash MCU with LCD & EEPROM 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions Symbol Nom. Max. A — 0.472 BSC — B — 0.394 BSC — C — 0.472 BSC — D — 0.394 BSC — E — 0.032 BSC — F 0.012 0.015 0.018 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.50 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A — 12.00 BSC — B — 10.00 BSC — C — 12.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.45 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 160 August 13, 2014 HT67F488/HT67F489 TinyPowerTM A/D 8-Bit Flash MCU with LCD & EEPROM Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 161 August 13, 2014