ACTS573MS Radiation Hardened Octal Three-State Transparent Latch January 1996 Features Pinouts • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96725 and Intersil’s QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) • Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) • SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg • Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse • Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW • Input Current ≤ 1µA at VOL, VOH • Fast Propagation Delay . . . . . . . . . . . . . . . . 18ns (Max), 12ns (Typ) 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW Description The Intersil ACTS573MS is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable (LE) is High. When the latch goes low the data is latched. The output enable controls the three-state outputs. When the output enable pins (OE) are high the output is in a high impedance state. The latch operation is independent of the state of output enable. The ACTS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. OE 1 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 LE 20 VCC OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 10 11 LE GND The ACTS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9672501VRC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP 5962F9672501VXC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack ACTS573D/Sample 25oC Sample 20 Lead SBDIP ACTS573K/Sample 25oC Sample 20 Lead Ceramic Flatpack ACTS573HMSR 25oC Die Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 518892 File Number 4092 Spec Number ACTS573MS Functional Diagram 1 OF 8 IDENTICAL CIRCUITS VCC LE p Dn n p OE LE LE p Qn n LE n OE VSS COMMON CONTROLS LE LE LE OE OE OE TRUTH TABLE OE LE DATA OUTPUT L H H H L H L L L L l L L L h H H X X Z NOTE: L = Low Logic Level, H = High Logic Level, X = Don’t Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 2 518892 ACTS573MS Die Characteristics DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125kÅ ±1.125kÅ Metal 2 Thickness: 9kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110µm x 110µm Metallization Mask Layout (18) Q1 (19) Q0 (20) VCC (1) OE (2) D0 (3) D1 ACTS573MS D2 (4) (17) Q2 D3 (5) (16) Q3 NC NC NC NC Q6 (13) GND (10) Q7 (12) (14) Q5 LE (11) D5 (7) D7 (9) (15) Q4 D6 (8) D4 (6) Spec Number 3 518892