AND9237/D MatrixCamt Video Development Kit Hardware Developer's Guide Introduction This document describes the MatrixCam Video Development Kit’s HW design information from a system design perspective. Users seeking more detailed component level hardware specifications are encouraged to read the respective component data sheet from each vendor. The links to all vendors website are included in the end of the document. This HDG (Hardware Developer’s Guide) includes the following information: • MatrixCamt VDK Hardware Architecture Overview • MatrixCam VDK Hardware Blocks in Details • MatrixCam VDK System Board Schematics • MatrixCam VDK System Board Layout File • MatrixCam VDK System Board Gerber File • MatrixCam VDK System Board BOM www.onsemi.com APPLICATION NOTE MatrixCam VDK Overview The MatrixCam VDK is a low power smart 1080p camera over Wi-Fi® and Ethernet for the IoT applications. It is a reference design and can be easily integrated into a third party ID casing mechanical. MatrixCam VDK has different resolutions and frame rates for video streaming, as well as various options for video storage. The main features of the MatrixCam VDK are: • Low Power Sleep Mode can be Woken Up by PIR Motion Sensing or BLE • JPEG or Video Clips Stored in Local SD Card in Camera • Video Clips can be Optionally Stored in the Cloud • View Streaming from a Remote Device through Cloud or Local Wi-Fi Viewing from any Smart Device, or PC Viewing through Wi-Fi/Wired Ethernet • Two Way audio Communications: Speaker and Microphone • Push Notifications to Smart Devices Figure 1. MatrixCam VDK Camera The diagram below shows the top level blocks of the camera: Figure 2. MatrixCam VDK Camera Block Diagram © Semiconductor Components Industries, LLC, 2015 September, 2015 − Rev. 1 1 Publication Order Number: AND9237/D AND9237/D MatrixCam VDK Key Components and Specs Application Processor: TI−DM368 • 1080p @ 30 fps H264 Video Streaming • Picture Capture Mode: 1920 × 1080 JPEG • Built-In Image Signal Processor (ISP) • Intelligent Video Streaming • DDR2 SDRAM Support with 256 MB Memory Capacity • NAND/NOR Memory Support for Boot Ethernet: • IEEE 802.3u 10/100 mbps Image Sensor: AR023Z LED: • Multi-Color LED for Status Display Motion Sensor: • Passive Infra-Red • Horizontal Range Up to 140° Storage: • microSDt Card Slot for microSD or SDHCt Cards • Low Noise, 1/3″, 2 MP CMOS Sensor • Parallel Interface • Resolution: 1920 × 1080 @ up to 60 fps Real Time Clock: • RTC in GS2011MIES Module • 32.768 kHz Wireless Connectivity: • Wi-Fi: GainSpain GS2011MIES ♦ Single Band (2.4 GHz) Wi-Fi Module Supporting 802.11 b/g/n ♦ Client Mode Wi-Fi Support ♦ Low Power in Standby Mode • Bluetooth®: nRF51822 ♦ BLE 4.0 ♦ Be able to Configure the Camera via Bluetooth (Micro) USB Connector: • For Debugging • Retrieving Pictures from SD Card • DC Power and Charging Power Switch: • To Turn ON/OFF the System Reset Button: Lens Specification: • Horizontal and Vertical Field of View ♦ HFOV: 110° ♦ VFOV: 82° • Manual Focus • IR Cut Filter • F 2.0 • To Reset the Board, Including DM368 and Wi-Fi Module Debug Header: • UART Header for GS2011MIES POWER Source: • Power/Charge through Micro-USB Port • Single Cell Lithium Ion Battery Audio: • Microphones: Omni-Directional Microphones • Audio Encoding: 8/16 kHz, 32/64 kbps AAC−LC or • Mechanical Dimensions: • Main Board Dimension 95 mm × 65 mm G.711 Speaker: Soberton 0.5 W Cellphone Speaker www.onsemi.com 2 AND9237/D MatrixCam VDK Overall Block Diagram The top level system architecture diagram of MatrixCam VDK is shown in Figure 3. Figure 3. MatrixCam VDK Interconnection Diagram www.onsemi.com 3 AND9237/D MAIN PROCESSOR The TI DaVinciDM368 SoC contains an ARM926EJ−S® Core, ARM9 Memory Architecture, Video Processing Subsystem as well as many peripherals and sub-systems. Following diagram shows the internal architecture of DM368 application processor. Figure 4. DM368 Internal Architecture www.onsemi.com 4 AND9237/D DM368 Memory Interfaces and External Interconnections DDR2 Controller • 256 MB memory space • 16 bits data bus width • CAS latencies DDR2: 2, 3, 4, and 5 • Internal banks: DDR2: 1, 2, 4, and 8 • Burst length: 8 • • • • 1 CS signal Page sizes: 256, 512, 1024, and 2048 DDR2 SDRAM with 340 MHz operating frequency Mobile LP DDR with 167 & 200 MHz operating frequency DDR_A[13:0] DDR_BA[2:0] DDR_DQ[15:8] DDR_DQ[7:0] DDR_DQM[1] DDR_DQS[1] DDR_DQS[1]# DM368 DDR2 Controller DDR_DQM[0] DDR_DQS[0] DDR_DQS[0]# DDR_CLK DDR_CLK# DDR_CS# DDR_CAS# DDR_RAS# DDR_WE# DDR_CKE DDR_VREF DDR_PADREF Figure 5. DM368 DDR2 Controller www.onsemi.com 5 AND9237/D DDR2 DRAM DDR2 part number MT47H128M16RT−25E/ AS4C128M16D2−25BCN is used in the MatrixCam VDK. It supports 8M location with 8 Banks in 16-bit data interface and CAS latency of CL = 5. DMSoC DM368 TI The diagram below shows the interface between DDR2 memory controller of DM368 and the DDR2 memory. DDR_A[13:0] A[13:0] DDR_BA[2:0] BA[2:0] DDR_DQ[15:8] DDR_DQM[1] DDR_DQS[1] DDR_DQS[1]# DQ[15:8] UDM UDQS UDQS# DDR_DQ[7:0] DDR_DQM[0] DDR_DQS[0] DDR_DQS[0]# DQ[7:0] LDM LDQS LDQS# DDR_CLK DDR_CLK# DDR_CS# DDR_CAS# DDR_RAS# DDR_WE# DDR_CKE CK CK# CS# CAS# RAS# WE# CKE DDR_VREF DDR_PADREF VREF ODT DDR2 MT47H64M16HR−25E MICRON Figure 6. DDR2 Memory Interface NOR Flash Interface NOR flash is used to support the fast booting of the system* [In a later FW update]. • • Asynchronous memory controller of DM368 supports • DM368 support asynchronous memory interface: SRAM on up to two asynchronous ships selects addressable up to 16 MB with 16 bit and 8 MB with 8 bit data line interface both normal mode and strobe mode of operation Normal mode of operation would be a suitable mode of operation for NOR Flash memory interface * NOR Flash boot is not supported in the initial release. EMC_CE#[3:2] EM_WE# EM_OE# EM_WAIT DM368−EMIF Controller EM_D[15:0] EM_A[13:0] EM_BA[13:0] Figure 7. DM368 EMIF Controller www.onsemi.com 6 AND9237/D • The EMIF address pin EM_A [0] always provides the • • • Micron NOR Flash PC28F128M29EWLA has the following specifications: • 65 nm Single-Level Cell (SLC) technology • Uniform block flash memory, highest block protected by VPP/WP# • Supply voltage: 2.7 to 3.6 V • VPP/WP# pin protection – protects first or last blocks regardless of block protection settings • Low power consumption: standby and automatic mode • Minimum 10000 PROGRAM/ERASE cycles per block • Random access: 70 ns least significant bit of a 32-bit address EM_A [0] does not represent the lowest AEMIF address bit. The EMIF supports only 16-bit and 8-bit data widths In 8-bit mode, EM_BA [1:0] represent the 2 least significant address bits Chip select with 16 MB with 16-bit is used in the MatrixCam VDK Table 1. UNIFORM BLOCK MEMORY MAP OF NOR FLASH Address Range (x8) Address Range (x16) Block Block Size Start End Block Size Start End 127 128 kB 0FE 0000h 0FE FFFFh 64 kB 07F 0000h 07F FFFFh … … … … … 63 07E 0000h 07E FFFFh 03F 0000h 03F FFFFh … … … … … 0 000 0000h 001 FFFFh 000 0000h 000 FFFFh Following image shows the mapping between the EMIF and the connected device’s data and address pins for 16-bit data bus interface. VCC WP# EM_D[15:0] DQ[15:0] A[15] EM_A14/EM_BA[0] DM368−EMIF EM_A[13:0] A[14:1] EM_A[21:15] A[22:16] EM_BA[1] A[0] EMC_CE#[0] CE# EM_WE# WE# EM_OE# OE# GPIO RY/BY# GPIO Reset Figure 8. NOR Flash Interface www.onsemi.com 7 NOR Flash PC28F128M29EWLA MICRON AND9237/D NAND Flash The on-board 128 MB NAND flash is used for system booting. EMIF address lines are used to drive the NAND Flash device’s command latch enable (CLE) and address latch enable (ALE) signals. Any EMIF address line may be used to drive the CLE and ALE signals of the NAND Flash. However, it is recommended, especially when booting from NAND Flash, that EM_A[2:1] be used. This is because these pins are not mux with another peripheral and are therefore always available. NOTE: Micron NAND Flash MT29F2G08ABAEAH4−ITE has the following specifications: • Open NAND Flash Interface (ONFI) 1.0-compliant • Single-Level Cell (SLC) technology • Memory organization ♦ Page size x8: 2112 bytes (2048 + 64 bytes) ♦ Block size: 64 pages (128 KB + 4 KB) ♦ Device size: 2 GB: 2048 blocks • Ready/Busy# (R/B#) signal provides a hardware method for detecting operation completion • WP# signal: write protect entire device • Internal data move operations supported within the device from which data is read. The EMIF will not control the NAND Flash device’s write protect pin. The write protect pin must be controlled outside of the EMIF. Figure 9 shows the NAND flash memory interface with EMIF of DM368. VCC WP# CLE_EM_A[2] CLE CLE_EM_A[1] ALE EM_WE# FLASH−NAND MT29F2G08ABAEAH4−IT:E MICRON WE EM_OE# OE CE EM_CE#[0] DM368 EMIF EM_D[7:0] IO[7:0] EM_WAIT R/B# Figure 9. NAND Flash Interface SD Card Interface The MatrixCam VDK has a microSD card slot for local storage and development purpose. It has a Push in-Push out mechanical design for ease of use. The part number of the microSD connector is DM3BT−DSF−PEJS from Hirose. Secure Digital Card Controller has these features: • Supports a max clock rate of 50 MHz (Fast Mode) for • • microSD cards Secure Digital (SD) Physical layer specification V1.1 Note the MMC/SD controller does not support the SPI mode of operation www.onsemi.com 8 AND9237/D DM368 uSD Card SD_CLK CLK SD_CMD CMD SD_DATA[3:0] DATA[3:0] Figure 10. SD Card Interface The MMC/SD controller has two clocks, the function clock and the memory clock. The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD controller on the device. The MMC/SD controller is capable of operating with a function clock up to 100 MHz. The memory clock appears on the SD_CLK pin of the MMC/SD controller interface. The memory clock controls the timing of communication between the MMC/SD controller and the connected memory card. The memory clock is generated by dividing the function clock in the MMC/SD controller. The divide-down value is set by CLKRT bits in the MMC memory clock control register (MMCCLK) and is determined by the equation: • Memory Clock Frequency = Function Clock Frequency / (2 ⋅ (CLKRT + 1)) • CLKEN bit in MMCCLK determines whether the memory clock appears on the SD_CLK pin. If CLKEN is cleared to 0, the memory clock is not provided except when required • SD card is interfaced to SD0 of the DM368 For Debugging Firmware Upgrade UART Table 2. SD INTERFACE SIGNAL DESCRIPTION Type SD Communications MMCSD0_CLK Pin O Clock Line MMCSD0_CMD I/O Command Line MMCSD0_DAT0 I/O Data Line 0 MMCSD0_DAT1 I/O Data Line 1 MMCSD0_DAT2 I/O Data Line 2 MMCSD0_DAT3 I/O Data Line 3 USB Interface Two micro-USB connectors present on the MatrixCam VDK supporting the following features: • For debugging • Retrieving pictures from the SD card • For DC power and for battery charging USB TO UART Converter Micro USB PORT1 Serial Console for Debugging DM368 Micro USB PORT2 USB For Battery Charging USB BATTERY BATTERY CAHRGER USB PC/LAPTOP Dedicated Charger Figure 11. USB Ports Feature Mapping www.onsemi.com 9 AND9237/D Features of DM368 USB2.0 controller: • Supports USB 2.0 peripheral at high speed (480 Mbps) • • Each endpoint can support all transfer types (control, and full speed (12 Mbps) Supports USB 2.0 host at high speed (480 Mbps), full speed (12 Mbps), and low speed (1.5 Mbps) bulk, interrupt, and isochronous) Table 3. USB 2.0 INTERFACE DESCRIPTION Name I/O USB_DP A I/O/Z USB D+ (Differential Signal Pair) Description USB_DM A I/O/Z USB D− (Differential Signal Pair) USB_ID A I/O/Z USB operating mode identification pin for device mode operation only, pull up this pin to VDD with a 1.5 kW resistor. For Host mode operation only, pull down this pin to ground (VSS) with a 1.5 kW resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration. USB_VBUS A I/O/Z Five volt input that signifies that VBUS is connected. The OTG section of the PHY can also pull up/down on this signal for HNP and SRP. For device or host mode operation only, pull up this pin to 5 V with a 1 kW resistor. For host mode operation, tie USB power signal on USB connector to 5 V also. For mixed host/device mode operation, tie this to the charge pump. USBDRVVBUS I/O/Z Digital Output to Control External 5-V Supply DM368 Audio Interface For Debugging MatrixCam VDK has an on-board FT230XS USB to UART converter therefore there is no need tu use an external USB to UART device for debugging. An omnidirectional microphone and a 0.5 W Speaker are in the MatrixCam VDK. 8/16 kHz, 32/64 kbps AAC−LC and G.711 audio encoding are supported for capturing surrounding noise and playing back the recorded files stored in the SD card. DM368 has a Voice Codec with FIFO (Read/Write). The following features are supported on the Voice Codec module: • Full differential microphone amplifier • Monaural single ended line output • Monaural speaker amplifier (BTL) • Dynamic range: 70 dB (DAC) • Dynamic range: 70 dB (ADC) • 200-300 mW speaker output at RL = 8 W • Sampling frequency: 8 kHz or 16 kHz • Automatic level control for recording Retrieving Pictures/Video from SC Card When the product USB port connect into host PC in client mode, it will detected as USB mass storage to transfer the stored data from microSD card into Host PC [To be implemented in the future release]. For DC Power and Battery Charging The internal main battery of the product is charged by the external wall charger or USB downstream port though USB connector. The DC 5 V power can also be fed to the MatrixCam VDK through the USB connector. Pre−Amp Microphone MICIP MICIN DM368−Voice Codec VCOM SPP Amplifier NCP2824 SPN Speaker Figure 12. Voice Codec Interface www.onsemi.com 10 AND9237/D Speaker Output The SPP and SPN pins are monaural speaker differential outputs (BTL) with a maximum of 240 mW rms into an 8 W load per spec, but for this product this power would not be sufficient hence a Class-D Amplifier NCP2824 of 0.6 W @ 3.6 V THD + N < 1% or 0.8 W THD + N < 1% is used. The NCP2824 is a Filter less Class D amplifier capable of delivering up to 2.4 W to a 4 W load with a 5 V supply voltage. With the same battery voltage, it can deliver 1.2 W to an 8 W load with less than 1%THD+N. The non-clipping function automatically adjusts the output voltage in order to control the distortion when an excessive input is applied to the amplifier. This adjustment is done from an Automatic Gain Control circuitry (AGC) built into the chip. A simple single wire interface allows to the non-clipping function to be enabled and disabled. It also allows the maximum distortion level in the output to be configured. A programmable power limit function is also embedded in order to protect speakers from damage caused by an excessive sound level. The ARM can boot from either Asynchronous EMIF (for NOR Boot) or from ARM ROM (for NAND Boot), as determined by the setting of the device configuration pins BTSEL[2:0]. The boot selection pins (BTSEL[2:0]) determine the ARM boot process. • BTSEL[2:0] = 000 − NAND Boot mode • BTSEL[2:0] = 001 − NOR/One NAND Boot mode • BTSEL[2:0] = 010 − MMC0/SD0 Boot mode • BTSEL[2:0] = 011 − UART0 Boot mode • BTSEL[2:0] = 100 − USB Boot mode • BTSEL[2:0] = 101 − SPI0 Boot mode • BTSEL[2:0] = 110 − EMAC Boot mode • BTSEL[2:0] = 111 − HPI Boot mode Device Boot Configuration Registers The device boot configuration value is the state of the BTSEL[2:0] and AECFG[2:0] signals are captured in the BOOTCFG register. The AECFG[2:0] input pins determine the AEMIF configuration immediately after reset. By using AECFG[2:0] to properly configure the AEMIF address and Data pins. MIC Input The microphone input pins (MICIN and MICIP) can be used as a fully differential microphone of line input with selectable 20 dB or 26 dB boost and 0.07 V rms input. These analog inputs have high input impedance (10 kW), which is not changed by gain setting. The single ended output mic shall be connected with Pre-amplifier circuit to meet full scale input voltage range of Mic input and Band pass filter circuit to bypass the high & low frequency noise. Booting Options The MatrixCam VDK supports both NOR Flash and NAND Flash boot in the initial FW release. NOR Flash Boot If BTSEL[2:0] = 001 − Asynchronous EMIF boot mode (NOR Flash). This mode is handled by hardware control and does not involve the ROM. If booting from NOR Flash then the appropriate number of address output must be enabled by the AECFG[2:0] inputs at reset. In 16-bit mode, EM_BA[1] represents the least significant address bit (the half−word address) and EM_BA[0] represents the address bit (A[14]). The device has 23 address lines and 2 chip selects with an 8-bit or 16-bit option. For boot from 16 bit NOR Flash interface, the resistor/register setting of AECFG is set to 101 to get MSB data lines and 16 address lines (EM_A[14:0] and EM_BA[1]) for NOR Flash boot. Table 4. DM368 AUDIO INTERFACE DESCRIPTION Signal Name Signal Type MICIP Input MIC Positive Signal MICIN Input MIC Negative Signal SPP Output Speaker Amplifier Positive Signal SPN Output Speaker Amplifier Positive Signal VCOM Input Function Analog Block Common Voltage NAND Flash Boot If the value of BTSEL[2:0] = 000, the NAND Boot mode executes. NAND Flash boot wouldn’t support for a full firmware boot. Instead, copies a second stage user-boot loader (UBL) from NAND Flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL and it support 4-bit ECC. The NAND boot mode assumes the NAND is located on the EM_CE0 interface, the bus configuration is configured by the AECFG[2:0] pins. There is specific AECFG configuration required for NAND boot as all the required signals are available in the default state AECFG[2:0] = 000. NAND Boot supports 8-bit Flash interface only and it is recommended that EM_A[2:1] should be used for CLE and ALE especially when booting from NAND Flash. This is Microphone Interface Details Please refer to the DM368 data sheet for a detailed description of the microphone anti-aliasing filter, preamplifier design, and single ended to differential conversion. DM368 Boot Modes DM368 supports 8 different Boot modes and configurable Power-Saving modes. These boot modes support in two different ways. • On-chip ARM ROM Boot Loader (RBL) to boot from NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI • AEMIF (NOR and one NAND) www.onsemi.com 11 AND9237/D because these pins are not muxed with another peripheral and are therefore always available. Chip Select: EM_CE[0] is used for the default boot and ROM boot modes. By default, NOR Flash will be connected in EM_CE[0] and NAND Flash will be connected in EM_CE[1]. And option will be provided to swap the chip selects, to select NAND Flash as a Boot memory. Following flow chart shows the Boot sequence in case of NAND Flash as boot device: Reset BTSEL[2:0] = 001 RBL BOOT ? NOR Yes Supported RBL Boot Loader NAND NAND Boot MMCSD UART MMCSD Boot Boot OK ? No Yes Boot OK ? UART Boot Boot OK ? No Yes USB USB Boot No Boot OK ? Yes No Yes UBL Figure 13. Boot Mode Selection Flow Chart downloaded to the on-chip ARM internal RAM via the on-chip serial UART and executed. A host program, (referred to as serial host utility program), manages the interaction with RBL and provides a means for operator feedback and input. • The UART moot mode execution assumes the following UART settings: 24 MHz reference clock, time-out 500 ms, one-shot Serial RS−232 port 115.2 kbps, 8-bit, no parity,one stop bit Command, data, and check sum format. Everything sent from the host to the device UART RBL must be in ASCII format • No support for a full firmware boot. Instead, loads a second stage user boot loader (UBL) via UART to ARM internal RAM (AIM) and transfers control to the user software • Support for up to 30 kB UBL (32 kB − ~2 kB for RBL stack) SD Card Boot: If BTSEL[2:0] = 010 or NAND boot fails. No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from MMC/SD to ARM Internal RAM (AIM) and transfers control to the user software. • Support for MMC/SD native protocol (MMC/SD SPI protocol is not supported) • Support for descriptor error detection and retry (up to 24 times) when loading UBL • Support for up to 30 kB UBL (32 kB − ~2 kB for RBL stack) • SDHC boot supported by RBL UART Boot: If the state of BTSEL[2:0] pins at reset is 011, then the UART boot mode executes. This mode enables a small program, referred to here as a user boot loader (UBL), to be www.onsemi.com 12 AND9237/D DM368 Clock Requirement operating frequency is 24 MHz, which is the frequency used in the MatrixCam VDK. The 24 MHz input drives two separate PLL for ARM and clock required for peripherals. The external crystal load capacitors must be connected only to the oscillator ground pin (VSS_MX1). DM368 requires Main oscillator (MXI1) that provides the Primary reference clock for the device with external crystal or resonator. The optimal frequencies for the crystals are 19.2 MHz, 24 MHz, 27 MHz, and 36 MHz and typical Table 5. CRYSTAL REQUIREMENT FOR THE DM368 INPUT CLOCK Parameter Min Typ Max Unit Start-Up Time (from Power-Up until Oscillating at Stable Frequency) − − 2 ms Oscillation Frequency − 19.2/24/27/36 − MHz Crystal ESR 19−30 MHz 30−36 MHz − − − − 60 40 Frequency Stability − − ±50 W ppm DM368 Reset Requirement In the MatrixCam VDK the ABM8−24.000MHZ−R60− D−1−W−T part is used along with C1 and C2 witch are both 36 pF. The DM368 has two pins (RTCXI/RTCXO) for the external crystals or ceramic resonators to provide clock inputs. The oscillator mainly supplies the clock to the RTC block and since the internal RTC of DM368 is not used in the design, the RTCXI shall be pulled down & RTCXO shall be NC. DM368 requires reset for PRTC subsystem and DM368 device. Reset pin RESETN is for Global reset and PWRST is for PRTC subsystem. The active low width of the nRESETpulse should be less than 12 Clock cycle. (C = MXI1/CLKIN) RESET Figure 14. PRTCSS of DM368 is not used in the design and will be operated in the External reset mode. In External reset mode, PWRCNTON input pin should be held at 1 and the PWRST pin should be held at 0 and the device reset signal (RESET#) will reset the PRTCSS. The following steps should be followed for the simple power-off method: 1. Power off the Main/Analog I/O (3.3-V) 2. Power off the PRTCSS/Main I/O (1.8-V) 3. Power off the PRTCSS/Main core (1.35-V) DM368 Power-Supply Sequencing Notes for simple power-off: • If RESET is low, steps 2 and 3 may be performed Simple Power-On and Power-Off Method The following steps must be followed in sequential order for the simple power-on method: 1. Power on the PRTCSS/ Main core (1.35-V) 2. Power on the PRTCSS/Main I/O (1.8-V) 3. Power on the Main/Analog I/O (3.3-V) • simultaneously If RESET is not low, these steps must be followed sequentially Note for simple power-on: • RESET must be low until all supplies are ramped up www.onsemi.com 13 AND9237/D AR023Z Imager and DM368 DATA[11:0] DATA[11:0] PIXCLK PIXCLK LINE_VALID LINE_VALID FRAME_VALID FRAME_VALID FLASH SHUTTER DM368−VPFE AR023Z TRIGGER GIOxx OE_BAR GIOxx 1.8 V to 3.3 V Translator RESET_BAR GIOxx EXTCLK GIO93 SADDR SCLK SDATA I2C_SCLK PCA9306 I2C_DATA Figure 15. AR023Z For the AR023Z the parallel pixel data interface is disabled by default at power up and after a reset. It can be enabled by programming the AR023Z’s R0x301A register. Please refer to the AR023Z data sheet for other details about the configuration of this image sensor. Table 6. PARAMETERS OF AR023Z IMAGE SENSOR Parameter Typical Value Optical Format 1/2.7-inch (6.6 mm) Active Pixels 1924 (H) × 1088 (V) (19:9 Mode) Pixel Size 3.0 × 3.0 mm Color Filter Array RGB Bayer Shutter Type Electronic Rolling Shutter and GRR Input Clock Range 6−48 MHz Output Clock Maximum 148.5 Mp/s (4-Lane HiSPi) 74.25 Mp/s (Parallel) Output Serial Parallel HiSPi 10-, 12-, 14-, 16-, or 20-bit 10-, 12-bit Frame Rate − 1080p 60 fps Responsivity 4.0 V/Lux-sec SNRMAX 41 dB Max Dynamic Range Up to 105 dB Supply Voltage I/O Digital Analog HiSPi 1.8 or 2.8 V 1.8 V 2.8 V 0.3−0.6 V (SLVS), 1.7−1.9 V (HiVcm) Power Consumption (Typical) < 896 mW (HDR 1080p 60, 8x gain, 25°C) Operating Temperature −30°C to 85°C Ambient Package Options 10 × 10 mm 80-pin iBGA www.onsemi.com 14 AND9237/D AR023Z Parallel Interface • The parallel pixel data interface uses these output-only signals: ♦ FV ♦ LV ♦ PIXCLK ♦ DOUT[11:0] • The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A • When the parallel pixel data interface is in use, the serial data output signals and VDD_SLVS can be left unconnected AR023Z Imager Data/Control from DM368: • AR023Z has two interface options with the processor ♦ HiSPi ♦ Parallel • DM368 does not support the MIPI interface. So a parallel interface is implemented in this design. • The 12 bit data lines are connected to the ISIF block of DM368 processor • The data and control line implementation for sensor interface is shown in Figure 15 • The Data lines are interfaced directly with the ISIF block as it can be directly powered with 1.8 V. So the level translators can be avoided • However for clock out from processor and other control lines which are not in ISIF block need a level shifting from 3.3 V to 1.8 V • External clock input for the imager is given by the DM368 processor on pin CLKOUT0 • The CLKOUT0 of DM368 is directly coming from main clock i.e. 24 MHz AR023Z Output Enable Control • When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control Table 7. OUTPUT ENABLE CONTROL OF AR023Z IMAGE SENSOR OE_BAR Pin Drive Signals R0x301A−B[6] Description Disabled 0 Interface High-Z Disabled 1 Interface Driven 1 0 Interface High-Z X 1 Interface Driven 0 X Interface Driven • The protocols described in the two-wire serial interface AR023Z Imager Configuration from DM368 I2C Interface • The imager is configured via I2C interface from the processor • The two-wire serial interface bus enables read/write access to control and status registers within the AR023Z. This interface is designed to be compatible with the electrical characteristics and transfer protocols of the I2C specification • The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 kW resistor. Either the slave or master device can drive SDATA LOW − the interface protocol determines which device is allowed to drive SDATA at any given time • • specification allow the slave device to drive SCLK LOW; the AR023Z uses SCLK as an input only and therefore never drives it LOW The I2C interface from processor to the Imager requires a level translator. PCA9306 I2C level shifter is used for this purpose AR023Z SADDR pin is used for configuring I2C address. An option of pull-up and pull-down resistor would be provided to configure the address AR023Z Unconnected Pins • When parallel interface is implemented the serial HiSPi lines & VDD_SLVS can be left unconnected • The shutter and the flash lines if not used can also be left unconnected • Trigger and OE_BAR are pulled down to DGND www.onsemi.com 15 AND9237/D AR023Z Power-Up and Power-Down Sequence Power-Up Sequence The recommended power-up sequence for the AR023Z is shown in Figure 16. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply 2. After 100 ms, turn on VAA and VAA_PIX power supply 3. After 100 ms, turn on VDD_IO power supply 4. After 100 ms, turn on VDD power supply 5. After 100 ms, turn on VDD_SLVS power supply VDD_PLL (2.8) 6. After the last power supply is stable, enable EXTCLK 7. Assert RESET_BAR for at least 1 ms. The parallel interface will be tri-stated during this time 8. Wait 150000 EXTCLKs (for internal initialization into software standby 9. Configure PLL, output, and image settings to desired values 10. Wait 1 ms for the PLL to lock 11. Set streaming mode (R0x301a[2] = 1) t0 VAA_PIX VAA (2.8) t1 t2 VDD_IO (1.8/2.8) VDD (1.8) t3 VDD_SLVS (0.4) EXTCLK t4 RESET_BAR tX t5 Hard Reset Internal Initialization t6 Software Standby PLL Lock Streaming Figure 16. AR023Z Sensor Initialization Table 8. AR023Z POWER-UP SEQUENCE TIMING PARAMETERS Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX (Note 3) t0 0 100 − ms VAA/VAA_PIX to VDD_IO t1 0 100 − ms VDD_IO to VDD t2 0 100 − ms VDD to VDD_SLVS t3 0 100 − ms Hard Reset t4 1 (Note 2) − − ms Internal Initialization t5 150000 − − EXTCLKs PLL Lock Time t6 1 − − ms 1. Xtal settling time is component-dependent, usually taking about 10–100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. www.onsemi.com 16 AND9237/D Power-Down Sequence The recommended power-down sequence for the AR023Z is shown in Figure 17. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, and VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended 3. Turn off VDD_SLVS 4. Turn off VDD 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX 7. Turn off VDD_PLL VDD_SLVS (0.4) t0 VDD (1.8) t1 VDD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until next Power Up Cycle Figure 17. AR023Z Power-Down Sequence Table 9. AR023Z POWER-DOWN SEQUENCE TIMING PARAMETERS Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD t0 0 − − ms VDD to VDD_IO t1 0 − − ms VDD_IO to VAA/VAA_PIX t2 0 − − ms VAA/VAA_PIX to VDD_PLL t3 0 − − ms PwrDn until Next PwrUp Time (Note 4) t4 100 − − ms 4. t4 is required between power-down and next power-up time; all decoupling caps from regulators must be completely discharged. Camera Lens The MatrixCam VDK uses an F2.0 2.8 mm fixed lens manufactured by Xiamen Leading Optics. www.onsemi.com 17 AND9237/D MICROCONTROLLER To maintain the low power consumption of the MatrixCam VDK the application processor will be put in the low power/off mode. All the other devices will be put in the deep sleep/off mode as well. To wake up the application processor and to monitor the trigger coming from the PIR and the BLE module, a housekeeping microcontroller is used. The MatrixCam VDK uses GainSpan GS2011MIES module for this purpose. WAKE on PIR Sensor DM368 uC WAKE on BLE Figure 18. Application Processor Trigger Event GS2011MIES Module Overview The MatrixCam VDK has the following requirements and the GS2011MIES Module meets all of these requirements: 1. Application controller should be always active in low power state 2. Be proactive for the interrupts from PIR sensor and wake up the application 3. Be proactive for the interrupts from BLE and wake up the application processor 4. Control the DM368 power on/off sequence 5. Control and monitor the battery charger and fuel gauge 6. Real time controller 7. To provide status indication Figure 19. GS2011MIES Internal Architecture www.onsemi.com 18 AND9237/D The GS2011MIES Module uses GS2000 SoC, which combines ARM Cortex® M3-based processors with a 802.11b/g/n Radio, MAC, security, and PHY functions, as well as RTC and SRAM. It has up to 2 MB FLASH, and on board and off module certified antenna options. The module provides a Wi-Fi and regulatory certified IEEE 802.11b/g/n radio with concurrent network processing services for variety of applications. backup copy, it can be accomplished by asserting the appropriate GPIO pins as shown in the table below during power up or reset. GS2011MIES Pin Multiplexing The GS2011MxxS pins have multiple functions that can be selected by software. Each pin has an independent MUX select register. Table 10 below shows the various MUX functions for each pin. All pins are GPIO inputs at reset. For pins that are inputs to functional blocks only one pin may be assigned to any input function. For example, UART1_RX may be assigned to GPIO3 but not to both GPIO3 and GPIO37. GPIO assignment of GS2011MIES can be seen in the main block diagram and for a quick reference. Please refer Table 10 below. GS2011MIES Boot Modes The respective GPIO pins are sampled at reset by device and depending on the values seen on these pins the module goes into the appropriate mode. Code for the GS2011MxxS resides on the internal flash of the module and up to two back-up copies could be stored in flash. If a software designer wants to restore the execution code to one of the Table 10. GS2011MIES PIN ASSIGNMENT S# Pin Name Net Name Function I/O Interface 1 ADC_1 ADC_MCU TP 2 RTC_IO_1 3 RTC_IO_2 SoC_MCU_STDY_WAKE 4 I2C_CLK/ GPIO9 MCU_I2C_SCL I2C CLK I I2C Refer to I2C Interface Section 5 I2C_DATA/ GPIO8 MCU_I2C_SDA I2C DATA I/O I2C Refer to I2C Interface Section 6 DC_DC_CNTRL/ RTC_I/O_4 DC_DC_CNTRL TP 7 SPI0_CS#_0/ SDIO_DAT3/ GPIO33 MCU_SPI_CS SPI Interface I SPI 8 SPI0_CLK/ SDIO_CLK/ GPIO35 MCU_SPI_CLK SPI Interface I SPI 9 SDIO_DAT1_INT/ GPIO37 MCU_BT_GPIO GPIO I/O SDIO 10 SPI0_DIN/ SDIO_CMD/ GPIO34 MCU_SPI_MOSI SPI Interface I SPI SPI1 of DM368 11 SPI0_DOUT/ SDIO_DAT0/ GPIO36 MCU_SPI_MISO SPI Interface O SPI SPI1 of DM368 12 SPI1_CS#_0/ GPIO4 MCU_SoC_GPIO2 GPIO I/O As per Requirement 13 SPI1_CS#_1/ GPIO13 MCU_OFF_REQ GPIO I Active Low Int# from LTC2950−1 IC. After a push button turn-off event is detected, the LTC2950 interrupts the system (mP) by bringing the INT pin low. Once the system finishes its power down and housekeeping tasks, it sets KILL low (MCU_OFF), which in turn releases the enable output. If at the end of the power down timer (1024 ms) KILL (MCU_OFF) is still high, the enable output is released immediately. 14 SPI1_CLK/ GPIO5 MCU_OFF GPIO O Active Low Forcing KILL(MCU_OFF) low releases the enable output. During system turn on, this pin is blanked by a 512 ms internal timer to allow the system to pull KILL high. This pin has an accurate 0.6 V threshold and can be used as a voltage monitor input. TP I Sense Remarks NA NC NA NC NA Not Required but Connected for Future Use NC www.onsemi.com 19 Active Low SPI1 of DM368 SPI1 of DM368 Connected to BT GPIO P0_7 for Handshaking if Required Connected to DM368 GPIO44 for Handshaking AND9237/D Table 10. GS2011MIES PIN ASSIGNMENT (continued) S# Pin Name Net Name Function I/O 15 SPI1_DIN/ GPIO6 PIR_DIG_OUT GPIO I Active High 16 SPI1_DOUT/ GPIO7 ON_OFF_SWITCH GPIO I Active Low 17 UART0_RX/ GPIO0 MCU_UART0_RX UART I UART Provided on 4-pin Header 18 UART0_TX/ GPIO1 MCU_UART0_TX UART O UART Provided on 4-pin Header 19 UART0_CTS/ GPIO24 MCU_SoC_GPIO1 GPIO I/O 20 UART0_RTS/ GPIO25 MCU_PRGM_SoC_WAKE GPIO O 21 UART1_RX/ GPIO3 MCU_BT_UART_RX UART O UART Connected to P0_11 of the BT 22 UART1_TX/ SDIO_DAT2/ GPIO32 MCU_BT_UART_TX UART I UART Connected to P0_09 of the BT 23 UART1_CTS/ GPIO26 SoC_nRESET GPIO O Active Low Drive High to Take Out the DM368 Out of Reset 24 UART1_RTS/ GPIO27 MCU_PRGM_BT_PWR_EN GPIO O Active High Terminated on the DIP Switch 25 PWM0/GPIO10 SYS_PWR_EN GPIO O 26 PWM1/GPIO31 GPIO_IO_EXP_INT GPIO 27 CLK_HS_XTAL/ GPIO19 MCU_SoC_GPIO4 GPIO 28 CLK_RTC/ GPIO21 CLK_RTC RTC_CLK 29 EXT_RESET# MCU_RESET_SCH RESET VPP MCU_OTP_VPP TP 30 NOTE: Interface Sense As per Requirement Remarks This Signal will be used for Factory Reset of the Device Connected to DM368 GPIO22 for Handshaking Connected to GIO0 of DM368 Drive High to Enable DM368 Power Interrupt from I/O Expander I/O As per Requirement Connected to DM368 GPIO37 for Handshaking NC I Reset Button is Connected for GS2011MIES Reset NA MCU_OFF and MCU_OFF_REQUEST signals need to be taken care for power on and off as mentioned. GS2011MIES Host Interface the Standby state. It is powered by a supply pin (VRTC) from the digital core, or it can receive power directly from a battery. The RTC implementation supports a voltage range of 1.6 V to 3.6 V. GS2011MIES supports SPI0, SPI1 and SDIO as host interface. Due to the lack of SDIO interface in DM368, SPI0 is used as the host interface to DM368. SPI0 of GS2011MIES is in slave mode and can support 10 MHz max. Note that OEM can also use SPI1 as the host interface to DM368. NOTE: GS2011MIES I2C Interface The MatrixCam VDK is battery powered and the same battery is used for the RTC backup. A “Battery Low” notification will be provided to the user over Wi-Fi when the main battery is discharged to 3.2 V. In MatrixCam VDK the GS2011MIES module is required to operate in the master mode to control and monitor the Sensor interfaces. Image sensor primary control is by GS2011MIES through I2C slave select and it can be handover to DM368 by GS2011MIES. Please refer to the “System I2C Interface” section for details. GS2000 SoC Clock Requirement RTC in the GS2000 SoC The GS2011MIES module has both clocks built in so no external clock is required. The GS2000 SoC requires two separated clocks for its operation: • A slow clock running at 32.768 kHz is used for the RTC • A fast clock running at 40 MHz is used by the module for the internal processor and the WLAN subsystem GS2011MIES has a RTC which provides the global time (and date) to the system. The RTC is always on to manage www.onsemi.com 20 AND9237/D 3V3 GS2011MIES Module Reset GS2011MIES EXT_RESET_n is an active low signal. It is an output during power up to indicate to the system when GS2011MxxS device is coming out of the power-on-reset. After power-on-reset this pin is an input. It is not necessary to assert reset to the GS2011MxxS after power on because the GS2011MxxS has a built-in power on reset. Also, the EXT_RESET_n signal does not clear the RTC, RTC RAM, or the SRAM. If the external host is driving the EXT_RESET_n pin, it MUST do so with an open drain driver. This is because this pin is also driven by the RTC. In addition, if an external host is connected to the EXT_RESET_n pin, there must be an external 10 kW resistor pulling the pin to VDDIO. EXT_RESET_N Figure 20. GS2011MIES Reset Section GS2011 GPIO I/O Expander Due to non-availability of the GPIOs in GS2011MIES, we are using the I/O expander PCA9538BS from NXP to provide some extra GPIOs. Table 11 shows how this IO expander’s GPIOs are used. Table 11. GS2011MIES AND THE I/O EXPANDER PIN ASSIGNMENT I2C I/O Expander Pin Name Signal Name Direction Sense I/O1 BT_MCU_WAKE_UP I Programmable I/O2 SoC_MCU_WAKE_UP I Programmable I/O3 MCU_LED_RED_CTRL O Active High Drive to Glow the LED I/O4 MCU_LED_GREEN_CTRL O Active High Drive to Glow the LED I/O5 FG_ALARMB I Active Low Wake Up the System through “GPIO_IO_EXP_INT” Signal Connected to GPIO31 Note: GPIO31 Needs to be Configured as Interrupt Source. I/O6 MCU_BT_PWR_EN O Active Low Drive High to Enable BT Power I/O7 MCU_SoC_GPIO3 I/O Programmable I/O8 USB_WAKEUP_MCU I Active High Remarks Wake Up the System through “GPIO_IO_EXP_INT” Signal Connected to GPIO31 Note: GPIO31 Needs to be Configured as Interrupt Source. Handshaking Signal between DM368 and GS2011MIES To Tell the GS Module USB Plug In GS2011MIES WLAN RF GS2011MIES has on board UFL connector for connecting the external flexible PCB antenna. The MatrixCam VDK uses Taoglas FXP73.07.0100A antenna. Table 12. GS2011MIES WLAN RECEIVER CHARACTERISTICS Parameter RF Frequency Range Radio Bit Rate Minimum Typical Maximum Unit 2400 − 2497 MHz 1 − HT20 MCS7 Mbps Notes TRANSMIT/RECEIVE SPECIFICATION FOR GS2011MIxS Output Power (Average) − − − − − − 17 12 14 10 12 6 − − − − − − dBm 11b, 1 Mbps 11b, 11 Mbps 11g, 6−18 Mbps 11g, 64-QAM 11n, MCS 0 − MCS 3 11n, MCS 7 Spectrum Mask − − − dBr Meet 802.11 Requirements for Selected Data Rates Receive Sensitivity at Antenna Port − − − −93 −74 −71 − − − dBm 11b, 1 Mbps, BPSK/DSSS 11g, 54 Mbps, 64-QAM/OFDM 11n, MCS 7 (72 Mbps), 64-QAM/OFDM NOTE: Sufficient clearance should be kept between the two (BLE and Wi-Fi) antennas. www.onsemi.com 21 AND9237/D System Wake Up through GS2011MIES As stated earlier, to maintain the low power state of the MatrixCam VDK the application processor should be in the low power/off mode and all other devices should also be in deep sleep/off mode. The main processor can be woken up by the PIR and BLE module through interfacing to the GS2011MIES and some glue logic. The glue logic is the I/O expander mentioned in GS2011 GPIO I/O Expander section. There are three low power states in the GS2011MIES. They are standby, Sleep and Deep-sleep. The MatrixCam VDK is designed to be in the Deep-sleep mode all the time and will only be woken up on interrupt from PIR or BLE. Any GPIO of the GS2011MIES can be configured as an interrupt source to wake up the DM368. The MatrixCam VDK will give a push notification to the user in case the battery is low. The interrupt form the fuel gauge “FG_ALARMB” connected to I/O4 of the I/O expander will wake up the system and give a notification to the user when battery is low. There is one more I/O which needs to be configured as interrupt to do the factory reset. Tactile switch is connected to the GPIO7 of the GS2011MIES. PIR is directly connected to the GPIO6 of the GS2011MIES and GPIO6 needs to be configured as interrupt. Please refer to GS2011MIES DS for complete description of the different low power modes. Note that the MatrixCam VDK does not support STANDBY mode of GS2011MIES. www.onsemi.com 22 AND9237/D BLE MODULE • Supports non-concurrent multi-protocol operation • Flexible power management • Power supply features: In the MatrixCam VDK BLE (Bluetooth Low Energy) is used to wake up the system but it can also be used for other purposes, such as to configure the MatrixCam VDK from the smart devices. The MatrixCam VDK uses a Multi protocol BLE 4.0 SoC nRF51822 from Noridic semiconductors. Figure 25 shows the BLE & Wi-Fi module interface on a block diagram level. ♦ ♦ ♦ nRF51822−QFAA Specification • • • • 2.45 GHz transceiver ARM Cortex−M0 32-bit processor Built-in 256 kB Flash memory and 16 kB RAM UART & SPI interface for intercommunication Supply voltage range of 1.8 to 3.6 V using internal LDO regulator Low voltage mode of 1.75 to 1.95 V (external voltage regulator is required) Supply voltage range of 2.1 to 3.6 V using internal buck DC/DC converter BLE Interface Block Diagram BLE will be used to wake up the GS2011MIES and it will in turn wake up the DM368. Figure 21. BLE Interface Block Diagram nRF51822 Power Supply Figure 22 shows the power supply module present in nRF51822 BLE SoC. VDD nRF51 DCDCEN VDD System Power DC/DC Converter LDO DCC AVDD DEC2 DEC1 VSS Figure 22. BLE Power Supply nRF51822 has an internal DC/DC converter to step down the input supply voltage (VDD). By default the DC/DC converter is disabled (DCDCEN = 0x0 default). Without enabling it the AVDD pin of the IC will have the VDD voltage. This VDD will be the input to the internal LDO. The internal LDO outputs 1.8 V at the DEC2 pin. The DEC1 pin is only used for decoupling purpose. For the MatrixCam VDK the BLE part is powered by a 3.3 V pre-regulated power source, so the IO voltage is also 3.3 V. www.onsemi.com 23 AND9237/D CPU in nRF51822 nRF51822 Clock Management A low power ARM Cortex−M0 32 bit CPU is embedded in the nRF51822. The ARM Cortex−M0 has a 16 bit instruction set with 32 bit extensions (Thumb)−2 technology) that delivers high density code with a small memory footprint. There are 32 GPIOs available in the BLE controller. Among these GPIOs any of the pin can be configured to any functionality supported by nRF51822 SoC. The system depends on, and generates, two different clocks, i.e. a high frequency clock (HFCLK) and a low frequency clock (LFCLK). These clocks are only available when the system is in ON mode. The HFCLK is fixed to 16 MHz and the LFCLK is fixed to 32.768 kHz. HFCLK − The system supports two high frequency clock sources 16/32 MHz crystal oscillator and the 16 MHz RC oscillator. The HFCLK crystal oscillators require an external AT-cut quartz crystal (16/32 MHz) to be connected to the XC1 and XC2 pins in parallel resonant mode. When the system enters ON mode, the 16 MHz RC oscillator will start up automatically to provide the HFCLK to the CPU and other active parts of the system. The 16 MHz RC oscillator is automatically switched off when one of the HFCLK crystal oscillators is running. LFCLK − Possible clock sources for the LFCLK are the 32.768 kHz crystal oscillator, the 32.768 kHz RC oscillator, and the 32.768 kHz synthesized clock. For crystal oscillator AT-cut quartz crystal to be connected to the XL1 and XL2 pins in parallel resonant mode. The XL1 and XL2 share pins with the GPIO. For the MatrixCam VDK design a 16 MHz crystal (with 12 pF load capacitors) is used for the HFCLK, and a 32.768 kHz crystal (with 18 pF load capacitors) is used for the LFCLK. To achieve correct oscillation frequency, the load capacitance must match the specification of nRF51822 SoC. nRF51822 Interface UART & SPI interfaces are available for Intercommunication in nRF51822 SoC. BLE interfaces to the GS2011MIES through an UART interface. For a development option, the SPI on the device is connected to the DM368. Upon receiving any BLE packet the device will wake up the GS2011MIES through “BT_MCU_WAKE_UP”. UART is featuring a Full-Duplex operation and automatic Flow Control. Enabling and disabling the flow control is available. SPI Master/Slave mode is configurable in the nRF51822 SoC. SPI Master can provide a simple interface with CPU. The SPI master does not implement support for chip select directly. Therefore, the CPU must use available GPIOs to select the correct slave and control this independently of the SPI master. The SPI master supports SPI modes 0 to 3. SPIS is a SPI slave with EasyDMA support for ultra-low power serial communication from an external SPI master. For this product SPIS is chosen for communication between DM368 application processor and the BLE SoC. NOTE: UART of the device will also be provided on the header to provide the flexibility to program the device by Segger. XC1 XC2 C1 C2 16/32 MHz Crystal Figure 23. 16/32 MHz Crystal Oscillator Circuit Diagram The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by: CL + C1Ȁ @ C2Ȁ C1Ȁ ) C2Ȁ Where: C_pin − Pin Input Capacitance C_pcbX − Stray Capacitance (eq. 1) C1Ȁ + C1 ) C_pcb1 ) C_pin (eq. 2) C2Ȁ + C2 ) C_pcb2 ) C_pin (eq. 3) www.onsemi.com 24 AND9237/D nRF51822 Software Debugging Interface SWD − Serial Wire Debugging interface is used for software debugging. SWDCLK SWDCLK DIF SWDIO DAP ARM CoreSigtht DAP-Lite nRESET SWDIO/nRESET POWER Figure 24. nRF51822 Debug Interface The interface has two lines SWDCLK and SWDIO. SWDIO and nRESET share the same physical pin. The Debugger Interface (DIF) module is responsible for handling the resource sharing between SWD traffic and reset functionality. The SWDCLK pin has an internal pull down resistor and the SWDIO/nRESET pin has an internal pull up resistor. The DIF module will be in normal mode after power on reset. In this mode the SWDIO/nRESET pin acts as a normal active low reset pin. To guarantee that the device remains in normal mode, the SWDCLK line must be held low, that is, ‘0’, at all times. Failing to do so may result in the DIF entering into an unknown state and may lead to undesirable behavior and power consumption. Debug interface mode is initiated by clocking one clock cycle on SWDCLK with SWDIO = 1. Due to delays caused by starting up the DAP’s power domain, a minimum of 150 clock cycles must be clocked at a speed of minimum 125 kHz on SWDCLK with SWDIO = 1 to guaranty that the DAP is able to capture a minimum of 50 clock cycles. In debug interface mode, the SWDIO/nRESET pin will be used as SWDIO. The pin reset mechanism will therefore be disabled as long as the device is in debug interface mode. Normal mode can always be resumed by performing a “hard-reset” through the SWD interface: 1. Enter debug interface mode 2. Enable reset through the RESET register in the POWER peripheral 3. Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 ms In the MatrixCam VDK a 6-pin JTAG header is used for the SWD and UART interface. VCC_BT_3V3 H15 1 BT_UART_T- 3 X 5 2 4 6 DB_SWDIO/BLE_RST# DB_SWDCLK BT_UART_RX HDR_2X3 Figure 25. nRF51822 JTAG Header www.onsemi.com 25 AND9237/D • Transmitter with programmable output power of RESET to the nRF51822 The RESET signal for the nRF51822 is coming from the DM368 Application processor. The reset pin in nRF51822 is an low active pin multiplexed with SWDIO (in software debugging mode). The default condition of this SWDIO pin is for “RESET”, and it will be changed to “SWDIO” under DIF when certain special conditions are met (see section nRF51822 Software Debugging Interface above). Under normal mode the minimum Hold time for RESET pin to do a full RESET is 0.2 ms. It is 100 ms during the debug mode. • • • • • BLE RF The nRF51 series 2.4 GHz RF transceiver is designed and optimized to operate in the worldwide ISM frequency band at 2.400 to 2.4835 GHz. Radio modulation modes and configurable packet structure make the transceiver inter-operable with Bluetooth low energy (BLE), ANTt, Enhanced ShockBurstt, and other 2.4 GHz protocol implementations. The transceiver receives and transmits data directly to and from system memory for flexible and efficient packet data management. The nRF51822 transceiver has the following features: • General modulation features • GFSK modulation • Data whitening • On-air data rates ♦ 250 kbps ♦ 1 Mbps ♦ 2 Mbps +4 dBm to −20 dBm, in 4 dB steps Transmitter whisper mode −30 dBm RSSI function (1 dB resolution) Receiver with integrated channel filters achieving maximum sensitivity ♦ −96 dBm at 250 kbps ♦ −93 dBm at 1 Mbps BLE ♦ −90 dBm at 1 Mbps ♦ −85 dBm at 2 Mbps RF synthesizer Baseband controller The MatrixCam VDK has an UFL connector for the external antenna to connect to. The model number of the UFL connector is U.FL−R−SMT−1 from Hirose. Please refer to the nRF51822 data sheet for the layout instructions details. www.onsemi.com 26 AND9237/D PIR SENSOR The components for PIR section include PIR detector (Dual Type Pyroelectric Infrared Sensor IRA−E700 Series from Murata), PIR signal conditioning IC (NCS36000DG from ON Semiconductor), I2C controlled digital Potentiometer (CAT5132ZI-00-GT3 from ON Semiconductor) and the Fresnel Lens. The MatrixCam VDK PIR has the following features: • The sensitivity can be controlled by software • The lens has the coverage of 140° in the horizontal axis • The length of coverage is around 10 to 15 feet The PIR detector supports the single face of 45 degree; hence for both faces it can support 90 degree. The 140 degree coverage can be achieved by using the external Fresnel lens. PIR Detector Controller − NCS36000DG The ON Semiconductor NCS36000 is a fully integrated mixed-signal CMOS device designed for low-cost passive infrared controlling applications. The device integrates two low-noise amplifiers and a LDO regulator to drive the sensor. The output of the amplifiers goes to a window comparator that uses internal voltage references from the built in regulator. The digital control circuit processes the output from the window comparator and provides the output to the OUT and LED pin. PIR Detector VREF VDD VSS Dual Type Pyro electric Infrared Sensor IRA−E700 Series from Murata has high sensitivity around 4.3 mV (Peak-to-Peak), and can be amplified and filtered by the signal conditioning unit. The fundamental frequency range of detector output is in the range of 0.5 Hz to 25 Hz. 2 LDO & Voltage References OP1_P MODE OP1_N OP1_O Amplifier Circuit Window Comparator 2 Digital Control Circuit XLED_EN OP2_N LED OP2_O OUT OSC System Oscillator Figure 26. NCS3600 Internal Block Diagram NCS3600DG Two Stage Amplifier PIR Fresnel Lens The 2.15 mV output from the PIR detector can be amplified with gain up to 70 dB which can be achieved by the two consecutive amplifier stages which are the OP1_x and OP2_x pins. The output of PIR detector is fed to the first amplifier section (opamp−1), which is then fed to the second amplifier to achieve the total gain of gan1+gain2. For details of the R, C calculation and selection for the first and the second stage amplifier please refer to the NCS3600 data sheet. The Fresnel Lens is from Fresnel Factory to best match the PIR detector. The lens model number is PD55−14006. www.onsemi.com 27 AND9237/D SYSTEM I2C INTERFACE Following I2C interface mapping shows the I2C intercommunication between the various devices in the system. GS2011MIES Slave Address:1101100 Battery Charger NCP1855 Slave Address:0001011 Fuel Guage LC709202F Slave Address:0101000 Digital POT CAT5132ZI−00−G Figure 27. GS2011MIES I2C Interface with Address Slave Address:1111000 I2C CLK I2C CLK DM368 I2C SDA Slave Address:0010000 I2C Master Select PCA9306 Image Sensor I2C SDA Figure 28. DM368 I2C Interface with Address www.onsemi.com 28 AR023Z AND9237/D ETHERNET PHY • • • • RTL8201CP part from Realtek is used for providing the Ethernet functionality to the MatrixCam VDK. Main Features of RTL8201CP−LF are: • Fully compliant with IEE802.3/IEEE802.3u Base-TX standard • Selectable MII and RMII interface • Auto-negotiation ability, compliant with IEE802.3u • Support auto-cross over detection Support power down mode Support scrambling and de-scrambling Provide loopback mode for easy system diagnostics LED outputs for link/activity, speed 10/100 Ethernet PHY is interfaced to DM368 through MII interface. TXD[3:0] TXD[3:0] TX_CLK TXCLK TXEN TXEN RXD[3:0] RXD[3:0] RX_CLK DM368 SoC MAC RXCLK RX_ER RXER RX_DV RXDV COL COL CRS 10 /100M Ethernet Phy RTL8201CP−LF PHY_ADDR: 10000B CRS GPIO INTR# GPIO RESET GPIO LINKSTS MDCLK MDC MDIO MDIO GPIO PWRDWN TXER Figure 29. Ethernet PHY Interface www.onsemi.com 29 AND9237/D RTL8201CP Pin Definition The table below has information about the pins in RTL8201CP. For detailed pin connections and setup information please refer to the RTL8201CP data sheet for details. Table 13. ETHERNET MII INTERFACE Function Connected to EMAC of DM368 Pin Name Type TXD [3:0] I Data Transmit, Synchronous with TXC when TXEN is Asserted EMAC_TXD[3−0] RXD[3:0] O Receive Data, Driven Synchronously to RXC for Reception by PHY EMAC_RXD[3−0] TXC O Transmit clock EMAC_TX_CLK RXC O Receive Clock. RXC is 25 MHz in 100 Mbps and 2.5 MHz in 10 Mbps Mode (for MII) EMAC_RX_CLK TXEN I Transmit Enable, Indicates that Presence of Valid Data on TXD [3:0] EMAC_TX_EN Collision Detect, Asserted high when a collision is detected on media. During power on reset mode, this pin status is latched to determine at which LED mode to operate 1: BL LED Mode 0: CP LED Mode CRS LI/O RXDV O RXER/FXEN LI/O Carrier sense, Asserted high if media is not in ideal state. Receive Data Valid, Asserted high when received data is presented on RXD[3:0] and de-asserted at the end of packet Receive Error, any Invalid Symbol, this Pin Goes High. EMAC_CRS EMAC_RX_DV MRXER Fiber/UTP Enable MDC I Management Data Clock, Clock Synchronous to MDIO MDCLK MDIO I/O Management Data Input and Output, Used to Transfer Management Information MDIO Table 14. ETHERNET 10 Mbps/100 Mbps NETWORK INTERFACE Type TPTX+ O Differential Transmit Output, Shared by 100Base-Tx, 100Base-FX and 10Base-T Modes Connected to Magnetics I Differential Receive Input, Shared by 100Base-Tx, 100Base-FX and 10Base-T Modes Connected to Magnetics I Transmit Base Resistor, will Clear the Resistor and Re-Initialize them by Using 2 kW (1%) Resistor, by Pull Down this Pin Connected to 2 kW 1% Resistor TPTX− TPRX+ TPRX− RTSET Function Connected to EMAC of DM368 Pin Name Table 15. ETHERNET SERIAL MANAGEMENT INTERFACE Function Connected to EMAC of DM368 Pin Name Type MDC I Management Data Clock, Clock Synchronous to MDIO MDCLK MDIO I/O Management Data Input and Output, Used to Transfer Management Information MDIO Table 16. ETHERNET CLOCK INTERFACE Pin Name Type Function X2 O 25 MHz Crystal Output X1 I 25 MHz Crystal Input Connected to EMAC of DM368 Crystal Part number: 25 MHz, 403C35D25M00000 from CTS with C1, C2 = 24 pF www.onsemi.com 30 AND9237/D Table 17. ETHERNET DEVICE CONFIGURATION INTERFACE Connected to EMAC of DM368 Pin Name Type Function Isolate I Set high isolate the RTL8201Cp from the MAC. This will also isolate the MDC/MDIO management interface. In this mode, the power consumption is minimum. This Pin can be directly connected to GND or VCC GND as this Functionality is Not Required RPTR I Set high to put the RTL8201CP in to repeater mode. This pin can be directly connected to GND or VCC GND as this Functionality is Not Required SPEED LI This pin is latched to input during a power on or reset condition. Set high to put the RTL8201CP in to 100 Mbps operation. This pin can be directly connected to GND or VCC Connected to VCC to Put it into 100 Mbps Mode DUPLEX LI This pin is latched to input during a power on or reset condition. Set high to enable full duplex. This pin can be directly connected to GND or VCC Connected to VCC to Put it into Full Duplex Mode ANE LI This pin is latched to input during a power on or reset condition. Set high to enable Auto-Negotiation mode, set low to force mode. This pin can be directly connected to GND or VCC Connected to VCC to Enable ANE Mode LDPS I Set high to put the RLT8201CP into LPDS mode. This pin can be directly connected to GND or VCC. Connected to VCC to Enable LPDS Mode MII/SNIB LI/O This pin is latched to input during a power on or reset condition. Pull high to set the RLT8201CP into MII mode. Set low for SNI mode. This pin can be directly connected to GND or VCC. Connected to VCC to Enable MII Mode Table 18. ETHERNET LED/PHY ADDRESS CONFIGURATION Function Connected to EMAC of DM368 Pin Name Type PHYAD0/ LED0 LI/O PHY Address [0] Link LED Lit when Linked PHYAD0 = 0 Used as LED as well PHYAD1/ LED1 LI/O PHY Address [1] Full Duplex LED Lit when in Full Duplex Operation PHYAD1 = 0 Used as LED as well PHYAD2/ LED2 LI/O PHY Address [2] CP LED Mode: 10ACT LED Blinking when Transmitting or Receiving Data BL LED Mode: Link 10/ACT LED Active when Linked in 10base-T Mode, and Blanking when Transmitting or Receiving Data PHYAD2 = 0 PHYAD3/ LED3 LI/O PHY Address [3] CP LED Mode: 100ACT LED Blinking when Transmitting or Receiving Data. BL LED Mode: Link 100/ACT LED Active when Linked in 100base-T Mode, and Blanking when Transmitting or Receiving Data PHYAD3 = 0 PHYAD4/ LED4 LI/O PHY Address [4] Collision LED Blinks when Collisions Occur PHYAD1 = 0 Table 19. ETHERNET POWER & GND Pin Name Type Function AVDD33 P 3.3 V Analog Power Input 3.3 V should be well Decoulpled AGND P Analog GND Should be Connected to Larger GND Plane DVDD33 P 3.3 V Digital Power Input 3.3 V Power Supply for Digital Circuit DGND P Digital GND. Should be Connected to a Larger GND Plane Connected to EMAC of DM368 Connected to 3.3 V through Ferrite Bead to Isolate from Digital Power Supply www.onsemi.com 31 Connected to AGND, AGND Separated to DGND by Ferrite Bead Connected to 3.3 V DGND AND9237/D SYSTEM RESET SCHEME System reset scheme is shown below in Figure 31. Though the resets are interconnected, they can be grouped as the following subsets: DM368 Reset System Reset • When microcontroller asserts reset • When manual reset switch is pressed (SW2) DM368 will be reset by any of the following conditions: • If there is any voltage drop at 1.35 V, 1.8 V, 3.3 V and 2.8 V voltage rails To reset the complete system there is a factory reset button connecting to the GPIO7 of the GS2011MIES. This will reset the whole camera system. Note that the Global RESET# pin of the DM368 has a weak pull down resistor (10 kW). The signal SoC_POR_nRESET connected to this RESET# pin will drive it (high) out of the reset state. GS2011MIES Reset GS2011MIES has an internal POR circuitry to take care of any dip in power rail. If GS2011MIES is reset then it will reset the rest of the system. There is tactile switch connected to “EXT_RESET#” pin to reset the GS2011MIES which in turn resets the whole system. Peripheral Reset Through some of the DM368 GPIO pins, peripheral can be independently reset. The following device resets are controlled by DM368. 1. NOR Flash 2. AR023Z Image sensor 3. Ethernet PHY (RTL8201CP−LF) Figure 31 shows the complete reset scheme as discussed above. Figure 30. Reset Button to the GS2011MIES Module Figure 31. System Reset Scheme www.onsemi.com 32 AND9237/D POWER SUPPLY DESIGN Power Consumption As it is a USB powered device, it should follow the following criteria as per USB BCS Rev1.2. 1. For a Dedicated Charge Port (DCP) it is allowed to draw 1.5 A 2. A DCP shall output a voltage of 4.75 to 5.25 V for all currents less than 1.5 A min 3. Portable device allowed operating range: V = 4.75 to 5.25 V and I = 0.5 to 1.5 A The estimated total power consumption of the MatrixCam VDK under various conditions are: • Sleep mode: 7.5 mW • Video streaming Wi-Fi: 2894 mW • Video streaming wired Ethernet: 2333 mW • Video saved to the SD card: 2467 mW • Total maximum power: 4009 mW Note that the above numbers do not consider the efficiency of the DC−DC converters. 5.25 5.0 4.75 4.50 1 Voltage (V) 4.0 Allowed Operating Range for a Portable Device 3.0 Portable Device Operation Not Allowed 2.0 1.0 0 0 0.5 1.0 1.5 2.0 5.0 Current (A) Portable Device Allowed Operating Range Figure 32. USB Powered Operating Condition Battery Charger Management Li-Ion Battery Li-Ion battery capacity should provide long run support for this product during the day time where the manual access is not possible for battery charging. Battery Specifications are follows: Battery management comprise of Li-Ion Battery with temperature sensor, Battery charger and Fuel Gauge. Table 20. BATTERY SPECIFICATIONS Parameter Value Battery Model No U884048−2P Battery Pack Construction 2 Cells of 2100 mAh Battery Cell 2100 mAh Nominal Voltage 3.7 V Maximum Charge Voltage 4.2 V Voltage at End Discharge 3.3 ±0.1 V Suggestion Charge Current 840 mAh Suggestion Continuous Discharge Current(max) 1000 mAh Operation Temperature Charge: 0°C ~ 45°C; Discharge: −20°C ~ 60°C www.onsemi.com 33 AND9237/D The selected battery has built-in protection function as shown in the following table. Table 21. BATTERY PROTECTIONS Parameter Description Over Charge Prohibition Shut Down Circuitry and Stop Charge if anyone of Cells Voltage Exceeds more than 4.28 ±0.0025 V Over Discharge Prohibition Shut Down Circuitry and Stop Discharge if Cell Voltage Becomes less than 2.90 ±0.08 V Battery Charger Overview To satisfy the MatrixCam VDK’s goal of minimal power dissipation (Higher efficiency), the Switching mode type charging is used in the design. This camera uses the ON Semiconductor NCP1855 battery charger and LC709202F battery fuel gauge. Since a higher switching frequency leads to the selection of smaller components, 1.5 MHz switching frequency is used in this camera. Here the NCP1855IC accepts the input voltage in the range of 3.8 V to 16 V and the recommended maximum input current is 2 A (Default value input current limit is set to 100 mA). And it would produce the output voltage of minimum 3.3 V (3.6 V default) at the system (load) side. The charge current can be controlled through I2C with the minimum current of 1000 mA and maximum of 2.5 A. The NCP1855IC charging profile is shown in Figure 33. IBAT VBAT VCHG VRECHG ICHG IPRE VPRE IEOC ISAFE VSAVE Safe Charge Pre Charge Constant Charge Constant Voltage Figure 33. Battery Charge Cycles www.onsemi.com 34 End of Charge AND9237/D NCP1855 Battery Charger Details NCP1855 has the following features: • Single input USB-compliant/adapter charger • High efficiency 2.5 A switch mode charger • Autonomous battery charging with or without host management • 1.5 MHz switching frequency for low profile inductor The NCP1855is an I2C controlled power path management and a single cell Li-Ion battery charger device. It integrates the input reverse-blocking FET, high-side switching FET, low-side switching FET, and BAT FET between system and battery. VSYS BUCK/BOOST FET 5V USB Conn USB Detection USB Data+/− BAT NCP1855 SCL SDA GS2011MIES NC NC I2C Slave SPM FTRY Control and Monitoring STATUS Figure 34. Battery Charger Functional Blocks The selected battery pack will cutoff the supply when the cell voltage goes below 3.0 V. If the voltage of the battery is very low the battery must be slow charged to 2.8 V first, and once the battery is above 2.8 V the battery can be charged with the fast current. the system by opening QBAT, while the DC-DC remains active. This will keep the battery in a fully charged state with the system being supplied from the DC-DC. If a load transient appears exceeding the DC-DC output current and thus causing VSENSEN to fall below VRECHG, the FET QBAT is instantaneously closed to reconnect the battery in order to provide enough current to the application. The FET QBAT remains closed until the end of charge state conditions are reached again. The power path management function is enabled through the I2C interface (register CRTL2 bit PWR_PATH = 1). In the MatrixCam VDK ON Semiconductor’s NTLUS3A18PZ is used as the QBAT. Switch-Mode Battery Charger Design – NCP1855 The NCP1855 is a highly-integrated switch-mode battery charge management and system power path management devices for single cell Li-Ion battery in a wide range of tablet and other portable devices. For the system design details about the inductor selection, input capacitor selection, output capacitor selection, capacitor ripple voltage, inductor ripple current etc please refer to the NCP1855 data sheet. Fuel Gauge The ON Semiconductor LC709202F measures the power level of 1-cell Lithium (Li+) battery used for a portable device. It is normally referred to as a “Fuel Gauge”. Figure 35 is an interface diagram showing how the Fuel Gauge interfaces the microcontroller. Power Path Management Power path management can be supported when a battery FET (QBAT) is placed between the application and the battery. When the battery is fully charged (end of charge state), power path management disconnects the battery from www.onsemi.com 35 AND9237/D VDD1 VDD2 PACK+ SCL SDA GS2011MIES TEMP Fuel Gauge LC709202F PACK− Figure 35. Fuel Gauge Interconnection Power Supply Management Figure 36 shows the detailed power supply architecture with battery management: Figure 36. Power Supply Architecture www.onsemi.com 36 Battery Pack AND9237/D Power supply regulators are selected by considering the following parameter: 1. It should operate from battery voltage range 3.0 V to 4.25 V 2. Power on sequence should meet “Fast Boot & Capture” requirement 3. High efficient power components to improve battery life cycle time R1 is the resistance from VOUT to FB, which has a normal value range from 50 kW to 1 MW and a typical value of 220 kW for applications with the typical output filter. Assume R1 = 220 kW Then R2 = 176 kW Since the 176 kW is not a standard value hence 174 kW and 178 kW are considered. Output voltage is 1.358 and 1.341 with 174 kW and 178 kW respectively. DM368 has core voltage range 1.28 to 1.42 hence any of the value can be used. The MatrixCam VDK design is using 174 kW with 0.5% tolerance. Power Supply Design for 3.3 V 3.3 V is a primary IO Voltage and it is an operating voltage of many devices in the design including microcontroller and DM368. A Buck/Boost converter LM3668SD−2833 is selected for 3.3 V to operate in battery voltage with high efficiency. This is a synchronous Buck/Boost converter employed to source constant 3.3 V output for the input variations in the range of 2.6 V to 4.75 V. The automatic buck mode is enabled when the input voltage is more than 3.3 V and boost mode is enabled when the input is less than 3.3 V. Battery charger IC output which ranges from 2.6 V to 4.25 V can be directly connected to the input supply of the Buck/Boost converter. Please refer to the LM3668 data sheet for details of the inductor and input/output capacitor selection under both the Buck and the Boost modes. Power Supply Design for 1.8 V The synchronous Buck converter NCP6332B is employed to source adjustable output voltage 1.8 V with maximum of 1.2 A current. For the adjustable output voltage version, an external resistor divider is used to set the output voltage. By selecting the R1 and R2, the output voltage is programmed to the desired value and the relation is given by: ǒ V OUT + V FB @ 1 ) R1 is the resistance from VOUT to FB, which has a normal value range from 50 kW to 1 MW and a typical value of 220 kW for applications with the typical output filter. Assume R1 = 220 kW Then R2 = 110 kW 110 kW with 0.5% tolerance resistor is used in the MatrixCam VDK. Power Supply Design for 2.8 V Aptina image sensor AR023Z requires 2.8 V for VDD_PLL, VAA_PIX and VAA for its internal operation with around 58 mA as a current requirement. To meet this requirement low noise LDO NCP752BSN28T1G is used in the MatrixCam VDK. NCP752BSN28T1G is an 130 mV low dropout regulator with input voltage of 2.0 V to 5.5 V. Please refer to the NCP752BSN28T1G data sheet for details about the “input/output capacitor selection”. Output Voltage Setting for 1.35 V: For the adjustable output voltage version, an external resistor divider is used to set the output voltage. By selecting the R1 and R2, the output voltage is programmed to the desired value and the relation is given by: ǒ Ǔ R1 R2 (eq. 5) Where: VOUT = 1.8 V VFB = 0.6 V Power Supply Design for 1.35 V The synchronous Buck converter NCP6332B is employed to source adjustable outputs with maximum of 1.2 A current. Two NCP6332B is employed to source outputs of 1.35 V at 1 A and 1.8 V at 0.5 A current for loading the peripherals section in the SoC DM368 and 1.8 V IO devices. These high efficient regulators will be controlled by the enable signal from GS2011MIES controller. Rest of the time these down converters will be disabled to save battery backup power. Please refer to the NCP6332B data sheet for details of “inductor selection”, “input/output capacitor selection” related topics. V OUT + V FB @ 1 ) Ǔ R1 R2 (eq. 4) 3.3 V Power MOSFET To use the same power 3.3 V power source i.e. LM3668SD−2833 extra MOSFET is used to turn on the 3.3 V power of the DM368. The MOSFET will be enabled by the power sequence IC (LM3881). Where: VOUT = 1.35 V VFB = 0.6 V www.onsemi.com 37 AND9237/D The complementary P−CH and N−CH will be used here as shown in the below figure. MCU_3V3 EN by Seq IC P−CH FET i.e. The following conditions make the RESET pin go high: 1. The voltage at VDD should be greater than 3.08 V 2. The Voltage at the sense PIN should be greater than 1.25 V VCC_3V3 This is used to monitor the 3.3 V and 1.8 V for DM368 and check the Manual reset switch position condition. Reset is maintained with 200 ms of delay time after VCC rise above the reset threshold. Reset pin shall be pull down to 100 kW to keep the output valid when VCC < 1 V. The reset output is driven active within 20 ms of VCC falling through the reset voltage threshold. Note: Transient immunity can be improved by adding a capacitor (100 nF for example) in close proximity to the VCC pin of theMAX708TESA−TG. N−CH FET Figure 37. 3.3 V MOSFET Switching Calculating R1: 2.4 kW & R2: 10 kW N-Channel MOSFET: NTK3134NT1G and P-Channel MOSFET: NTLUS3A18PZTCG. Voltage Monitoring Circuit The MAX708TESA−TG device has a fixed-sense threshold voltage VIT (3.08 V) set by an internal voltage divider. In addition to the fixed sense threshold monitored at VDD, the MAX708 devices provide a second adjustable SENSE input. RESET is asserted in case VDD voltage drops below VIT. www.onsemi.com 38 AND9237/D SYSTEM POWER ON/OFF SEQUENCE The MatrixCam VDK has a button to turn on the complete system. Tactile ON/OFF Button: A tactile button is connected to LTC2950−1 to enable the power of the system. After pressing the button, GS2011MIES is supposed to drive the “MCU_OFF” high with in 500 ms to keep the power enable. This switch is used to turn ON the power of GS2011MIES only. Rest of the system (DM368, Image Sensor and other peripherals) will remain powered OFF and will be powered based on the interrupt i.e. PIR, BLE and WOW. Voltage DM368 Power On Sequence CC3200 GPIO − To Trigger Power On Sequence VTH = 1.1 V 300 ms 100 ms 1.35 V REGULATION POWER GOOD SIGNAL 1.15 ms 120 ms 2.8 V: VDD_PLL VTH = 1.2 V 120 ms 2.8 V: VAA, VAA_PIX VTH = 1.2 V 300 ms 100 ms 1.8 V: REGULATION 3.3 V (Enable MOSFET) 30 ns 200 ms + 7.4 ns Reset# to DM368 Propagation Delay of AND Gates = 7.4 ns TOTAL POWER ON RESET TIME = 200.79 ms Time Figure 38. DM368 Power On Sequence www.onsemi.com 39 AND9237/D REFERENCE All design files; schematics, PCB layout files, Gerber files as well as the BOM file can be found in the “Hardware Design Files” folder. http://tiny.cc/matrixcam ARM, Cortex, and Thumb are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. Bluetooth is a registered trademark of Bluetooth SIG. Wi-Fi is a registered trademark of the Wi-Fi Alliance. MatrixCam is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. microSD and SDHC are trademarks of SD−3C, LLC in the United States, other countries or both. ANT is a trademark of Dynastream Innovations Inc. ShockBurst is a trademark of Nordic Semiconductor ASA. All other brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 40 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AND9237/D