AK5385BVS

ASAHI KASEI
[AK5385B]
AK5385B
24Bit 192kHz ∆Σ ADC
GENERAL DESCRIPTION
The AK5385B is a 24bit, 192kHz sampling 2ch A/D converter for high-end audio system. The modulator in
the AK5385B uses the Enhanced Dual Bit architecture and the AK5385B realizes high accuracy and low
cost. The AK5385B performs 114dB dynamic range, so the device is suitable for AV-amp, AV recorder
and musical instruments. The AK5385B is available in 28pin VSOP and SOP package, utilizing less board
space.
FEATURES
‡ Sampling Rate: 8kHz ~ 216kHz
‡ Full Differential Inputs
‡ S/(N+D): 103dB
‡ DR: 114dB
‡ S/N: 114dB
‡ High Performance Linear Phase Digital Anti-Alias filter
• Passband: 0~21.768kHz (@fs=48kHz)
• Ripple: 0.005dB
• Stopband: 100dB
‡ Digital HPF
‡ Power Supply: 5V ± 5%(Analog), 3.0 ~ 5.25V(Digital)
‡ Power Dissipation: 183mW (@fs=48kHz)
‡ Package: 28pin SOP / 28pin VSOP
‡ AK5383/AK5393/AK5394A Semi-Pin compatible
VCOM
OVF
M/S DFS1 DFS0 CKS1 CKS0
PDN
VREFL
LIN+
LIN-
Delta-Sigma
Modulator
Decimation
Filter
HPF
LRCK
Audio I/F
Controller
RIN+
RIN-
Delta-Sigma
Modulator
Decimation
Filter
BICK
MCLK
SDTO
HPF
VREFR
TEST
AVDD AVSS DVDD DVSS BVSS
DIF HPFE
Block diagram
MS0406-E-00
2005/08
-1-
ASAHI KASEI
[AK5385B]
„ Ordering Guide
AK5385BVS
AK5385BVF
AKD5385B
–10 ~ +70°C
28pin SOP (1.27mm pitch)
–40 ~ +85°C
28pin VSOP (0.65mm pitch)
Evaluation Board for AK5385B
„ Pin Layout
VREFL
1
28
VREFR
AVSS
2
27
AVSS
VCOM
3
26
TEST
LIN+
4
25
RIN+
LIN-
5
24
RIN-
CKS0
6
23
AVDD
DVDD
7
22
AVSS
DVSS
8
21
BVSS
OVF
9
20
DFS1
PDN
10
19
HPFE
DIF
11
18
DFS0
M/S
12
17
MCLK
LRCK
13
16
CKS1
BICK
14
15
SDTO
Top View
MS0406-E-00
2005/08
-2-
ASAHI KASEI
[AK5385B]
„ Compatibility with AK5383/AK5394A
Pin 1
Pin 2
Pin 3
Pin 6
Pin 9
Pin 11
Pin 12
Pin 16
Pin 18
Pin 20
Pin 26
Pin 27
Pin 28
fs
MCLK at 48kHz
MCLK at 96kHz
MCLK at 192kHz
DR, S/N
Input Voltage
Offset Calibration
AK5385B
VREFL
AVSS
VCOM
CKS0
OVF
DIF
M/S
CKS1
DFS0
DFS1
TEST
AVSS
VREFR
8kHz ∼ 216kHz
256/384/512fs
256fs
128fs
114dB
±2.9Vpp
Not Available
MS0406-E-00
AK5383
VREFL
GNDL
VCOML
ZCAL
CAL
SMODE2
SMODE1
FSYNC
DFS
TEST
VCOMR
GNDR
VREFR
1kHz ∼ 108kHz
256fs
128fs
Not Available
110dB
±2.45Vpp
Available
AK5394A
VREFL+
VREFL−
VCOML
ZCAL
CAL
SMODE2
SMODE1
FSYNC
DFS0
DFS1
VCOMR
VREFR−
VREFR+
1kHz ∼ 216kHz
256fs
128fs
64fs
123dB
±2.4Vpp
Available
2005/08
-3-
ASAHI KASEI
[AK5385B]
„ Compare PCB layout example between AK5385B and AK5383
Analog Ground
Analog Ground
0.1µ
10µ
0.22µ
3.0 ~ 5.25V
Digital
0.1µ
10µ
0.1µ
VREFL
2
GNDL
3
VCOML
4
AINL+
AINR+ 25
5
AINL-
AINR- 24
6
ZCAL
VA 23
7
VD
AGND 22
8
DGND
BGND 21
9
CAL
0.1µ
10µ
VREFR 28
1
10µ
GNDR 27
VCOMR 26
0.22µ
0.22µ
0.1µ
5V
Analog
3.0 ~ 5.25V
Digital
10µ
10µ
TEST 20
10 RSTN
HPFE 19
1
6
9
11
12
16
18
20
26
28
VREFL
2
AVSS
AVSS 27
3
VCOM
TEST 26
4
LIN+
5
LIN-
6
CKS0
AVDD 23
7
DVDD
AVSS 22
8
DVSS
BVSS 21
9
OVF
DFS1 20
10 PDN
HPFE 19
10µ
RIN+ 25
RIN- 24
11 SMODE2
DFS 18
11 DIF
DFS0 18
12 SMODE1
MCLK 17
12 M/S
MCLK 17
13 LRCK
FSYNC 16
13 LRCK
CKS1 16
14 SCLK
SDATA 15
14 BICK
SDTO 15
AK5383
Pin #
0.1µ
0.1µ
VREFR 28
1
0.1µ
5V
Analog
10µ
AK5385B
AK5383
VREFL
Lch Voltage Reference Output Pin, 3.75V
Normally, connected to GNDL with a 10µF
electrolytic capacitor and a 0.1µF ceramic capacitor.
ZCAL
Zero Calibration Control Pin
This pin controls the calibration reference signal.
CAL
Calibration Active Signal Pin
SMODE2
Serial Interface Mode Select Pin
SMODE1
Serial Interface Mode Select Pin
FSYNC
Frame Synchronization Signal Pin
AK5385B
VREFL
Lch Voltage Reference Input Pin, AVDD
Normally, connected to AVSS with a 10µF
electrolytic capacitor and a 0.1µF ceramic capacitor.
CKS0
Master Clock Select 0 Pin
(Internal Pull-down Pin, typ. 100kΩ)
OVF
Analog Input Overflow Detect Pin
DIF
Audio Interface Format Pin
M/S
Master / Slave Mode Pin
CKS1
Master Clock Select 1 Pin
(Internal Pull-down Pin, typ.100kΩ)
DFS
DFS0
Double Speed Sampling Mode Pin
Sampling Speed Select 0 Pin
TEST
DFS1
Test Pin (Internal Pull-down Pin)
Sampling Speed Select 1 Pin
VCOMR
TEST
Rch Common Voltage Pin, 2.75V
Test Pin (Internal Pull-down Pin, typ. 100kΩ)
VREFR
VREFR
Rch Voltage Reference Input Pin, AVDD
Rch Voltage Reference Output Pin, 3.75V
Normally, connected to AVSS with a 10µF
Normally, connected to GNDL with a 10µF
electrolytic capacitor and a 0.1µF ceramic capacitor. electrolytic capacitor and a 0.1µF ceramic capacitor.
MS0406-E-00
2005/08
-4-
ASAHI KASEI
[AK5385B]
„ Compare PCB layout example between AK5385B and AK5394A
Analog Ground
Analog Ground
0.1µ
0.1µ
0.1µ
1
VREFL+
VREFR+ 28
10µ
10µ
1
VREFL
10µ
2
VREFL-
VREFR- 27
10µ
(short)
2
AVSS
AVSS 27
3
VCOML
VCOMR 26
3
VCOM
TEST 26
4
AINL+
AINR+ 25
4
LIN+
RIN+ 25
5
AINL-
AINR- 24
5
LIN-
RIN- 24
6
ZCAL
6
CKS0
AVDD 23
7
VD
AGND 22
7
DVDD
AVSS 22
8
DGND
BGND 21
8
DVSS
BVSS 21
9
CAL
9
OVF
DFS1 20
HPFE 19
0.22µ
3.0 ~ 5.25V
Digital
0.1µ
10µ
0.22µ
0.1µ
0.22µ
5V
Analog
VA 23
3.0 ~ 5.25V
Digital
1
2
6
9
11
12
16
27
26
28
0.1µ
10µ
10µ
DFS1 20
10µ
VREFR 28
10 RSTN
HPFE 19
10 PDN
11 SMODE2
DFS0 18
11 DIF
DFS0 18
12 SMODE1
MCLK 17
12 M/S
MCLK 17
13 LRCK
FSYNC 16
13 LRCK
CKS1 16
14 SCLK
SDATA 15
14 BICK
SDTO 15
AK5394A
Pin #
0.1µ
10µ
(short)
0.1µ
5V
Analog
10µ
AK5385B
AK5394A
VREFL+
Lch Positive Voltage Reference Output Pin, 3.75V
Normally connected to AGND with a large
electrolytic capacitor and connected to VREFL−
with a 0.22µF ceramic capacitor.
VREFL−
Lch Negative Voltage Reference Output Pin, 1.25V
Normally connected to AGND with a large
electrolytic capacitor and connected to VREFL+
with a 0.22µF ceramic capacitor.
ZCAL
Zero Calibration Control Pin
This pin controls the calibration reference signal.
CAL
Calibration Active Signal Pin
SMODE2
Serial Interface Mode Select Pin
SMODE1
Serial Interface Mode Select Pin
FSYNC
Frame Synchronization Signal Pin
VREFR−
Rch Negative Voltage Reference Output Pin, 1.25V
Normally connected to AGND with a large
electrolytic capacitor and connected to VREFR+
with a 0.22µF ceramic capacitor.
VCOMR
Rch Common Voltage Pin, 2.75V
VREFR+
Rch Positive Reference Output Voltage, 3.75V
Normally connected to AGND with a large
electrolytic capacitor and connected to VREFR−
with a 0.22µF ceramic capacitor.
MS0406-E-00
AK5385B
VREFL
Lch Voltage Reference Input Pin, AVDD
Normally, connected to AVSS with a 10µF
electrolytic capacitor and a 0.1µF ceramic capacitor.
AVSS
Analog Ground Pin
CKS0
Master Clock Select 0 Pin
(Internal Pull-down Pin, typ. 100kΩ)
OVF
Analog Input Overflow Detect Pin
DIF
Audio Interface Format Pin
M/S
Master / Slave Mode Pin
CKS1
Master Clock Select 1 Pin
(Internal Pull-down Pin, typ. 100kΩ)
AVSS
Analog Ground Pin
TEST
Test Pin (Internal Pull-down Pin, typ. 100kΩ)
VREFR
Rch Voltage Reference Input Pin, AVDD
Normally, connected to AVSS with a 10µF
electrolytic capacitor and a 0.1µF ceramic capacitor.
2005/08
-5-
ASAHI KASEI
[AK5385B]
PIN / FUNCTION
No.
Pin Name
I/O
1
VREFL
I
2
3
4
5
6
7
8
AVSS
VCOM
LIN+
LIN−
CKS0
DVDD
DVSS
O
I
I
I
-
9
OVF
O
10
PDN
I
11
DIF
I
12
M/S
I
13
LRCK
I/O
14
BICK
I/O
15
SDTO
O
16
17
18
CKS1
MCLK
DFS0
I
I
I
19
HPFE
I
20
21
22
23
24
25
26
27
DFS1
BVSS
AVSS
AVDD
RIN−
RIN+
TEST
AVSS
I
I
I
I
-
28
VREFR
I
Function
Lch Voltage Reference Input Pin, AVDD
Normally, connected to AVSS with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor.
Analog Ground Pin
Common Voltage Output Pin, AVDD/2
Lch Analog Positive Input Pin
Lch Analog Negative Input Pin
Master Clock Select 0 Pin
(Internal Pull-down Pin, typ. 100kΩ)
Digital Power Supply Pin, 3.0 ∼ 5.25V
Digital Ground Pin
Analog Input Overflow Detect Pin
This pin goes to “H” if analog input overflows.
Power Down Mode Pin
“H”: Power up, “L”: Power down
Audio Interface Format Pin
“H” : 24bit I2S Compatible, “L” : 24bit MSB justified
Master / Slave Mode Pin
“H” : Master Mode, “L” : Slave Mode
Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
Audio Serial Data Output Pin
“L” Output at Power-down mode.
Master Clock Select 1 Pin
(Internal Pull-down Pin, typ. 100kΩ)
Master Clock Input Pin
Sampling Speed Select 0 Pin
High Pass Filter Enable Pin
“H” : Enable, “L” : Disable
Sampling Speed Select 1 Pin
Substrate Ground Pin
Analog Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Rch Analog Negative Input Pin
Rch Analog Positive Input Pin
Test Pin
(Internal Pull-down Pin, typ. 100kΩ)
Analog Ground Pin
Rch Voltage Reference Input Pin, AVDD
Normally, connected to AVSS with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor.
Note: All digital input pins except pull-down pins should not be left floating.
MS0406-E-00
2005/08
-6-
ASAHI KASEI
[AK5385B]
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
LIN+, LIN−
RIN+, RIN−
VREFL, VREFR
OVF
TEST
Setting
These pins should be connected to AVSS.
These pins should be connected to AVSS.
These pins should be connected to AVDD.
This pin should be open.
This pin should be connected to DVSS.
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS=0V; Note 1)
Parameter
Symbol
Power Supplies:
Analog
AVDD
Digital
DVDD
|BVSS – DVSS|
(Note 2)
∆GND
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (LIN+/–, RIN+/–, VREFL/R pins)
VINA
Digital Input Voltage (All digital input pins)
VIND
Ambient Temperature (Power applied)
28SOP Package
Ta
28VSOP Package
Ta
Storage Temperature
Tstg
min
−0.3
−0.3
−0.3
−0.3
−10
−40
−65
max
6.0
6.0
0.3
±10
AVDD+0.3
DVDD+0.3
70
85
150
Units
V
V
V
mA
V
V
°C
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS BVSS, and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, BVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies
Analog
AVDD
4.75
5.0
(Note 3)
Digital
DVDD
3.0
3.3
Voltage Reference (VREFL/R pins)
VREF
3.0
-
max
5.25
AVDD
AVDD
Units
V
V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD and DVDD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0406-E-00
2005/08
-7-
ASAHI KASEI
[AK5385B]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=5.0V, DVDD=3.3V; AVSS=BVSS=DVSS=0V; VREFL=VREFR=AVDD; fs=48kHz, 96kHz,
192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz,
40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 4)
±2.7
±2.9
±3.1
Vpp
−1dBFS (Note 5)
103
dB
S/(N+D)
fs=48kHz
−1dBFS
92
100
dB
BW=20kHz
−20dBFS
91
dB
−60dBFS
51
dB
−1dBFS
90
98
dB
fs=96kHz
−20dBFS
86
dB
BW=40kHz
−60dBFS
46
dB
−1dBFS
98
dB
fs=192kHz
−20dBFS
86
dB
BW=40kHz
−60dBFS
46
dB
Dynamic Range
(−60dBFS with A-weighted)
107
114
dB
S/N
(A-weighted)
107
114
dB
Input Resistance
9
13
kΩ
Interchannel Isolation
100
120
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Power Supply Rejection
(Note 6)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD
DVDD
(fs=48kHz)
DVDD
(fs=96kHz)
DVDD
(fs=192kHz)
Power down mode (PDN pin = “L”)
AVDD+DVDD
30
10
17
20
45
15
25
30
mA
mA
mA
mA
10
100
µA
(Note 7)
Note 4. This value is (LIN+)−(LIN−) and (RIN+)−(RIN−). Input voltage is proportional to VREF voltage.
Vin = 0.58 x VREF (Vpp).
Note 5. 100µF capacitors are connected between the VREFL/R pins and AVSS.
Note 6. PSR is applied to AVDD and DVDD with 1kHz, 20mVpp. The VREFL and VREFR pins held a constant voltage.
Note 7. All digital input pins are held DVDD or DVSS.
MS0406-E-00
2005/08
-8-
ASAHI KASEI
[AK5385B]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; DFS1 = “L”, DFS0 = “L”)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) −0.005dB
PB
0
−0.02dB
22.038
−0.06dB
22.2
−6.0dB
24.0
Stopband
SB
26.5
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 9)
GD
43.2
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
1.0
−0.1dB
6.5
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; DFS1 = “L”, DFS0 = “H”)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) −0.005dB
PB
0
−0.02dB
44.081
−0.06dB
44.5
−6.0dB
48.0
Stopband
SB
53.0
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 9)
GD
43.1
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
2.0
−0.1dB
13.0
max
Units
21.5
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
max
Units
43.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
Note 8. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
MS0406-E-00
2005/08
-9-
ASAHI KASEI
[AK5385B]
FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; DFS1 = “H”, DFS0 = “L”)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) −0.005dB
PB
0
−0.02dB
88.183
−0.06dB
89.0
−6.0dB
96.0
Stopband
SB
106.0
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 9)
GD
38.2
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
4.0
−0.1dB
26.0
max
Units
86.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
Note 8. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage
(Iout=−400µA)
VOH
DVDD−0.4
Low-Level Output Voltage
(Iout=400µA)
VOL
Input Leakage Current
(Note 10)
Iin
-
typ
-
Max
30%DVDD
0.4
±10
Units
V
V
V
V
µA
Note 10. CKS1, CKS0 and TEST pins are internally connected to a pull-down resistor. (typ. 100kΩ)
MS0406-E-00
2005/08
- 10 -
ASAHI KASEI
[AK5385B]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
2.048
Pulse Width Low
tCLKL
14.5
Pulse Width High
tCLKH
14.5
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Slave mode
Master mode
Audio Interface Timing
Slave mode
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 11)
BICK “↑” to LRCK Edge
(Note 11)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
(Note 12)
(Note 13)
typ
8
54
108
45
max
Units
27.648
MHz
ns
ns
54
108
216
55
kHz
kHz
kHz
%
%
50
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
fBCK
dBCK
tMBLR
tBSD
tPD
tPDV
1/128fsn
1/64fsd
1/64fsq
33
33
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
Hz
%
ns
ns
64fs
50
−20
−20
150
516
ns
1/fs
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK5385B can be reset by bringing the PDN pin = “L”.
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”. This value is in master mode
This value is longer 1/fs in slave mode than master mode.
MS0406-E-00
2005/08
- 11 -
ASAHI KASEI
[AK5385B]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%DVDD
Audio Interface Timing (Slave mode)
MS0406-E-00
2005/08
- 12 -
ASAHI KASEI
[AK5385B]
LRCK
50%DVDD
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
Audio Interface Timing (Master mode)
VIH
PDN
VIL
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Power Down & Reset Timing
MS0406-E-00
2005/08
- 13 -
ASAHI KASEI
[AK5385B]
OPERATION OVERVIEW
„ System Clock
MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling
frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in Table 2 and LRCK
frequency is selected by DFS1-0 pins as shown in Table 3.
As the AK5385B includes the phase detect circuit for LRCK, the AK5385B is reset automatically when the
synchronization is out of phase by changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5385B may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5385B in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
MCLK
128fs
256fs
384fs
N/A
8.192MHz
12.288MHz
N/A
11.2896MHz
16.9344MHz
N/A
12.288MHz
18.432MHz
N/A
24.576MHz
N/A
24.576MHz
N/A
N/A
Table 1. System Clock Example
CKS1 pin
L
L
H
H
DFS1 pin
L
L
H
H
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
CKS0 pin
MCLK Frequency
L
256fs
H
128fs
L
512fs
H
384fs
Table 2. MCLK Frequency
DFS0 pin
LRCK Frequency
L
8kHz ≤ fs ≤ 54kHz
H
54kHz < fs ≤ 108kHz
L
108kHz < fs ≤ 216kHz
H
N/A
Table 3. Sampling Speed
When changing MCLK frequency in master/slave mode, the AK5385B should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) to 24.576MHz(@fs=96kHz) at CKS1 pin = CKS0 pin = “L”.
If the CKS1-0 and DFS1-0 pins are changed with same MCLK frequency in master/slave mode (ex. MCLK is fixed to
24.576MHz and fs is changed from 48kHz (CKS1 pin = “L”, CKS0 pin = “L”) to 96kHz (CKS1 pin = “L”, CKS0 pin =
“H”)), no reset by PDN pin = “L” is required.
MS0406-E-00
2005/08
- 14 -
ASAHI KASEI
[AK5385B]
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 4). In both modes, the serial data is in MSB first, 2’s
complement format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and
slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
L
H
SDTO
LRCK
24bit, MSB justified
H/L
24bit, I2S Compatible
L/H
Table 4. Audio Interface Format
BICK
≥ 48fs
≥ 48fs
Figure
Figure 1
Figure 2
LRCK
0 1 2
31 0 1 2
20 21 22 23 24
20 21 22 23 24
31 0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
„ Master Mode and Slave Mode
The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The
AK5385B outputs BICK and LRCK in master mode. In slave mode, provide MCLK, BICK and LRCK.
M/S pin
L
H
Mode
BICK, LRCK
BICK = Input
Slave Mode
LRCK = Input
BICK = Output
Master Mode
LRCK = Output
Table 5. Master mode/Slave mode
MS0406-E-00
2005/08
- 15 -
ASAHI KASEI
[AK5385B]
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
HPF is controlled by HPFE pin. If HPF setting (ON/OFF) is changed at operating, click noise occurs by changing DC
offset. It is recommended that HPF setting is changed at PDN pin = “L”.
„ Overflow Detection
The AK5385B has overflow detect function for analog input. OVF pin goes to “H” if Lch or Rch overflows (more than
−0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC ([email protected]=48kHz).
OVF is “L” for 516/fs ([email protected]=48kHz) after PDN pin = “↑”, and then overflow detection is enabled.
„ Power Down and Reset
The AK5385B is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after
516 cycles of LRCK clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs
of both channels are forced to “0”. The ADC outputs settle in the data corresponding to the input signals after the end of
initialization (Settling approximately takes the group delay time).
The AK5385B should be reset once by bringing PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
(1)
PDN
Internal
State
Normal Operation
Power-down
Initialize
Normal Operation
GD (2)
GD
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(3)
“0”data
Idle Noise
“0”data
Idle Noise
(4)
Notes:
(1) 517/fs in slave mode and 516/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D output is “0” data at the power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5385B should be in the power-down state.
Figure 3. Power-down/up sequence example
MS0406-E-00
2005/08
- 16 -
ASAHI KASEI
[AK5385B]
SYSTEM DESIGN
Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
0.1µ
0.1µ
1 VREFL
VREFR 28
10µ
10µ
0.22µ
2 AVSS
AVSS 27
3 VCOM
TEST 26
4 LIN+
RIN+ 25
5 LIN-
RIN- 24
0.1µ
6 CKS0
0.1µ
Digital Supply
3.0 ~ 5.25V
7 DVDD
10µ
Reset
Analog Supply
4.75 ~ 5.25V
AVDD 23
AK5385B
10µ
AVSS 22
8 DVSS
BVSS 21
9 OVF
DFS1 20
10 PDN
HPFE 19
11 DIF
DFS0 18
12 M/S
MCLK 17
13 LRCK
CKS1 16
14 BICK
SDTO 15
DSP and uP
Note:
- AVSS, BVSS and DVSS of the AK5385B should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All input pins except pull-down (CKS0, CKS1 and TEST pin) pin should not be left floating.
Figure 4. Typical Connection Diagram
Digital Ground
Analog Ground
System
Controller
1
VREFL
VREFR
28
2
AVSS
AVSS
27
3
VCOM
TEST
26
4
LIN+
RIN+
25
5
LIN-
RIN-
24
6
CKS0
AVDD
23
7
DVDD
AVSS
22
8
DVSS
BVSS
21
9
OVF
DFS1
20
10
PDN
HPFE
19
11
DIF
DFS0
18
12
M/S
MCLK
17
13
LRCK
CKS1
16
14
BICK
SDTO
15
AK5385B
Figure 5. Ground Layout
Note:
- AVSS BVSS, and DVSS must be connected to the same analog ground plane.
MS0406-E-00
2005/08
- 17 -
ASAHI KASEI
[AK5385B]
1. Grounding and Power Supply Decoupling
The AK5385B requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and
DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the AK5385B must be
connected to analog ground plane. System analog ground and digital ground should be connected together near to
where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5385B as
possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The reference voltage for A/D converter is supplied from VREFL/R pins at AVSS reference. AVSS pin is connected to
analog ground and an electrolytic capacitor over 10µF parallel with a 0.1µF ceramic capacitor between the VREFL/R pins
and the AVSS pin eliminate the effects of high frequency noise. Especially, a ceramic capacitor should be as near to the
pins as possible. And all digital signals, especially clocks, should be kept away from the VREFL/R pins in order to avoid
unwanted coupling into the AK5385B. No load current may be taken from the VREFL/R pins.
VCOM is a signal ground of this chip. An electrolytic capacitor 0.22µF attached to VCOM pin eliminates the effects of
high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept
away from the VCOM pin in order to avoid unwanted coupling into the AK5385B.
3. Analog Inputs
Analog signal is differentially input into the modulator via the LIN+ (RIN+) and the LIN− (RIN−) pins. The input voltage
is the difference between the LIN+ (RIN+) and LIN− (RIN−) pins. The full scale of each pin is nominally ±2.9Vpp(typ).
The AK5385B can accept input voltages from AVSS to AVDD. The ADC output data format is 2’s complement. The
internal HPF removes the DC offset.
The AK5385B samples the analog inputs at 128fs ([email protected]=48kHz, Normal Speed Mode). The digital filter rejects
noise above the stop band except for multiples of 128fs. The AK5385B includes an anti-aliasing filter (RC filter) to
attenuate a noise around 128fs.
The AK5385B accepts +5V supply voltage. Any voltage which exceeds the upper limit of AVDD+0.3V and lower limit
of AVSS−0.3V and any current beyond 10mA for the analog input pins (LIN+/−, RIN+/−) should be avoided. Excessive
currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these
limits. Use caution specially in case of using ±15V in other analog circuits.
MS0406-E-00
2005/08
- 18 -
ASAHI KASEI
[AK5385B]
4. External Analog Circuit Examples
Figure 6 shows an input buffer circuit example 1. This is a full-differential input buffer circuit with an inverted-amp (gain:
−10dB). The capacitor of 10nF between LIN+/− (RIN+/−) decreases the clock feed through noise of modulator, and
composes a 1st order LPF (fc=360kHz) with 22Ω resistor before the capacitor. This circuit also has a 1st order LPF
(fc=370kHz) composed of op-amp. The evaluation board should be referred about the detail.
910
4.7k
4.7k
470p
VP+
47µ
Analog In
3k
22
2.9Vpp
4 LIN+
VP9.56Vpp
Bias
NJM5532
910
VA
10k
47µ
3k
AK5385B
10n
470p
22
5 LIN-
0.1µ 10µ
VA = 5V
VP+ = 15V
VP- = -15V
Bias
10k
Bias
2.9Vpp
Figure 6.Input Buffer example
Figure 7 shows an input buffer circuit example 2. (1st order HPF: fc=0.66Hz, Table 6; 1st order LPF: fc=590kHz,
gain=−14dB, Table 7). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC
input, open JP1 and JP2 for XLR input). The input level of this circuit is +/−14.7Vpp.
14.7Vpp
JP1
22µ
Vin+
91
1k
2.9Vpp
4 LIN+
BNC
VA
XLR
4.7k
0.1µ
10k
NJM5534
4.7k
1.5n
Bias
10µ
4.7k
AK5385B
4.7k
10k
91
JP2
NJM5534
100
5 LINVin14.7Vpp
22µ
1k
2.9Vpp
NJM5534
Figure 7.Input Buffer example
fin
1Hz
10Hz
Frequency Response
−1.56dB
−0.02dB
Table 6. Frequency Response of HPF
fin
20kHz
40kHz
Frequency Response
−0.005dB
−0.02dB
Table 7. Frequency Response of LPF
MS0406-E-00
6.144MHz
−15.6dB
2005/08
- 19 -
ASAHI KASEI
[AK5385B]
5. Measurement Example
Figure 8 shows the S/(N+D) vs. VREF capacitor that is connected between VREFL/R pins and AVSS pin with the 0.1µF
capacitor in parallel. X-AXIS is the capacity for VREF; Y-AXIS is S/(N+D).
[Measurement Condition]
- AVDD = 5.0V, DVDD = 3.3V; AVSS = BVSS = DVSS = 0V
- fs = 48kHz
- Measurement Bandwidth = 10Hz ∼ 20kHz
- Ta = 25°C
- Using Audio Precision System Two Cascade
S/(N+D) vs. VREF Cap
S/(N+D) [dB]
106.0
105.0
104.0
103.0
102.0
101.0
100.0
0
50
100
150
200
250
VREF Cap [uF]
Lch
Rch
Figure 8. S/(N+D) vs. VREF Cap
6. Synchronization of Multiple Devices
In system where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the MCLK and LRCK must be the same for all of the AK5385Bs in the system. The all
AK5385Bs should be reset at the same timing with preventing the reset signal for AK5385B from overlapping on the edge
of MCLK, so that all AK5385Bs begin sampling on the same clock edge.
MS0406-E-00
2005/08
- 20 -
ASAHI KASEI
[AK5385B]
PACKAGE (AK5385BVF)
28pin VSOP (Unit: mm)
*9.8±0.2
1.25±0.2
0.675
28
A
7.6±0.2
*5.6±0.2
15
14
1
0.65
0.22±0.1
+0.1
0.15-0.05
0.1±0.1
0.5±0.2
Detail A
Seating Plane
| 0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0406-E-00
2005/08
- 21 -
ASAHI KASEI
[AK5385B]
PACKAGE (AK5385BVS)
1.095TYP
18.7±0.3
0.75 ± 0.2
10.4 ± 0.3
7.5 ± 0.2
28pin SOP (Unit: mm)
1.27
0.10
0.4±0.1
+0.1
0.1-0.05
2.2 ± 0.1
+0.1
0.15-0.05
0.12 M
0-10°
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0406-E-00
2005/08
- 22 -
ASAHI KASEI
[AK5385B]
MARKING (AK5385BVF)
AKM
AK5385BVF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB :Lot number (X : Digit number, B : Alpha character)
YYYYC : Assembly date (Y : Digit number, C : Alpha character)
MS0406-E-00
2005/08
- 23 -
ASAHI KASEI
[AK5385B]
MARKING (AK5385BVS)
AKM
AK5385BVS
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB :Lot number (X : Digit number, B : Alpha character)
YYYYC : Assembly date (Y : Digit number, C : Alpha character)
Revision History
Date (YY/MM/DD)
05/08/10
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0406-E-00
2005/08
- 24 -
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