AK4617VQ

[AKD4617-A]
AKD4617-A
AK4617 Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD4617-A is an evaluation board for AK4617, which is a 24bit CODEC including 2ch ADC and
12ch DAC. The control settings of this board may be controlled via USB port, allowing for easy A/D and
D/A evaluation. RCA connectors are used for the input and output of the analog signals. This board also
has a digital interface which can be connected to the digital audio system via optical connector.
 Ordering guide
AKD4617-A
--- Evaluation board for AK4617
Control software included with package
FUNCTION
 Clock generator circuits (AK4118A used)
 Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for external data source
 RCA connector for external clock input
 ADC 2ch input, DAC 12ch output
 USB port and 10pin header for board control
Figure 1. AKD4617-A Block Diagram
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Evaluation Board Diagram
 Board Diagram
Figure 2. AKD4617-A Board Diagram
 Description
(1) IN1; IN2; L/ROUT1; L/ROUT2; L/ROUT3; L/ROUT4; L/ROUT5; L/ROUT6 (RCA Jack)
IN1-2;: Analog input jacks for IN1-2..
L/ROUT1-6: Analog output jacks for L/ROUT1-6.
White jacks are used for left channel and red ones are for right channel.
(2) AK4118A
AK4118A has DIR, DIT and X’tal oscillator. Transports input data to AK4617 when working in master mode, and
output data from AK4617 when working in slave mode.
(3) PLTx/PLRx (Optical Connector)
PLRx PORT1: Input optical signal to AK4118A
PLTx PORT2: Output optical signal from AK4118A.
(4) VOP +12V/AVDD1/AVDD2/TVDD/D3V/AVSS/DGND (Power supply)
VOP +12V: +12V Power Supply
AVDD1-2,TVDD: 3V Power Supply
D3V: 3V Power Supply
Connect to +12V and GND according to the following operation sequence.
(5) PIC18F4550
USB control chip. Sets up AK4617 registers from PC via USB port.
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(6) SW1
DIP type switch. Sets clock and audio format of AK4118A. DIF[2:0] used to set audio interface format and
OCKS[1:0] used to master clock frequency. Please refer to Table 3. SW1 Setting, Table 4. Audio format, Table 5.
Master Clock Frequency Select for details.
(7) SW2
Toggle type switch. Power-down switch for AK4118A.
(8) SW3
Toggle type switch. Power-down switch for AK4617. Reset board by bringing down SW2 once upon power-up.
(9) SW4
DIP type switch. SMUTEN switch for AK4617.
(10) PORT3 (10-pin header)
DSP port. Input/output MCLK, BICK, LRCK
(11) PORT4 (10-pin header)
DSP port. Input SDTI2, SDTI3, SDTI4, SDTI5, SDTI6.
(12) PORT5 (6-pin header)
DSP port. Output SDTO1, SDTO2 and SDTI1.
(13) PORT6 (10-pin header)
DSP port. Input/output CCLK / SCL / MS and CDTI / SDA / DIF..
(14) EXT (RCA jack)
Input external clock source.
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[AKD4617-A]
Evaluation Board Manual
 Operation sequence
[1] Power supply line settings
[2] Jumper pins settings
[3] DIP switches settings
[4] Toggle switches settings
[5] LED indication
[6] Register control (Serial control)
[7] Evaluation modes
Refer to the following pages for details.
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[1] Power Supply Line Settings
Red
Voltage
Range
+9+12V
Typ
Voltages
+12V
A3V31
Green
+3.0+3.6V
+3.3V
A3V32
Green
+3.0+3.6V
D3V3
Green
+3.0+3.6V
D3V
Green
+3.0+3.6V
AVSS
DGND
Black
Black
0V
0V
Name
Color
VOP+
(12V)
Function
Comments
Regulator power
supply
OPAmp +terminal
power supply
AK4617 AVDD1
Should always be connected
3.3V regulator is used (JP31
= REG) by default, when
jack is used (JP31=A3V31).
+3.3V
AK4617 AVDD2
3.3V regulator is used (JP32
= REG) by default, when
jack is used (JP32=A3V32).
+3.3V
AK4617 TVDD
3.3V regulator is used (JP33
= REG) by default, when
jack is used (JP33=D3V3).
+3.3V
AK4118 D3V,
3.3V regulator is used (JP34
Logic IC power
= REG) by default, when
supply
jack is used (JP34=D3V).
0V
Analog ground
Should always be connected
0V
Digital ground
Should always be connected
Table 1. Power supply line setting
Default
Settings
+12V
REG
REG
REG
REG
0V
0V
Note 1. Each power supply should be powered up while PDN pin = “L”. The PDN pin may be brought to “H” after all
power supplies are powered up. Do not turn off AK4617 while surrounding devices are still powered on and I2C bus is in
use. A3V31 and A3V32 must be connected to the same power supply.
<Operation procedure>
1) Connect power supply as above.
2) Set up jumper pin and evaluation mode (See below for details)
3) Power-up
Reset AK4617 once by bringing SW3 “L” upon power up. A dummy command must be inputted after SW3 = “H”
to release reset. The dummy command is executed by writing all “0” to the register address 00H.
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[2] Jumper Pin Settings
No
1
Names
IN1N
Default
Open
Functions
Select Single-ended/Differential input.
Rch Analog Negative input to AK4617 (U1)
Open: Single-ended input (default)
Short: Differential Input
2
IN2N
Open
Select Single-ended/Differential input.
Lch Analog Negative input to AK4617 (U1)
Open: Single-ended input (default)
Short: Differential Input
5
IN2/IN2P
Single
Select Single-ended/Differential input.
Rch Analog Positive input to AK4617 (U1)
Single: Single-ended input (default)
Diff: Differential Input
6
IN1/IN1P
Single
Select Single-ended/Differential input.
Lch Analog Positive input to AK4617 (U1)
Single: Single-ended input (default)
Diff: Differential Input
7
8
11
12
13
IN3N
IN4N
IN3/IN3P
IN4/IN4P
BICK-SEL
Open
Open
Open
Open
DIR
Not implemented.
Not implemented.
Not implemented.
Not implemented.
Select input to AK4617 (U1) BICK Buffer
64fs: 64fs divider
32fs: 32fs divider
DIR: DIR-AK4118-BICK (default)
10-pin: 10pin-BICK
Open: No signal
14
BICK-PHASE
THR
Select polarity (non-inverted output / inverted output) of BICK_SEL
outputs.
THR: Non-inverted output. (default)
INV: Inverted output.
15
LRCK-SEL
DIR
16
SDTI6-SEL
DIR
Select input to AK4617 (U1) LRCK Buffer
1fs: 1fs divider
DIR: DIR-AK4118-BICK (default)
10-pin: 10pin-BICK
Open: No signal
Select input to AK4617 (U1) SDTI6/TDMI
DIR: DIR-AK4118-SDTO (default)
10-pin: 10pin-SDTI6
GND: Digital ground
17
SDTI6/TDMI
SDTI6
18
SDTI5-SEL
DIR
Select input to AK4617 (U1) SDTI6/TDMI
SDTI6: SDTI6-JP16(SDTI6-SEL)_DIR-AK4118-SDTO (default)
TDMI: TDMI-SW5(pin.1)_TDMI
Select input to AK4617 (U1) SDTI5
DIR: DIR-AK4118-SDTO (default)
10-pin: 10pin-SDTI5
GND: Digital ground
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19
SDTI4-SEL
DIR
Select input to AK4617 (U1) SDTI4
DIR: DIR-AK4118-SDTO (default)
10-pin: 10pin-SDTI4
GND: Digital ground
20
SDTI3-SEL
DIR
21
SDTI2-SEL
DIR
Select input to AK4617 (U1) SDTI3
DIR: DIR-AK4118-SDTO (default)
10-pin: 10pin-SDTI3
GND: Digital ground
Select input to AK4617 (U1) SDTI2
DIR: DIR-AK4118-SDTO (default)
10-pin: 10pin-SDTI2
GND: Digital ground
22
SDTI1-SEL
DIR
Select input to AK4617 (U1) SDTI1
DIR: DIR-AK4118-SDTO (default)
10-pin: 10pin-SDTI1
GND: Digital ground
23
MCKI-SEL
DIR
24
EXT
Open
10-pin: 10pin-MCKI
EXT: External MCLK (JACK: J17) input
GND: GND
DIR: DIR-AK4118-MCKI (default)
Open: No input (default)
Short: External MCLK(JACK: J17) input
25
DAUX-SEL
SDTO1
26
CCLK/SCL/MS
CCLK/SCL
27
CDTI/SDA/DIF
CDTI/SDA
Select input to AK4617 (U1) CDTI/SDA
CDTI/SDA: CDTI/SDA-JP30(CTRL-SEL)-PIC(U11)-USB (default)
DIF: DIF-SW5(pin.3)_DIF
28
PIC
Open
Connect PIC microchip connector
VDD(pin.1),MCLR(pin.2),PGD(pin.3),PGC(pin.4),GND(pin.5)
29
CSN/PS
PS
Select input to AK4617 (U1) CSN/PS
CSN: CSN-JP30(CTRL-SEL)-PIC(U11)-USB
PS: Bus serial control / Parallel control mode select. (default)
PS-SW5(pin.4)_PS
30
CTRL-SEL
USB
Select control setting mode
SDA(ACK): USB (default)
SDA: USB (default)
SCL:USB (default)
10-pin: Parallel
31
A3V31-SEL
REG
Select power supply to A3V31
REG: Regulator T2 (default)
(When regulator “T2” is selected, power supply jack “A3V31” should be
open.)
JACK: Power supply jack J19 “A3V31”
Select input to DIT:AK4118 (U6) DAUX
SDTO1: AK4617-SDTO1 (pin 1) (default)
SDTO2: AK4615-SDTO2 (pin 3)
Open: Connect DIT-AK4118-DAUX input side of JP9 to Digital ground
with a clip. No signal
Select input to AK4617 (U1) CCLK/SCL
CCLK/SCL: CCLK/SCL-JP30(CTRL-SEL)-PIC(U11)-USB (default)
MS: MS-SW5(pin.2)_MS
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32
A3V32-SEL
REG
Select power supply to A3V32
REG: Regulator T2 (default)
(When regulator “T2” is selected, power supply jack “A3V32” should be
open.)
JACK: Power supply jack J20 “A3V32”
33
D3V3-SEL
REG
Select power supply to D3V3
REG: Regulator T2 (default)
(When regulator “T2” is selected, power supply jack “D3V3” should be
open.)
JACK: Power supply jack J21 “D3V3”
34
D3V-SEL
REG
Select power supply to D3V
REG: Regulator T3 (default)
(When regulator “T3” is selected, power supply jack “D3V” should be
open.)
JACK: Power supply jack J22 “D3V”
35
GND
Short
Select connection / separation between analog ground and digital ground.
Open: Separate analog ground from digital ground
Short: Connect analog ground to digital ground (default)
Table 2. Main board Jumper pin setting
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[3] DIP switch setting
(1). Setting for SW1 (Sets AK4118 (U6) audio format and master clock setting)
No.
1
2
3
4
5
Switch Name
DIF0
DIF1
DIF2
OCKS1
OCKS0
Mode
DIF2 pin
(SW1_1)
DIF2 bit
Function
Set-up of DIF0 pin. (in parallel mode)
Set-up of DIF1 pin. (in parallel mode)
Set-up of DIF2 pin. (in parallel mode)
Set-up of OCKS1 pin. (in parallel mode)
Set-up of OCKS0 pin. (in parallel mode)
Table 3. SW1 Setting
DIF1 pin
(SW1_2)
DIF1 bit
DIF0 pin
(SW1_3)
DIF0 bit
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
OCKS1 pin
(SW1_4)
OCKS1 bit
OCKS0 pin
(SW1_5)
OCKS0 bit
0
0
1
1
0
1
0
1
DAUX
default
H
L
H
L
L
SDTO
LRCK
BICK
I/O
24bit, Left
16bit, Right
justified
justified
24bit, Left
18bit, Right
justified
justified
24bit, Left
20bit, Right
justified
justified
24bit, Left
24bit, Right
justified
justified
24bit, Left
24bit, Left
justified
justified
24bit, I2S
24bit, I2S
24bit, Left
24bit, Left
justified
justified
24bit, I2S
24bit, I2S
Table 4. Audio format
(X’tal)
MCKO1
MCKO2
256fs
256fs
256fs
256fs
256fs
128fs
512fs
512fs
256fs
128fs
128fs
64fs
Table 5. Master Clock Frequency Select
I/O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
L/H
O
64fs
O
H/L
I
64-128fs
I
L/H
I
64-128fs
I
default
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
default
(2). Setting for SW4 (Sets AK4617 (U1) Soft mute setting)
No.
1
2
Switch Name
SMUTEN
-
Function
Soft Mute pin. (L: Mute, H: Normal Operation)
Not used
Table 6. SW4 Setting
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H
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(3). Setting for SW5 (Sets AK4617 (U1) Serial/TDM Select setting)
No.
1
Switch Name
SPI
Function
Control mode select pin.
L: I2C Bus/Parallel control mode.
H: 3-wire serial control mode.
Case1: SPI pin = “H” or SPI pin = “L”, PS pin =”L”
Chip Address Pin in serial control mode.
2
3
4
CAD1/TDM0
PS
DIF
5
MS
6
TDM1
Case2: SPI pin =”L”,PS pin = “H”
TDM I/F Format mode 0 pin in parallel control mode.
L: Normal mode.
H: TDM mode.
Control mode select pin. SPI pin = “L”
L: I2C Bus/Parallel control mode.
H: Parallel control mode.
Audio Data I/F format pin in parallel control mode.
SPI pin =”L”,PS pin = “H”
L: 24bit, Left justified.
H: 24bit,I2S
Master mode select pin.
SPI pin =”L”,PS pin = “H”
L: Slave mode.
H: Master mode.
TDM Data input pin.
TDM1-0 bits = “01” or “10”
Table 7. SW5 Setting
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default
L
L
L
L
L
L
L
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[4] Toggle switch settings
SW2, SW3 Settings
SW2
DIO-PDN
SW3
PDN
Power down switch for DIR/T: AK4118 (U6).
Reset AK4118 (U6) once by brining SW2 to “L” once upon power-up.
Keep “H” when AK4118 is in use; keep “L” when AK4118 is not in use.
Power down switch for AK4617 (U1).
Reset AK4617 (U1) once by brining SW3 to “L” once upon power-up.
Keep “H” during normal operation.
Table 8. Toggle switch settings
[5] LED
LE1 Indication
LE1
INT0
DIR: AK4118 (U6) INT0 pin output. Turns on when DIR: AK4118 (U6) is unlocked
Table 9. LED Indication
[6] Register control
NC
GND
NC
CDTI / SDA
CCLK / SCL
GND
CSN
GND
9
GND
AKD4617-A can be controlled via USB (serial port) or printer port (parallel port) of IBM-AT. Connect board to PC
using the USB cable (U13 – serial) or 10-wire flat cable (Port6 – uP-IF) included with the AKD4617-A. There is a
mark on the no.1-pin of the 10-pin connector. See Figure 3. The pin assignments of PORT below.
1
PORT5
10
GND
uP I/F
2
Figure 3. The pin assignments of PORT6
The control software is packed with the evaluation board. The software operation sequence is included in the
evaluation board manual.
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[7] Evaluation modes
(1) ADC (Analog  Digital): Stereo ADC
(2) DAC (Digital  Analog)
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(1) ADC (Analog  Digital)
 Toggle switch setting:
SW2
SW3
H
L→H
AK4118(U6) : Used
AK4617(U1) : Used
Table 6. Toggle switch setting
 Start up Control Register Setting
1. Release reset by writing the dummy command Addr: 00h = “00”
2. Set Addr: 00H = “21” to release Internal timing reset and power on ADC. Other control register settings are
default.
RSTN bit: Internal timing reset
0: Reset.
1: Normal operation (default)
PMADC bit: Power management of mono-stereo
0: All ADC’s power-down
1: Normal operation (default)
Addr
00H
Register Name
Power Management
R/W
Setting
D7
D6
D5
D4
0
0
PMADC
PMDAC
RD
RD
R/W
R/W
0
0
1
0
Table 11. Addr 00H control register setting
D3
0
RD
0
D2
0
RD
0
D1
MS
R/W
0
D0
RSTN
R/W
1
 Analog Input Mode Selector for ADC
Control Register Setting:
IN1-2 bit: ADC Input Mode Table
DIE2 bit
0
1
Addr
12H
Register Name
Input Selector
R/W
Setting
D7
0
RD
0
DIE1 bit
Input Mode Selector
IN1/IN2 Single-ended Input.(default)
0
Single-ended input to the IN1/IN1P and
IN2/IN2P pins.
IN1/IN2 Differential Input.
1
Differential input to the IN1P/IN2P and
IN1N/IN2N pins.
Table 12a.Input Mode Selector for ADC
D6
D5
D4
D3
0
0
0
0
RD
RD
RD
RD
0
0
0
0
Table 12b. Addr 13H control register setting
D2
0
RD
0
D1
DIE2
R/W
X
D0
DIE1
R/W
X
 For Differential Input Select for Amp. (DIE2-1 = “1”):
Change to following jumper setting:
JP2 (IN1N)
= Short
JP6 (IN1/IN1P) = Diff
JP1 (IN2N)
= Short
JP5 (IN2/IN2P) = Diff
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(2) DAC (Digital  Analog)
 Toggle switch setting:
SW2
SW3
H
L→H
AK4118(U6) : Used
AK4617(U1) : Used
Table 13. Toggle switch setting
 Start up Control Register Setting
1. Release reset by writing the dummy command Addr: 00h = “00”
2. Set Addr: 00H = “11” to release Internal timing reset and power on DAC. Other control register settings are
default.
RSTN bit: Internal timing reset
0: Reset.
1: Normal operation (default)
PMDAC bit: Power management of DAC1-6
0: All DAC’s power-down. PMDA1-6 bits are invalid.
1: Normal operation (default). PMDA1-6 bits are valid.
Addr
00H
Register Name
Power Management
R/W
Setting
D7
D6
D5
D4
0
0
PMADC
PMDAC
RD
RD
R/W
R/W
0
0
0
1
Table 14. Addr 00H control register setting
D3
0
RD
0
D2
0
RD
0
D1
MS
R/W
0
D0
RSTN
R/W
1
 Power management of DAC
Control Register Setting:
PMDA6-1 bit: Power management of DAC 1-6 (0: Power-down, 1: Normal operation)
PMDA1 bit: Power management control of DAC1
PMDA2 bit: Power management control of DAC2
PMDA3 bit: Power management control of DAC3
PMDA4 bit: Power management control of DAC4
PMDA5 bit: Power management control of DAC5
PMDA6 bit: Power management control of DAC6
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
D6
D5
D4
D3
0
0
PMDA6 PMDA5 PMDA4
RD
RD
R/W
R/W
R/W
0
0
1
1
1
Table 15. Addr 01H control register setting
D2
PMDA3
R/W
1
D1
PMDA2
R/W
1
D0
PMDA1
R/W
1
Only the DAC bit being used should be powered on for best results.
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[AKD4617-A]
Control Software Manual
 Set-up evaluation board and control software
1. Set up AKD4617-A evaluation board according to above instructions.
2. Connect PC with AKD4617-A evaluation board by USB cable (included in package).
(The driver included in the CD-ROM must be installed when running this control software on Windows 2000/XP.
Please refer to the “Driver Control Install Manual for AKM Device Control Software” for instructions. If running
on Windows95/98/ME, this installation is not necessary. This control software does not operate on Windows NT.)
3. Insert the CD-ROM labeled “AKD4617-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive, double-click on “akd4617-a.exe” and set up the control program.
5. Evaluate according to the following.
 Operation flow
1.
Set up control program as above and open control program.
The following operation screen will be shown. (Default setting)
Figure 4. Control software window
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2.
Click the “Write” button on right side of Addr 00H register.
Figure 5. Register set window
3.
Input dummy command settings and click “OK” to write dummy command to AK4617.
The following No Ack error message will pop up. Click “OK”.
Figure 6. No ack message window
4.
Input registers accordingly into dialog box to evaluate AK4617.
 Button Functions
1. [Port Reset]
2. [Write Default]
3. [All Write]
4. [All Read]
5. [Save]
6. [Load]
7. [All Reg Write]
8. [Data R/W]
9. [Read]
10. [Close]
:
:
:
:
:
:
:
:
:
Set up USB interface board (AKDUSBIF-B).
Initialize all register setting.
Write all registers currently displayed.
Read all register setting.
Save the current register setting to .akr file.
Load register setting from saved .akr file.
Opens “All Register Write” dialog box. (see Dialog boxes below)
Opens “Data Read/Write” dialog box . (see Dialog boxes below)
Read and display current register setting in register window (on right side of main window).
Different from [All Read] as it does not reflect to the register map.
: Close Control Software window.
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 Dialog boxes
1. [All Register Write]: Dialog box to write register setting files
Clicking the [All Reg Write] button in the main window opens the dialog box below.
Multiple register setting files created by the [SAVE] button can be set and applied.
Figure 7. Window of [All Reg Write]
<Operation flow>
(1) Click [Open(left) Button.
(2) Select file (*.akr) and Click [Open] Button. Up to 10 files can be selected.
(3) Click [Write] to write each file. [Write ALL] writes all files selected.
Button Functions:
1. [Open (left)] :
2. [Write]
:
3. [Write ALL] :
4. [Help]
:
5. [Save]
:
6. [Open (right)] :
7. [Close]
:
Select register setting file (*.akr).
Write register setting file in textbox.
Write all register setting files selected. Write is executed in descending order.
“Help” window pops up.
Save the current register map setting (*.mar).
Load register map setting file (*.mar ).
Close dialog box.
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[AKD4617-A]
2. [Data Read/Write]: Dialog box to manually enter register setting
Click the [Data R/W] button in the main window to open the data read/write dialog box.
Data manually entered into Data box is written to the specified address.
Figure 8. Window of [Data R/W]
Textbox Functions:
[Address] : Input register address in 2 hexadecimal digits.
[Data]
: Input register data in 2 hexadecimal digits.
[Mask]
: Input mask data in 2 hexadecimal digits. This value is AND-ed with input data.
Button Functions:
[Write]
: Writes data generated from [Data] and [Mask] to register specified in [Address]
[Read]
: Displays register data specified in [Address] in [Read Data] box in hexadedimal.
[Close]
: Closes dialog box. To cancel a process close the dialog box without writing
※ Register map updated after [Write] and [Read] operation.
[ KM111800 ]
2012/09
- 18-
[AKD4617-A]
Tab Functions
1. [REG]: Register Map
Register data is indicated on the register map. Each bit on the register map is a push-button switch.
Button DOWN and red lettering indicates “1” and button UP with blue lettering indicates “0”.
Buttons with “---“are undefined in the datasheet.
Figure 9-1. [REG] window (REG 0H-FH)
Figure 9-2. [REG] window (REG 10H-1FH)
[ KM111800 ]
2012/09
- 19-
[AKD4617-A]
2. [Tool]: Testing Tools
This tab screen is for the evaluation testing tool.
Click button for each testing tool.
Figure 10. [Tool] window
[ KM111800 ]
2012/09
- 20-
[AKD4617-A]
Measurement Results
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
: Audio Precision, SYS-2722
: 256fs (12.288MHz)
: 64fs
: 48kHz
: 24bit
: ADC @ Master Mode / DAC @ Slave Mode
: VOP+(12V)=12V, GND
AVDD1=AVDD2=3.3V (Regulator), TVDD=3.3V (Regulator)
・ Input Frequency
: 1kHz
・ Measurement Frequency : 20 ~ 20kHz @48kHz
・ Temperature
: Room
[Measurement Results]
1. Stereo ADC
(Single-ended Inputs)
Result
Lch
Rch
90.0
97.4
97.6
89.8
97.3
97.4
Unit
Stereo ADC : AIN1L/R => ADC => SDTO1
S/(N+D)
DR
S/N
2. Stereo ADC
fs = 48kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
fs = 48kHz (A-weighted)
dB
dB
dB
(Differential Inputs)
Result
Lch
Rch
89.5
98.2
98.5
89.3
98.1
98.1
Unit
Stereo ADC : AIN1L/R => ADC => SDTO1
S/(N+D)
DR
S/N
fs = 48kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
fs = 48kHz (A-weighted)
dB
dB
dB
3. DAC1
Result
Lch
Rch
Unit
DAC1 : SDTI1 => DAC1 => L/ROUT1
S/(N+D)
fs = 48kHz (0dBFS)
98.0
98.2
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
106.1
106.2
dB
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
106.1
106.2
dB
4. DAC 2
Result
Lch
Rch
Unit
DAC2 : SDTI2 => DAC2 => L/ROUT2
S/(N+D)
fs = 48kHz (0dBFS)
98.2
98.3
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
106.1
106.1
dB
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
106.2
106.2
dB
[ KM111800 ]
2012/09
- 21-
[AKD4617-A]
5. DAC3
Result
Lch
Rch
Unit
DAC3 : SDTI3 => DAC3 => L/ROUT3
S/(N+D)
fs = 48kHz (0dBFS)
98.0
98.3
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
106.1
106.0
dB
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
106.1
106.1
dB
6. DAC4
Result
Lch
Rch
Unit
DAC4 : SDTI4 => DAC4 => L/ROUT4
S/(N+D)
fs = 48kHz (0dBFS)
98.4
98.2
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
106.1
106.1
dB
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
106.1
106.1
dB
7. DAC5
Result
Lch
Rch
Unit
DAC5 : SDTI5 => DAC5 => L/ROUT5
S/(N+D)
fs = 48kHz (0dBFS)
98.3
97.6
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
106.2
106.2
dB
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
106.2
106.3
dB
8. DAC6
Result
Lch
Rch
Unit
DAC6 : SDTI6 => DAC6 => L/ROUT6
S/(N+D)
fs = 48kHz (0dBFS)
98.0
97.6
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
106.1
106.1
dB
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
106.1
106.1
dB
[ KM111800 ]
2012/09
- 22-
[AKD4617-A]
[Plot Data]
1.
Stereo ADC (IN1/IN2)
(Single-ended Inputs)
ADC (fs = 48kHz); IN1/IN2(Single-ended) => ADC => SDTO
AK4617 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 11. ADC (Single-ended) – FFT (-1dBFS) [fs = 48kHz]
AK4617 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 12. ADC (Single-ended) – FFT (-60dBFS) [fs = 48kHz]
[ KM111800 ]
2012/09
- 23-
[AKD4617-A]
AK4617 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, no signal]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 10. ADC (Single-ended) – FFT (No Signal) [fs = 48kHz]
AK4617 THD+N vs Amplitude Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 114. ADC (Single-ended) – THD+N vs. Amplitude (Input Level) [fs = 48kHz]
[ KM111800 ]
2012/09
- 24-
[AKD4617-A]
AK4617 THD+N vs Input Frequency Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 125. ADC (Single-ended) – THD+N vs. Input Frequency [fs = 48kHz]
AK4617 Linearity Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
+0
T
T
T T
TT
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 136. ADC (Single-ended) – Linearity [fs = 48kHz]
[ KM111800 ]
2012/09
- 25-
[AKD4617-A]
AK4617 Frequency Response Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 147. ADC (Single-ended) – Frequency Response [fs = 48kHz]
AK4617 Crosstalk Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-80
T T T T T TT
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
Hz
Figure 158. ADC (Single-ended) – Crosstalk [fs = 48kHz]
[ KM111800 ]
2012/09
- 26-
[AKD4617-A]
2.
Stereo ADC (IN1P/IN2P,IN1N/IN2N)
(Differential Inputs)
ADC (fs = 48kHz); IN1P/IN2P,IN1N/IN2N(Differential) => ADC => SDTO
AK4617 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 19. ADC (Differential) – FFT (-1dBFS) [fs = 48kHz]
AK4617 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 20. ADC (Differential) – FFT (-60dBFS) [fs = 48kHz]
[ KM111800 ]
2012/09
- 27-
[AKD4617-A]
AK4617 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, no signal]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. ADC (Differential) – FFT (No Signal) [fs = 48kHz]
AK4617 THD+N vs Amplitude Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 22. ADC (Differential) – THD+N vs. Amplitude (Input Level) [fs = 48kHz]
[ KM111800 ]
2012/09
- 28-
[AKD4617-A]
AK4617 THD+N vs Input Frequency Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 23. ADC (Differential) – THD+N vs. Input Frequency [fs = 48kHz]
AK4617 Linearity Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
+0
T T
TT T
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 24. ADC (Differential) – Linearity [fs = 48kHz]
[ KM111800 ]
2012/09
- 29-
[AKD4617-A]
AK4617 Frequency Response Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 25. ADC (Differential) – Frequency Response [fs = 48kHz]
AK4617 Crosstalk Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-80
TT TTT TTTTTT
T TT
TTTT
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
Hz
Figure 26. ADC (Differential) – Crosstalk [fs = 48kHz]
[ KM111800 ]
2012/09
- 30-
[AKD4617-A]
3.
DAC (SDTI1-6 => L/ROUT1-6)
DAC1 (fs = 48kHz); SDTI1 => DAC1 => L/ROUT1
AK4617 FFT Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz, 0dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 27. DAC1 – FFT (0BFS) [fs = 48kHz]
AK4617 FFT Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 28. DAC1 – FFT (-60dBFS) [fs = 48kHz]
[ KM111800 ]
2012/09
- 31-
[AKD4617-A]
AK4617 FFT Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz, no signal]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 29. DAC1 – FFT (No Signal) [fs = 48kHz]
AK4617 THD+N vs Amplitude Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz] 20kHz SPCL
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
r
-92.5
A
-97.5
-95
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 30 DAC1 – THD+N vs. Amplitude (Input Level) [fs = 48kHz]
[ KM111800 ]
2012/09
- 32-
[AKD4617-A]
AK4617 THD+N vs Input Frequency Single-end DAC (L/ROUT1)
[fs=48kHz, 0dBFS] 20kHz SPCL
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
r
-92.5
A
-97.5
-95
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 31. DAC1 – THD+N vs. Input Frequency [fs = 48kHz]
AK4617 Linearity Single-end DAC (L/ROUT1)
[fs=48kHz,fin=1kHz]
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 32. DAC1 – Linearity [fs = 48kHz]
[ KM111800 ]
2012/09
- 33-
[AKD4617-A]
AK4617 Frequency Response Single-end DAC (L/ROUT1)
[fs=48kHz, 0dBFS]
+1
+0.9
+0.8
+0.7
+0.6
+0.5
+0.4
+0.3
+0.2
d
B
r
+0.1
A
-0.1
+0
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 33. DAC1 – Frequency Response [fs = 48kHz]
AK4617 Crosstalk Single-end DAC (L/ROUT1)
[fs=48kHz, 0dBFS]
-80
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
Hz
Figure 34. DAC1 – Crosstalk [fs = 48kHz]
[ KM111800 ]
2012/09
- 34-
[AKD4617-A]
REVISION HISTORY
Date
(yy/mm/dd)
12/09/18
Manual
Revision
KM111800
Board
Revision
0
Reason
Page
Contents
First edition
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
[ KM111800 ]
2012/09
- 35-
R2
R3
R4
R5
R6
R7
51
51
51
51
51
51
51
1
AK4617-AVDD2
AK4617-SPI
AK4617-CSN/PS
AK4617-CDTI/SDA/DIF
R1
D
AK4617-CAD1/TDM0
2
AK4617-CCLK/SCL/MS
AK4617-SDTI5
AK4617-SDTI4
AK4617-SDTI6/TDMI
3
AK4617-SDTI3
4
AK4617-SDTI2
5
D
R9
51
LRCK
2
2
R10
51
AK4617-MCLK
MCLK
3
3
37
38
VSS3
37
C2 0.1u
38
SPI
39
AVDD2
39
40
41
CAD1/TDM0
40
CSN/PS
41
42
43
44
42
43
CDTI/SDA/DIF
CCLK/SCL/MS
44
SDTI6/TDMI
45
46
45 SDTI5
47
SDTI3
47
AVDD2
VSS3
SPI
CAD1/TDM0
CSN/PS
SDTI5
SDTI4
SDTI3
SDTI1
CDTI/SDA/DIF
1
CCLK/SCL/MS
SDTI1
1
AK4617-LRCK
46 SDTI4
SDTI2
SDTI2
51
SDTI6/TDMI
R8
1.0u
48pin_3
CN2
AK4617-SDTI1
C1
AVSS
CN1
+
48
48
48pin_4
LOUT1
LRCK
ROUT1
MCLK
LOUT2
BICK
ROUT2
TST1
LOUT3
36
LOUT1
35
ROUT1
34
LOUT2
36
AK4617-LOUT1
35
AK4617-ROUT1
34
AK4617-LOUT2
33
AK4617-ROUT2
32
AK4617-LOUT3
31
AK4617-ROUT3
30
AK4617-LOUT4
29
AK4617-ROUT4
28
AK4617-LOUT5
27
AK4617-ROUT5
26
AK4617-LOUT6
25
AK4617-ROUT6
C
C
R11
51
AK4617-BICK
BICK
4
4
TST1
5
5
ROUT2
33
32
LOUT3
31
ROUT3
TP17
REGO
REGO
6
6
C3
REGO
1.0u
VSS1
7
7
+
TVDD
1.0u
0.1u
8
SDTO1
R12
51
9
AK4617-SDTO1
SDTO2
R13
(open)
10
AK4617-SDTO2
AK4617
VSS1
LOUT4
LOUT4
30
C5
C4
AK4617-TVDD
ROUT3
U1
8
9
10
TVDD
ROUT4
SDTO
LOUT5
TST2
ROUT5
ROUT4
29
28
LOUT5
27
ROUT5
26
LOUT6
B
B
SMUTEN
AK4617-SMUTEN
11
AK4617-PDN
12
11
SMUTEN
LOUT6
PDN
ROUT6
ROUT6
25
NC
NC
NC
NC
VCOM
VSS2
AVDD1
NC
IN2/IN2P
IN1N
12
IN2N
PDN
IN1/IN1P
AVSS
48pin_1
23
22
21
20
24
C128
C127
C126
C125
short
short
+
C6
IN4/IN4P
IN4P-MICBIAS
24
IN4N
23
IN3/IN3P
IN3N
IN3P-MICBIAS
22
18
VSS2
TP1
IN3N-MICBIAS
C9
21
+
1.0u
C8
IN4N-MICBIAS
1.0u
AVDD1
IN2P-MICBIAS
IN2/IN2P
IN2N
IN1P-MICBIAS
IN2N-MICBIAS
IN1/IN1P
IN1N
IN1N-MICBIAS
AVSS
17
R19
16
(open)
CN4
15
R18
14
(open)
13
R17
short
short
+
VCOM
19
C7
+
VCOM
C124
20
C123
0.1u
19
C122
18
17
16
14
15
short
open
A
4
3
AK4617-IN4/IN4P
AK4617-IN4N
- 36-
AK4617-IN3/IN3P
48pin_2
AK4617-IN3N
R20
R21
AK4617-AVDD1
(open)
(open)
AVSS
5
short
+
AK4617-IN2/IN2P
IN4N-MICBIAS
C121
(open)
short
AK4617-IN2N
IN3N-MICBIAS
short
AK4617-IN1/IN1P
IN2N-MICBIAS
R16
AK4617-IN1N
IN1N-MICBIAS
A
(open)
+
+
IN4P-MICBIAS
R15
+
IN3P-MICBIAS
R14
+
IN2P-MICBIAS
(open)
(open)
+
IN1P-MICBIAS
+
13
CN3
MICBIAS
Title
AVSS
<AKD4617-A>
Size
A3
Date:
2
Document Number
<AK4617>
Tuesday, July 31, 2012
Rev
<0>
Sheet
1
1
of
7
5
4
3
LOUT1
2
1
ROUT1
C10
+
J1
D
R22
(open) 7.5mm
R23
100k
1.0u(A)
C13
open 5mm
R24
(open) 7.5mm
AVSS
AVSS
2
3
1
AK4617-ROUT1
LOUT1
MR-552LS(W)
AVSS
J2
+
AK4617-LOUT1
C12
open 5mm
C11
2
3
1
ROUT1
D
MR-552LS(R)
AVSS
AVSS
LOUT2
R25
100k
1.0u(A)
AVSS
ROUT2
C14
+
J3
R26
(open) 7.5mm
C16
open 5mm
R27
100k
1.0u(A)
C15
C17
open 5mm
R28
(open) 7.5mm
AVSS
AVSS
2
3
1
AK4617-ROUT2
LOUT2
MR-552LS(W)
AVSS
J4
+
2
3
1
AK4617-LOUT2
ROUT2
MR-552LS(R)
AVSS
AVSS
LOUT3
R29
100k
1.0u(A)
AVSS
ROUT3
C18
+
J5
C20
open 5mm
R30
(open) 7.5mm
R31
100k
1.0u(A)
C21
open 5mm
R32
(open) 7.5mm
AVSS
AVSS
2
3
1
AK4617-ROUT3
LOUT3
MR-552LS(W)
AVSS
J6
+
AK4617-LOUT3
C
C19
2
3
1
ROUT3
C
MR-552LS(R)
AVSS
AVSS
LOUT4
R33
100k
1.0u(A)
AVSS
ROUT4
C22
+
J7
R35
(open) 7.5mm
C24
open 5mm
R34
100k
1.0u(A)
C23
C25
R36
open 5mm
(open) 7.5mm
AVSS
AVSS
2
3
1
AK4617-ROUT4
LOUT4
MR-552LS(W)
AVSS
J8
+
2
3
1
AK4617-LOUT4
ROUT4
MR-552LS(R)
AVSS
AVSS
LOUT5
R37
100k
1.0u(A)
AVSS
ROUT5
C26
J9
+
AK4617-LOUT5
R38
(open) 7.5mm
C28
open 5mm
R39
100k
1.0u(A)
C27
2
3
1
C29
open 5mm
R40
(open) 7.5mm
MR-552LS(W)
AVSS
AVSS
AVSS
2
3
1
AK4617-ROUT5
LOUT5
R41
100k
1.0u(A)
ROUT5
MR-552LS(R)
AVSS
AVSS
LOUT6
B
J10
+
B
AVSS
ROUT6
C30
+
J11
AK4617-LOUT6
C32
open 5mm
R42
(open) 7.5mm
R43
100k
1.0u(A)
C31
AVSS
2
3
1
AK4617-ROUT6
LOUT6
C33
open 5mm
R44
MR-552LS(W)
AVSS
J12
+
2
3
1
R45
100k
1.0u(A)
(open) 7.5mm
AVSS
ROUT6
MR-552LS(R)
AVSS
AVSS
AVSS
A
A
Title
<AKD4617-A>
Size
A3
- 375
4
3
Date:
2
Document Number
<Analog OUT>
Rev
<0>
Sheet
Tuesday, July 31, 2012
1
2
of
7
5
4
3
2
1
AREA: SHORTEST WIRING
D
D
JP1
C34
IN2
JP2
C35
C36
J14
+
IN1N
1.0u(A)
AVSS
C47
AVSS
R61
1k
AK4617-IN1/IN1P
1.0u(A)
Single
R60
1k
open 5mm
C51
0.1u
C50
10u
6
R56
5
2k
U3B
LME49720MA
IN2/IN2P
C42
Diff
7
JP5
+
R52
4.7k
1
AK4617-IN2/IN2P
1.0u(A)
Single
C46
open 5mm
AVSS
VOP-ADC
+
C43
open 5mm
R57
1k
JP6
U3A
LME49720MA
8
IN1/IN1P
Diff
7
+
5
2k
8
R58
C44
3
2k
8
4
6
+
C45
open 5mm
R59
1k
1
R53
8
4
-
3
2k
+
R55
-
VOP-ADC
U2B
LME49720MA
+
2
2
VOP-ADC
R54
4.7k
4
4
AVSS
AVSS
AVSS
U2A
LME49720MA
IN2N
1.0u(A)
C39
open 5mm
Single
C41
open 5mm
Single
C38 68p
22u(A)
MR-552LS(R)
MR-552LS(W)
R47 4.7k
-
C40 68p
R48
4.7k
+
R50 4.7k
22u(A)
Diff
T
B
S
Diff
T
B
S
AK4617-IN1N
R46
4.7k
-
+
C37
J13
R51
4.7k
+
R49
4.7k
AK4617-IN2N
+
IN1
VOP-ADC
+
C49
0.1u
C48
10u
AVSS
AVSS
AVSS
C54
0.1u
+
TP3
LC-3-G_B
C52
0.1u
AVSS
C53
10u
+
TP2
LC-3-G_B
AVSS
C55
10u
AVSS
AVSS
AVSS
AVSS
C
C
AVSS
AVSS
C113
AVSS
+
C112
1.0u(A)
+
1.0u(A)
C60 open
open
C61
open 5mm
Single
4
AVSS
+
C72
open
Diff
AK4617-IN3/IN3P
8
Single
C69
open 5mm
U5A
NONE
R68
(open)
1
6
R70
IN3/IN3P
R76
(open)
+
C70
open
5
(open)
C68
AVSS
VOP-ADC
C73
open
C65
open 5mm
R72
(open)
JP11
3
(open)
8
C66
7
open
AVSS
R77
(open)
5
(open)
R69
+
4
4
R75
(open)
6
R74
U4B
NONE
8
C67
open 5mm
1
+
3
(open)
-
R73
R71
(open)
+
2
VOP-ADC
2
VOP-ADC
U4A
NONE
-
Single
+
AVSS
AVSS
-
MR-552LS(W)
AVSS
C64
Diff
7
JP12
AK4617-IN4/IN4P
open
Single
open 5mm
VOP-ADC
C71
open
AVSS
AVSS
AVSS
C74
open
C76
open
+
C77
open
AVSS
B
IN4/IN4P
U5B
NONE
+
C62
open 5mm
4
IN3N
open
MR-552LS(R)
C63 open
open
IN4N
open
8
+
R66 (open)
R63 (open)
+
B
C59
+
Diff
T
B
S
Diff
T
B
S
R64
(open)
-
AK4617-IN3N
R62
(open)
C58
+
J15
R67
(open)
AK4617-IN4N
+
J16
R65
(open)
JP7
C56
IN4
JP8
C57
IN3
TP4
LC-3-G_B
+ C75
open
AVSS
TP5
LC-3-G_B
AVSS
AVSS
AVSS
AVSS
AVSS
C117
AVSS
AVSS
+
C116
open
+
open
AREA: No Implementation
A
A
Title
<AKD4617-A>
5
4
- 383
Size
A2
Date:
2
Document Number
<AnalogIN>
Rev
<0>
Tuesday, July 31, 2012
1
Sheet
3
of
7
5
4
L1
1
GND
OUT
2
1
47uH
2
D3V
PORT1
VCC
3
D3V
3
C78
0.1u
2
1
PLRx
+
C79
10u
TP6
R78
51
+
DGND
D
C80
RX
DGND
D
10u
C81
0.1u
R79
10k
C82
1
2
10
9
8
7
6
D3V
H
3
38
37
INT1
R
AVDD
39
40
VCOM
41
VSS3
42
RX0
43
NC
44
RX1
45
TEST1
46
RX2
RX3
VSS4
47
48
0.47u
IPS0/RX4
INT0
NC
OCKS0/CSN/CAD0
DIF0/RX5
OCKS1/CCLK/SCL
36
INT0
35
OCKS0
34
OCKS1
SW1
4
TEST2
CM1/CDTI/SDA
33
D3V
1
2
3
4
5
L
C
5
6
OCKS0
OCKS1
7
DIF1/RX6
CM0/CDTO/CAD1
U6
VSS1
DGND
PDN
AK4118A
DIF2/RX7
32
XTI
31
DIO-PDN
30
1
DIF2
DIF1
DIF0
OCKS1
OCKS0
C
C83
5p
C84
5p
5
4
3
2
1
X1
12.288MHz
IPS1/IIC
XTO
29
2
8
DGND
DGND
9
P/SN
DAUX
XTL0
MCKO2
XTL1
BICK
28
DAUX
RP1
47k (R-PACK5R)
10
11
27
26
DIR-BICK
25
LRCK
DIR-SDTO
24
MCKO1
23
22
VSS2
DVDD
SDTO
21
VOUT/GP7
20
UOUT/GP6
19
18
17
TX1/GP3
16
TX0/GP2
15
14
13
TVDD
NC/GP1
VIN/GP0
COUT/GP5
B
12
BOUT/GP4
B
0.1u
0.1u
+
D3V
C86
+
DIR-LRCK
C85
C87
10u
C88
10u
DIR-MCKI
DGND
A
PORT2
IN
VCC
GND
TP7
3
2
A
TX
C89
D3V
0.1u
1
PLTx
Title
<AKD4617-A>
DGND
Size
A3
- 395
4
3
Date:
2
Document Number
<DIR/DIT>
Tuesday, July 31, 2012
Rev
<0>
Sheet
1
4
of
7
5
4
3
2
1
U7
10
CLK
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
VD
Q11
DGND Q12
11
RST
D3V
D
16
8
C90
0.1u
9
7
6
5
3
2
4
13
12
14
15
1
JP13
DIR-BICK
JP15
THR
AK4617-BICK
INV
BICK-PHASE
BICK-SEL
4040-1fs
DIR
10pin
DIR-LRCK
JP14
4040-64fs
4040-32fs
DIR
10pin
AK4617-LRCK
D
LRCK-SEL
74HC4040
TDMI
DGND
JP16
D3V
K
D3V
A
C
H
U8
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
PORT3
10
8
6
4
2
C91
0.1u
INT0
9
7
5
3
1
LE1
74HC14
1k 2
1
LRCK
BICK
MCLK
CLK
AK4617-SDTI4
DIR
10pin
GND
DIR-SDTO
AK4617-SDTI3
SDTI5-SEL
AK4617-SDTI2
AK4617-SDTI1
DGND
JP19
DGND
DGND
C
DIR
10pin
GND
DIR-SDTO
DGND
SDTI4-SEL
DGND
DIO-PDN
D3V
AK4617-SDTI5
JP18
SDTI6
SDTI5
SDTI4
SDTI3
SDTI2
SDTI2
INT0
DGND
9
7
5
3
1
AK4617-SDTI6/TDMI
SDTI6/TDMI
DGND
PORT4
10
8
6
4
2
JP17
SDTI6
SDTI6-SEL
R81
C92
0.1u
2
SW2
DIO-PDN
1
3
L
R80
10k
D1
HSU119
TDMI
DIR
10pin
GND
DIR-SDTO
K
JP20
A
DIR
10pin
GND
DIR-SDTO
Ak4617-PDN
R82
10k
D2
HSU119
SDTI3-SEL
1
L
SW3
PDN
JP21
H
DIR
10pin
GND
DIR-SDTO
C93
0.1u
2
3
DGND
SDTI2-SEL
DGND
JP22
DGND
DIR
10pin
GND
DIR-SDTO
B
2
3
4
5
J17
EXT
10pin
EXT
GND
DIR
1
R83
DIR-MCKI
DGND
PORT5
6
4
2
MCKI-SEL
51
B
SDTI1-SEL
JP23
JP24
EXT
5
3
1
SDTI1
SDTO2
SDTO1
AK4617-SDTO2
AK4617-SDTO1
JP25
SDTO/SDTI1
DAUX
SDTO2
DGND
SDTO1
DAUX-SEL
DGND
AK4617-MCLK
L
H
D3V
SW4
SMUTEN
D3V
1
2
SMUTEN
A
R84
4
3
R85
R86
10k
10k
U9
(Short)
C95
AK4617-SMUTEN
open 5mm
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
C94
0.1u
A
74HC14
DGND
Title
<AKD4617-A>
DGND
Size
A3
- 405
4
3
Date:
2
Document Number
<LOGIC>
Tuesday, July 31, 2012
Rev
<0>
Sheet
1
5
of
7
5
4
3
2
1
R103
D
D
D3V
100k
10k
10k
10k
PCA9306DP1
5V => 3.3V
NC
NC
Vin
Vout
Vcont PCL
NC
GND
7
SCL
6
SDA
5
U10
EN
GND
VREF2
VREF1
SCL2
SCL1
SDA2
SDA1
R88
DGND
1
R92
C98
2 0.1u
1k
1k
MS
3
MS
4
+
+
C99
10u
470
C100
10u
R94
470
0.1u
DGND
RD1
TP11
RD3
TP13
RD5
TP15
RD7
RD0
TP10
RD2
TP12
RD4
TP14
RD6
38
39
40
41
2
3
4
5
7
VDD0
VSS0
CDTI/SDA/DIF
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
TP8
PIC18F4550
TQFP 44-PIN
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
U11
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VUSB
32
35
36
B
U13
VUSB
DD+
GND
USB(B type)
1
2
3
4
R101
R102
0
0
42
43
44
1
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
18
USB-RST
12
13
33
34
30
31
R95
0.1u
100k
0.1u
25
26
27
37
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
C109
DGND CSN
22p
R98
R99
R100
2
VCC_A
VCC_B
GND
DIR
6
R96
5
1k
3
A
B
PS
JP29
AK4617-CSN/PS
CSN
4
CSN/PS
X2
20MHz
C108
22p
R97
470
SN74LVC1T45DRLR
0.47u
JP30
19
20
21
22
23
24
1
C106
C107
PS
C105
0.1u
XTI
XTO
D3V
U12
C104
DGND
51
51
51
CSN
SCL
SDA
JMP3x3
USB
10pin
USB
10pin
USB
10pin
B
CSN
SCL
D3V
SDA
CTRL-SEL
H
DGND
SW5
Serial/TDM SEL
L
PIC18F4550
10
8
6
4
2
PORT6
9
7
5
3
1
CSN
CCLK/SCL
CDTI/SDA
TDMI
MS
DIF
PS
AK4617-CAD1/TDM0
AK4617-SPI
6
5
4
3
2
1
10pin-CTRL
A
C
AK4617-CDTI/SDA/DIF
CDTI/SDA
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
JP27
DIF
12
11
10
9
8
7
PIC
17
16
15
14
11
10
9
8
VDD1
1
2
3
4
5
6
28
29
C102
0.1u
VSS1
JP28
DIF
DGND
C101
TMDI 1
MS 2
DIF 3
PS 4
CAD1/TDM0 5
SPI 6
DGND
1u/25V(A)
C
TP9
AK4617-CCLK/SCL/MS
CCLK/SCL/MS
R93
C103
SILK-SCREEN(P1)
1:VDD
2:MCLR
3:PGD
4:PGC
5:GND
JP26
CCLK/SCL
DGND
8
7
6
5
T1
1
2
3
4
R89
R90
R91
8
TK73633AME
0.1u
4.7k
R87
2.2u
C97
C96
A
DGND
DGND
RP2
R-PACK6R
Title
<AKD4617-A>
Size
A3
- 415
4
3
Date:
2
Document Number
<PC-IF>
Tuesday, July 31, 2012
Rev
<0>
Sheet
1
6
of
7
5
4
3
2
1
JP31
REG
J19
A3V31
J18
AK4617-AVDD1
A3V31
A3V31-SEL
1
1
VOP+ (12V)
D
C110
47u(A)
+12V-->+3.3V
T2
LT1963AEST-3.3
+
AVSS
JP32
47u(A)
1
C160
0.1u
REG
C161
+
J20
A3V32
C162
0.1u
AK4617-AVDD2
A3V32
A3V32-SEL
47u(A)
1
47u(A)
OUT
3
2
+
C159
AVSS
IN
GND
C111
D
+
AVSS
AVSS
AVSS
AVSS
AVSS
C114
47u(A)
+
AVSS
JP33
REG
J21
D3V3
AK4617-TVDD
D3V3
D3V3-SEL
C
1
C
C115
47u(A)
+
AVSS
+12V-->+3.3V
T3
LT1963AEST-3.3
C164
0.1u
3
REG
C163
+
J22
D3V
C165
0.1u
D3V
D3V
D3V-SEL
47u(A)
1
47u(A)
OUT
2
+
C166
IN
GND
JP34
1
DGND
DGND
DGND
DGND
DGND
C118
47u(A)
+
B
B
DGND
VOP-ADC
C119
10u
+
C120
0.1u
J23
DGND
J24
AVSS
1
1
AVSS
JP35
TP16
GND
GND1
A
A
DGND
AVSS
Title
<AKD4617-A>
Size
A3
- 425
4
3
Date:
2
Document Number
<POWER>
Tuesday, July 31, 2012
Rev
<0>
Sheet
1
7
of
7
- 43-
- 44-
- 45-
- 46-
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