Designing High-Efficiency ATX Solutions Practical Design Considerations & Results from a 255 W Reference Design Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 2 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 3 Drivers for Efficiency Improvements • Reducing Energy consumption has become a major goal for governments and consumers across the globe • Businesses need to adapt to these ever increasing demands for higher efficiency • “Green” groups are continuing to constantly push the boundaries • Higher integration into end-products and smaller form factors are also pushing the need for higher efficiency • Early enablers of increased efficiency are gaining lot of attention and garnering increased rewards • The Climate Savers Computing Initiative (CSCI) is an influential group that is pushing high efficiency requirements in computing – This group has the most aggressive efficiency targets of any major group or regulation agency world-wide – Their specifications were quickly adopted by other groups, including 80Plus in the US www.onsemi.com 4 CSCI Efficiency Requirements • With active involvement from Intel, Microsoft, Google, HP, Dell & Lenovo this is a very influential group • In addition, CSCI members are asked to have minimum purchase commitments listed above every year www.onsemi.com 5 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 6 Reference Design • ATX reference design that meets Climate Savers Year 3 targets (similar to 80 PLUS Silver targets) is presented • The 255 W design was built to real-world specs – – – – Specifications from 3 major OEMs were incorporated Standard ATX dimensions and outputs Standard protection features The finished unit was fully tested in a rigorous manner • Overall cost of the system was a key consideration during every design step • LLC-HB Resonant Topology adopted for this design www.onsemi.com 7 Reference Design – Target Specifications • Input range: 90 Vac to 264 Vac (100 Vac, 115 Vac, 230 Vac, and 240 Vac as the label voltage) • Output power: 255 W • Output voltage: 12 VA, 12 VB, -12 V, 3.3 V, 5 V, and 5 Vsb • Efficiency requirement: – Above 85% at 20 % and full load – Above 88% at 50 % load • Power factor: > 0.9 at 230 Vac, 50 % load • Standby power requirement (FEMP): < 1 W www.onsemi.com 8 Reference Design – Output Loading Output 12 VA 13.0 9.5 4.75 1.90 12 VB 7.0 5.12 2.56 1.02 -12 V 0.4 0.32 0.16 0.06 3.3 V 8.0 5.03 2.52 1.01 5V 15.0 9.44 4.72 1.89 5 Vsb 3.0 2.39 1.20 0.48 Total Power (W) 361.2 255 128 51 > 85 % > 88 % > 85 % Efficiency Requirement www.onsemi.com 9 Max Current (A) Full Load (A) 50% Load (A) 20% Load (A) Efficiency Targets by Stage • AC Input To meet the overall efficiency target of 85%, each stage has to meet a minimum efficiency SMPS Stage PFC Stage 96% Secondary Stage (with Standby) X 94% X 95% = Multiple Outputs Overall 85% Min. efficiency needed to achieve 85% overall efficiency (across load/line) • • In order to meet the minimum efficiency targets, the architecture, key components, and overall design has to be carefully considered ON Semiconductor’s reference design has achieved the objective while still keeping the overall cost down!! www.onsemi.com 10 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 11 Topology Comparison Dual switch Forward LLC HB Resonant Active Clamp Forward Transformer Easy to design Leakage sensitive 1Q operation Lower creepage Hardest to design Controlled Lleakage 2Q operation Lower creepage Hardest to design No leakage sensitive 2Q operation Higher creepage MOSFET 500 V (600 V) 2 pcs high current 500 V (600 V) 2 pcs high current 800 V 1pcs high current 1pcs low current Output Choke Conventional design No needed Conventional design (smaller by 15%) Output Capacitor Conventional design Needs higher ripple capability (more losses) Cross regulation Good with coupled choke Not Very Good Good with coupled choke Switching Hard Switching Soft Switching Soft Switching Efficiency Mid High High www.onsemi.com 12 Conventional design Topology Options for Main Converter • Output Power level and Efficiency requirements dictate specific choices! FULL BRIDGE PHASE SHIFTED 4-Switch, 2-Diode 1-Xfmr, 1-Inductor Traditional and Emerging Approaches 75 W PFC ACTIVE CLAMP Flyback 2-Switch, 1-Diode, 1-Xfmr FLYBACK REG 1-Switch, 1-Diode 1-Xfmr ACTIVE CLAMP FWD (ZVS) 2-Switch, 2-Diode, 1-Xfmr, 1-Inductor QR Flyback 1-Switch, 1-Diode 1-Xfmr FLYBACK CTRL 1-Switch, 1-Diode 1-Xfmr LLC Resonant (ZVS) 2-Switch, 2-Diode, 1-Xfmr 1SW FORWARD 1-Switch, 2-Diode 1-Xfmr, 1-Inductor FULL BRIDGE 4-Switch, 2-Diode 1-Xfmr, 1-Inductor ATX POWER SUPPLIES ADAPTERS NOTEBOOK ADAPTERS 10 W 100 W 250 W Power www.onsemi.com 13 2SW FW/HALF BRIDGE 2-Switch, 2-Diode 1-Xfmr, 1-Inductor Interleaved LLC(ZVS) 4-Switch, 4-Diode 2-Xfmr 500 W Topology Summary 2-SW Forward or other Hard Switching topology: • • • • • • • Does not facilitate soft switching Does not facilitate sync rectification Lower Efficiency 2-sw forward has 30% worse MOSFET figure of merit (Vds*Irms) Higher cost in Magnetic components (Transformer + Output choke) 2 high current/voltage diodes required Heatsink required for both power MOSFETs www.onsemi.com 14 Benefits of LLC Series Resonant Converter • Type of serial resonant converter that allows operation in relatively wide input voltage and output load range when compared to other resonant topologies • Limited number of components: resonant tank elements can be integrated to a single transformer – only one magnetic component needed • Zero Voltage Switching (ZVS) condition for the primary switches under all normal load conditions • Zero Current Switching (ZCS) for secondary diodes • Soft-switching and lower EMI are additional benefits www.onsemi.com 15 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 16 PFC Efficiency Improvements • • First, select the mode of operation (CCM or DCM/CrM) ON Semiconductor has >94% efficient solutions for both CrM and CCM applications Operating Mode IL Continuous Conduction Mode (CCM) Always hard-switching Inductor value is largest Minimized rms current IL Discontinuous Conduction Mode (DCM) Highest rms current Reduced coil inductance Best Stability IL Critical conduction Mode (CrM) Good performance to cost Large rms current Switching frequency not fixed – EMI becomes harder www.onsemi.com 17 Main Feature Considerations for Different Operation Mode • For CCM, high efficiency can be achieved by: – Optimal switch selection (at light load, switching losses dominate, so it is more advisable to sacrifice Rds-on for faster switching) – Soft recovery boost diode – Inductor sized for copper loss reduction (Core losses are low) • For DCM/CrM, high efficiency can be achieved by – Optimizing the inductor core for low core loss and low highfrequency winding losses – Selecting a lower Rds-on switch – Less attention to be paid to boost diode selection www.onsemi.com 18 PFC – Output Power Positioning Part number NCP1601 NCP1606 NCP1653 NCP1654/55 NCP1650 Recommended 75-150 W 150-250 W 250-500 W >500 W Better fit exists Fixed Freq. Discontinous Conduction & Critical Critical Conduction Mode Continuous conduction Mode • • There is a grey area in the mode of operation to be chosen for a 250 W application For this reference design, a CCM mode PFC was chosen using ON Semiconductor’s NCP1654 www.onsemi.com 19 PFC – CCM MOSFETs Choice 20N60C3 Rds(on) = 0.19Ω Coss = 780 pF Switching losses (Coss) Conduction losses Switching losses (Coss) Conduction losses 100 % load 270 W 1.28 W 1.34 W 0.88 W 1.98 W 50 % load 135 W 1.28 W 20 % load 54 W 1.28 W Conduction losses: Sub-total: 2.62 W www.onsemi.com Sub-total: 2.86 W 0.34 W 0.88 W Sub-total: 1.61 W 1.28 W Sub-total: 1.33 W Pon ,max 0.5 W Sub-total: 1.38 W 0.05 W 0.08 W Sub-total: 0.96 W ⎞ ⎛P = RDS ( on ) ⋅ ⎜⎜ in ,max ⎟⎟ ⎝ VacLL ⎠ Switching losses caused by Coss: 20 15N60C3 Rds(on) = 0.28Ω Coss = 540 pF Vend ∫ 0 2 ⎛ 8 2VacLL ⎞ ⎟ ⋅ ⎜⎜1 − 3πVout ⎟⎠ ⎝ 2 CV2dv = C25 25⋅V1.5 ⋅ f 3 PFC – CCM MOSFETs Choice (cont’d) Efficiency of 270 W CCM PFC based on NCP1654 (Vin = 115 Vac) Efficiency 97.0% 96.5% 20N60C3 15N60C3 96.0% 95.5% 95.0% 0% 50% 100% Output Power • At light load, switching losses dominate. In some conditions, MOSFETs with lower rating provide better efficiency www.onsemi.com 21 PFC – CCM Boost Diode Choice Boost diode MOSFETs • In CCM operation, the IRRM (Qrr), and (tr + ta + tb) of boost diode impact the switching losses of MOSFETs and boost diodes significantly www.onsemi.com 22 PFC – CCM Boost Diode Choice (cont’d) 40.0 400 vds 20.0 0 id1 in amperes Plot1 vds in volts 200 -200 34 5 0 Id_MSR860 -20.0 Id_MUR860 -400 -40.0 12.996850m 12.996860m 12.996870m time in seconds 12.996880m 12.996890m • A soft recovery diode, e.g. MSR860, with s = tb/ta = 3 and Qrr = 700 nC, reduces the switching losses www.onsemi.com 23 PFC – CCM Boost Diode Choice (cont’d) • To further improve the efficiency, here come several choices: – Silicon Carbide Schottky Diode – zero recovery diode • This provides better performance at added cost – Qspeed Q-series PFC rectifier – soft recovery diode with s = tb / ta =1.3 and Qrr = 35 nC www.onsemi.com 24 Efficiency NCP1654 CCM PFC 270 W Application 98.5% 98.0% 97.5% 97.0% 96.5% 96.0% 95.5% 95.0% 94.5% 100 Vac 115 Vac 230 Vac 0% 50% 100% Output Power PFC MOSFET Q1 = 20N60C3 PFC Diode D1 = Qspeed LQA08TC600 Efficiency > 95 % at 100 Vac PFC choke = 650 μH • By selecting suitable components, efficiency is optimized • But some people might think the boost diode costs more, what other solutions can be used? www.onsemi.com 25 Summary of PFC Stage Considerations • Both CCM and CrM/DCM PFC can provide good efficiency at power range around 250 W • The design considerations for each topology are different • For CCM, high efficiency can be achieved by: – Optimal switch selection – Soft recovery boost diode – Inductor sized for copper loss reduction (Core losses are low) • For DCM/CrM, high efficiency can be achieved by – Optimizing the inductor core for low core loss and low high-frequency winding losses – Selecting a lower Rds-on switch – Less attention to be paid to boost diode selection www.onsemi.com 26 Key Components used in PFC Stage for Reference Design • NCP1654, 65 kHz CCM PFC controller in SO-8 • PFC choke – PQ3319 – Inductance is 650 µH – 0.1 * 50 Litz wire • PFC MOSFET – SPP15N60C3, 15 A, 650 V, 0.19 Ω Rds(on) • PFC Diode – Qspeed LQA08T600, 8 A, 600 V www.onsemi.com 27 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 28 Topology Options for Main Convertor (cont’d) Advantage with Soft Switching solutions: • • • • • • • Cost effective, highly efficient and lower EMI due to soft switching ACF and LLC are being used for 80 PLUS and 85 PLUS solutions Self-driven Sync Rectification in ACF Facilitates Synchronous Rectification in LLC 15% lower output inductor in ACF or No output choke required in LLC Better Transformer core utilization (2Q operation) Allows operation at higher frequency, thus smaller size Active clamp was used in 1st 80 PLUS ref design in past. In order to show another example, LLC was chosen in this 85 PLUS efficiency design www.onsemi.com 29 Design Tips for Light Load Efficiency • Reduce switching losses with soft-switching operation by selecting FETs with low capacitance (trade-off with low Rds-on) Dual switch Forward Active Clamp Forward Total FET Coss 1560 pF 1560 pF 930 pF Turn-on voltage 400 V 0V 200 V Turn-on losses (100 kHz) 4.8 W 0W 1.1 W Turn-off current 2.5 A 1.6 A 2.0 A Turn-off losses 0.8 W (25 ns, 100 kHz) 0.4 W 0.6 W www.onsemi.com 30 LLC HB Resonant Design Tips for Light Load Efficiency (cont’d) • At light load, every 0.1 W counts! – For a 250 W output system, 0.6 W loss reduction leads to 1.2% efficiency improvement at 20% load • Within the high-volume ATX application space of 240 – 300 W, LLC HB Resonant topology is a good solution to achieve higher efficiency at light load due to ZVS on primary MOSFETs www.onsemi.com 31 The Optimized Operating Point • Gain characteristics shape and needed operating frequency range is given by these parameters: – – – – Lm/Ls ratio Characteristic impedance of the resonant tank Load value Transformer turns ratio • The operating point of fop = fs is the most attractive – Sinusoidal primary current – MOSFETs and secondary rectifiers optimally used – This operating point can be reached only for specific input voltage and load (usually full load and nominal Vbulk) www.onsemi.com 32 Normalized Gain Characteristic 2.0 Q=0.05 Q=0.5 Q=1 Q=2 Q=3 Q=4 Q=5 Q=10 Q=20 Q=50 Q=100 Q=200 Q=200 – Light load Lm/Ls=6 1.8 Region 2 1.6 ZVS voltage gain 1.4 1.2 Region 1 1.0 0.8 0.6 ZCS Region 3 0.4 Q=0.05 – Heavy load 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 f / fs Region3: ZCS region www.onsemi.com 33 Region 1 and 2: ZVS operating regions Secondary Waveforms of LLC with Diode a) Fop < Fs b) Fop = Fs █ - rectifier current █ - rectifier voltage c)Fop > Fs Assumptions: 1. Secondary current is sinusoidal 2. Operating state is in resonant frequency Fs. www.onsemi.com 34 Secondary Current Calculations Equations RMS diode current I D _ RMS = I out ⋅ π 12 V/20 A output I D _ RMS = 7.85 A I D _ RMS = 15.7 A I D _ AVG = 5 A I D _ AVG = 10 A I D _ PK = 15.7 A I D _ PK = 31.4 A 4 AVG diode current I D _ AVG = 24 V/10 A output I out 2 Peak diode current I D _ PK = I out ⋅ • 2 Even at 12 V, the RMS current is still in the acceptable range for LLC topology www.onsemi.com 35 π Synchronous Rectification Solution using 2 x NCP4302 Sync signal (patent pending) www.onsemi.com 36 SR Operation for Fop= Fs █ - SR MOSFET gate signal █ - Rectifier current █ - SR MOSFET drain voltage █ - Trigger input www.onsemi.com 37 The Operation Point of LLC HB Vds of primary MOSFET Current in resonant tank • The resonant frequency, fs, is 77 kHz • The operating frequency at full load is 85 kHz • Primary MOSFETs operate at ZVS www.onsemi.com 38 Key Components of Main SMPS Stage in Reference Design – Primary Side • NCP1396, LLC controller featuring high voltage driver • Integrated resonant tank solution, i.e. the leakage inductance of transformer acts as resonant inductance. – – – – – EE35 bobbin Lm = 630 µH Ls = 80 µH Np = 33 Turns, 0.08 * 80 Litz wires Ns = 2 Turns, 0.2 *25 Litz wires • MOSFETs at primary side – STP12NM50, 12 A 500 V, 0.35 Ω Rds(on) www.onsemi.com 39 Key Components of Main SMPS Stage in Reference Design – Secondary Side • 2 pcs of NCP4302, the synchronous rectifier controller, to control SR MOSFETs • MOSFETs as rectifiers – STP80NF55, 80 A, 55 V, 5 mΩ Rds(on) • Diodes in parallel the SR MOSFETs to reduce dead time losses – MBR20L45CTG, 20 A, 45 V www.onsemi.com 40 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 41 Topology Options for Secondary Convertor • New stringent requirements for cross regulation require zero load operation on +3.3 V and +5 V outputs • Stacking transformer windings, coupling the output chokes, Mag-amp approach is hard to meet new requirements Input Voltage 5V D1 Ls1 DRV D2 4T D4 MAGAMP Regulation Circuit www.onsemi.com 42 12 V out 5 V out D3 3.3 V GND 7:3 ratio 3T Topology Options for Secondary Converter • LLC HB does not have an output choke – So, it lends itself to moving to a single +12 V output followed by a dc-dc stage to generate the +5 V and +3.3 V outputs – This provides better cross-regulation – However, the efficiency is a challenge due to additional power processing stages (+12 V Æ +5 V and +3.3 V) +12V +5 V Output DC-DC Converter +12Vt +3.3 V Output www.onsemi.com 43 Why Synchronous Rectification in DC-DC? 0.50 Conduction Voltage (V) 0.45 0.40 Diode Voltage 0.35 0.30 0.25 MOSFET Voltage 0.20 0.15 0.10 0.05 0.00 0 2 4 6 8 10 Forward Current (A) • Diode forward drop (0.35 V to 0.45 V) limits efficiency to 3.3/(3.3+0.45)=88% www.onsemi.com 44 Design Consideration in SR Buck What can be done to Reduce Power Loss? • Upgrade MOSFET, Reduce Rdson and chose low Qg • Add Schottky diode in parallel low side FET to reduce dead time loss • Use inductor with Low DCR • Use reasonably high frequency (200 kHz ~ 400 kHz) due to the switching lost • Increase PCB layers and copper thickness www.onsemi.com 45 Design Consideration in SR buck (cont’d) Layout Consideration: • Sensitive signals should be kept away from the high dV/dT trace such as gate drive (minimum 5 mm or 0.2 in) • In some practical design, noise isolation technique is also an alternative solution for compact PCB board • The MOSFET gate traces to the IC must be short, straight, and as wide as possible • Minimize the “Star” or “T” trace length on gate traces • The VCC bypass capacitor (0.1 F or greater) should be located as close as possible to the IC and connection to GND must be as short as possible www.onsemi.com 46 MOSFETs Selection for SR Buck Application Vin = 12V HIGH SIDE Low Gate charge Fair Rdson Sync. FET LOW SIDE Fair Gate charge Low Rdson • The losses in the Low side FET is dominated by conduction losses – Therefore Rdson is the most important • High side FET affects the switching speed – Therefore, it is important to minimize the switching charge Qsw and gate resistance Rg, while maintaining a reasonable on-resistance Rdson www.onsemi.com 47 Key DC to DC Buck Converter Components used in Reference Design • 2 pcs of NCP1586, the buck converter controller, for 5 V and 3.3 V outputs – NCP1586 built in non overlap timing control prevents cross conduction of rectification MOSFETs • Power chokes – 5.7 µH • MOSFETs – NTD4809N, 58 A, 30 V, 14 mΩ Rds(on) www.onsemi.com 48 Key Components for Standby Converter in Reference Design • NCP1027, 65 kHz PWM controller featuring 700 V MOSFET – The efficiency at full load is optimized because it allows deep CCM operation thanks to the adjustable ramp compensation feature – The light load efficiency is optimized thanks to the skip mode operation • The Stby transformer – – – – EEL19 bobbin Np = 105 T, 1.4 mH Ns = 6 T Naux = 20 T • Diode – MBR20L45CTG, 20 A, 45 V www.onsemi.com 49 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 50 255 W, 85 PLUS ATX Power Supply Reference Design www.onsemi.com 51 The Input Current at 230 Vac, 50 % Load Vbulk Input Current • PF = 0.991 at 230 Vac input, full load • PF = 0.952 at 230 Vac, input, 50 % load www.onsemi.com 52 Efficiency Results Input 20% Load 50% Load 100% Load 100 Vac 85.35% 88.61% 86.78% 115 Vac 85.57% 89.12% 87.59% 230 Vac 86.25% 90.69% 89.73% 240 Vac 86.69% 90.93% 89.86% Requirement @ 115 Vac 85% 88% 85% www.onsemi.com 53 Efficiency Results Efficiency > 85% @ 4 line voltages and 3 loads Efficiency (%) 91% 89% 240 Vac / 50 Hz 230 Vac / 50 Hz 115 Vac / 60 Hz 100 Vac / 50 Hz 87% 85% 20% 50% 100% Loading (% of rated output power) www.onsemi.com 54 The Output Voltage Regulation DC Terminal Voltage (V) & DC Load Current (A) Load (%) (V) 20 12.01 50 100 (A) (V) (A) 3.3V 5Vsb -12V (V) (A) (V) (A) (V) (A) (V) (A) 1.90 12.02 1.03 5.01 1.89 3.25 1.01 4.99 0.48 -12.78 0.06 11.97 4.75 11.97 2.56 4.98 4.71 3.22 2.52 4.96 1.20 -12.37 0.16 11.86 9.50 11.87 5.12 4.93 9.43 3.18 5.02 4.91 2.39 -11.95 0.32 www.onsemi.com 55 5V 12VB 12VA The Thermal Result @ 100 Vac, Full load LLC-HB transformer is 85℃ The ambient temperature outside the case is around 33 ℃ • The thermal performance is optimized. www.onsemi.com 56 Agenda • • • • Regulation and Market Requirements Target Specification for the Reference Design Architectural Considerations Design Approach & Key considerations for each stage – PFC Stage – Main SMPS Stage – Secondary Stage • Results • Summary www.onsemi.com 57 Summary • In order to obtain high overall efficiency for the power supply, up-front architectural considerations and component selection for each stage are critical • A soft-switching topology, coupled with highly efficient PFC stage and output stage are required to meet the new efficiency requirements of the OEMs • ON Semiconductor’s 85% PLUS reference design offers a fully tested, robust and cost-effective solution – This solution can be optimized for higher efficiencies and other output power ratings www.onsemi.com 58 For More Information • View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com • View reference designs, design notes, and other material supporting the design of highly efficient power supplies at www.onsemi.com/powersupplies www.onsemi.com 59