### Achieving High Power Density Designs

```Achieving High Power Density
Designs in DC-DC Converters
Agenda
• Marketing / Product Requirement
• Design Decision Making
• Translating Requirements to Specifications
• Passive Losses
• Active Losses
• Layout / Thermal PCB Guidelines
• Reference Designs
2
Regulation Division
Marketing / Product Requirement
Area Required For
World’s Greatest Idea
Marketing
51 mm
Input: +12 V
Output: 3.3 V @ 10 A
Size: 77 x 51 mm
Height: 21 mm
Ripple: <30 mV
Thermal: <72 °C case
Transient: ~2.5 A/us
Cost: Low
Does this sound familiar?
Marketing has come up with a
new product idea, but it requires
more power and less space than
the previous designs.
3
Design Engineering
77 mm
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c
stere
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Syn
c
tic
a
b
y
l
F
There are so many choices for a
solution. Which one do you select?
Regulation Division
Reviewing potential options
In order to meet the high power density design
requirement, you must first understand the efficiency
losses in your system and make some design decisions.
4
Regulation Division
Black box thermal analysis
ΔT = Tsurf − Tamb
In Kelvin or Celsius
l
h
Heat Convection can be calculated for a a 5 sided box
[
w
]
Pdconv = 10 −3 × 4.6(l + w)h 0.75 + 1.8(l × w) 0.75 × (l + w) 0.25 × ΔT 1.25
The surface radiated heat transfer can be calculated using Boltzman’s law
[
Pdrad = 3.66 ×10 −11 × f × e × A Tsurf − Tamb
4
4
]
Surface area in square inches
Emissivity = .9
View factor = .5
5
Regulation Division
General system thermal analysis
If the height and width are fixed at 20.5 mm and 77 mm respectively then the length can be
selected from the graph.
Power Density and Efficency
6
0.933
5
0.9
η (w)
P.D_max(w) 4
0.85
Efficency(%)
Power Disipation(W)
5.747
3
2.223
PI − PO
PdMAX
→ η = 1 − MAX
η = 1−
PO
PO
0.826
2
0
15
20
40
60
w⋅25.4
Width (mm)
80
0.8
100
100
Height & Width
Fixed
Select
Length
44mm
A length of 77 mm indicates that the system efficiency must be a minimum of of 88.7 %,
allowing 3.72 W of dissipation.
6
Regulation Division
Efficiency target
Loss contributions of the
system will be tracked using a
target table
Cond. Loss (Rdson)
Switching Loss
Gate Charge Loss
Winding Cu Loss
Core Loss
Iin
Io
+
+
ESR Loss
Vin
Cond Loss (Rdson)
Switching Loss
Body Diode
7
Vo
-
Passive Losses
Inductance
Input / Output Cap
Traces
Est. (W)
0%
0%
0%
Active Losses
MOSFETs
Diodes
Target
0%
0%
3.72
Regulation Division
0%
Inductor losses in switch mode power supplies
Inductor Losses
Copper
DC Copper
Losses
8
Skin
Effect
Core
Proximity
Effect
Hysteresis
Losses
Eddy Current
Losses
Regulation Division
Aw = Wire Cross Sectional Area
DC copper losses
L = Length of Wire
I
ρ = Resitivity of Wire
R=
ρ×L
Aw
(copper = 2.3X10-6 Ωcm)
•
PDC = I DC × RDC
2
If a current is flowing in a conductor then Ampere’s Law can be used to
calculate the flux density both inside and outside a conductor for an
infinitely long wire
Bϕ
μo I
b 2π
∫ B • bl = μ I
o
r1
C1
C
C2
b
0
9
b
r
r2
Regulation Division
Eddy currents
•
•
Since the current flowing inside the conductor is not dc, the
effects to current flow must be considered
Electromotive Force (EMF) in Volts
Lenz’s law indicates:
Magnetic Flux in Webers where ФB = B*Area
Change in Time
Number of Turns
•
•
If the ac current produces a changing B field and that in turn
produces a voltage in a conductive medium, then by ohms law a
current must flow
The diagram below shows that eddy currents decrease the
current flow at the center of a conductor
Wire
Ф(t) (Magnetic Flux)
i(t)
10
Eddy
Currents
Regulation Division
Skin effect
•
•
•
Eddy current produced by the ac current adds to the outer
conductor current and subtracts from the inner current
When frequency increases, the majority of the current flows on the
surface
The wave attenuation factor can be expressed as e-αz, where skin
depth is the point where e-1 = 0.368 or 63.2 % of the wave flows:
δ
Current
Density
ρ = Resistivity of a Wire
ρ CU = 2.3X10-6 Ωcm
δ=
ρ
π ×μ× f
Frequency
Permeability of Free Space
4πx10-7 N · A-2
2.3 X 10 −6 Ω * cm
.129mm =
π × 4 × π ×10 −7 × N × A− 2 × 350 * kHz
11
Regulation Division
Skin effect
•
The DC resistance calculated earlier will now have to be modified to
account for AC currents
With a Wire Length of 12 cm
Power Loss vs Height of a Wire
1 .10
3
δ
P AC_75kHz( h)
× RDC
P AC_150kHz( h)
100
P AC_300kHz( h)
P AC_500kHz( h)
Loss (W)
RAC =
h
10
P AC_700kHz( h)
P AC_900kHz( h)
P AC_1200kHz( h)
1
3.72
Target 25% of Total
Losses
•
Power loss increases at higher
frequency because of increasing
AC resistance
P1Layer = I
12
2
L , RMS
× RAC
3.72⋅25%
0.1
0.01
0.01
0.1
1
10
h
mm
Hight of a Wire (mm)
Select Frequency based on targeted
power loss
(50 – 350 kHz)
Regulation Division
Proximity effect
•
•
When two conductors, thicker than δ, are in proximity and carry
opposing currents, the high frequency current components spread
across the surfaces facing each other in order to minimize magnetic
field energy transfer
Thus an equal and opposite current is induced on the adjacent
conductor
PLayer 2 = (2 × I L , RMS ) × RAC _ Layer 2 → 4 PLayer1
h
h
⎡
⎤ ⎡
⎤
Pwinding = ⎢ I L2, RMS × × RDC ⎥ + 4⎢ I L2, RMS × × RDC ⎥ + ......
δ
δ
⎣
⎦ ⎣
⎦
Layer 2
Second Layer has 4X the loss of the First !!
Layer 1
2
Area 2i
Goal: Minimize the number of # of Layers in the Winding
Area i
13
Area i
Regulation Division
Proximity effect
•
•
When two conductors, thicker than δ, are in proximity and carry
opposing currents, the high frequency current components spread
across the surfaces facing each other in order to minimize magnetic
field energy transfer
Thus an equal and opposite current is induced on the adjacent
conductor
PLayer 2 = (2 × I L , RMS ) × RAC _ Layer 2 → 4 PLayer1
2
Φ
2Φ
Goal: Minimize the number of # of Layers
in the Winding
Current
Density J
Area
i
14
Layer 3
h
h
⎡
⎤ ⎡
⎤
Pwinding = ⎢ I L2, RMS × × RDC ⎥ + 4⎢ I L2, RMS × × RDC ⎥ + ......
δ
δ
⎣
⎦ ⎣
⎦
Layer 2
Layer 1
Second Layer has 4X the loss of the First !!
Area
-i
Area
2i
Area
-2i
Regulation Division
Magnetic eddy current losses
•
•
•
•
Magnetic eddy current losses are similar to the losses experienced in
copper
Instead of having current moving inside of a copper conductor, a field
is moving within a core material
The faster the field moves in the material, the greater the magnetic
eddy current losses
Magnetic eddy current can be decreased by increasing the resistivity
of the magnetic material
Eddy
Current i(t)
Flux Ф(t)
15
Core
Regulation Division
Hysteresis losses
• Hysteresis losses are caused from
friction between magnetic domains
as they align to the applied fields
• The larger the area of the
hysteresis loop, the more loss per
cycle. Hysteresis loss gets worse at
lower frequencies
• The red indicates power lost during
one switching cycle due to friction
between magnetic domains
B=Tesla (T)
• The green indicates power
delivered during one switching cycle
e
H=0
H
H=A/m
16
Regulation Division
Core losses
•
•
•
The hysteresis and magnetic eddy current losses are grouped into one
general volumetric loss equation not calculated directly
Manufacturer provide a loss curves
of tested data at various frequencies
Manufacturers may also provide loss
coefficients a, c and d are found by
curve fitting the charted data.
Frequency
Change in Flux
P = a × f c × (ΔB) d
kW/m3 or 10-3 W/cm3
From a Curve Fit
•
17
The loss per unit volume is
dependent on the material selected,
frequency and temperature.
Regulation Division
Choosing core materials
18
Ferrite- MnZn
Low core loss, High perm, High
frequency up to MHz
Fast roll off, Low B sat, Temp
stability, gap losses
Ferrite- NiZn
Low conductivity, Wind on core,
High frequency up to 300 MHz
Higher core losses than MnZn,
Low B sat, Low permeability
Powder Iron
Low cost
High core losses, Low frequency,
Possible aging issues
Permalloy
Good DC bias, Low core loss
High cost, Excellent temperature
stability
High Flux
Best DC bias, High B sat, Low
core losses
Average cost
Regulation Division
Ripple current inductance and core loss
•
Ampere’s law, Faraday’s Law, and core characteristics are the only
tools needed to choose a proper core
V
(V − V ) ×
Inductor ripple current at full load is characterized by ΔI = L × F V
Using the loss equation for Magnetics INC R type material with a
standard drum core with a volume of 1.73 cm3
The change in B can be calculated by
OUT
•
•
•
IN
IN
LO
O
Ripple Current vs. Inductance
10
31.9
( )
( )
ΔI.out_300kHz ( L.o)
ΔI.out_500kHz ( L.o)
ΔI.out_700kHz ( L.o)
ΔI.out_900kHz ( L.o)
ΔI.out_1200kHz ( L.o)
8.058
ΔI.out_75kHz L.o
10
1
0.1
10⋅ 25%
1
( )
P150kHz ( L.o)
0.1
P300kHz ( L.o)
0.01
P500kHz ( L.o)
P700kHz ( L.o)
3
1 .10
P900kHz ( L.o)
4
P1200kHz ( L.o) 1 .10
P75kHz L.o
Core loss (mW)
ΔI.out_150kHz L.o
SW
Core Loss vs. Inductance
100
Ripple Current (A)
OUT
1 .10
5
1 .10
6
−6
6.847×10
1
10
1
L.o
0.02
0.01
μH
1
10
1
L.o
μH
100
Inductance(uH)
100
Target: 2.5 A p-p MAX
Target: 3.3 uH
Inductance(uH)
19
Regulation Division
100
100
Core technology choices
Classical E
EFD
ER
EP
Pot core of 'RM' type
1. Surface Mount
2. Inexpensive
U-shaped
C-shaped
Planar 'E'
Toroid
3. Time Constraints
4. Size Requirement
Unshielded drum
20
Shielded drum
Vertical mount
Shielded toroid
Power wafer
Integrated inductor
5. NO EMI Requirement
Regulation Division
Off the shelf solutions
•
•
The inductors shown
meet the size and
electrical requirements
at 350 kHz
Inductor 1 was chosen
as it has lower
temperature rise and
losses
3 mm
+2 mm
8.5 mm
2 mm
20.5 mm
+2 mm
3 mm
21
Passive Losses
Inductance
Input / Output Cap
Traces
Est. (W)
0.889
24%
0%
0%
Active Losses
MOSFETs
Diodes
Target
0%
0%
3.72
24%
Regulation Division
Input / output capacitor selection
ESR = Equivalent Series Resistance
Typical ESR
C
Electrolytic
ESR
Ceramic
N/A
N/A
10 mΩ
1 µF
1Ω
2Ω
20 mΩ
10 µF
50 mΩ
3Ω
35 mΩ
100 µF
50 mΩ
1Ω
45 mΩ
100 nF
V
Tantalum
Realistic Capacitor Value on the PCB
22
Regulation Division
Capacitor electrical model
Rleak = 1 Mohm
ESL = 20 nH
ESR = 0.1 ohm
C= 400 uF
Full Model
Removing the Inductor
.941
Removing the Inductor and ESR
1.2850
.970
Ripple
Current
(A)
-.950
.989
-1.2692
Voltage Spike from Inductance
3.424
3.191
23
Ripple
Voltage
(V)
3.3997
3.2038
3.3024
3.2998
Regulation Division
Ripple voltage
•
Ripple voltage can be simplified by eliminating package inductance
ΔVout = ESR × ΔI OUT →
•
•
ΔVout
30mV
= ESR →
= 12mΩ
ΔI OUT
2.41A
The low ESR requirement will prompt the use of ceramic capacitors
The designer must be aware of the derating over voltage and
frequency when using ceramic capacitors
68%
3.8 mΩ
24
Regulation Division
•
Input Capacitor Losses
2
PCin
•
Losses
4 x 47 uF Capacitors
2
⎡I
⎤
⎡10 A ⎤
= ⎢ OUT ⎥ × ESRIN → ⎢
⎥ × .714mΩ = 17.8mW
⎣ 2 ⎦
⎣ 2 ⎦
Output Capacitor Losses
4 x 100 uF Capacitors
PCin = [ΔI OUT ] × ESROUT → [2.41] × .95mΩ = 5.5mW
2
2
Passive Losses
Inductance
Input / Output Cap
Traces
Est. (W)
0.889
0.023
Active Losses
MOSFETs
Diodes
Target
25
24%
1%
0%
0%
0%
3.72
Regulation Division
25%
Power loss in PCB traces
Copper Area Required for Temperature Rise
C Area = (I OUT /(0.0647 * (ΔT)^0.4281))^ (1/0.6732)
∆T= Surface Temperature – Ambient Temperature
Output Current
Required Trace Width for Temperature Rise
WREQ = C AREA /(C thick *1.378)
Copper Thickness in oz per square feet
Resistance of a Trace
RTrace = Con length * (0.6255 + 0.00267 * (Tamb + ΔT))/C AREA
Length of the trace
Power Dissipation of a Trace
PTrace = I OUT × RTRACE
2
26
Regulation Division
Trace resistance
•
The dimensions required from the surface temperature calculation
combined with the fact that power must be carried from one end of
the PCB to the other, gives the diagram shown
½ of the design is input ½ of the design is output
The design uses a 10 °C rise with an ambient of 25 °C
Other components contribute to the final temperature of the traces
•
•
•
0.24 W
0.14 W
VOUT
VIN
3.12 A
GND
3.12 A
0.14 W
27
Converter
10 A
GND
10 A
0.24 W
Passive Losses
Inductance
Input / Output Cap
Traces
Est. (W)
0.889
0.023
0.76
Active Losses
MOSFETs
Diodes
Target:
24%
1%
20%
0%
0%
3.72
Regulation Division
45%
Review of the active losses
Cond. Loss (Rdson)
Switching Loss
Gate Charge Loss
Winding Cu Loss
Core Loss
Iin
Io
+
+
ESR Loss
Vin
Vo
-
-
Cond Loss (Rdson)
Switching Loss
Body Diode
28
Regulation Division
Conduction losses
MOSFET Conduction Loss
•MOSFET are selected based on peak
current & voltage.
•Conduction loss calculated as shown in
figure
•A range of MOSFETs with different
Rdson can be selected.
isw
Isw,RMS
Isw,avg
DTS
DTS
DTS
2
2
Psw,cond = I sw
, RMS × RDS ,ON ≈ DI o RDS ,ON
29
Regulation Division
t
Switching losses
Switching Losses: High Side Switch
Pturn,on =
•During turn on (t2+t3) and turn off
(t5+t6) both ID and VDS are nonzero
•This results in significant power
loss during switching transitions
Pswitching =
1
I DSVDS (tturn ,on + tturn ,off ) ⋅ f sw
1442443
2
switch −transition −time
• Switching Losses are dominant loss
components at higher switching
frequencies
1
I DVDS tturn,on
123
2
Pturn,off =
1
I DVDS tturn,off
123
2
( t5 + t6 )
( t 2 + t3 )
VDS
ID
VGS
Vth
t1
t2 t3
Turn on
t4
t5 t6
Turn off
• MOSFET datasheet provides information
for estimation of switching losses.
30
Regulation Division
Gate charge losses
•There is a power loss associated with
the gate charge supplied at turn on.
This power loss can be calculated as
Psw,GATE = QG (VGS )VGS f s
•QG(VGS) can be found from the gate charge
curve in Power MOSFET datasheets
•Gate Charge Losses can be appreciable
at very high switching frequency
31
Parasitic Capacitance
Regulation Division
Synchronous rectifier
At Vin=12 V, Vo=3.3 V, Losses in Diode (VF= 0.6 V)
alone will cause a 15% drop in efficiency!
•In Synchronous Rectifier Diode is
replaced by a MOSFET
•Low RDSON of MOSFET allows
higher efficiency
•Introduces extra gate drive
32
Regulation Division
Synchronous rectifier
gate drive circuit
•Gate Charge Loss of synchronous rectifier
should be taken into account while estimating
efficiency gain
Gate
Driver
CGS
•The gate can be driven by a low voltage supply
to reduce gate charge losses
Psw,GATE = QG (VGS )VGS f s
•Low gate drive voltage results in higher Rdson from being only partially
turned on resulting in higher conduction loss
33
Regulation Division
Body diode
•
•
•
•
•
34
cross conduction
Body diode of synchronous switch
Body diode is lossy and is slow to
turn on/off
A Schottky diode is used in
parallel with synchronous rectifier
MOSFET
Non-overlap time conduction can
be significant at high switching
frequencies
Can cause 12% efficiency
drop
External
Schottky Diode
Regulation Division
Frequency selection
80%
High Power
Density/Small Size
% of Total Power Loss
70%
P switching
60%
High Frequency Design
1.2 MHz
50%
Select
200-500 kHz
40%
30%
P gate charge
20%
50 kHz
High Efficiency
P conduction
10%
Low Frequency to Limit
Switching Losses
0%
100
200
300
400
500
600
700
800
900
1,000 1,100 1,200
Frequency (kHz)
35
Regulation Division
Summary
36
•
In order to design high power density products it’s important to
understand the passive and active losses in the system
•
PCB layout plays a key part in achieving the desired performance
•
ON Semiconductor offers several products to meet your high
power density design needs
• Complete System: Regulators, Controllers, FETs, Diodes
Regulation Division
```