AN056 The Future of Analog IC Technology Peak-Power Design with Optimized Power Loss and Transformer Size for the HFC0300 Application Note for Peak-Power Design with Optimized Power Loss and Transformer Size for the HFC0300 Prepared by Jian Zhao/Yangwei Yu Feb 2012 AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 AN056 –PEAK POWER DESIGN FOR THE HFC0300 ABSTRACT Applications—including printers, data-storage equipment, audio amplifiers and motor drivers—usually require power supplies that deliver high peak-to-nominal load ratios. The HFC0300 is a variable off-time controller optimized for these applications. This application note introduces the operating principles and features of HFC0300 for delivering peak load, and outlines an optimized peak-power design method that lowers power loss and minimizes transformer size. Finally, this application note provides a detailed step-by-step design example with peak load profile, which includes both theoretical calculations and experimental verification. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 AN056 –PEAK POWER DESIGN FOR THE HFC0300 INDEX ABSTRACT ........................................................................................................................................... 2 1. INTRODUCTION ............................................................................................................................... 4 2. HFC0300 FEATURES FOR PEAK POWER ...................................................................................... 4 3. DESIGN METHOD FOR PEAK POWER ........................................................................................... 6 3.1 Current Solution........................................................................................................................ 6 3.2 Optimized Design Introduction .................................................................................................. 7 3.3 Optimized Design Flow ............................................................................................................. 9 A. Predetermined Input and Output Specifications .................................................................. 9 B. Determine Input Capacitor and DC Bus Voltage Range ...................................................... 9 C. Duty Cycle, Turns Ratio and CFSET Selection .................................................................... 10 D. Various Combinations of LP and RS for Required Peak Power .......................................... 11 E. Calculate Output Power within COMP Voltage Range ...................................................... 12 F. Estimating Transformer Size and Power Loss ................................................................... 14 G. Transformer Design .......................................................................................................... 16 4. EXPERIMENTAL VERIFICATION ................................................................................................... 19 4.1 Steady State ........................................................................................................................... 20 4.2 Over-load Protection ............................................................................................................... 20 4.3 Load Regulation...................................................................................................................... 22 4.4 Efficiency ................................................................................................................................ 22 REFERENCES: ................................................................................................................................... 23 AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 AN056 –PEAK POWER DESIGN FOR THE HFC0300 1. INTRODUCTION Peak power is defined as the amount of energy that exceeds the nominal rating for short specified durations (typically tens of milliseconds and up to seconds at the most).[1] Many applications require power supplies that can deliver high peak-to-nominal load ratios due to high start-up currents or sudden short-duration heavy loads. Therefore, a good alternative power controller allows the power system to deal with the worst-case short-duration peak current while providing good operating performance at nominal load. The HFC0300 is a power conversion IC with intelligent peak-power management technology that enables the system to stay within peak power constraints. The device also provides significant size and cost savings. This application note is intended for engineers designing AC-DC flyback power supplies using the HFC0300 for peak power applications. This note provides guidelines to help the engineer to quickly select key components and also complete a suitable transformer design. 2. HFC0300’S PEAK-POWER FEATURES HFC0300 is a variable off-time controller that uses an external capacitor connected to the FSET pin to set the frequency. It can also boost its frequency with increased loads. The variable off-time control scheme offers various advantages over traditional PWM-controlled power supplies. For instance, the feedback signal can boost the primary-side switching frequency and increase the current-limit threshold to transfer energy as appropriate to the load conditions to the power output. Since variable off time control only initiates a switching cycle when the system requires an energy transfer, the effective-average switching frequency under light-load conditions is much lower, which benefits efficiency performance. When the output power falls below a given level, the controller enters burst mode to further reduce the power loss at no load or light load condition. Figure 1 shows frequency variation against the COMP voltage. [2] Vfset Controlled by the COMP Voltage Minimum Frequency Pout Decrease IFSET=28µA Pout Increase Maximum Frequency Figure 1: COMP Voltage as a Function of the Switching Frequency AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 AN056 –PEAK POWER DESIGN FOR THE HFC0300 Additionally, reducing the frequency results in the peak current decreasing with the load to protect the transformer against mechanical resonance. Figure 2 shows the peak current vs. COMP voltage curve. The COMP voltage ranges from 0.9V to 3.2V. Peak current decreases when COMP voltage exceeds 2.1V. The part stops switching when the COMP voltage increases over the 3.2V threshold and resumes switching when the COMP voltage falls below the 3.1V threshold. Peak Current(V) Constant Burst Mode Peak Current Compression Peak Current 0.5 0.167 0.9 2.1 3.1 3.2 VCOMP(V) Figure 2: Peak Current vs. COMP Voltage In addition, the HFC0300 integrates a variety of protection features to minimize the external component count, such as internal VCC Under-Voltage Lockout (UVLO), Over-Load Protection (OLP), Over-Voltage Protection (OVP), Short-Circuit Protection (SCP), and Thermal Shutdown (TSD). The HFC0300 adjusts the output power by changing the frequency where peak power occurs at the maximum frequency. The COMP voltage drops to its bottom value at the meantime. Figure 3 plots the average switching frequency of a 60W nominal load using a 90W peak-load power supply with a low-line input (90V) and various distinct load conditions. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 AN056 –PEAK POWER DESIGN FOR THE HFC0300 90 80 Frequency(kHz) 70 60 50 40 30 20 10 0 0 20 40 60 Output Power(W) 80 100 Figure 3: Switching Frequency vs. Output Power The frequency can go as high as 80kHz at a 90W extreme peak load, and can go as low as 40kHz at a 60W nominal load, and drop further to 28kHz at half the nominal load. The high frequency under peak load conditions allows a minimal transformer core size. Therefore, for the HFC0300, the core size can be chosen for the nominal load condition to meet the thermal requirement, since the peak current is already at its maximum value under this condition. Consequently the increase in effective-switching frequency at peak load does not increase the core-flux density. On the contrary, traditional PWM controlled power supplies typically run at a fixed frequency of only 40kHz or less over the entire load range up to the maximum peak load. Therefore the transformer core size must be selected for the peak load condition to avoid saturation when the primary current increases to satisfy the peak load requirement. [3] 3. DESIGN METHOD FOR PEAK POWER 3.1 Current Solution The traditional design method initially determines the converter operation mode, such as CCM, BCM or DCM given low line input and peak load conditions. Then select the primary peak current and primary inductance accordingly. This kind of circuit delivers a much higher peak power than needed, which results in cost over-runs and big core sizes of the magnetic components because this method treats the peak power as continuous maximum power. However, the application only demands peak power for very short periods due to start up or a heavy pulse load. Typical peak-to-nominal ratio is usually PPEAK≥1.5PCONT., depending on the load configuration. The HFC0300’s high switching frequency allows for a smaller core to deliver the peak power, but the short duration prevents the transformer windings from overheating and reduces the heatsink requirements. If necessary, select a smaller transformer to reduce the winding current density. Ultimately, these features contribute to the HFC0300’s optimal use in applications that demand short duration, high-peak power, and low nominal power. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 AN056 –PEAK POWER DESIGN FOR THE HFC0300 3.2 Optimized Design Introduction An optimized design procedure requires specified peak and nominal powers. The peak power contributes to electrical stress, which is a deciding factor in selecting the device, while the nominal power determines the RMS rating selection. Take both peak power and nominal power into consideration when designing the transformer for power delivery at the minimum input line voltage— this may optimize the transformer and heatsink sizes. Furthermore, the optimization method in this application note also takes efficiency at nominal power into consideration. This section presents a design procedure as per the schematic of Figure 4. The peak power for the HFC0300 must be guaranteed when the frequency reaches its maximum value in any operation mode. From Figure 2, the following equation determines the switching frequency range based on CFSET and COMP voltage range. fS = 1 CFSET × VCOMP + 0.6μs 28 (1) The maximum frequency corresponds to 0.9V minimum COMP voltage and the minimum frequency corresponds to 3.1V maximum COMP voltage, which are constant values once the capacitor connected to the FSET pin is given. AN056 Rev. 1.0 12/30/2013 fS −MAX = 1 CFSET × 0.9 V + 0.6μs 28 fS −MIN = 1 CFSET × 3.1V + 0.6μs 28 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (2) (3) 7 AN056 –PEAK POWER DESIGN FOR THE HFC0300 Figure 4: Typical Application Usually, each specification has a pre-determined frequency range for nominal and peak load. The design target is to achieve the required peak power and good performance at nominal power. Equations (4) and (5) describe the power delivered by the power supply: In DCM mode: PDCM = 1 LPIP 2 fS 2 (4) In CCM mode: PCCM = VDC(MIN)NVO VDC(MIN) + NVO Ip − V NV 1 ( DC(MIN) O )2 2fSLP VDC(MIN) + NVO (5) Based on Figure 2, the peak current is ⎧ 0.5 VCOMP ≤ 2.1 ⎪R ⎪ S IP = ⎨ ⎪1.1993 − 0.333VCOMP ⎪⎩ RS AN056 Rev. 1.0 12/30/2013 (6) 2.1 < VCOMP ≤ 3.1 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 AN056 –PEAK POWER DESIGN FOR THE HFC0300 Where: • LP is the primary inductance, • IP is the primary peak current, • VDC(MIN) is the minimum input DC voltage, • VO is the output set voltage, • N is the turns ratio (primary/secondary), • RS is the current-sense resistance, • VCOMP is the COMP voltage. Substituting fS with fS-MAX can get the peak power values PPEAK-DCM and PPEAK-CCM. Basically, VDC(min) is determined by the AC input voltage and input capacitors, N is determined by the trade off between primary MOSFET’s and secondary Schottky diode’s voltage ratings. The other parameters are pre-determined, leaving LP and RS as the remaining key parameters in the power system design. However, given the numerous combinations of LP and Rs that can deliver the required peak power for a given maximum-frequency condition, selecting appropriate LP and RS values must account for the required peak power, good performance at nominal load, while minimizing cost and size. 3.3 Optimized Design Flow A. Predetermined Input and Output Specifications Determine the following input and output specifications first when designing a power supply with peak power profile: Input AC voltage range, VAC(MIN), VAC(MAX): for example 90VAC to 265VAC Input AC frequency, f: for example f=50Hz Output voltage and nominal/peak output power, VO, PNOM, PPEAK: for example VO=24V, PNOM=60W, PPEAK=90W Estimated efficiency, η: for example η=85% Estimate the power conversion efficiency to calculate the required input power. With the estimated efficiency, the nominal input power is: PIN = PNOM η (7) B. Determine Input Capacitor and DC Bus Voltage Range Typically, select the input capacitor (CIN) at around 1.5µF to 2µF per watt of input power. With the input capacitor chosen, the minimum input capacitor voltage at nominal load condition is obtained as: VDC(MIN) = 2(VAC(MIN) )2 − 2PIN τ1 CIN (8) Where τ1 is the input capacitor discharging time per cycle as shown in Figure 5. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 AN056 –PEAK POWER DESIGN FOR THE HFC0300 Figure 5: Input Capacitor Voltage Waveform The maximum input capacitor voltage is given as: VDC(MAX) = 2VAC(MAX) (9) C. Duty Cycle, Turns Ratio and CFSET Selection When the MOSFET is OFF, the input voltage (VDC) and the output voltage reflected on the primary side, appear across the MOSFET, as shown in Figure 6. Figure 6: Voltage Stress of Primary MOSFET and Secondary Rectifier Diode The maximum MOSFET voltage (VDS) is then: VDS = VDC(MAX) + N(VO + VF ) + VSPIKE −MOSFET k (10) Where VF is the rectifier diode’s forward voltage, k is the derating factor (typically 0.9), and VSPIKE-MOSFET is produced by the transformer’s primary leakage inductance and is typically around 60V. When the MOSFET turns on, the output voltage (VO) and the input voltage reflected on the secondary winding appear across the diode. The maximum diode voltage (VR) is then: VDC(MAX) VR = AN056 Rev. 1.0 12/30/2013 N + VO + VSPIKE−DIODE k www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (11) 10 AN056 –PEAK POWER DESIGN FOR THE HFC0300 Where the secondary parasitic inductance and capacitance causes VSPIKE-DIODE, which is typically around 20V. With a low-line input voltage and nominal load condition, the controller enters CCM. The maximum duty cycle is: DMAX = N(VO + VF ) VDC(MIN) + N(VO + VF ) (12) Based on equations (10) and (11), reducing N reduces the voltage stress across the MOSFET, but increases the voltage stress on the secondary-side rectifier diode. Therefore, the value of N is a tradeoff between MOSFET’s and diode’s voltage stresses. In addition, select a maximum duty cycle below 0.5 in order to avoid sub-harmonic oscillation that can limit N’s range. HFC0300 has Over-Load Protection (OLP) with a delay time relative to CFSET: τ DELAY = 74ms × CFSET 330pF (13) A very small CFSET can trigger the OLP before completing start-up under heavy-load conditions, so determine CFSET according to the load condition. In addition, keep the minimum frequency (fS-MIN) above 20kHz to avoid audible noise—select CFSET less than 446pF as per equation (3). D. Combinations of LP and RS for a Required Peak Power As described in section 3.2 Optimized Design Introduction there are multiple LP and RS combinations that can deliver the required peak power for a given maximum frequency (pre-determined by CFSET). For a given peak power, determining LP ultimately determines RS. The following example is based on the following conditions: (except LP, actual applications either provide the other parameters, or they can be calculated based on the previous-discussed design flow). • LP=200µH, • VDC(MIN)=95V, • VO=24V, • PNOM=60W, • PPEAK=90W, • η=85%, • N=3, • CFSET=330pF, • CIN=150µF For a given maximum frequency, different RS values result in different operating modes and deliver different peak power values. First, determine the operating mode (DCM or CCM) for a given RS. Then, calculate the peak power. Following calculations can determine the operation mode for a given RS. Given, PPEAK-DCM=PPEAK-CCM (from equations (4) and (5) with fS=fS-MAX), the root RBCM=0.228Ω. When RS<RBCM, the HFC0300 works in CCM; when RS=RBCM, it works in BCM; and when RS>RBCM, it enters DCM. Equation (14) describes the relationship between PPEAK and RS, and Figure 7 shows the curve. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 AN056 –PEAK POWER DESIGN FOR THE HFC0300 ⎧PPEAK −DCM PPEAK = ⎨ ⎩PPEAK −CCM RS ≥ RBCM RS < RBCM (14) Figure 7 shows clearly that a lower RS results in a higher PPEAK. At the same time, the operating mode switches from DCM to CCM when RS decreases. This example works in CCM at 90W peak power, resulting in RS=0.152Ω from equation (14). So, LP=200µH and RS=0.152Ω can deliver 90W peak power at the maximum frequency. CCM DCM PPEAK=90 PPEAK(W) 0.228 0.152 RS(Ω) Figure 7: Peak Power vs. Sense Resistor E. Output Power Calculation within the COMP Voltage Range Apart from achieving the peak power, the nominal power also figures into design optimization. For a given LP and RS pair, various COMP voltage results in different output power levels and operation modes. Finding the root from PDCM=PCCM with given LP=200µH, RS=0.152Ω and CFEST=330pF, then VCOMP-BCM=1.349V is obtained. If VCOMP<VCOMP-BCM, HFC0300 works in CCM; for VCOMP=VCOMP-BCM, it works in BCM; while for VCOMP>VCOMP-BCM, it is in DCM. Therefore, a 60W nominal load works in DCM mode while 90W peak load in CCM mode. Figure 8 shows the curve of the output power vs. COMP voltage for LP=200µH, RS=0.152Ω and CFSET=330pF. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 AN056 –PEAK POWER DESIGN FOR THE HFC0300 CCM DCM 90 72 PNOM=60 54 PO(W) 36 18 0 1.3491.515 3.1 VCOMP(V) Figure 8: Output Power vs. COMP Voltage (LP=200µH RS=0.152Ω) For a given LP, use the aforementioned calculation method to estimate the corresponding RS. Table 1 shows the various RS values for a given LP and the operation mode for the both peak and nominal loads: Table 1: Combinations of LP and RS for 90W Peak Power LP(µH) RS(Ω) Operation Mode @ PNOM=60W Operation Mode @ PPEAK=90W Curve # from Figure 9 100 0.114 DCM BCM #1 200 0.152 DCM CCM #2 300 0.171 BCM CCM #3 400 0.182 CCM CCM #4 500 0.19 CCM CCM #5 600 0.195 CCM CCM #6 700 0.199 CCM CCM #7 800 0.202 CCM CCM #8 Figure 9 shows the output power vs. COMP voltage curves for the various combinations of LP and RS. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 AN056 –PEAK POWER DESIGN FOR THE HFC0300 90 #6 72 PNOM=60 54 #4 #7 #5 #8 #3 #2 PO(W) #1 36 18 0 0.9 1.34 1.78 2.22 VCOMP (V) 2.66 3.1 BCM Point Figure 9: Output Power vs. COMP Voltage for Various LP and RS F. Estimating Transformer Size and Power Loss Although the listed combinations of LP and RS can deliver the required peak power, the transformer size and the power loss are not be optimized. The goal of the design is to get the optimized solution with both a small transformer for peak power delievery and low power loss at nominal load. Transformer Core Size Calculation Based on the AP rule for transformer core size calculation, estimate the core size with equation (15): Tsize = LPIPIPRMS LPIPRMS = BMAXK JK U 2BMAXRSK JK U (15) Here, RS determines the peak current by equation (6), where: • BMAX is the maximum-allowed flux density, which is usually 0.3T, • KJ is the current-density coefficient, usually 450A/cm2, • KU is winding factor, which is 0.2, • IPRMS is the primary RMS current which can be simplified as a constant value (1.1A under 60W nominal load condition—verified by calculation that the RMS current varies little and thus has little impact on core size). Power Loss Calculation (Electrical) The power loss is comprised of several parts (electrical only—magnetic loss not yet specified due to undetermined core size, type and material): the MOSFET conduction loss, the MOSFET turn-on loss, the MOSFET turn off loss, and the secondary-diode conduction loss. MOSFET Conduction Loss: AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 AN056 –PEAK POWER DESIGN FOR THE HFC0300 LPIP PMOS −CON−DCM = fs ∫ VDC(MIN ) ( VDC(MIN) t LP 0 D PMOS −CON−CCM = fS ∫ fS (IP − VDC(MIN)D 0 LP fS + )2 RDS dt VDC(MIN) t LP )2 RDS dt (DCM mode) (16) (CCM mode) (17) Where RDS is the ON resistance of the primary MOSFET. MOSFET Turn-On Loss: PMOS −ON−DCM = 0 (VDC(MIN) + NVO )(IP − PMOS −ON−CCM = (DCM mode) (18) VDC(MIN)D LP fS )τCROSS _ ON fS 6 (CCM mode) (19) Where τCROSS-ON is the overlapping time between the MOSFET voltage and current when it turns on. MOSFET Turn-Off Loss: PMOS−OFF = ( VDC(MIN) + NVO )IP τ CROSS −OFF fS (20) 6 Where τCROSS-OFF is the overlapping time between the MOSFET voltage and current when it turns off. Diode conduction loss: LPIP NVO S 0 N2 VO VDIODE (NIP − t)dt LP (DCM mode) (21) 1−D fS S 0 N2 VO VDIODE (NIP − t)dt LP (CCM mode) (22) ∫ PDiode −CON−DCM = f PDiode−CON−CCM = f ∫ Where VDIODE is the diode forward voltage drop. The total electrical power loss is the sum of the resulting values from the previous equations. Based on equations (15)-(22), calculate the transformer size and electrical power loss for various combinations of LP and RS. Figure 10 shows the plot of the final result . AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 AN056 –PEAK POWER DESIGN FOR THE HFC0300 6 9 8 4 -9 Size(x10 m ) 6 5 Power Loss(W) 5 7 4 3 4 3 2 Transformer Size 2 Power Loss 1 0 1 0 0 200 400 Lp(uH) 600 800 1000 Figure 10: Transformer Size and Power Loss (Electrical) vs. LP The curves show that lower LP results in smaller transformer. However, reducing the electrical power loss involves an optimized range of LP. The transformer size and power loss curve in Figure 10 shows that the best combination is LP=400µH and RS=0.18Ω (Choose the closest values in practice if the inductance and resistance values are not available) for an appropriate trade-off between power loss and transformer size. G. Transformer Design The last step is to design the transformer based on the selected LP and RS values. The core area product (AEAW) is the core magnetic cross-section area multiplied by the available winding window area, and can estimate the core size for a given application. The following is a rough estimate of AEAW(cm4) is:[4] AE A W = LPIPIPRMS BMAXK JK U (23) Where IPRMS is the primary RMS current under a 60W nominal load condition: ⎡ IP + Ivalley 2 1 ⎤ IPRMS = ⎢( ) + (IP − Ivalley )2 ⎥ D 2 12 ⎣ ⎦ (24) In this example, AEAW is around 4.82x10-9m4 based on equation (23). For traditional PWM control with a 40kHz fixed frequency (choose the HFC0300’s nominal load frequency for comparison), a 1.15mH primary inductor could deliver the same peak power with the same peak-current condition based on equation (5), and AEAW is 1.45x10-8m4 based on equation (23)—which is nearly three times the HFC0300’s optimized core size. Therefore, the transformer core size could be significantly reduced. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 AN056 –PEAK POWER DESIGN FOR THE HFC0300 For a given core size, equation (25) defines the minimum value of primary turns (NP) to prevent the core from saturating: NP = LPIP A EBMAX (25) The number of secondary winding turns (NS) is a function of N and NP as per equation (26): NS = NP N (26) The winding loss depends on the RMS current value and the length and the cross-sectional area of the wire, so select it to minimize the winding conduction loss. The primary-side RMS current is given by equation (24), and the RMS current on secondary side is given by equation (27): ⎡ IP + Ivalley 2 1 ⎤ ISRMS = N × ⎢( ) + (IP − Ivalley )2 ⎥ D 2 12 ⎣ ⎦ (27) Then equations (28) and (29) provide the the primary- and secondary-side wire sizes: SPRMS = IPRMS J (28) SSRMS = ISRMS J (29) Here, J is the wire current density, which is 450A/cm2 typically. Given the skin effect and proximity effect on the conductor, select a wire diameter of less than 2△d, where △d is the skin effect depth as determined by: Δd = 1 × 103 (mm) πfsμσ (30) Where μ is the magnetic permeability of the conductor which is usually 4πx10-7H/m, σ is the conductive of the wire which is typically 6x107S/m. Based on the determined wire size, check the window coefficient (winding area/total window area) for a sufficient margin (basically the ratio is 0.1-0.2). The following describes the transformer for this example: NP: NS: NAUX=50:15:8 with 400µH primary inductance. The core is EER28. The more detailed and specific wire structure is shown in Figure 11, Figure 12 and Table 2. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 AN056 –PEAK POWER DESIGN FOR THE HFC0300 1 N4 2 3 4 12 11 N1 N3 N2 9 8 5 PRI. SEC. WINDING START TEFLON TUBE Figure 11: Connection Diagram Pri. Side Sec. Side 2mm 2mm 3T N4 3T 3T N3 N2 1T N1 1T Figure 12: Winding Diagram AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 18 AN056 –PEAK POWER DESIGN FOR THE HFC0300 Table 2: Winding Order Tape(T) Winding Edge Tape (Pri.) Terminal (start-end) Edge Tape (Sec.) Wire Size (Φ) Turns (N) N1 2mm 3→2 2mm 0.33mm*2 25 N2 2mm 5→4 2mm 0.2mm*1 8 N3 2mm 11,12 → 8,9 2mm 0.33mm*7 15 N4 2mm 2→1 2mm 0.33mm*2 25 1 1 3 3 3 4. EXPERIMENTAL VERIFICATION To verify the design based on the procedure presented in this application note, we built and tested the circuit in Figure 13 for the given input/output conditions (Input: 90VAC to 265VAC; Output: 24V, nominal/peak load: 2.5A/3.75A). Figure 13:Schematic of 90W Peak Power Converter with HFC0300 AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 19 AN056 –PEAK POWER DESIGN FOR THE HFC0300 4.1 Steady State Figure 14 shows 60W nominal power with a low line input waveform: VCOMP VDS Figure 14: Norminal Load (60W) at Low Line Input (90VAC) Figure 15 shows 90W peak power with a low line input waveform : VCOMP VDS Figure 15: Peak Load (90W) at Low Line Input (90VAC) Both are in CCM. As the load increases from 60W to 90W, the frequency increases from 39kHz to 80kHz, while the COMP voltage drops from 2.0V to 0.98V, which is very close to the 60W/90W points in curve 4 (Lp=400µH Rs=0.18Ω) in Figure 9. This experiment verifies the accuracy of the theoretical calculations. 4.2 Over-load Protection When the output power just exceeds the 90W peak value, OLP triggers and the part enters hiccup mode as shown in Figure 16 and Figure 17. Figure 16 shows the dynamic output transient from 60W to 90W with 100ms duration, separately, and that the device can handle this required nominal power. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 20 AN056 –PEAK POWER DESIGN FOR THE HFC0300 VO IO Figure 16: 60W to 90W Transient at Low Line Input (90VAC) Figure 17 shows the output dynamic transient from 60W to 93W with 100ms duration, separately. It cannot sustain the 93W output for 100ms and the output voltage quickly drops to zero since OLP is triggered. Part enters hiccup mode at this time. This shows that even small margins need optimized transformer sizes for significant cost saving. VCOMP IO Figure 17: 60W to 93W Transient at Low Line Input (90VAC) AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 21 AN056 –PEAK POWER DESIGN FOR THE HFC0300 4.3 Load Regulation Figure 18 shows the load regulation at various input voltages. To guarantee 90W peak power at low line (90VAC), leave some power margin for high line inputs. OUTPUT VOLTAGE(V) 24.0 VIN=110VAC 23.9 23.8 VIN=220VAC 23.7 VIN=90VAC 23.6 VIN=265VAC 23.5 23.4 0 1 2 3 4 5 OUTPUT CURRENT(A) 6 Figure 18: Load Regulation 4.4 Efficiency Figure 19 shows the measured efficiency. Based on the efficiency curve, the efficiency exceeds than 85% with a load between 25% to 100%. 90.0 89.5 89.0 VIN=110VAC 88.5 88.0 87.5 87.0 86.5 86.0 VIN=220VAC 85.5 85.0 0 0.5 1 1.5 2 2.5 OUTPUT CURRENT(A) 3 Figure 19: Efficiency vs. Load AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 22 AN056 –PEAK POWER DESIGN FOR THE HFC0300 REFERENCES: [1]. “Understanding Peak Power,” TDK-Lambda, 2009. [2]. Henry Xu, “Flyback Converter Using Variable Off-time Controller—HFC0300,” MPS, AN043, 2011. [3]. “Peak Switch Design Guide,” POWERINTEGRATIONS, AN41. [4]. Lisa Dinwoodie, “Isolated 50 Watt Flyback Converter Using the UCC3809 Primary Side Controller and the UC3965 Precision Reference and Error Amplifier,” UNITRODE, AN165. [5]. “Applying FAN6747 to Control a Flyback Power Supply with Peak Current Output,” FAIRCHILD, AN6747, 2010. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN056 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 23

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