>85% Efficient 12 to 5 VDC Buck Converter

AND8291/D
>85% Efficient 12 to 5 VDC
Buck Converter
Prepared by: DENNIS SOLLEY
ON Semiconductor
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General Description
This switching regulator is based on a very flexible ”gated
oscillator or bust mode” architecture that can be used to
create step-down (buck), step-up (boost) and buck-boost
voltage regulators. The NCP3063 contains an internal
switch capable of up to 1.5 A but in applications requiring
higher current, this device can be configured as a controller
driving an external MOSFET.
This application note describes how the NCP3063 can be
configured as a buck controller to drive an external PFET
transistor to produce a cost effective, high efficiency 3 A
switching regulator. The NCP3063 has a wide input voltage
range up to 40 V which makes it attractive for industrial and
consumer applications such as LCD-TVs. The design
example illustrates a buck converter delivering 3 A at 5 or
3.3 V from a 12 V supply.
The block diagram of the NCP3063 controller is shown in
Figure1.
NCP3063
8
1
TSD
NC
Switch Collector
SET Dominant
R
Q
S
7
Comparator
+
Ipk Sense
2
R
Q
Switch Emitter
SET Dominant
S
+
0.2 V
Oscillator
6
3
Timing Capacitor
CT
+VCC
5
Comparator
+
-
1.25 V
Reference
Regulator
4
GND
Inverting Input
Figure 1. Block Diagram of the NCP3063
© Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 1
1
Publication Order Number:
AND8291/D
AND8291/D
Typical operating waveforms, including the timing ramp CT, are illustrated in Figure 2.
1
Feedback Comparator Output
0
1
IPK Comparator Output
0
Timing Capacitor, CT
On
Output Switch
Off
Nominal Output Voltage Level
Output Voltage
Startup
Operation
Figure 2. Typical Operating Waveforms
between the charge current and the discharge current is set
within the controller to be 1:6. This ratio creates a fixed duty
cycle DMAX of 6/7 or 0.86. The ramp circuit is modified
(also illustrated in Figure 3) by adding of an external current
source IFF to ICHARGE at the CT pin. This current source, in
the simplest case, is created by adding a feedforward resistor
between VIN and CT. (Additional information is available in
the application note AND8284.)
For detailed information regarding controller operation
refer to the NCP3063 data sheet. The essentials of the
control method can be observed in the waveforms of
Figure2. The output voltage is fed back to the inverting
input 5 of the comparator (Figure 1) via a resistor divider. If
the output is below the set point, the comparator “gates” a
series of clock cycles through the power switch. Control of
the output voltage is achieved by varying the average
number of “on cycles” to the number of “off cycles” in a
given time interval.
The transfer function (or gain) VOUT/VIN for a
conventional buck converter, neglecting circuit losses, is
given by the following equation:
BuckTransferFunction + D
ICC
ICHARGE
IFF
(eq. 1)
If the value for DMAX (0.86) set by the NCP3063 is
inserted into the above equation, the maximum gain is
determined.
MaximumAvailableGain + 0.86
VIN
IDISCHARGE
CT
(eq. 2)
This maximum gain value may be considerably more than
a particular application requires. For example, a typical
12V to 5 V buck application requires a gain of 0.42 and a
corresponding D = 0.42. Consequently the “gated
oscillator” operates at a small effective duty cycle,
delivering power to the load for a few switching cycles
before turning off for extended periods. The burst mode
frequency is low causing the converter's output ripple to be
high. The design may be optimized as follows.
The NCP3063 oscillator section consists of two current
sources; one charging, the other discharging the timing
capacitor CT, between two fixed voltage levels (Figure 3).
The levels are approximately 500 mV apart. The ratio
Figure 3. Current Sources Charging and
Discharging the Timing Capacitor CT
Adding an external current will reduce the time it takes to
charge the CT capacitor between the ramps's minimum and
maximum thresholds. The design equations relating to the
oscillator section are given below.
ȍ ICHARGE
T OFF + C T @ DV RAMPń ȍ I DISCHARGE
T ON + C T @ DV RAMPń
T S + (T ON ) T OFF)
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(eq. 3)
(eq. 4)
(eq. 5)
AND8291/D
D MOD + T ONńT S
(eq. 6)
F S + 1ńT S
(eq. 7)
The table also shows the change in normalized oscillator
frequency. Once an optimum duty cycle has been identified
and IFF selected, the value of CT can be ratio metrically
increased to reset the design frequency. This done, the
converter's design frequency remains constant over a wide
range of operating conditions.
Table 1 shows the corresponding reduction in duty cycle
DMOD as a normalized function of the charging and
discharging currents flowing into the timing capacitor CT.
Table 1. Variation of Duty Cycle
External Charging
Current
Internal Charging
Current
Internal Discharging
Current
Duty Cycle DMOD
Frequency FMOD
0
1
6
0.86
1.00
1
1
5
0.71
1.43
2
1
4
0.66
1.71
3
1
3
0.50
1.71
4
1
2
0.29
1.43
5
1
1
0.14
0.86
Variation of duty cycle DMOD and frequency FMOD as a function of normalized external current, charging the timing capacitor CT.
Practical Example
Figure 4 is a schematic of the buck converter. The input is
a nominal 12 V while the output is regulated to 5 V. The
VIN = 12 V
NTMS5P02R2
Q1
R1
0.05
R4
3.76 k
NCP3063 is used as the imbedded controller driving an
external PFET switch.
R2
1k
L1
22 mH
D3
MBRD320
Q2
VOUT = 5 V
C2
10 mF / 6V3
C12
220 mF / 6V3
MMBT3904TT1G
D1
U1
NCP3063
C1
C11
220 mF / 25 V
D2
NC
SWC 1
ISENS
SWE 2
VCC
CT 3
6
CMPINV GND
5
4
R6
RTN
MMSZ5V6T1
8
7
10 mF /
25 V
R5
1.24 k
MMSD914T1G
15 k
C3
C4
3.9 nF
2.2 mF / 25 V
RTN
Figure 4. Schematic of Buck Topology
- charging current is 260 mA @ 5 V VCC / 25°C and
280ĂmA @ 40 V VCC / 25°C.
- discharging current is 1550 mA @ 5V VCC / 25°C and
1700 mA @ 40 V VCC / 25°C.
Assume we chose to operate at a switching frequency of
approximately 200 kHz. Then TS is 5 mS and TON is 2.5 mS
giving the required modified duty cycle DMOD of 0.5.
Rearranging Equation 3, a value for the timing capacitor CT
is obtained:
The selection of the timing capacitor CT (C4) and
feedforward resistor R6 is discussed next.
Assuming no circuit losses, the transfer function or gain
of this application is 0.42 and is also 0.42. Referring to
Table1, a 3:1 ratio for the external charging current to
internal charging current would generate a modified duty
DMOD of 0.5. This is a good starting point.
The nominal charge and discharge currents for the
NCP3063 are listed below:
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AND8291/D
CT + ń
ȍ ICHARGE @ TONńDVRAMP
The value of R6 is selected as follows. Assume the
average amplitude of the ramp waveform is 0.9 V. We
require an external charging current IFF of 3 x 260 mA, hence
R6 equals (12 V - 0.9 V) / 780 mA or 14.2 kW. The nominal
value selected for R6 was 15 kW
(eq. 8)
Substituting values of ∑ICHARGE of 4 x 260 mA and
ΔVRAMP of 0.6 V into Equation 8, gives a nominal value of
CT as 4.3 nF. The nearest standard value for CT is 3.9 nF.
Figure 5. Ramp Waveform CT = 3900 pF, TS = 4.88 mS
With the values selected the observed ramp was captured
in Figure 5. The measured values are given below.
continuous conduction mode, the maximum switch current
and voltage ratings of the MOSFET must be considered. A
20 V, 5 A, 26 mW PFET such as the NTMS5P02 meets our
criteria with margin for de-rating. For a smaller package
footprint, the NTHS5441T1G PFET could also be an option,
depending on output current and thermal considerations.
The RDS(on) and total gate charge Qg curves for
ONSemiconductor's NTMS5P02R2 P channel MOSFET
are shown in Figures 6 and 7.
TON = 2.10 mS TS = 4.88 mS FS = 205 kHz
ΔVRAMP = 0.54 V ΔVAVG = 0.94 V
DMOD = 2.1 / 4.88 = 0.43.
The experimental duty cycle is close to our actual design
requirement of DMOD = 0.42.
Selection of External Transistor Q1
-VGS, GATE-TO-SOURCE VOLTAGE (V)
0.05
TJ = 25°C
VGS = -2.5 V
0.04
VGS = -2.7 V
0.03
VGS = -4.5 V
0.02
0.01
2
4
6
8
-ID, DRAIN CURRENT (A)
10
5
-VGS
3
Q1
12
Q2
2
8
1
ID = -5.4 A
TJ = 25°C
0
4
16
8
12
20
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Qg vs. VGS NTMS5P02R2
Figure 6. RDS(on) vs. Drain Current ID NTMS5P02R2
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16
-VDS
0
12
20
QT
4
-VDS, DRAIN-TO-SOURCE VOLTAGE (V)
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Given the design requirements for a 12 V input and 3 A
output buck converter running with low ripple current in
4
0
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AND8291/D
and R2, illustrated in the schematic (Figure 4) provides a fast
turn off for the PFET Q1.
The turn on/off behavior of the external PFET Q1 is
determined as follows. When the internal switch within the
NCP3063 turns “on”, the gate charge for Q1 is provided by
current flowing from VIN via D1 and D2 to ground return.
The positive voltage across D1 creates a reverse bias
condition across Q2's base emitter junction. Q2 remains in the
off state until the internal switch in the NCP3063 is itself
turned “off”. At this time, current flowing through resistor R2
is diverted to provide Q2 base current. Q2 conducts until Q1's
gate charge is neutralized.
The conduction loss PQ1 is given by Equation 9.
P Q1 + ńI OUT @ R DS(on) @ D MOD
2
(eq. 9)
PQ1 = 32* 26 mW * 0.43 = 101 mW
A 5.6 V zener diode D2 (Figure 4) is used to drop the gate
drive voltage VGS below VIN
The gate power PG required to switch the FET channel on
and off is given by:
PG + QG @ VG @ FS
(eq. 10)
For VGS = 4.5 V, the gate charge QG (from Figure 6) is 20nC
PG = 20 nC * 4.5 V * 200 kHz = 180 mW
The gate drive waveform is captured in Figure 8. The
network consisting of a small signal NPN transistor Q2, D1
Figure 8. High Side Gate Drive for PFET Q1 with Clock Ramp
Selection of Output Inductor L1
output inductor value is 25 mH. A 22 mH inductor would
meet our design objective and is commercially available
from several vendors. For example, part number
SLF12575T-220M4R0 is a 22 mH inductor from TDK with
a winding resistance RW of 26 mW and rated DC current of
4A. The winding loss PL1 in the output inductor is given by
the equation,
The value selected for L1 determines the AC ripple current
in the inductor as well as the output current boundary
between discontinuous conduction mode (DCM) and
continuous conduction mode (CCM) operation.
The ripple current ΔIL1 flowing in the output inductor IL1
is calculated from the standard flux equation
DI L1 + (V IN * V OUT) @ D MOD @ T SńL 1
(eq. 11)
P L1 + I OUT 2 @ R W
Since CCM was selected to keep the peak current to a
minimum, a peak ripple of 20 % of the output current (3 A)
is our design criteria, requiring ΔIL1 to be 0.6 A. Also (VIN
- VOUT) = 7 V, DMOD = 0.43 and TS = 5 mS, so L1 may be
determined by substitution into equation 11. The required
(eq. 12)
PL1 = 32 A2 * 26 mW = 234 mW
By employing the feedforward technique, the maximum
flux (VmS) the component “sees” has been reduced. Being
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AND8291/D
able to selecting a lower value for L1 reduces the winding
resistance RW, improving converter efficiency.
Small value MLCC capacitors in 805 and 1206 SMD
packages can be an alternative to electrolytic or tantalum
capacitors. These MLCCs have extremely low ESR (2mW)
and ESL (100 nH) parasitic values and so individually or in
parallel combinations can form the “perfect” lossless
capacitor when used for filtering at mid to high switching
frequencies.
For example if C1 = C2 = 10 mF, ΔIL1 = 0.6 A and DMOD
= 0.43, the peak to peak voltage ripple ΔVC across the input
and output of the converter are 130 mV and 171 mV
respectively. However as the NCP3063 controls the output
voltage by gating the oscillator on and off, additional
electrolytic or tantalum capacitances C11 and C12 are
required at the input and output to filter these lower
frequencies.
Selection of Freewheel Diode D1
Figure 9 shows the forward drop of the MBRD320 series
of SWITCHMODEt power rectifiers in a DPAK surface
mount package.
IF, INSTANTANEOUS FORWARD CURRENT (A)
10
TJ = 25°C
150°C
125°C
Current Limit
The NCP3063 has a peak current limit sense circuit, set by
connecting a sense resistor R1 (Figure 4) between pins 7 and
8 of the controller. The reference voltage for the current limit
function is nominally 200 mV so selecting a 50 milliohm
resistor for R1 allows the converter to operate above 3A
before current limit protection is activated. The power loss
in the sense resistor is 32 * R1 or Ps = 450 mW.
75°C
1
Bias Current
The maximum bias current to power the NCP3063 is
7mA. Bias power PB is 84 mW.
0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VF, INSTANTANEOUS VOLTAGE (V)
Loss Budget
Figure 9. Forward Drop of MBRD320
PFWD = 3.0 A * 0.4 V * 0.43 = 0.52 W
Summing the theoretical losses for Q1's conduction and
gate drive, inductor winding, freewheel diode , current sense
and bias power, we obtain a loss budget of 101 mW
+180mW + 234 mW + 520 mW + 450 mW + 84 mW or
1.57W, neglecting hysteresis losses in the inductor and esr
losses in the input and output capacitors. The converter's
maximum theoretical efficiency is 15/16.57 or 90.5%.
Selection of Input and Output Capacitors
Experimental Results
The input and output voltage peak to peak ripple across C1
and C2 are given by the equations below:
The efficiency of the buck converter at 5 V and 3.3 V
output is shown in Figure 10. The 5.0 V output data is in
good agreement with the calculated loss budget above.
As can be seen from Figure 9, the typical forward drop
VFWD at 3.0 A is 0.4 V at 75°C. The conduction loss PFWD
for the free wheel diode is given by the equation:
P D + I OUT @ V D @ (1 * D MOD)
(eq. 13)
DV C1 + DI L1 @ D MOD @ T SńC1
(eq. 14)
DV C2 + DI L1 @ (1 * D MOD) @ T SńC2
(eq. 15)
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AND8291/D
BUCK CONVERTER EFFICIENCY
100
5.0 V
EFFICIENCY (%)
90
3.3 V
80
70
60
50
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT AMPS (A)
Figure 10. Measured Efficiency Data
The waveforms across freewheel diode D3 and ramp
capacitor C4 are illustrated in Figure 11 at the full load
condition of 5 V and 3 A. By reducing the duty cycle to
DMOD, the gated oscillator operates in a near continuous
mode, providing drive pulses every clock cycle.
Figure 11. Voltage across freewheel diode D3 and ramp capacitor C4
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AND8291/D
Figure 12 illustrates the output ripple, under the same test
condition, together with the switch node (D3) for reference.
Note the ripple frequency is 52 mV p/p and approximately
one third of the converter's 200 kHz clock frequency.
Figure 12. Output Ripple (C2) referenced to switch node (D3)
Conclusion
to be designed for lower stress. Input capacitors, output
capacitors, inductor, switches and diodes can all benefit
from the DMAX reduction. In the case of a 12 V to 5 V buck
converter, the selection criteria of each component is
discussed and experimental data and waveforms presented.
By summing an external current source into the CT pin of
the NCP3063, it is possible to optimize the open loop gain
of buck, boost or buck boost topologies for any given
application. Reducing the controller's maximum duty cycle
of 0.86 to a lower value DMOD allows the power components
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