A 30 W Power Supply Operating in A Quasi-Square Wave Resonant Mode

AND8129/D
A 30 W Power Supply
Operating in Quasi−Square
Wave Resonant Mode
Prepared by: Christophe Basso
ON Semiconductor
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APPLICATION NOTE
INTRODUCTION
230
Quasi−Square Wave Resonant converters, often noted QR
converters, offer an elegant means to make Flyback supplies
look more friendly on the Electro−Magnetic Interference
(EMI) point of view. By delaying the ON switching event
until the drain−source voltage has decayed to a minimum,
switching losses are reduced and rising slopes lose their
stiffness. Designers get an immediate benefit from this
configuration since the MOSFET runs cooler and the EMI
input filter becomes easier to implement. Designing QR
Switch−Mode Power Supplies (SMPS) requires some
attention but is not an area dedicated to experts only.
You will discover through the following lines how new
ON Semiconductor solutions can help you to quickly turn
your quasi−resonant project into a working device.
Ip ·
170
Lf
Ctot
110
50
−10
1.69U
1.73U
1.77U
1.81U
1.85U
Figure 1. A Truly Resonating Vds Signal on a
Quasi−Resonant Flyback Converter
What is Quasi−Resonance?
The main problem with this technique lies in the very high
voltage generated at the switch opening. Most of the time,
these resonant offline designs require around 1.0 kV BVdss
MOSFETs whose price is clearly incompatible with high
volume markets. As a result, designers orientate their choice
toward another compromise called quasi−square wave
resonant power supplies.
The term quasi−resonance is normally related to the
association of a real hard−switching converter and a
resonant tank. While the operation in terms of control is
similar to that of a standard PWM controller, an additional
network is added to shape the variables around the
MOSFET: current or voltage. Depending on the operating
mode, it becomes possible to either switch at zero current
(ZCS) or zero voltage (ZVS). Compared to a conventional
PWM converter, a QR operation offers less switching losses
but the RMS current circulating through the MOSFET
increases and forces higher conduction losses. However,
one of the main advantage in favor of the quasi−resonance
is the reduced spectrum content either conducted or radiated.
True ZVS quasi−resonance means that the voltage present
on the switch looks like a sinusoidal arch. Figure 1 shows
how such a signal could look.
 Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 0
Quasi−Square Wave Resonant Converters
As we saw, true resonant operation hampers the MOSFET
selection by imposing a high voltage at the switch opening.
If we closely look at the standard hard−switching waveform
(Figure 2), we can see that there exists a time where the drain
voltage gets minimum. This occurs just after the core reset.
1
Publication Order Number:
AND8129/D
AND8129/D
1
2 · · Lleak · Ctot
Drain Voltage
Core is Reset
1
2·
Vds is Minimum
Lp · Ctot
Ip
Drain Current
Figure 2. Hard−Switching Waveforms in Discontinuous
Conduction Mode (DCM)
transformer via the coupling flux. However, the leakage
inductance, which models the coupling between both
transformer sides, reverses its voltage and imposes a
quickly rising drain voltage. The slope of this current
From Figure 2, it is possible to imagine a controller that
turns a MOSFET ON until its current grows−up to the
setpoint to turn it off and then waits until the core reset is
detected (usually via an auxiliary winding) to reactivate this
transistor. As a result, the controller does not include any
standalone clock but only detects the presence of events
conditioned by load/line conditions: this is a so−called
free−running operation. Converters based on this technique
are often designated as Self−Oscillating Power Supplies
(SOPS), valley switching converters, etc.
Oscillations origins can be seen from Figure 3
arrangement where L−C networks appear. Depending on the
event, two different configurations are in play:
• At the switch closing, the primary current crosses the
primary inductance but also the leakage inductance,
Lleak. When the turn−on time expires, the energy
stored in Lp is transferred to the secondary side of the
is
Ip
(eq. 1) where Ctot lumps all capacitances
Ctot
surrounding the drain node: MOSFET capacitors,
primary transformer parasitics but also those reflected
from the secondary side etc. As a result, Lleak and
Ctot form a resonating network of natural frequency
1
(eq. 2). The maximum drain
2 · · Lleak · Ctot
voltage can then be computed using the characteristic
impedance of this LC network.
Vds max Vin 1 · (Vout Vf) Ip ·
N
Leak
Ctot
700
Rp
1:N
+
Lp
500
1
⋅ (Vout + Vf )
N
1
⋅ (Vout + Vf )
N
t=0
−
e
Rp
⋅t
2⋅Lp
Vout
Vin
300
Lleak
+
Vin
100
Drv
Ctot
tvalley
Vds
Multiple valleys…
−100
1.005M
Figure 3. A Typical Flyback Arrangement
Unveils Two Different Resonating Networks
1.015M
1.025M
1.035M
1.045M
Figure 4. A Typical Flyback Ringing
Waveform Occurring at the Switch Opening
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2
(eq. 3)
AND8129/D
• When the transformer core resets, primary and
Vin is the input voltage, Vf the diode’s forward drop and
N, the Ns:Np turn ratio.
secondary currents drop to zero: the secondary diode
stops its conduction and the reflected voltage on the
primary naturally dies out. From eq. 3, this implies that
the terms after Vin all collapse to zero and Vds tends
toward Vin. However, the transition would be brutal in
the lack of a resonating network, this time made by Lp,
the primary inductance, and nearly the same Ctot as
before. As you can imagine, a sinusoidal ringing takes
place, damped by the presence of ohmic losses (DC +
AC resistance of the primary winding modeled by Rp).
The drain−source shape rings as the below formula
details:
Vds(t) Vin 1 · (Vout Vf) · e−·t
N
· cos(2 · · fprim · t)
with: 1
2··
We can see from Figure 4 that the drain is the seat of various
voltage drops when going down the ringing wave. These drops
are called “valleys”. If we manage to switch the MOSFET right
in the middle of these valleys, we ensure minimum turn−on
losses, particularly those related to capacitive dissipation:
Pavgcap 1 · Ctot · Vds2 · Fsw (eq. 7) →0. Thus, quasi−
2
square wave operation or valley switching, will imply a
reactivation of the switch when Vds is minimum. As various
figures portray, this occurs some time further to the
transformer core reset. By implementing this method, we
build a converter which naturally exhibits a variable
frequency operation since the reset time depends upon the
input/output operating conditions. Figure 5 shows a typical
shot of a quasi−square wave converter.
(eq. 4)
Rp
(eq. 5) (the damping factor), fprim =
2 · Lp
Lp · Ctot
(eq. 6)
(natural ringing frequency),
Ipeak
S = N . (Vout + Vf) / Lp
S = Vin / Lp
ON
OFF
Ip = 0
1st Valley
0
Figure 5. A Typical Drain−Source Shot of a
Quasi−Square Wave Converter
Figure 6. The Primary Inductance Current
is Made of Two Different Slopes
(here a restart occurs on the second one)
As one can see, the total period is made of different events,
where the core is first magnetized (Ton), then fully reset
(Toff) and finally a time (Tw) delay is inserted to reach the
lowest value on the drain. Let us look at how the frequency
moves by respect to the input/output conditions.
For the Tw event, which is one fourth of the natural ringing
frequency given by equation 4, we will compute the
derivative of equation 4 and null it to find its minimum:
Evaluating the Free−Running Switching Frequency
Which gives a result of:
d(Vin e(−·t) · cos(2 · · fprim · t))
0 (eq. 10)
dt
The free−running frequency can be evaluated by looking
at Figure 6, where the primary current (circulating in the
primary inductance) is depicted. From the definition of the
various slopes, we can express the first two events, Ton and
Toff quite easily:
ton toff Lp
· Ip
VinDC
Lp
Np
· (Vout Vf)
Ns
Tw 1 1 ·
2 · ft 2
2 · · fprim
· fprim
(eq. 11)
However, this result is not very practical because of its
inherent complexity. If we observe equation 10, we can see
that the minimum is reached when the term
cos(2 · · fprim · t) equals −1. Otherwise stated, we can
solve t for which the cosine is null or the full product equals
(eq. 8)
· Ip
tan
(eq. 9)
. This gives: Tw http://onsemi.com
3
1
·
2 · fprim
Lp · Cp
(eq. 12)
AND8129/D
However, this result is valid only for low damping
coefficient, that is to say, e−·t 1. Experience shows that
it is good enough for the vast majority of cases.
As a result, the final switching period is computed by
summing up all these sequences and introducing the input
power expression:
Tsw Ton Toff Tw
1 VinDC Ton Toff Tw Ip · Lp ·
1
2
Pin Pout
2 · Lp · Ip · Fsw
from eq. 15, Ip 2 · Pout
· Lp · Fsw
1 1 Tw Lp · Ip2 · VinDC
Pout · 2
Vreflect
Ip (eq. 14)
Tw = · Lp · Cp
(eq. 15)
the converter efficiency
Pout the output power
Vout and Vf, respectively the output voltage and the rectifier
drop @ Id = Iout
Lp the primary inductance
(eq. 16)
(eq. 16a)
with:
Vreflect =
· Lp · Cp 1
Fsw
· (Vout Vf)
1
Np
Ns
Now, plugging Fsw (eq. 14) in eq. 16, gives:
Ip · Lp ·
(eq. 13)
Stating that Lp x Pout = A:
Np
· [Vout Vf]
Ns
A · Vreflect A · Vin A · (A · Vreflect2 2 · A · Vreflect · Vin A · Vin2 2 · · Vin2 · Vreflect2 · Tw)
( · Lp · Vin · Vreflect)
From equation 16, one can then compute the switching
frequency using the calculated peak current:
Fsw 2 · Pout
Lp · Ip2
(eq. 17)
Fsw (eq. 18)
1
Lp · 2 · Pout( · (Vin · (N · (VoutVf))))2
N · (VoutVf)Vin
(eq. 19)
Entering equation 18 into a spreadsheet and plotting Fsw
versus various parameters (Vout, Iout etc.), it gives an idea
about the high frequency variability of the system. Figure 7
and Figure 8 respectively plot Fsw in function of the input
voltage and the output current for a given application.
However, equation 17 is not very practical since it
involves Lp, what we are actually looking for. It can
certainly be used to discover the operating peak current from
known inductance and capacitor values but neglecting Tw,
offers a simpler formula that can be used as first frequency
iteration (e.g. to feed a Spice simulator for instance):
7*104
2*105
6*104
1.5*105
f(Po)
f(VinDC)
5*104
4*104
1*105
3*104
5*104
2*104
1*104
100
150
200
250
300
350
400
0
0
VinDC
20
40
60
80
100
Po, OUTPUT POWER (W)
Figure 7. Frequency Variations for a 100 W SMPS
Operated from Universal Mains
Figure 8. Frequency Dependency with Load
at a Given Input Voltage (100 V)
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AND8129/D
3.5
Ip(VinDC)
3
2.5
2
1.5
100
150
200
250
300
350
400
VinDC
Figure 9. Peak Current Variations for a 100 W Output
Power with Different Line Voltages
A Quiet EMI Signature
Manipulating sinusoidal (or close−to) variables always
offer a narrower spectrum content compared to
hard−switching systems. Figures 10 and 11 depict the
conducted EMI signature of two systems operated at the
same point but implementing different switching
techniques.
Figure 10. A soft−switching approach reduces the
energy content above 1.0 MHz . . .
Figure 11. . . . while a hard−switching system
generates a lot of noise in this portion
Detecting the Core Reset Event
Since the MOSFET is reactivated at the lowest drain
level, the classical Coss capacitor discharge at the switch
closing is non−existing and the very narrow peak current
has gone (also this peak is often confusing the
current−sense comparator when it is really energetic, even
sometimes despite the presence of the LEB circuitry). As
a result, Quasi−square wave converters are recommended
where the Switch−Mode Power Supply (SMPS) needs to
operate close to Radio−Frequency section, e.g. Set Top
Boxes, TV sets, etc.
Core reset detection is usually done via a dedicated
auxiliary winding whose voltage image is directly linked
to the transformer flux by Vaux N ·
d
(eq. 20) .
dt
Depending on the controller device, the polarity of the
observed signal must fit its detection circuitry. In
ON Semiconductor NCP1205, this polarity should be of
Forward type, that is to say, when the MOSFET opens, the
auxiliary voltage (actually the Flyback level) dips below
ground and stays there, safely clamped at –0.7 V, until the
core reset occurs. Figure 12 gives an example of a
demagnetization signal given by an auxiliary winding wired
in both types.
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AND8129/D
20.0
10.0
0
−10.0
−20.0
−N.Vin
20.0
10.0
N.Vin
Flyback operation
Forward operation
65mV
0
−10.0
−20.0
Leakage contribution
Watch out for possible re−start!
Figure 12. Core Reset Detection Signal Coming From Either
a Forward or Flyback Winding
fixed to 4.0 A. It means that the overcurrent condition exists
as soon as the output load slightly increases, perhaps to
120 W, which is what was defined with a maximum peak of
4.0 A. Now, if you run the converter at high line, e.g.
350 VDC, the peak current will decrease, as shown by
Figures 9 thru 14, down to 1.8 A. As a result, you still have
a dynamic of 2.2 A to go before hitting the 4.0 A maximum
current trip point. The SMPS can thus theoretically deliver
up to 220 W before it actually trips. To overcome this
problem, you can wire a resistor between the Vcc and the
current sense pin since, in forward polarity,
Operating the auxiliary winding in Forward offers various
advantages as the use of the variable Vcc level to introduce
overpower compensation. Also the controller is always
operating (supplied) whatever the secondary output
conditions. Figure 14 shows a possible way to do that.
Please note the presence of a small RC filter necessary to
a) introduce a time delay after the core resets (and thus
activate the MOSFET right in the minimum of the valley
wave) b) to filter out any leakage contribution that could
adversely restart the controller at a higher switching
frequency (see Figure 12 evidence).
Overpower compensation is there to avoid a larger over
current trip point at high−line compared to low−line
conditions. For instance, suppose that the maximum peak
current at low line (100 V) would be 3.3 A to pass 100 W and
that your maximum peak current (given by the sensing
element and the internal clamping setpoint, usually 1.0 V) is
Vcc Naux · VinDC (eq. 21) which is a direct image of
Np
the mains. As a result, Vcc moves with the high−voltage rail
and offsets the current sense reading, offering a natural, low
power, input feedforward.
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AND8129/D
Demag
Rlimit
R
C
HV
Max Ip
Vcc
Aux
+
Low Line
Operation
+
Vout
Overpower
Max Ip
Drv
CS
High Line
Operation
1k
Figure 13. Quasi−resonant applications impose
different operating peak current depending on
the input line.
Figure 14. Wiring the auxiliary in forward mode offers the
ability to build an inexpensive overpower compensation
since Vcc aux. moves with the input voltage.
Care should be taken however, to not inject too much over
power level into the CS pin otherwise it may affect the VCO
operation.
In some applications, it is difficult to cope with a variable
auxiliary level and a Flyback option is better.
The NCP1205 Quasi−Resonant Controller
HV
Vcc
Aux
+
Demag
By adding a second diode, it becomes easy to wire the
auxiliary winding in Flyback mode, but still offering a core
reset signal in the Forward polarity. Figure 15 offers an
example, where the demagnetization signal undergoes a
high−frequency filtering via a RC network.
+
Rlimit
This NCP1205 available in DIP8, DIP14 and SO−16,
offers many features that make it the right candidate in
quasi−resonant applications:
• Full Quasi−Square Wave Resonant Operation: By
detecting the end of the transformer core demagnetization
to initiate a new cycle, the NCP1205 ensures drain−source
valley switching or QR operation. Furthermore, due to
comprehensive logic circuitry, the device jumps between
the valleys as the built−in VCO starts to decrease the
switching frequency. As a result, Electromagnetic−
Interference (EMI) are reduced and turn−on losses are
virtually null.
• Voltage−Controlled Oscillator: An internal VCO
takes over as soon as the free−running frequency hits a
maximum user adjustable value. As the output power
demand further diminishes, the switching frequency is
naturally reduced to ensure a better efficiency at light
loads.
Vout
R
C
Drv
CS
Rsense
Figure 15. Wiring the Winding in Flyback Mode is
also possible with the NCP1205
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AND8129/D
• Low Standby Power: If SMPS naturally exhibits a
•
•
•
•
•
• External MOSFET Connection: By leaving the
good efficiency at nominal load, they begin to be less
efficient when the output power demand vanishes. By
smoothly reducing the number of switching cycles per
second, the NCP1205 drastically reduces the power
wasted during light load conditions. In no−load
conditions, the NCP1205 allows the total standby
power to easily reach and exceed the next International
Energy Agency (IEA) recommendations.
Short−Circuit Protection: By permanently monitoring
the feedback line activity, the IC is able to detect the
presence of a short−circuit, immediately reducing the
output power for a total system protection. Once the
short has disappeared, the controller resumes and goes
back to normal operation. For given applications, you
can easily disconnect this protective feature. This
short−circuit detection is independent from the auxiliary
level, hence a lose coupling between auxiliary and
power windings is not a problem.
Overvoltage Protection: By continuously checking its
own Vcc rail, the NCP1205 can safely go into latch−off
phase when the operating voltage exceeds 36 V. In
Forward winding applications, this options lets you also
protect the design against transient mains over voltages.
For application where an adjustment is necessary, the
DIP14 versions pins out the dedicated comparator input
to let you select the protection level of your choice.
Large Supply Range: Battery charger applications
require that the controller can still control the output
current when the output voltage is close to zero (e.g. a
discharged battery). This is called Constant−Current/
Constant−Voltage (CC−CV) operation. To allow the
controller self−supply when the output voltage disappears,
one needs to wire the auxiliary winding in the Forward
mode. However, most of today’s primary side controllers
have difficulty to cope with a Forward auxiliary winding
operated on a universal mains because of the large voltage
dynamics it implies. Fortunately, by authorizing 7.0 V
through 36 V operation, the NCP1205 eases the designer
task on the self−supply side.
Low Output Ripple in Standby: Some loads are
sensitive to the ripple present on the output. This is
the case for Li−Ion batteries where a clean voltage
is required to ensure the longest service. Standard
hysteretic controllers produce un−acceptable output
ripple. By smoothly reducing the operating frequency,
the NCP1205 generates a lower ripple when entering
the standby mode.
No Acoustic Noise While Operating: Instead of
reducing the switching frequency at high peak currents,
the NCP1205 waits until the peak current demand falls
below a fixed 1/3rd of the peak maximum limit. As a
result, frequency reduction takes place without having a
singing transformer. You can thus select cheap magnetic
components free of noise problems.
external MOSFET external to the IC, you can select
avalanche proof devices which, in certain cases (e.g.
low output powers), let you work without an active
clamping network. Also, by controlling the MOSFET
gate signal flow, you have an option to slow down the
device commutation, therefore reducing the amount of
ElectroMagnetic Interference (EMI).
• SPICE Model: A dedicated model that lets you run
transient cycle−by−cycle simulations is available to
verify your theoretical design. Ready−to−use templates
can be downloaded in OrCAD’s PSpice and INTUSOFT’s
from ON Semiconductor web site, NCP1205 related
section.
Complete details regarding the implementation of the
NCP1205 are given in the application note AND8043.
A 30 W Power Supply Design Using the
Quasi−Resonant Approach
Pout nominal = 30 W
Vout = 16.8 V
Universal input voltage = 90–265 VAC
Vdc min ≈ 100 VDC (including losses and ripple)
Vdc max ≈ 370 VDC
Short−circuit protection
Standby power less than 300 mW at no−load
The design of a quasi−resonant converter featuring low
standby power requires the understanding of several
parameters before calculating anything:
1. Do we need to ensure true Zero Voltage Switching
(ZVS) operation over a large operating input
range?
2. If we ensure high switching frequency at
maximum power and low mains, while it
minimizes the magnetics, the frequency foldback
will eventually take place at higher input voltages.
3. At what peak current level do we authorize the
frequency foldback to avoid acoustical noise in the
transformer?
Answer 1:
Yes, because we will shape the drain−source voltage
(especially at the switch opening) to be as smooth as possible
to a) soften the EMI signature b) wire a large resonating
capacitor whose losses should be minimized (see eq. 7)
c) due to b, we will save a costly RCD clamping network. As
a result, we will reflect as much as we can, taking into
account a 800 V BVdss MOSFET and higher secondary
rectifier losses (peak and RMS secondary currents go up).
We have selected a turn ratio of 16.6 who gives a reflected
voltage of 288 V. The drain stress at high line without
leakage, is thus: (265 x 1.414) + 288 = 662 V, which gives
room for the leakage effects. Please remember that the best
is to reflect the maximum voltage from the secondary side,
best case being Vreflect = N x (Vout + Vf) = Vin. But in that
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AND8129/D
generate burst of pulses to drive the MOSFET. The
discontinuity associated with the burst sequence is more
favorable to trigger mechanical resonances compared to
evenly spaced pulses. Suppose that a 550 mA peak current
is offering the best value with your transformer. Since the
1205 folds back at 30% of the maximum primary current,
you will select a maximum peak current of 1.0 V/1.65 A or
an Rsense of 0.6 . Iterations using the dedicated Excel
spreadsheet will therefore help to select the right primary
inductance and turns−ratio to reach good performance in
standby without making noise.
Let’s now follow the below design steps to build our 30 W
QR Switch−Mode Power Supply:
1. In our opinion, the very first element to dimension
is the primary to secondary turn ratio. In effect, it
will condition, among other parameters, a) the
drain−source stress of the MOSFET at its opening
b) the Peak Inverse Voltage (PIV) of the secondary
rectifier at the switch closing c) the area where the
supply operates in Zero Voltage Switching (ZVS).
As we have seen before, if we select an 800 V
MOSFET, we can select the turn ratio by (including
a 10% safety margin):
latest case, you would probably need to pick up a 900 V or
1.0 kV BVdss MOSFET.
Answer 2:
In our case, we prefer to avoid any foldback at nominal
load over the whole input voltage. Frequency foldback starts
by discrete jumps between valleys and can create some
noise. If we accept to increase the frequency at high line
before folding the frequency back (with a 1.0 nF connected
to pin 4, we clamp at Fmin = 90 kHz), then we can accept to
lower the switching frequency at low lines, but not too low
to avoid entering audible frequencies.
Answer 3:
The answer really depends upon the transformer structure
you have used, e.g. the type of core, bobbin, etc. The best is
to setup a test structure where you impose a peak current in
your transformer prototype at low, audible, frequency (e.g.
around 5.0 kHz). Figure 16 offers a possibility to do that via
a power MOSFET.
1
Np
max VinDC · (Vout Vf) 800 V−10%
Ns
(eq. 22)
2
→ Np/Ns 19.5. We selected a 16.6 turn−ratio
which will ensure ZVS up to Vin = 16.6 x (16.8 + 1)
= 295 VDC.
2. Having the right turn ratio, we can calculate the
primary peak current needed to pass the 30 W of
power. If we neglect the delay to reach the valley
of Vds(t) (see eq. 12), then we end up with a
simplified current definition:
+
Vin
PULSE
4
3
Current
Reading
Ip max 2 · Pout ·
1
Np
Ns
· (Vout Vf) min VinDC
· min VinDC ·
Np
Ns
· (Vout Vf)
plugging values into it gives us a maximum peak
current of: 0.94 A. This value will slightly change
as soon as you consider other parasitic elements
(see AND8089, “Determining the Free−Running
Frequency for QR Systems”), but is a good starting
point.
3. From that value, we know that the NCP1205 will
start folding back the frequency into the audible
range at a peak current equal to 30% of the
maximum value (this is the way the NCP1205 is
designed). We know by experience (see Figure 16),
that we shall not go over 550 mA to avoid having
a singing transformer. In our case, 30% of 0.94 A
is well within our specs. We even have place for
improvement if we feel a need to increase Ip max
for parameter variation reasons.
Figure 16. A power MOSFET and an
adjustable duty−cycle generator lets you
select the right peak current.
By adjusting the PULSE source duty−cycle, it becomes
possible to impose a given peak current, directly sensed
across the 1.0 resistor via an oscilloscope. The freewheel
diode could be a 1N4937/MUR160 or equivalent whereas
the source Vin can be around 30 VDC with a 100 V BVdss
6.0 A MOSFET. Start by low peak currents and slowly
increase the duty−cycle until noise can be heard. This
corresponds to the very maximum peak current you can pass
while skipping cycles or when entering frequency foldback
without having a singing transformer. The best is actually to
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AND8129/D
obviously one of the most sensitive parameters
which influences others. Increasing the reflected
voltages to keep a wider ZVS operating range has
a price on other numbers:
The switching frequency increases (reset voltage on
Lp is stronger)
The primary peak current and conduction losses are
improved (if Fsw goes up, the peak demand goes
low)
The secondary peak current and conduction losses
increase
The MOSFET undergoes a bigger stress at the
switch opening
MOSFET turn−on losses can be really null (if ZVS
is achieved)
7. Final values will be obtained due to the
design spreadsheet available to download from
ON Semiconductor web site which includes
parasitic elements (such as the leakage inductance
and the Cds capacitor) and whose formulae are
described in AND8089. After we entered our
desired operating conditions, the below numbers
were extracted from the spreadsheet:
Lp = 1.2 mH
Lleak (measured) = 15 H
Np/Ns = 16.6
Ip max = 1.5 A, to include various tolerances
Rshunt = 2 x 1.2 in parallel
Creso = 1.5 nF/1.0 kV
Calculated frequency at nominal load and minimum
input voltage = 50 kHz (120 VDC and 30 W)
Calculated frequency at nominal load and
maximum input voltage = 87 kHz (370 VDC and
30 W)
4. The inductor is defined knowing what frequency
range we want to cover. As exemplified by
Figure 16, the switching frequency increases at
high input voltage (whereas Ip goes low) and
decreases at low input voltages (whereas Ip goes
up). In some cases, it is desirable to keep the
magnetics small and thus operate at high
frequency at low line. On the other way, some
designers find that is desirable to compensate the
higher RMS losses at low line, by reducing the
switching losses via a lower switching rate. We
will stick for this latest option and calculate Lp to
be above the audible range at low line and
maximum output power. Rearranging equation 19,
leads to solve:
Lp 1
Fsw min · 2 · Pout
Np
· (VoutVf)Vin min
Ns
· Vin min ·
2
Np
· (VoutVf)
Ns
(eq. 23)
or Lp greater than 1.9 mH. This number is a first
result and we will see that further iterations are
needed to freeze this number.
5. Since we implement true ZVS up to 295 V, we can
connect a large capacitor between drain and
ground to clamp the maximum voltage generated
by the leakage inductance. The V2 capacitor losses
will be null in ZVS (see eq. 7) but will start to
increase at high line when ZVS is lost. We believe
that even if it is a bit detrimental to efficiency, the
cost improvement brought by the absence of a
RCD clamping network and smoother waveforms
(good for EMI), really justifies the addition of this
drain−ground capacitor. By tweaking equation 3,
we can calculate the amount of necessary
capacitance we need between drain and ground:
Creso Lleak
Np
Vds max −Vin− Ns
· (Vout Vf)2
Using SPICE to Check for the Validity of the
Assumptions
· Ip2
Despite the existence of a dedicated NCP1205 SPICE
model, it is faster and easier to use a simplified free−run
approach to have an idea of the final results. Figure 17 offers
a possible way to represent a free−running controller: the
demagnetization path includes a standard flip−flop which
latches the transition while the feedback signal fixes the
current setpoint. Due to a simple arrangement, the system
simulates really quickly and allows an immediate
assessment of what has been suggested by the Excel
spreadsheet. The feedback loop is purposely simplified with
a Zener diode arrangement, but you can upgrade it with a
TL431 circuitry. It will simply take longer simulation time
to settle. As Figures 18 and 19 show, it is difficult to make
the distinction between the simulation and the real
measurement on the demoboard.
(eq. 24)
If we consider a leakage inductance of around
30 H (first estimation) and we plug our values into
equation 24, then Creso needs to be greater than
1.6 nF.
By losing ZVS at 295 V, we can imagine that the
switch restart will occur on a drain wave at
330 V−295 = 35 V. These nominal conditions imply
a theoretical switching frequency of 131 kHz
(eq. 19) and capacitive losses of (eq. 7): Ploss = 0.5
x 352 x 1.6 n x 131 k = 130 mW which is acceptable.
6. You can see through the lines we wrote that many
parameters can be changed to obtain different
converters at the end. The reflected voltage is
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AND8129/D
X4
XFMR−AUX
RATIO_POW = −0.06
RATIO_AUX = 0.06
Rprim
0.5
Iout
+
X1
MBR20100
Icoil
VCoil
+
Resr1
60 m
Idiode
Lprim
1.2 mH
dem
R6
5.6 k
Cout1
2.2 mF
IC = 16
C6
330 p
Vout
Vout
Rload
9.4
Lleak
15 u
+
Vin
360
X2
Free Run DT
R1
22 k
dem
1
fb
+
8
2
Id
fb
Rled
1k
IReso
6
Free
Run
Vout
Feedback
7
3
4
Vdrain
5
Creso
1.5 n
C5
10 n
Rsense
0.5
X7
MOC8101
Figure 17. A Simplified Free−Running Controller Eases the Simulation Setup and Increases Speed
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11
D4
BV = 15.6
AND8129/D
Vds = 200 V/div
Vsense = 200 mV/div
X = 3 s/div
Figure 18.
Figure 19.
It becomes difficult to differentiate the simulation from the real world . . . Figure 18 is simulation,
Figure 19 is measured.
Resonating Capacitor: This device shall sustain the voltage
peak but also a large RMS current. Simulations show that
worse case occurs at high line with a RMS current of
370 mA. We have used a WIMA FPK1 series with good
results.
The Spice simulation offers another advantage which is
the evaluation of the component stresses. Due to good
models, you can immediately measure the MOSFET
conduction losses worse case, the RMS current in the
rectifiers, in the resonating capacitor, etc. Figure 20 portrays
these typical waveforms. In light of this data, we can now
select components and peripherals accordingly:
Primary Inductance: Low line imposes the highest stress on
the transformer. The following specs to be passed to the
transformer manufacturer:
Lp = 1.2 mH
Ipmax = 2.0 A
IpRMS = 571 mA
Np:Ns = 1:0.06
Np:Naux = 1:0.06
MOSFET: Depending on the type, you compute the power
using: Pconduction = RDS(ON) @ Tj = 100°C x IdRMS2 =
3 x 0.4652 = 650 mW at low line. In our case, switching
losses are close to zero due to ZVS and ZCS. When the main
grows up to 370 VDC on the bulk capacitor, the ZVS effect
goes away and capacitive losses appear due to Creso.
Simulation shows that conduction losses stay below 1.0 W.
We selected an 800 V MOSFET from ST.
Secondary Rectifier: The conduction losses of a diode are
given by: P = IdRMS2 x Rd + Vf @ Id x IdAVG. In our case,
we obtain theoretical total losses of 1.21 W. An MBR10100
can be a good choice.
A small note about MOSFET Spice models: They do not
reflect Tj temperature effects on the RDS(ON) and other
parameters (e.g. Vth). As a result, calculating the total
power (including switching losses) by multiplying and
averaging Vds(t) x Id(t) over one period does only make
sense for junction temperatures of 27°C.
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12
AND8129/D
1 id
2 icoil
3 idiode
4 ireso
5 i(cout1)
plot1
id in amperes
1.20
1
800m
400m
0
Idrain − RMS = 465mA
Plot2
icoil in amperes
−400m
1.20
2
800m
400m
0
Icoil − RMS = 571mA
Plot4
ireso in amperes
Plot3
idiode in amperes
−400m
28.7
21.6
Id sec − RMS = 5.02A
14.6
7.51
434m
3
1.00
ICreso − RMS = 223mA
600m
200m
4
−200m
Plot5
i(cout1) in amperes
−600m
30.0
ICout − RMS = 5.72A
20.0
10.0
0
5
−10.0
2.01m
2.03m
2.05m
Time in Seconds
2.07m
2.09m
Figure 20. Typical Waveforms Obtained by a Spice Simulation of the Quasi−Resonant Converter
voltage but a diode (D5) is placed in series with ground to
generate the right Forward polarity (see Figure 15). Because
of the resonating capacitor placed between drain and
ground, a spike can occur at high line as soon as the ZVS
effect is lost. To help the LEB circuitry inside the NCP1205,
an additional cleaning network is added through R2−C2.
Please note that the resonating capacitor C14 is wired
between drain and ground and not between drain and source.
This is to avoid any negative current flowing inside the
current sense pin at turn−off (during the natural
drain−source ringing). The feedback loop is standard and
uses a TLV431 to further lower the secondary side standby
power. Since its minimum operating current is 100 A, there
is no need to waste 1.0 mA in it as with traditional TL431
series.
Output Capacitor: This component will be selected based
on the required output ripple but also on its ability to sustain
the total RMS current. The dissipation of the capacitor is
dictated by its Equivalent Series Resistor (ESR) and follows
the following formula: Pcap = RESR x Iripple2. A 5.7 A RMS
current will thus be the primary criterion when selecting the
right device. It is also possible to wire capacitors in parallel
to split the total current between devices.
Final Schematic
Figure 21 shows the final schematic implemented in the
NCP1205 demoboard. As you can see, the large capacitor
placed on the drain allows us to avoid a costly and noisy
RCD clamping network. However, the PCB layout offers the
necessary place to include one if experiments are needed.
The auxiliary winding is wired to offer a stable Flyback
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13
D3, D5 = 1N4148
R32
6.8 k
Rclamp
T1
1000 F/25 V
C15/C16/C17
Ground
R21 3.3 k
R22
1k
R20 33
7
3
6
5
4
10
R14
3W
NCP1205
IC4
18 k
R17
C20
1 nF
C2
220
pF
R24
39 k
R2 1 k
Optional
Network
+ 47 F/
25 V
C22
M2
800 V/4 A
IC5
SFH6156−2
R25
1.2
R26
1.2
C18
18 k
6.8
nF
R23
IC6
TLV431
C23
2.2 nF
Y1 Type
R30
3.9 k
AND8129/D
1.5 nF/1 kV
C14
WYMAFKP1
1000 V
8
2 x 27 mH
CM L4
Schaffner
RN114−08/02
2
Universal
Input
D5
C13 82 pF
R19
100 k
1
Figure 21. The Final Electrical Diagram of the NCP1205−Based Demoboard
14
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220 F
C1
X2
R15 2.2 k
Optional Network
B1
2KBP08M
R16
1 Meg
Not
Wired
R1
00
Dclamp
13.5 V @ 2.5 A
+ 220 F/
25 V
C19
+
R31
6.8 k
+
Coilcraft
PCV−2−103−05
L3
10 H
D7 MBR20100
D3
Cclamp
C12
47 F/
400 V
Lp = 1.2 mH
1:0.06 (power)
1:0.06 (aux.)
AND8129/D
Demoboard Performance and Typical Waveforms
The use of a TLV431 really reduces the output power
wasted in no−load. But sometimes, the repetition rate of the
switching pulses in standby is so low, that the auxiliary goes
down and reaches the NCP1205 UVLOlow, restarting the
high−voltage current source. To avoid this situation, you
either need to increase a bit the auxiliary turn ratio (this is not
a problem because the extended Vcc range offers that
flexibility) or slightly load the output by a resistor.
Experience has shown that when the auxiliary Vcc was close
to 8.2 V, a simple 10 mW bleeding element connected to
Vout was enough to bring Vauxiliary to around 9.0 V, giving
the necessary headroom.
The 30 W demoboard is available from ON Semiconductor.
It corresponds to Figure 21 sketch. Below are some shots and
measurements captured on the board, testifying for its good
characteristics:
Efficiency @ 230 VAC = 86.6%
Standby power (Pout = 0) = 174 mW
Efficiency @ 110 VAC = 84.4%
Standby power (Pout = 0) = 65 mW
P4
P3
P2
P1
Figure 22. Drain−source signals at different powers: P1 P2 P3 P4,
you can note the multiple valley jumping.
Figure 23. At high line and nominal power, the drain level is kept below
the MOSFET breakdown.
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15
AND8129/D
Figure 24. At high line, an output short circuit does not jeopardize the
MOSFET’s life.
Figure 25. An output bang−bang test (1 to 2.5 A) does not reveal any
instability. The spikes are related to the LC filter installed on the output.
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16
AND8129/D
Bill of Materials
All resistors are 1/4 W 5% SMD unless otherwise noted.
Part Value
Designator
Type
Manufacturer
Reference
Comments
00
R1
1.0 k
R2
10
R14
2.2 k
R15
18 k
R17
100 k
R19
33
R20
18 k
R23
1.2
R26
1.0 W
1.2
R25
1.0 W
3.3 k
R21
1.0 k
R22
39 k
R24
3.9 k
R30
6.8 k
R31
Through Holes
6.8 k
R32
Through Holes
220 nF
C1
Through Holes
220 pF
C2
47 F/400 V
C12
82 pF
C13
1.5 nF/1.0 kV
C14
1000 F/25 V
C15
Vertical
1000 F/25 V
C16
Vertical
1000 F/25 V
C17
Vertical
6.8 nF
C18
220 F/25 V
C19
1.0 nF
C20
47 F/25 V
C22
2.2 nF
C23
Roederstein
WY Series Y1
10 H
L3
Coilcraft
PCV−2−103−05
2 x 27 mH
L4
Schaffner
RN114−08/0.2
Snap−in
BRIDGE D8
BC Comp.
2222−057−56479
Wima
1500−FKP1
KBU−8J
MBR20100
D7
ON Semiconductor
STP5NB80
M2
ST
NCP1205P
IC4
ON Semiconductor
SFH6156−2
IC5
Infineon
TLV431
IC6
ON Semiconductor
30 W Transformer
T1
Coilcraft
Z9508−A
Pulse−Engineering
PF0137
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17
TO−92
AND8129/D
Transformer Vendor Details
Coilcraft
1102 Silver Lake Road
Cary, Illinois 60013 USA
Tel.: (847) 639–6400
Fax: (847) 639–1469
Email: [email protected]
http://www.coilcraft.com
Pulse Engineering
Site d’Orgelet
Zone industrielle
39270 − ORGELET
Tel.: 33 (0)3 84 35 04 04
Fax: 33 (0)3 84 25 46 41
http://www.pulseeng.com/
Email: [email protected]
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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AND8129/D
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