DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER

SN74LS90
DECADE COUNTER;
DIVIDE-BY-TWELVE
COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are
high-speed 4-bit ripple type counters partitioned into two sections.
Each counter has a divide-by-two section and either a divide-by-five
(LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which
are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP) to form BCD,
bi-quinary, modulo-12, or modulo-16 counters. All of the counters
have a 2-input gated Master Reset (Clear), and the LS90 also has a
2-input gated Master Set (Preset 9).
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DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
•
Binary
Input Clamp Diodes Limit High Speed Termination Effects
HIGH
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
1
LOADING (Note a)
PIN NAMES
CP0
14
J SUFFIX
CERAMIC
CASE 632-08
Clock (Active LOW going edge) Input to
÷2 Section
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
LOW
0.5 U.L.
1.5 U.L.
0.5 U.L.
2.0 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
14
1
LS90
MS
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 6
14
1
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
6 7
1 2
N SUFFIX
PLASTIC
CASE 646-06
LS92
14
1
LS93
14
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
1
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
6 7 12 11 9 8
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
1
Publication Order Number:
SN74LS90/D
SN74LS90
LOGIC DIAGRAM
MS1
MS2
CP0
CONNECTION DIAGRAM
7
Q
S
J DQ
S
J DQ
S
R DQ
CP
KC Q
CP
KC Q
CP
KC Q
CP
SC Q
J
14
SD
D
CP1
MR1
MR2
DIP (TOP VIEW)
LS90
6
D
D
D
1
2
Q0
3
12
Q1
9
Q2
8
11
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
J
14
Q
J
CP
KC Q
MR1
MR2
Q
J
Q
J
CP
KC Q
D
Q
CP
KC Q
D
D
1
6
12
11
Q0
7
9
Q1
8
Q2
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
14
J
Q
J
CP
KC Q
MR1
MR2
Q
J
Q
J
CP
KC Q
D
Q
CP
KC Q
D
D
1
2
12
3
MR2 3
12 Q0
NC 4
11 Q3
VCC 5
10 GND
MS1 6
9 Q1
MS2 7
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
CP1 1
14 CP0
NC 2
13 NC
NC 3
12 Q0
NC 4
11 Q1
VCC 5
10 GND
MR1 6
9 Q2
MR2 7
8 Q3
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
DIP (TOP VIEW)
CP
KC Q
D
CP1
13 NC
CONNECTION DIAGRAM
LS93
CP0
MR1 2
DIP (TOP VIEW)
CP
KC Q
D
CP1
14 CP0
CONNECTION DIAGRAM
LS92
CP0
Q3
CP1 1
Q0
9
Q1
8
11
Q2
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
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CP1 1
14 CP0
MR1 2
13 NC
MR2 3
12 Q0
NC 4
11 Q3
VCC 5
10 GND
NC 6
9 Q1
NC 7
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
SN74LS90
FUNCTIONAL DESCRIPTION
C. Divide-By-Two and Divide-By-Five Counter — No
external interconnections are required. The first flip-flop is
used as a binary element for the divide-by-two function
(CP0 as the input and Q0 as the output). The CP1 input is
used to obtain binary divide-by-five operation at the Q3
output.
The LS90, LS92, and LS93 are 4-bit ripple type Decade,
Divide-By-Twelve, and Binary Counters respectively. Each
device consists of four master/slave flip-flops which are
internally connected to provide a divide-by-two section and a
divide-by-five
(LS90),
divide-by-six
(LS92),
or
divide-by-eight (LS93) section. Each section has a separate
clock input which initiates state changes of the counter on the
HIGH-to-LOW clock transition. State changes of the Q
outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject
to decoding spikes and should not be used for clocks or
strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1 • MR2) is
provided on all counters which overrides and clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 • MS2) is provided on the LS90 which
overrides the clocks and the MR inputs and sets the outputs
to nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
LS92
A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
must be externally connected to the Q0 output. The CP0
input receives the incoming count and Q3 produces a
symmetrical divide-by-twelve square wave output.
B. Divide-By-Two and Divide-By-Six Counter —No external
interconnections are required. The first flip-flop is used as
a binary element for the divide-by-two function. The CP1
input is used to obtain divide-by-three operation at the Q1
and Q2 outputs and divide-by-six operation at the Q3
output.
LS93
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are
applied to input CP0. Simultaneous divisions of 2, 4, 8,
and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as
shown in the truth table.
LS90
A. BCD Decade (8421) Counter — The CP1 input must be
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence
is produced.
B. 3-Bit Ripple Counter— The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4,
and 8 are available at the Q1, Q2, and Q3 outputs.
Independent use of the first flip-flop is available if the reset
function coincides with reset of the 3-bit ripple-through
counter.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
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SN74LS90
LS90
MODE SELECTION
LS92 AND LS93
MODE SELECTION
RESET / SET INPUTS
MR1 MR2 MS1 MS2
H
H
X
L
X
L
X
H
H
X
X
L
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
X
OUTPUTS
RESET
INPUTS
Q0
Q1
Q2
Q3
L
L
H
L
L
L
L
L
L
L
L
H
MR1 MR2
H
L
H
L
Count
Count
Count
Count
LS90
BCD COUNT SEQUENCE
0
1
2
3
4
5
6
7
8
9
H
H
L
L
Q0
Q1
Q2
Q3
L
L
L
L
Count
Count
Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
LS92
TRUTH TABLE
OUTPUT
COUNT
OUTPUTS
OUTPUT
COUNT
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
NOTE: Output Q0 is connected to Input
CP1 for BCD count.
0
1
2
3
4
5
6
7
8
9
10
11
LS93
TRUTH TABLE
OUTPUT
COUNT
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
NOTE: Output Q0 is connected to Input
CP1.
NOTE: Output Q0 is connected to Input
CP1.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
−55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
−0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
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SN74LS90
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
MS, MR
CP0
CP1 (LS90, LS92)
CP1 (LS93)
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
2.0
54
0.7
74
0.8
−0.65
−1.5
Unit
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = − 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
μA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
mA
VCC = MAX, VIN = 0.4 V
−100
mA
VCC = MAX
15
mA
VCC = MAX
−0.4
−2.4
−3.2
−1.6
−20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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5
SN74LS90
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)
Limits
LS92
LS90
Symbol
Typ
Min
Parameter
Max
Min
Typ
LS93
Max
32
Min
Typ
Max
32
Unit
fMAX
CP0 Input Clock Frequency
32
fMAX
CP1 Input Clock Frequency
16
tPLH
tPHL
Propagation Delay,
CP0 Input to Q0 Output
10
12
16
18
10
12
16
18
10
12
16
18
ns
tPLH
tPHL
CP0 Input to Q3 Output
32
34
48
50
32
34
48
50
46
46
70
70
ns
tPLH
tPHL
CP1 Input to Q1 Output
10
14
16
21
10
14
16
21
10
14
16
21
ns
tPLH
tPHL
CP1 Input to Q2 Output
21
23
32
35
10
14
16
21
21
23
32
35
ns
tPLH
tPHL
CP1 Input to Q3 Output
21
23
32
35
21
23
32
35
34
34
51
51
ns
tPLH
MS Input to Q0 and Q3 Outputs
20
30
ns
tPHL
MS Input to Q1 and Q2 Outputs
26
40
ns
tPHL
MR Input to Any Output
26
40
16
MHz
16
26
40
MHz
26
40
ns
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
LS90
Symbol
Min
Parameter
LS92
Max
Min
LS93
Max
Min
Max
Unit
tW
CP0 Pulse Width
15
15
15
ns
tW
CP1 Pulse Width
30
30
30
ns
tW
MS Pulse Width
15
tW
MR Pulse Width
15
15
15
ns
trec
Recovery Time MR to CP
25
25
25
ns
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
and transfer HIGH data to the Q outputs
AC WAVEFORMS
*CP
1.3 V
1.3 V
tW
tPHL
Q
1.3 V
tPLH
1.3 V
1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS
1.3 V
1.3 V
MS
trec
tW
1.3 V
tW
trec
CP
1.3 V
CP
tPHL
Q
1.3 V
Q0 • Q3
(LS90)
1.3 V
Figure 2
1.3 V
tPLH
1.3 V
Figure 3
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SN74LS90
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