2EDN752x / 2EDN852x

EiceDRIVER ™
2EDN752x / 2EDN852x
Dual Channel 5A, High-Speed, Low-Side Gate Driver With High
Negative Input Voltage Capability and Advanced Reverse
Current Robustness
EiceDRIVER™
Fast Dual Channel Low-Side Gate Driver
Data Sheet
Revision 2.1, 2016-01-19
Power Management and Multimarket
EiceDRIVER™
2EDN752x / 2EDN852x
Revision History ,
Revision 2.1, 2016-01-19
Page/
Item
Subjects (major changes since previous revision)
Responsible
Date
updated from version 2.0
6
Table 1-1: better structure, no change on content level
Tobias Gerber 2015/08/06
17
Table 5-5 / Table 5-6: changed headline for better structure, no
change on content level
Tobias Gerber 2015/08/06
4-7, 13-14 Restructure text, no parameter change
Tobias Gerber 2015/08/27
6
New structured device list
Tobias Gerber 2015/12/03
28 - 31
Figures rearrangment, footprints, package
Tobias Gerber 2015/12/09
6, 31
Update of Packages: PG-WSON-8 and Figure 8-4: PG-TSSOP-8
outline
Tobias Gerber 2016/01/14
15
Table 5-1: Relax conditions for Reverse Current Peak
Tobias Gerber 2016/01/18
4, 6
New Package figure for PG-WSON-8
Tobias Gerber 2016/01/18
6-14
Typos and formating, no parameter change
Tobias Gerber 2016/01/18
Data Sheet
2
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Fast Dual Channel 5 A Low-Side Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
1.1
1.2
1.3
Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Undervoltage Lockout Versions 7
Logic Versions 7
Package Versions 7
2
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
4.1
4.2
4.3
4.4
4.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Introduction 13
Supply Voltage 13
Input Configurations 13
Driver Outputs 13
Undervoltage Lockout (UVLO) 14
5
5.1
5.2
5.3
5.4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings 15
Thermal Characteristics 15
Operating Range 16
Electrical Characteristics 17
6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
8.1
8.2
8.3
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PG-DSO-8-60 28
PG-TSSOP-8-1 29
PG-WSON-8-1 31
Data Sheet
3
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Fast Dual Channel 5 A Low-Side Gate Driver
Fast, precise, strong and compatible
•
Highly efficient SMPS enabled by 5 ns fast slew rates and 19 ns
propagation delay precision for fast MOSFET and GaN switching
•
1 ns channel-to-channel propagation delay accuracy enables safe
use of two channels in parallel
Two independent 5 A channels enable numerous deployment
options
Industry standard packages and pinout ease system-design
upgrades
•
•
PG-DSO-8
The new Reference in Ruggedness
•
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant
MOSFET protection under abnormal conditions
•
-10 V control and enable input robustness delivers crucial safety
margin when driving pulse-transformers or driving MOSFETs in
through hole packaging
5 A reverse current robustness eliminates the need for output
protection circuitry.
•
Typical Applications
•
Server SMPS
•
TeleCom SMPS
•
DC-to-DC Converter
•
Bricks
•
Power Tools
•
Industrial SMPS
•
Motor Control
•
Solar SMPS
PG-WSON-8
PG-TSSOP-8
Example Topologies
•
Single and interleaved PFC
•
LLC, ZVS with pulse transformer
•
Synchronous Rectification
Data Sheet
4
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Description
The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level
MOSFETs and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as
IGBTs and GaN Power devices.
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to
+20 V. -10 V input pin robustness protects the driver against latch-up or electrical overstress which can be
induced by parasitic ground inductances. This greatly enhances system stability.
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under
abnormal conditions. Under such circumstances, this UVLO mechanism provides crucial independence from
whether and when other supervisors circuitries detect abnormal conditions.
Each of the two outputs is able to sink and source 5 A currents utilizing a true rail-to-rail stage. This ensures
very low on resistance of 0.7 Ω up to the positive and 0.55 Ω down to the negative rail respectively. Very tight
channel to channel delay matching, typ. 1 ns, permits parallel use of two channels, leading to a source and
sink capability of 10 A. Industry leading reverse current robustness eliminates the need for Schottky diodes at
the outputs and reduces the bill-of-material.
From Controller
The pinout of the 2EDN family is compatible with the industry standard. Two different control input options,
non-inverted and inverted, offer high flexibility. Three package variants, DSO 8-pin, TSSOP 8-pin, WSON 8-pin,
allow optimization of PCB board space usage and thermal characteristics.
VDD
2EDN752x /
2EDN852x
1 ENA
ENB 88
2 INA
OUTA 7
33 GND
VDD 66
44 INB
Load1
Load2
M1
Rg1
Rg2
M2
OUTB 55
CVDD
Data Sheet
5
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1
Product Versions
The 2EDN752x / 2EDN852x are available in 2 different logic, 2 different undervoltage lockout and 3 package
versions.
Table 1-1
Package
Product Versions
Type.
UVLO
Control Input
Part Number
IC Topside
Marking Code
4.2V
direct
2EDN7524F
inverted
2EDN7523F
direct
2EDN8524F
inverted
2ED87523F
2N7524AF
EiceDRIV
XXHYYWW
2N7523AF
EiceDRIV
XXHYYWW
2N8524AF
EiceDRIV
XXHYYWW
2N8523AF
EiceDRIV
XXHYYWW
direct
2EDN7524R
inverted
2EDN7523R
direct
2EDN8524R
inverted
2ED87523R
direct
2EDN7524G
inverted
2EDN7523G
PG-DSO-8
8V
PG-TSSOP-8
4.2V
8V
2N7524
AR_XXX
HYYWW
2N7523
AR_XXX
HYYWW
2N8524
AR_XXX
HYYWW
2N8523
AR_XXX
HYYWW
PG-WSON-8
4.2V
Data Sheet
6
2N7524
AR_XXX
HYYWW
2N7523
AR_XXX
HYYWW
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1.1
Undervoltage Lockout Versions
The two Undervoltage Lockout versions are indicated by the variable x in the product version 2EDNy52x:
•
y=7: lower voltage for logic level MOSFETs (4.2 V)
•
y=8: higher voltage for standard and superjunction MOSFETs (8.0 V)
Please refer to the functional description section for more details in Chapter 4 Undervoltage Lockout
(UVLO).
1.2
Logic Versions
The 2 logic versions are indicated by the variable x in the product version 2EDNy52x:
•
x=3: inverting
•
x=4: non-inverting
The logic relations between inputs, enable pins and outputs are given in Table 1-2 for the inverting and noninverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the
respective input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or
an undervoltage lockout event, due to low voltage at VDD, causes the respective output to be low too,
regardless of the input signal.
Table 1-2
Logic Table
Inputs
Output Inverting
1)
Output non-inverting
OUTA
OUTB
OUTA
OUTB
active
L
L
L
L
x
inactive
L
L
L
L
L
x
inactive
H
L
L
L
L
H
x
inactive
L
L
H
L
L
H
x
L
inactive
L
H
L
L
L
H
x
H
inactive
L
L
L
H
H
H
L
L
inactive
H
H
L
L
H
H
H
L
inactive
L
H
H
L
H
H
L
H
inactive
H
L
L
H
H
H
H
H
inactive
L
L
H
H
ENA
ENB
INA
INB
UVLO
x
x
x
x
L
L
x
H
L
H
1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage.
Active means that UVLO disable active the output stages.
1.3
Package Versions
The logic and UVLO versions are available in 3 different packages.
•
•
•
a standard PG-DSO-8 (designated by “F”)
a leadless PG-WSON-8 (designated by “G”)
a small PG-TSSOP-8 (designated by “R”)
Drawings can be viewed in Chapter 8 Outline Dimensions.
Data Sheet
7
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
2
Pin Configuration and Description
The pin configuration for the inverting and standard input version of 2EDN7524F and 2EDN7523F in the
PG-DSO-8 package is shown in Figure 2-1.
1
ENA
2
INA
3
GND
4
INB
ENB
8
OUTA
7
VDD
6
OUTB
5
Figure 2-1 Pin Configuration PG-DSO-8, Top View
Table 2-1
Pin Configuration 2EDN7524F and 2EDN7523F in the PG-DSO-8 Package
Pin
Symbol
Description
1
ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2
INA
Input signal channel A
Logic input, controlling OUTA (inverting or non-inverting)
3
GND
Ground
4
INB
Input signal channel B
Logic input, controlling OUTB (inverting or non-inverting)
5
OUTB
Driver output channel B
Low-impedance output with source and sink capability
6
VDD
Positive supply voltage
Operating range 4.5 V to 20 V
7
OUTA
Driver output channel A
Low-impedance output with source and sink capability
8
ENB
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
Data Sheet
8
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for standard input version of 2EDN7524R, 2EDN8524R, 2EDN7523R and 2EDN8523R in
the PG-TSSOP-8 package is shown in Figure 2-2.
1
ENA
2
INA
3
GND
4
INB
Heat
Sink
ENB
8
OUTA
7
VDD
6
OUTB
5
Figure 2-2 Pin Configuration PG-TSSOP-8, Top View
Table 2-2
Pin Configuration 2EDN7524R, 2EDN8524R, 2EDN7523R and 2EDN8523R in the PG-TSSOP-8
Package
Pin
Symbol
Description
1
ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2
INA
Input signal channel A
Logic input, controlling OUTA (non-inverting)
3
GND
Ground
4
INB
Input signal channel B
Logic input, controlling OUTB (non-inverting)
5
OUTB
Driver output channel B
Low-impedance output with source and sink capability
6
VDD
Positive supply voltage
Operating range 4.5 V to 20 V
7
OUTA
Driver output channel A
Low-impedance output with source and sink capability
8
ENB
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
Heat sink of PG-TSSOP-8 packages has to be connected to GND pin.
Data Sheet
9
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for standard input version of 2EDN7524G and 2EDN7523G. In the PG-WSON-8 package
is shown in Figure 2-3.
ENA
1
INA
2
GND
INB
8
ENB
7
OUTA
3
6
VDD
4
5
OUTB
Heat
Sink
Figure 2-3 Pin Configuration PG-WSON-8, Top View
Table 2-3
Pin Configuration 2EDN7524G and 2EDN7523G in the PG-WSON-8 Package
Pin
Symbol
Description
1
ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2
INA
Input signal channel A
Logic input, controlling OUTA (non-inverting)
3
GND
Ground
4
INB
Input signal channel B
Logic input, controlling OUTB (non-inverting)
5
OUTB
Driver output channel B
Low-impedance output with source and sink capability
6
VDD
Positive supply voltage
Operating range 4.5 V to 20 V
7
OUTA
Driver output channel A
Low-impedance output with source and sink capability
8
ENB
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
Heat sink of PG-WSON-8 packages has to be connected to GND pin.
Data Sheet
10
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Block Diagram
3
Block Diagram
A simplified functional block diagram for the non-inverted version is given in Figure 3-1
VDD
VDD
6
UVLO
VDD
400k
ENA
1
Logic A
INA
7
OUTA
5
OUTB
2
100k
GND
GND
VDD
VDD
400k
ENB 8
Logic B
INB 4
100k
GND
GND 3
GND
Figure 3-1 Block Diagram, standard input, pull-up/pull-down resistor configuration
Data Sheet
11
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Block Diagram
A simplified functional block diagram for the inverted version is given in Figure 3-2.
VDD
VDD
6
UVLO
VDD
400k
ENA
1
VDD
Logic A
7
OUTA
5
OUTB
400k
INA
2
GND
VDD
VDD
VDD
400k
400k
ENB 8
Logic B
INB 4
GND
GND 3
GND
Figure 3-2 Block Diagram, inverting input, pull-up/pull-down resistor configuration
Data Sheet
12
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
4
Functional Description
4.1
Introduction
The 2EDN752x / 2EDN852x is a fast dual-channel driver for low-side switches. Two true rail-to-rail output
stages with very low output impedance and high current capability are chosen to ensure highest flexibility and
cover a high variety of applications.
The focus on robustness at the input and output side additionally gives this device a safety margin in critical
abnormal situations. An extended negative voltage range protects input pins against ground shifts. No current
flows over the ESD structure in the IC during a negative input level. All outputs are robust against reverse
current. The interaction with the power MOSFET, even reverse reflected power will be handled by the strong
internal output stage.
All inputs are compatible with LV-TTL signal levels. The threshold voltages with a typical hysteresis of 1.1 V are
kept constant over the supply voltage range.
Since the 2EDN752x / 2EDN852x aims particularly at fast-switching applications, signal delays and rise/fall
times have been minimized. Special effort has been made towards minimizing delay differences between the
2 channels to very low values of typically 1 ns.
4.2
Supply Voltage
The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current
capability of 2EDN752x / 2EDN852x when driving very large MOSFETs. The minimum operating supply voltage
is set by the undervoltage lockout function to a typical default value of 4.2 V or of 8 V. This lockout function
protects power MOSFETs from running into linear mode with subsequent high power dissipation.
4.3
Input Configurations
As described in Chapter 1, 2EDN752x / 2EDN852x is available in 2 different configurations with respect to the
logic configuration of the 4 input pins (input plus enable).
The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left
open. The direct PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event
during power up and a not driven input condition. Version with inverted PWM input have an internal pull up
resistor to prevent unwanted switch-on.
All inputs are compatible with LV-TTL levels and provide a hysteresis of 1.1 V typ. This hysteresis is
independent of the supply voltage.
All input pins have a negative extended voltage range. This prevents cross current over single wires during
GND shifts between signal source (controller) and driver input.
4.4
Driver Outputs
The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical
5 A of sourcing and sinking current. This driver output stage has a shoot through protection and current
limiting behavior. After a switching event, current limitation is raised up to achieve the typical current peak
for an excellent fast reaction time of the following power MOS transistor.
Data Sheet
13
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
The output impedance is very low with a typical value below 0.7 Ω for the sourcing p-channel MOS and 0.5 Ω
for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving
true rail-to-rail behaviour and avoiding a source follower’s voltage drop.
Gate Drive Outputs held active low in case of floating inputs ENx, INx or during startup or power down once
UVLO is not exceeded. Under any situation, startup, UVLO or shutdown, outputs are held under defined
conditions.
4.5
Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the output can be switched to its high level only if the supply
voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not
switched on if the driving voltage is too low to completely switch it on, thereby avoiding excessive power
dissipation.
The UVLO level is set to a typical value of 4.2 V / 8 V (with hysteresis). UVLO of 4.2 V is normally used for logic
level based MOSFETs. For higher level, like standard and high voltage superjunction MOSFETS, an UVLO
voltage of typical 8 V is available.
Data Sheet
14
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
5
Characteristics
The absolute maximum ratings are listed in Table 5-1. Stresses beyond these values may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
5.1
Absolute Maximum Ratings
Table 5-1
Absolute Maximum Ratings
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test Condition
Max.
Positive supply voltage
VVDD
-0.3
22
V
Voltage at pins INA, INB, ENA,
ENB
VIN
-10
22
V
Voltage at pins OUTA, OUTB
VOUT
-0.3
VVDD+0.3
V
Note1)
Reverse current peak at pins
OUTA, OUTB
ISNK_rev
ISRC_rev
-5
5
Apk
< 500ns
Junction temperature
TJ
-40
150
°C
Storage temperature
TS
-55
150
°C
ESD capability
VESD
1.5
kV
Charged Device Mode
(CDM) 2)
ESD capability
VESD
2.5
kV
Human Body Model
(HBM) 3)
Unit
Note or Test Condition
1) Voltage spikes resulting from reverse current peaks are allowed.
2) According to JESD22-C101
3) According to JESD22-A114
5.2
Thermal Characteristics
Table 5-2
Thermal Characteristics
Parameter
Symbol
Values
Min.
Typ.
Max.
Thermal resistance junctionambient 1)
RthJA25
125
K/W
PG-DSO-8, Tamb=25°C
Thermal resistance junctioncase (top) 2)
RthJC25
66
K/W
PG-DSO-8, Tamb=25°C
Thermal resistance junctionboard 3)
RthJB25
62
K/W
PG-DSO-8, Tamb=25°C
Characterization parameter
junction-top 4)
ΨthJC25
16
K/W
PG-DSO-8, Tamb=25°C
Characterization parameter
junction-board 5)
ΨthJB25
55
K/W
PG-DSO-8, Tamb=25°C
Data Sheet
15
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 5-2
Thermal Characteristics
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test Condition
Max.
Thermal resistance junctionambient 1)
RthJA25
64
K/W
PG-TSSOP-8, Tamb=25°C
Thermal resistance junctioncase (top) 2)
RthJP25
56
K/W
PG-TSSOP-8, Tamb=25°C
Thermal resistance junctionboard 3)
RthJB25
55
K/W
PG-TSSOP-8, Tamb=25°C
Characterization parameter
junction-top 4)
ΨthJC25
9
K/W
PG-TSSOP-8, Tamb=25°C
Characterization parameter
junction-board 5)
ΨthJB25
13
K/W
PG-TSSOP-8, Tamb=25°C
Thermal resistance junctionambient 1)
RthJA25
61
K/W
PG-WSON-8, Tamb=25°C
Thermal resistance junctioncase (top) 2)
RthJP25
54
K/W
PG-WSON-8, Tamb=25°C
Thermal resistance junctionboard 3)
RthJB25
52
K/W
PG-WSON-8, Tamb=25°C
Characterization parameter
junction-top 4)
ΨthJC25
8
K/W
PG-WSON-8, Tamb=25°C
Characterization parameter
junction-board 5)
ΨthJB25
11
K/W
PG-WSON-8, Tamb=25°C
1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDECstandard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No
specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture
to control the PCB temperature, as described in JESD51-8.
4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and
is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
5.3
Operating Range
Table 5-3
Operating Range
Parameter
Symbol
Values
Min.
Supply voltage
Data Sheet
VVDD
Typ.
4.5
Note or Test Condition
V
Min. defined by UVLO
Max.
20
16
Unit
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 5-3
Operating Range
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test Condition
Max.
Logic input voltage
VIN
-5
20
V
Junction temperature
TJ
-40
150
°C
1)
1) Continuous operation above 125 °C may reduce life time.
5.4
Electrical Characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They
are valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at TJ=25°C.
Table 5-4
Power Supply
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or Test Condition
VDD quiescent current
IVDDqu1
0.5
0.7
1.2
mA
OUT = high, VVDD= 12 V
VDD quiescent current
IVDDqu2
0.3
0.48
0.7
mA
OUT = low, VVDD= 12 V
Unit
Note or Test Condition
Table 5-5
Undervoltage Lockout for Logic Level MOSFET
Parameter
Symbol
Values
Min.
Typ.
Max.
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
3.9
4.2
4.5
V
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
3.6
3.9
4.2
V
UVLO threshold hysteresis
Table 5-6
0.3
UVLOhys
V
Undervoltage Lockout for Standard and Superjunction MOSFET Version
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
7.4
8.0
8.6
V
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
6.5
7.0
7.5
V
UVLO threshold hysteresis
—
1.0
—
V
Data Sheet
UVLOhys
17
Note or Test Condition
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 5-7
Logic Inputs INA, INB, ENA, ENB
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Input voltage threshold for
transition LH
VINH
1.9
2.1
2.3
V
Input voltage threshold for
transition HL
VINL
0.8
1.0
1.2
V
Input pull up resistor1)
RIN H
400
kΩ
RIN L
100
kΩ
2)
Input pull down resistor
Note or Test Condition
1) Inputs with initial high logic level
2) Inputs with initial low logic level
Table 5-8
Static Output Caracteristics (see Figure 6-2)
Parameter
Symbol
High Level (Sourcing) Output
Resistance
Ron_SRC
High Level (Sourcing) Output
Current
ISRC_Peak
Low Level (Sinking) Output
Resistance
Ron_SNK
High Level (Sinking) Output
Current
ISNK_peak
Values
Unit
Note or Test Condition
ISRC = 50mA
Min.
Typ.
Max.
0.35
0.7
1.2
Ω
5.0
1)
A
0.55
1.0
Ω
-5.0
2)
A
0.28
ISNK = 50mA
1) Active limited by design at approx. 6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
2) Active limited by design at approx. -6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
Data Sheet
18
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EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 5-9
Dynamic Characteristics (see Figure 6-1, Figure 6-2, Figure 6-3 and Figure 6-4)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or Test Condition
Input/Enable to output
propagation delay
TPDON
15
19
25
ns
CLOAD= 1.8 nF, VVDD= 12 V
Input/Enable to output
propagation delay
TPDOFF
15
19
25
ns
CLOAD= 1.8 nF, VVDD= 12 V
1
4
ns
5.3
101)
ns
CLOAD= 1.8 nF, VVDD= 12 V
1)
ns
CLOAD= 1.8 nF, VVDD= 12 V
ns
CLOAD= 1.8 nF, VVDD= 12 V
Input/Enable to output
delta tPD
propagation delay mismatch
between the two channels on
the same IC
Rise Time
TRISE
—
Fall Time
TFAll
—
4.5
10
Minimum input pulse width
that changes output state
TPW
—
10
20
1) Parameter verified by design, not 100% tested in production.
Data Sheet
19
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Timing Diagrams
6
Timing Diagrams
Figure 6-1 shows the definition of rise, fall and delay times for the inputs of the non-inverting version (with
Enable pin high or open).
ENx (high)
VIN H
VINL
VIN H
VINL
INx
90%
OUT
10%
TPDON
TRIS E
TPDOF F
TFAL L
Figure 6-1 Propagation delay, rise and fall time, non-inverted
Figure 6-2 shows the definition of rise, fall and delay times for the inputs of the inverting version (with enable
pins high or open).
ENx (high)
VINH
VIN L
INx
VINH
VINL
90%
OUT
10%
TPDON
TRIS E
TPDOF F
TFAL L
Figure 6-2 Propagation delay, rise and fall Time, inverted
Figure 6-3 illustrates the undervoltage lockout function.
UVLOon
UVLOoff
VDD
OUT
Figure 6-3 UVLO behaviour, input ENx and INx drives OUTx normally high
Data Sheet
20
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EiceDRIVER™
2EDN752x / 2EDN852x
Timing Diagrams
Figure 6-4 illustrates the minimum input pulse width that changes output state.
ENx (high)
VIN H
VINL
VIN H
INx
VINL
TPW
90%
OUTx
Figure 6-4 TPW, minimum input pulse width that changes output state
Data Sheet
21
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
7
Typical Characteristics
UVLO ON/OFF
vs
TEMPERATURE
4.5
UVLO HYSTERESIS
vs
TEMPERATURE
0.6
on value
off value
4.3
VDD delta [V]
VDD [V]
0.4
4.1
0.2
3.9
Inx, ENx high
Indication Outx
Inx, ENx high
Indication Outx
0
3.7
-50
0
50
100
T junction [°C]
-50
150
0
50
100
T junction [°C]
150
Figure 7-1 Undervoltage lockout 2ED7x (4.2V)
UVLO ON/OFF
vs
TEMPERATURE
8.8
UVLO HYSTERESIS
vs
TEMPERATURE
on value
1.1
off value
8.4
VDD delta [V]
VDD [V]
8
7.6
7.2
0.9
0.7
6.8
Inx, ENx high
Indication Outx
Inx, ENx high
Indication Outx
6.4
0.5
-50
0
50
100
T junction [°C]
150
-50
0
50
100
T junction [°C]
150
Figure 7-2 Undervoltage lockout 2ED8x (8V)
Data Sheet
22
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
INPUT THRESHOLD INx to OUTx
vs
TEMPERATURE
INx HYSTERESIS
vs
TEMPERATURE
1.2
typ ON threshold
2.7
typ OFF threshold
2.3
VINx delta [V]
VINx [V]
1.1
1.9
1.5
1
1.1
VDD=12V
VDD=12V
0.9
0.7
-50
0
50
100
T junction [°C]
-50
150
0
50
100
T junction [°C]
150
Figure 7-3 Input (INx) characteristic
INPUT THRESHOLD ENx to OUTx
vs
TEMPERATURE
ENx HYSTERESIS
vs
TEMPERATURE
1.2
typ ON threshold
2.7
typ OFF threshold
2.3
VENx delta [V]
VENx [V]
1.1
1.9
1.5
1
1.1
VDD=12V
VDD=12V
0.9
0.7
-50
0
50
100
T junction [°C]
-50
150
0
50
100
T junction [°C]
150
Figure 7-4 Input (ENx) characteristic
Data Sheet
23
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
VINx to OUTx PROPAGATION DELAY
vs
TEMPERATURE
25
VINx to OUTx PROPAGATION DELAY
vs
TEMPERATURE
25
typ turn-off
typ turn-off
typ turn-on
typ turn-on
22.5
TPD [ns]
TPD [ns]
22.5
20
17.5
20
17.5
VDD=12V
Input 5V
VDD=12V
Input 3.3V
15
15
-50
0
50
100
T junction [°C]
150
-50
0
50
100
T junction [°C]
150
Figure 7-5 Propagation delay (INx) on different input logic levels (see Figure 6-1)
VENx to OUTx PROPAGATION DELAY
vs
TEMPERATURE
25
VENx to OUTx PROPAGATION DELAY
vs
TEMPERATURE
25
typ turn-off
typ turn-on
typ turn-on
22.5
TPD [ns]
22.5
TPD [ns]
typ turn-off
20
17.5
20
17.5
VDD=12V
Enable 5V
VDD=12V
Enable 3.3V
15
15
-50
0
50
100
T junction [°C]
150
-50
0
50
100
T junction [°C]
150
Figure 7-6 Propagation delay (ENx) on different input logic levels (see Figure 6-1)
Data Sheet
24
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
OUTx RISE/FALL TIME 10% - 90%
vs
TEMPERATURE
6.5
typ turn-on
6
typ turn-off
Time [ns]
5.5
5
4.5
VDD=12V
OUTx with 1.8nF load
4
3.5
-50
0
50
100
T junction [°C]
150
Figure 7-7 Rise / fall times with load on output (see Figure 6-1)
Data Sheet
25
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
CURRENT CONSUMPTION
vs
OPERATING SUPPLY VDD
CURRENT CONSUMPTION
vs
TEMPERATURE
0.80
OUTx High
OUTx Low
0.65
IDD [mA]
IDD [mA]
0.8
0.6
0.4
0.50
OUTx High
0.35
Tj=25°C
ENx floating (VDD)
OUTx Low
0.2
0.20
0
10
VDD [V]
-50
20
0
50
100
T junction [°C]
150
CURRENT CONSUMPTION
vs
FREQUENCY
'50
Tamb 25°C
Input [email protected]
Device self-heating
Load 1.8nF serial
'40
I DD [mA]
VDD=12V
ENx NC
VDD 4,5V
'30
VDD 12V
VDD 20V
'20
'10
'0
0
250
500
750
Frequency [kHz]
1000
Figure 7-8 Power consumption related to temperature, supply voltage and frequency
Data Sheet
26
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
REVERSE CURRENT @OUTx
with OUTx HIGH
vs REVERSE VOLTAGE
REVERSE CURRENT @OUTx
with OUTx LOW
vs REVERSE VOLTAGE
-1.5
7.5
Test Conditions:
Tj = 25°C,
1µs positive Pulse
fsw = 1kHz
-3.0
2.5 W
10 W
IOUT [A]
IOUT [A]
6.0
Test Conditions:
Tj = 25°C,
1µs negative Pulse
fsw = 1kHz
4.5
7.5 W
3.0
5W
-4.5
5W
7.5 W
-6.0
10 W
2.5 W
1.5
0.0
-7.5
0.8
1.0
1.3
1.5
VOUT [V]
1.8
-2.3
2.0
-2.0
-1.8
-1.5
VOUT [V]
-1.3
-1.0
Figure 7-9 Output OUTx with reverse current and resulting power dissipation
Data Sheet
27
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
8
Outline Dimensions
Notes
1. For further information on package types, recommendation for board assembly, please go to:
http://www.infineon.com/cms/en/product/technology/packages/.
8.1
PG-DSO-8-60
Figure 8-1 PG-DSO-8 outline
Figure 8-2 PG-DSO-8 footprint
Data Sheet
28
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Figure 8-3 PG-DSO-8 packaging
8.2
PG-TSSOP-8-1
Figure 8-4 PG-TSSOP-8 outline
Data Sheet
29
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Figure 8-5 PG-TSSOP-8 footprint
Figure 8-6 PG-TSSOP-8 packaging
Data Sheet
30
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
8.3
PG-WSON-8-1
Figure 8-7 PG-WSON-8 outline
Figure 8-8 PG-WSON-8 footprint
Data Sheet
31
Revision 2.1, 2016-01-19
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Figure 8-9 PG-WSON-8 packaging
Data Sheet
32
Revision 2.1, 2016-01-19
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MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave
Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
www.infineon.com
Edition 2016-01-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG.
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