Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MM908E621
Rev. 6.0, 4/2012
Integrated Quad Half-bridge and
Triple High Side with Embedded
MCU and LIN for High End
Mirror
908E621
QUAD HALF-BRIDGE AND TRIPLE HIGH SIDE
SWITCH WITH EMBEDDED MCU AND LIN
The 908E621 is an integrated single package solution that
includes a high performance HC08 microcontroller with a
SMARTMOS analog control IC. The HC08 includes flash memory, a
timer, enhanced serial communications interface (ESCI), a 10 bit
analog-to-digital converter (ADC), internal serial peripheral interface
(SPI), and an internal clock generator module (ICG). The analog
control die provides four half-bridge and three high side outputs with
diagnostic functions, a Hall effect sensor input, analog inputs, voltage
regulator, window watchdog, and local interconnect network (LIN)
physical layer.
The single package solution, together with LIN, provides optimal
application performance adjustments and space saving PCB design.
It is well-suited for the control of automotive high end mirrors.
EK (Pb-Free)
98ASA10712D
54-PIN SOICW-EP
Features
•
•
•
•
•
•
•
•
•
•
•
High performance M68HC908EY16 core
16 KB of on-chip flash memory, 512 B of RAM
Two 16-bit, two-channel timers
LIN physical layer interface
Autonomous MCU watchdog / MCU supervision
One analog input with switchable current source
Four low RDS(ON) half-bridge outputs
Three low RDS(ON) high side outputs
Wake-up and 2 or 3-pin Hall effect sensor input
12 microcontroller I/Os
Pb-free packaging designated by suffix codes EK
ORDERING INFORMATION
VSP1:8]
LIN
VDDA/VREFH
EVDD
4.7 μF
VDD
100 nF
VSSA/VREFL
EVSS
VSS
RST A
RST
IRQ A
IRQ
PTA/KBD0
PTA1/KBD1
μC PortA
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTB3/AD3
μC PortB
PTB4/AD4
PTB5/AD5
PTC2/MCLK
μC PortC
PTC3/OSC2
PTC4/OSC1
Internally Connected PTD0/TACH0
μC PortD
PTD1/TACH1
μC PortE
Internally Connected PTE1/RXD
Device
(Add an R2 suffix for
Tape and reel orders)
Temperature
Range (TA)
Package
MM908E621ACPEK
-40 to 85°C
54 SOICW-EP
>22 μF
Wake-up Input
L0
HB1
HB2
908E621
HB3
HB4
HS1
M
M
4 x Half-brideOutputs
M
High Side Output 1
HS2
High Side Output 2
HS3
High Side Output 3
HVDD
A0
A0CST
H0
TESTMODE
Switched 5.0 V Output
Analog Input with Curet Source
Analog Input Current Source Trim
Two 3-pin Hall Sensor Input
Pull to GND for User Mode
EP
GND[1:4]
Figure 1. 908E621 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007-2012. All rights reserved.
100 nF
2
PTA6/SS
PTA5/SPSCK
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB0/AD0
PTB0/AD0
Security Module
Power-ON
Reset Module
DDRA
PORT A
PTB0/AD0
ADOUT
SPSCK
MOSI
PTC1/MOSI
PTA5/SPSCK
MISO
SS
PWM
PTC0/MISO
PTA6/SS
PTD0/TACH0
TXD
PTE0/TXD
IRQ_A
Analog
Multiplexer
SPI
&
CONTROL
Autonomous
Watchdog
Reset
Control
LIN
Physical Layer
Figure 2. 908E621 Simplified Internal Block Diagram
PTE0/TXD
PTE1/RXD
PTD0/TACH0
PTD1/TACH1
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTC1/MOSI
PTC0/MISO
BEMF Module
Prescaler Module
Arbiter Module
Periodic Wake-up
Timebase Module
Configuration
Register Module
Serial Peripheral
Interface Module
Computer Operating
Properly Module
Enhanced Serial
Communication
Interface Module
2-channel Timer
Interface Module B
PORT C
DDRC
FLSVPP
PTD1/TACH1
Single External
IRQ Module
24 Integral System
Integration Module
VREFH
VDDA 10 Bit Analog-toVREFL Digital Converter
Module
VSSA
VDD
POWER
VSS
IRQ
RST
OSC2 Internal Clock
OSC1 Generator Module
RST
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTA4/KBD4
VDDA/VREFH
User Flash Vector
Space, 36 Bytes
IRQ
PTA3/KBD3
EVDD
2-channel Timer
Interface Module A
PTD0/TACH0
RXD
PTE1/RXD
PTE1/RXD
RST_A
PTA2/KBD2
EVSS
5-Bit Keyboard
Interrupt Module
LIN
PTA1/KBD1
PTA0/KBD0
VSSA/VREFL
VSS
A0
A0CST
H0
HALLPORT
HB4
HB3
HB2
HB1
Analog Port
with Current
Source
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
HS3
HS2
High Side Driver
& Diagnostic
High Side Driver
& Diagnostic
HS1[a:b]
L0
HVDD
VDD
High Side Driver
& Diagnostic
Wakeup Port
Switched VDD
Driver &
Diagnostic
Voltage
Regulator
VSUP[1:8]
Control and Status
Register, 64 Bytes
User Flash, 15,872 Bytes
User RAM, 512 Bytes
Monitor ROM, 310 Bytes
Flash programming
(Burn-in), ROM 1024 Bytes
Single Breakpoint
Break Module
GND[1:4]
M68HC08 CPU
CPU
ALU
Registers
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
TESTMODE
PORT D PORT E
DDRD
DDRE
Internal Bus
DDRB
PORT B
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top
View of Package
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
1
54
2
53
3
52
4
51
5
50
6
49
IRQ
RST
7
48
8
47
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
9
46
10
45
RST_A
IRQ_A
11
44
12
43
LIN
A0CST
A0
GND1
HB4
VSUP1
GND2
HB3
VSUP2
NC
NC
TESTMODE
GND3
HB2
VSUP3
13
14
15
42
Exposed
Pad
41
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
(PTE1/RXD <- RXD)
VSS
VDD
HVDD
L0
H0
HS3
VSUP8
HS2
VSUP7
HS1b
HS1a
VSUP6
VSUP5
GND4
HB1
VSUP4
Figure 3. Pin Connections
Table 1. Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Die
Pin
Pin Name
Formal Name
Definition
MCU
1
2
3
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
Port C I/Os
These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
MCU
4
5
6
PTB5/AD5
PTB4/AD4
PTB3/AD3
Port B I/Os
These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
MCU
7
IRQ
External Interrupt
Input
MCU
8
RST
External Reset
MCU /
Analog
9
(PTD0/TACH0/BEMF
-> PWM)
PWM signal
This pin is an asynchronous external interrupt input pin.
This pin is bidirectional, allowing a reset of the entire system. It is driven
low when any internal reset source is asserted.
This pin is the PWM signal test pin. It internally connects the MCU
PTD0/TACH0 pin with the Analog die PWM input.
Note: Do not connect in the application.
MCU
10
PTD1/TACH1
Port D I/Os
This pin is a special function, bidirectional I/O port pin that is shared with
other functional modules in the MCU.
MCU /
Analog
44
(PTE1/RXD <- RXD)
LIN Transceiver
Output
This pin is the LIN Transceiver output test pin. It internally connects the
MCU PTE1/RXD pin with the Analog die LIN transceiver output pin
RXD.
Note: Do not connect in the application.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Die
Pin
Pin Name
Formal Name
Definition
MCU
45
VSSA/VREFL
VDDA/VREFH
ADC Supply and
48
Reference Pins
These pins are the power supply and voltage reference pins for the
analog-to-digital converter (ADC).
MCU
46
47
EVSS
EVDD
MCU Power Supply
Pins
These pins are the ground and power supply pins, respectively. The
MCU operates from a single power supply.
MCU
49
50
52
53
54
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
Port A I/Os
MCU
51
FLSVPP
Test Pin
Analog
11
RST_A
Internal Reset
Analog
12
IRQ_A
Internal Interrupt
Output
Analog
13
LIN
LIN Bus
Analog
14
A0CST
Analog Input Trim Pin
Analog
15
A0
Analog Input Pin
Analog
16
19
25
30
GND1
GND2
GND3
GND4
Power Ground Pins
These pins are device power ground connections.
Analog
29
26
20
17
HB1
HB2
HB3
HB4
Half-bridge Outputs
This device includes power MOSFETs configured as four half-bridge
driver outputs. These outputs may be configured for DC motor drivers,
or as high side and low side switches.
Analog
18
21
27
28
31
32
35
VSUP1
VSUP2
VSUP3
VSUP4
VSUP5
VSUP6
VSUP7
Power Supply Pins
–
22
23
NC
NC
No Connect
Analog
24
TESTMODE
TESTMODE Input
Analog
34
35
HS1a
HS1b
High Side HS1 Output This output pin is a low RDS(ON) high side switch.
Analog
36
HS2
High Side HS2 Output These output pins are low RDS(ON) high side switches.
High Side HS3 Output
38
HS3
Analog
39
H0
Hall-Effect Sensor /
General Purpose
Input
Analog
40
L0
Wake-up Input
This pin provides an high voltage input, which is wake-up capable.
Analog
41
HVDD
Switchable VDD
Output
This pin is a switchable VDD output for driving resistive loads requiring
a regulated 5.0 V supply; e.g. potentiometers.
Analog
42
VDD
Voltage Regulator
Output
These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
For test purposes only. Do not connect in the application.
This pin is the bidirectional reset pin of the analog die.
This pin is the interrupt output pin of the analog die indicating errors or
wake-up events.
This pin represents the single wire bus transmitter and receiver.
This is the analog input trim pin for the A0 input. This is to connect a
known fixed resistor value to trim the current source measurement.
This pin is an analog input port with selectable source values.
Note: The HB3 and HB4 have a lower RDS(ON) then HB1 and HB2.
These pins are device power supply pins.
These pins are not connected.
Pin for test purpose only. In application this pin needs to be tied GND.
This pin provides an input for a Hall-effect sensor or general purpose
input.
The +5. V voltage regulator output pin is intended to supply the
embedded microcontroller.
908E621
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Die
Pin
Pin Name
Formal Name
Analog
43
VSS
Voltage Regulator
Ground
–
EP
Exposed Pad
Exposed Pad
Definition
Ground pin for the connection of all non-power ground connections
(microcontroller and sensors).
The exposed pad pin on the bottom side of the package conducts heat
from the chip to the PCB board.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding limits on any pin may cause permanent damage
to the device.
Rating
Symbol
Value
Unit
Analog Chip Supply Voltage under Normal Operation (Steady-state)
VSUP(SS)
-0.3 to 28
Analog Chip Supply Voltage under Transient Conditions(1)
VSUP(PK)
-0.3 to 40
VDD
-0.3 to 5.5
VIN(ANALOG)
-0.3 to 5.5
VIN(MCU)
VSS -0.3 to VDD +0.3
All Pins except VDD, VSS, PTA0:PTA4
IPIN(1)
±15
PTA0:PTA4
IPIN(2)
±25
Maximum Microcontroller VSS Output Current
IMVSS
100
mA
Maximum Microcontroller VDD Input Current
IMVDD
100
mA
Normal Operation (Steady-state)
VBUS(SS)
-18 to 40
Transient Input Voltage (per ISO7637 Specification) and with
External Components (Figure 4, page 16)
VBUS(PK)
-150 to 100
Human Body Model H0 pin
VESD1-1
±1000
Human Body Model all other pins
VESD1-2
±2000
ELECTRICAL RATINGS
Supply Voltage
MCU Chip Supply Voltage
V
Input Pin Voltage
Analog Chip
Microcontroller Chip
V
Maximum Microcontroller Current per Pin
mA
LIN Supply Voltage
V
ESD Voltage(2)
V
Machine Model
VESD2
±200
Charge Device Model
VESD3
±750
Notes
1. Transient capability for pulses with a time of t < 0.5 sec.
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model
(CZAP =200 pF, RZAP = 0 Ω) and the Charge Device Model, Robotic (CZAP = 4.0 pF).
908E621
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground, unless otherwise noted. Exceeding limits on any pin may cause permanent damage
to the device.
Rating
Symbol
Value
Unit
Operating Ambient Temperature(3)
TA
-40 to 85
°C
Operating Junction Temperature(4)
TJ
-40 to 125
°C
Storage Temperature
TSTG
-40 to 150
°C
Peak Package Reflow Temperature During Reflow(5), (6)
TPPRT
Note 6
°C
THERMAL RATINGS
Notes
3. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.
4. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because
of higher power dissipation on the analog die. The analog die temperature must not exceed 150 °C under these conditions.
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP1
9.0
—
16
V
VSUP2
7.5
—
20
V
IRUN
—
25
—
mA
ISTOP
—
40
50
μA
ISLEEP
—
12
20
μA
Low-state Output Voltage (IOUT = -1.5 mA)
VOL
–
–
0.4
High-state Output Voltage (IOUT = 250 μA)
VOH
3.85
–
–
COUT
–
4.0
–
SUPPLY VOLTAGE RANGE
Nominal Operating Voltage
Extended Operating Voltage (LIN only 8…18
V)(8)
SUPPLY CURRENT RANGE
Normal Mode(8)
VSUP = 12 V, Analog Chip in Normal Mode (PSON=1), MCU Operating
Using Internal Oscillator at 32 MHz (8.0MHz Bus Frequency), SPI, ESCI,
ADC Enabled
Stop Mode(8), (9)
VSUP = 12 V, Voltage Regulator with limited current capability
Sleep Mode(8), (9)
VSUP = 12 V, Voltage Regulator off
DIGITAL INTERFACE RATINGS (ANALOG DIE)
V
Output pins RST_A, IRQ_A, RXD (MISO probe only)
Output pin RXD - Capacitance(10)
Input pins RST_A, PWM (SS, MOSI, TXD probe only)
pF
V
Input Logic Low Voltage
VIL
–
–
1.5
Input Logic High Voltage
VIH
3.5
–
–
Input pins - Capacitance(10)
CIN
–
4.0
–
pF
Pins IRQ_A, RST_A - Pull-up Resistor
RPULLUP1
–
10
–
kΩ
Pins SS - Pull-up Resistor
RPULLUP2
–
100
–
kΩ
RPULLDOWN
–
100
–
kΩ
IPULLUP
–
35
–
μA
Pins MOSI, SPSCK, PWM - Pull-down Resistor
Pin TXD - Pull-up Current Source
Notes
7. Device is fully functional, but some of the parameters might be out of spec.
8. Total current measured at GND pins.
9. Stop and Sleep mode current will increase if VSUP exceeds 15 V.
10.
This parameter is guaranteed by process monitoring but is not production tested.
908E621
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VLVRON
3.8
4.2
4.65
V
VLVR_HYS
50
–
300
mV
Threshold
VLVION
6.0
–
7.5
Hysteresis
VLVI_HYS
0.3
–
0.8
Threshold
VHVION
20
–
24
Hysteresis
VHVI_HYS
0.5
–
1.5
TION
125
–
150
TIH
5.0
–
10.0
TRON
155
–
180
TIH
5.0
–
10.0
IOUT = 60 mA, 7.5 V < VSUP < 20 V
VDDRUN1
4.75
5.0
5.25
IOUT = 60 mA, VSUP < 7.5 V and VSUP > 20 V
VDDRUN2
4.75
5.0
5.25
IOUTRUN
–
120
150
mA
VLR
–
–
100
mV
STOP Mode Output Voltage(13)
VDDSTOP
4.75
5.0
5.25
V
STOP Mode Total Output Current
IOUTSTOP
150
500
1100
μA
SYSTEM RESETS AND INTERRUPTS
Low Voltage Reset (LVR)
Threshold
Hysteresis
Low Voltage Interrupt (LVI)
V
V
High Voltage Interrupt (HVI)
°C
High Temperature Interrupt (HTI)(11)
Threshold TJ
Hysteresis
°C
High Temperature Reset (HTR)(11)
Threshold TJ
Hysteresis
VOLTAGE REGULATOR(12)
V
Normal Mode Output Voltage(13)
Normal Mode Total Output Current
Load Regulation - IOUT = 60 mA, VSUP = 9.0 V, TJ = 125 °C
Notes
11. This parameter is guaranteed by process monitoring but is not production tested.
12. Specification with external low ESR ceramic capacitor 1.0 μF< C < 4.7 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Its not recommended to use
capacitor values above 4.7 μF
13. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage
specification.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Recessive State, TXD HIGH, IOUT = 1.0 μA
V LIN_REC
VSUP -1
—
—
Dominant State, TXD LOW, 500 Ω External Pull-up Resistor
V LIN_DOM
—
—
1.4
Normal Mode Pull-up Resistor to VSUP
R PU
20
30
47
kΩ
Stop, Sleep Mode Pull-up Current Source
IPU
—
20
—
μA
Output Current Shutdown Threshold
IBLIM
100
230
280
mA
Output Current Shutdown Timing
IBLS
5.0
–
40
µs
µA
LIN PHYSICAL LAYER
LIN Transceiver Output Voltage
V
Leakage Current to GND
IBUS
–
1.0
10
IBUS-PAS-REC
0.0
3.0
20
µA
IBUS-NOGND
-1.0
–
1.0
mA
Receiver Threshold Dominant
VBUS_DOM
–
–
0.4
Receiver Threshold Recessive
VBUS_REC
0.6
–
–
Receiver Threshold Center
VBUS_CNT
0.475
0.5
0.525
Receiver Threshold Hysteresis
VBUS_HYS
–
–
0.175
RDS(ON)-HS1
–
185
225
IHSOC1
6.0
–
9.0
A
tOCB
–
4-8
–
µs
CRRATIOHS1
0.84
1.2
1.56
V/A
fPWMHS
–
–
25
kHz
VHSF
–
0.9
–
V
ILeakHS
–
<0.2
10
µA
VSUP Disconnected, VBUS at 18 V
Recessive state, 8.0 V ≤ VSUP ≤ 18 V, 8.0 V ≤ VBUS ≤ 18 V, VBUS ≥ VSUP
GND Disconnected, VGND = VSUP, VBUS at -18 V
VSUP
LIN Receiver
HIGH SIDE OUTPUT HS1
Switch On Resistance
mΩ
TJ = 25 °C, ILOAD = 1.0 A
Over-current Shutdown
Over-current Shutdown blanking time
(14)
Current to Voltage Ratio(15)
VADOUT [V] / IHS [A], (measured and trimmed IHS = 2.0 A)
High Side Switching Frequency(14)
High Side Freewheeling Diode Forward Voltage
TJ = 25 °C, ILOAD = 1.0 A
Leakage Current
Notes
14. This parameter is guaranteed by process monitoring but is not production tested.
15. This parameter is guaranteed only if correct trimming was applied.
908E621
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
RDS(ON)-HS23
–
440
500
IHSOC23
3.6
–
5.6
A
tOCB
–
4-8
–
µs
CRRATIOHS23
1.16
1.66
2.16
V/A
fPWMHS
–
–
25
kHz
VHSF
–
0.9
–
V
ILEAKHS
–
<0.2
10
µA
High Side, TJ = 25°C, ILOAD = 1.0A
–
750
900
Low Side, TJ = 25°C, ILOAD = 1.0A
–
750
900
High Side
1.0
–
1.5
Low Side
1.0
–
1.5
HIGH SIDE OUTPUTS HS2 AND HS3(18)
Switch On Resistance
mΩ
TJ = 25 °C, ILOAD = 1.0 A
Over-current Shutdown
Over-current Shutdown blanking
Current to Voltage
time(16)
Ratio(17)
VADOUT [V] / IHS [A], (measured and trimmed IHS = 2.0 A)
High Side Switching Frequency(16)
High Side Freewheeling Diode Forward Voltage
TJ = 25 °C, ILOAD = 1.0 A
Leakage Current
HALF-BRIDGE OUTPUTS HB1 AND HB2
Switch On Resistance
Over-current Shutdown
RDS(ON)-HB12
mΩ
IHBOC12
A
Over-current Shutdown blanking time(19)
tOCB
–
4-8
–
μs
Switching Frequency(19)
fPWM
–
–
25
kHz
High Side, TJ = 25 °C, ILOAD = 1.0 A
VHSF
–
0.9
–
Low Side, TJ = 25 °C, ILOAD = 1.0 A
VLSF
–
0.9
–
ILEAKHB
–
<0.2
10
VADOUT [V] / IHB [A], CSA = 1, (measured and trimmed IHB = 200 mA)
17.5
25.0
32.5
VADOUT [V] / IHB [A], CSA = 0, (measured and trimmed IHB = 500 mA)
3.5
5.0
6.5
Freewheeling Diode Forward Voltage
Leakage Current
Low Side Current to Voltage Ratio(20)
Notes
16.
17.
18.
19.
20.
V
µA
V/A
CRRATIOHB12
This parameter is guaranteed by process monitoring but is not production tested.
This parameter is guaranteed only if correct trimming was applied.
The high side HS3 can be only used for resistive loads.
This parameter is guaranteed by process monitoring but is not production tested.
This parameter is guaranteed only if correct trimming was applied
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
High Side, TJ = 25 °C, ILOAD = 1.0 A
–
275
325
Low Side, TJ = 25 °C, ILOAD = 1.0 A
–
275
325
High Side
4.8
–
7.2
Low Side
4.8
–
7.2
Unit
HALF-BRIDGE OUTPUTS HB3 AND HB4
Switch On Resistance
Over-current Shutdown
mΩ
RDS(ON)-HB34
IHBOC34
A
Over-current Shutdown blanking time(21)
tOCB
–
4-8
–
μs
Switching Frequency(21)
fPWM
–
–
25
kHz
High Side, TJ = 25 °C, ILOAD = 1.0 A
VHSF
–
0.9
–
Low Side, TJ = 25 °C, ILOAD = 1.0 A
VLSF
–
0.9
–
ILEAKHB
–
<0.2
10
VADOUT [V] / IHB [A], CSA = 1, (measured and trimmed IHB = 500 mA)
3.5
5.0
6.5
VADOUT [V] / IHB [A], CSA = 0, (measured and trimmed IHB = 2.0 A)
0.7
1.0
1.3
25
35
50
HVDDT1:0 = 00
–
950
–
HVDDT1:0 = 01
–
536
–
HVDDT1:0 = 10
–
234
–
HVDDT1:0 = 11
–
78
–
Freewheeling Diode Forward Voltage
Leakage Current
Low Side Current to Voltage Ratio(22)
V
CRRATIOHB34
µA
V/A
SWITCHABLE VDD OUTPUT HVDD
Over-current Shutdown
IHVDDOC
Over-current Shutdown Blanking Time(23)
tHVDDOCB
mA
µs
Over-current Flag Delay(23)
tHVDDOCFD
–
0.5
–
ms
Dropout Voltage @ ILOAD = 20 mA
VHVDDDROP
–
110
300
mV
RATIOVSUP
4.75
5.0
5.25
–
STTOV
–
26
–
mV/°C
VT25
1.7
1.9
2.1
V
VSUP DOWN SCALER(24)
Voltage Ratio (RATIO VSUP = VSUP / VADOUT)
INTERNAL DIE TEMPERATURE SENSOR(24)
Voltage / Temperature Slope(23)
Output Voltage @25°C
Notes
21.
22.
23.
24.
This parameter is guaranteed by process monitoring but is not production tested.
This parameter is guaranteed only if correct trimming was applied
This parameter is guaranteed by process monitoring but is not production tested.
This parameter is guaranteed only if correct trimming was applied
908E621
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
HALL-EFFECT SENSOR INPUT H0 - GENERAL PURPOSE INPUT MODE (H0MS = 0)
Input Voltage Low Threshold
VLT
–
–
1.5
V
Input Voltage High Threshold
VHT
3.5
–
–
V
Input Voltage Hysteresis
VHH
100
–
500
mV
Pull-up resistor
RPH
7.0
10
13
kΩ
HALL-EFFECT SENSOR INPUT H0 - 2PIN HALL SENSOR INPUT MODE (H0MS = 1)
V
Output Voltage
VSUP < 17 V
VHALL1
–
VSUP-1.2
–
VSUP >17 V
VHALL2
–
–
15.8
Output Drop @ IOUT = 15 mA
VH0D
–
–
2.5
V
Sense Current Threshold
IHSCT
6.0
7.9
10
mA
Sense Current Hysteresis
IHSCH
650
–
1650
µA
Sense Current Limitation
VHSCLIM
20
40
70
mA
CSSEL1:0 = 00
ICS1
–
40
–
CSSEL1:0 = 01
ICS2
–
120
–
ICS3
–
320
–
ICS4
–
800
–
Input Voltage Threshold Low
VLT
–
–
1.5
V
Input Voltage Threshold High
VHT
3.5
–
–
V
Input Voltage Hysteresis
VLH
0.5
–
–
V
IN
-10
–
10
µA
tWUP
–
20
–
µs
ANALOG INPUT A0, A0CST
µA
Current Source A0, A0CST(25), (26)
CSSEL1:0 = 10
CSSEL1:0 = 11
WAKE-UP INPUT L0
Input Current
Wake-up Filter Time(27)
Notes
25. This parameter is guaranteed only if correct trimming was applied
26. The current values are optimized to read a NTC temperature sensor, e.g. EPCOS type B57861 (R25 = 3000Ω, R/T characteristic 8016)
27. This parameter is guaranteed by process monitoring but is not production tested.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Dominant Propagation Delay TXD to LIN
t DOM-MIN
—
—
50
μs
Dominant Propagation Delay TXD to LIN
t DOM-MAX
—
—
50
μs
Recessive Propagation Delay TXD to LIN
t REC-MIN
—
—
50
μs
Recessive Propagation Delay TXD to LIN
t REC-MAX
—
—
50
μs
Duty Cycle 1: D1 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 50 μs, VSUP = 7.0 V…18 V
D1
0.396
–
–
Duty Cycle 2: D2 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 50 μs, VSUP = 7.6 V…18 V
D2
–
–
0.581
Dominant Propagation Delay TXD to LIN
t DOM-MIN
—
—
100
μs
Dominant Propagation Delay TXD to LIN
t DOM-MAX
—
—
100
μs
Recessive Propagation Delay TXD to LIN
t REC-MIN
—
—
100
μs
Recessive Propagation Delay TXD to LIN
t REC-MAX
—
—
100
μs
Duty Cycle 3: D3 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 96 μs, VSUP = 7.0 V…18 V
D3
0.417
–
–
Duty Cycle4: D4 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 96 μs, VSUP = 7.6 V…18 V
D4
–
–
0.590
SRFAST
—
20
—
V/μs
Receiver Dominant Propagation Delay(31)
t RL
—
3.5
6.0
μs
Receiver Recessive Propagation Delay(31)
t RH
—
3.5
6.0
μs
t R-SYM
-2.0
—
2.0
μs
t PROPWL
30
50
150
μs
t WAKE
—
20
—
μs
LIN PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate(28), (29)
Driver Characteristics for Slow Slew Rate(28), (30)
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
Receiver Characteristics and Wake-up Timings
Receiver Propagation Delay Symmetry
Bus Wake-up Deglitcher
Bus Wake-up Event Reported
(32)
Notes
28. VSUP from 7.0 to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
29. See Figure 6, page 16.
30. See Figure 7, page 17.
31. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal.
32.
t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 17. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD pin.
908E621
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MICROCONTROLLER PARAMETRICS
Table 4. Dynamic Electrical Characteristics (continued)
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPIOP
0.25
—
4.0
MHz
tRST
0.8
1.25
1.94
ms
tNORMREQ
51
80
150
ms
Watchdog Period (WDP1:0 = 00)
tWD80
52
80
124
ms
Watchdog Period (WDP1:0 = 01)
tWD40
26
40
62
ms
Watchdog Period (WDP1:0 = 10)
tWD20
13
20
31
ms
Watchdog Period (WDP1:0 = 11)
tWD10
6.5
10
15.5
ms
SPI INTERFACE TIMING
SPI Operating Recommended Frequency(33)
State Machine
Reset Low Level Duration after VDD High
Normal Request Timeout
Window Watchdog Timer(34)
Notes
33. This parameter is guaranteed by process monitoring but is not production tested.
34. This parameter is guaranteed only if correct trimming was applied. Additionally See Watchdog Period Range Value (AWD Trim) on page
46
MICROCONTROLLER PARAMETRICS
Table 5. Microcontroller
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module
Description
Core
High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz
Timer
Two 16-Bit Timers with 2 Channels (TIM A and TIM B)
Flash
16 k Bytes
RAM
512 Bytes
ADC
10-Bit Analog-to-Digital Converter
SPI
SPI Module
ESCI
Standard Serial Communication Interface (SCI) Module
Bit-Time Measurement
Arbitration
Prescaler with Fine Baud Rate Adjustment
ICG
Internal Clock Generation Module
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Transient Pulse
Generator
LIN, L0
10k
1nF
Note: Waveform in accordance to ISO7637 part 1, test pulses 1, 2, 3a and 3b.
Figure 4. Test Circuit for Transient Test Pulses
VSUP
VSUP
R0
TXD
LIN
RXD
C0
R0R0
and
C0C0
Combinations:
and
combinations:
‚Ä¢ 1.0 kΩ and 1.0
- 1k Ohm and 1nF
•- 600
Ω and
6.86.8nF
660 Ohm
and
•- 500
Ω and
1010nF
500 Ohm
and
Figure 5. Test Circuit for LIN Timing Measurements
TXD
tREC-MAX
VLIN
tDOM-MIN
58.1% VSUP
LIN
74.4% VSUP
40% VSUP
60% VSUP
28.4% VSUP
42.2% VSUP
tDOM-MAX
tREC-MIN
RXD
tRL
tRH
Figure 6. LIN Timing Measurements for Normal Slew Rate
908E621
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tREC-MAX
VLIN
tDOM-MIN
61.6% VSUP
LIN
77.8% VSUP
40% VSUP
60% VSUP
25.1% VSUP
38.9% VSUP
tDOM-MAX
tREC-MIN
RXD
tRL
tRH
Figure 7. LIN Timing Measurements for Slow Slew Rate
VLIN_REC
Vrec
LIN
0.4VSUP
0.4 VSUP
Dominant
Level
Dominant level
IRQ_A
tTpropWL
PROPWL
tTwake
WAKE
Figure 8. Wake-up Stop Mode Timing
Vrec
VLIN_REC
LIN
0.4VSUP
0.4 V
SUP
Dominant
Level
Dominant level
VDD
tTpropWL
PROPWL
tTwake
WAKE
Figure 9. Wake-up Sleep Mode Timing
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VSUP
VDD
RST_A
TRST
TNORMREQ
Figure 10. Power On Reset and Normal Request Timeout Timing
908E621
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E621 was designed and developed as a highly
integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
908E621 is well suited to perform complete mirror control via
a three wire LIN bus.
switches. Other ports are also provided, which include one
Hall-effect sensor input port, one analog input port with a
switched current source, one wake-up pin, and a selectable
HVDD pin. An internal voltage regulator provides power to
the MCU chip.
This device combines an HC908EY16 MCU core with
flash memory together with a SMARTMOS IC chip. The
SMARTMOS IC chip combines power and control in one
chip. Power switches are provided on the SMARTMOS IC
configured as half-bridge outputs and three high side
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables this device
to be compatible with three wire bus systems, where one wire
is used for communication, one for battery, and one for
ground.
FUNCTIONAL PIN DESCRIPTION
See Figure 2, 908E621 Simplified Internal Block Diagram,
page 2, for a graphic representation of the various pins
referred to in the following paragraphs. Also, see the pin
diagram on page 3 for a depiction of the pin locations on the
package.
PORT A I/O PINS
These pins are special function, bidirectional I/O port pins
that are shared with other functional modules in the MCU.
PTA0:PTA4 are shared with the keyboard interrupt pins,
KBD0:KBD4.
The PTA5/SPSCK pin is not accessible in this device and
is internally connected to the SPI clock pin of the analog die.
The PTA6/SS pin is not accessible in this device and is
internally connected to the SPI slave select input of the
analog die.
For details refer to the 68HC908EY16 datasheet.
PORT B I/O PINS
These pins are special function, bidirectional I/O port pins
that are shared with other functional modules in the MCU. All
pins are shared with the ADC module.
PTB0/AD0 is internally connected to the ADOUT pin of the
analog die, allowing diagnostic measurements to be
calculated (e.g., current recopy, VSUP, etc.).
The PTB1/AD1, PTB2/AD2, PTB6/AD6/TBCH0, PTB7/
AD7/TBCH1 pins are not accessible in this device.
For details refer to the 68HC908EY16 datasheet.
PORT C I/O PINS
These pins are special function, bidirectional I/O port pins
that are shared with other functional modules in the MCU. For
example, PTC2:PTC4 are shared with the ICG module.
PTC0/MISO and PTC1/MOSI are not accessible in this
device and are internally connected to the MISO and MOSI
SPI pins of the analog die.
For details refer to the 68HC908EY16 datasheet.
PORT D I/O PINS
PTD0/TACH0/BEMF and PTD1/TACH1 are special
function, bi-directional I/O port pins that can also be
programmed to be timer pins.
PTD0/TACH0 pin is internally connected to the PWM input
of the analog die and only accessible for test purposes (can
not be used in the application).
For details refer to the 68HC908EY16 datasheet.
PORT E I/O PIN
PTE0/TXD and PTE1/RXD are special function,
bidirectional I/O port pins that can also be programmed to be
enhanced serial communication.
PTE0/TXD is internally connected to the TXD pin of the
analog die. The connection for the receiver must be done
externally.
PTE1/RXD is internally connected to the RXD pin of the
analog die and only accessible for test purposes (can not be
used in the application).
For details refer to the 68HC908EY16 datasheet.
EXTERNAL INTERRUPT PIN (IRQ)
The IRQ pin is an asynchronous external interrupt pin. This
pin contains an internal pull-up resistor that is always
activated, even when the IRQ pin is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
EXTERNAL RESET PIN (RST)
HALL-EFFECT SENSOR INPUT PIN (H0)
A logic [0] on the RST pin forces the MCU to a known
startup state. RST is bidirectional, allowing a reset of the
entire system. It is driven LOW when any internal reset
source is asserted.
The Hall-effect sensor input pin H0 provides an input for
Hall-effect sensors (2-pin or 3-pin) or a switch.
This pin contains an internal pull-up resistor that is always
activated, even when the reset pin is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
These pins are analog inputs with selectable current
source values. The A0CST intent is to trim the A0 input.
ANALOG INPUT PINS (A0, A0CST)
WAKE-UP INPUT PIN (L0)
POWER SUPPLY PINS (VSUP1:VSUP8)
VSUP1:VSUP8 are device power supply pins. The
nominal input voltage is designed for operation from 12 V
systems. Owing to the low ON-resistance and current
requirements of the half-bridge driver outputs and high side
output drivers, multiple VSUP pins are provided.
All VSUP pins must be connected to get full chip
functionality.
POWER GROUND PINS (GND1:GND4)
GND1:GND4 are device power ground connections.
Owing to the low ON-resistance and current requirements of
the half-bridge driver outputs and high side output drivers,
multiple pins are provided.
GND1 and GND2 pins must be connected to get full chip
functionality.
HALF-BRIDGE OUTPUT PINS (HB1:HB4)
This pin is 40 V rated input. It can be used as wake-up
source for a system wake-up. The input is falling or rising
edge sensitive.
Important: If unused this pin should be connected to
VSUP or GND to avoid parasitic transitions. In Low Power
mode this could lead to random wake-up events.
SWITCHABLE VDD OUTPUT PIN (HVDD)
The HVDD pin is a switchable VDD output for driving
resistive loads requiring a regulated 5.0 V supply (e.g., 3 pin
Hall-effect sensors or potentiometers). The output is shortcircuit protected.
LIN BUS PIN (LIN)
The LIN pin represents the single wire bus transmitter and
receiver. It is suited for automotive bus systems and is based
on the LIN bus specification.
The 908E621 device includes power MOSFETs
configured as four half-bridge driver outputs. The HB3:HB4
have a lower RDS(ON), to run higher currents (e.g. fold motor),
than the HB1:B2 outputs.
+5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD)
The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy.
Over-current protection is done on both high side and low
side FET’s. The current recopy are done on the low side
MOSFETs.
Important: The VDD pin should not be used to supply
other loads; use the HVDD pin for this purpose. The VDD,
EVDD and VDDA/VREFH pins must be connected together.
HIGH SIDE OUTPUT PINS (HS1:HS3)
The VSS pin is the ground pin for the connection of all nonpower ground connections (microcontroller and sensors).
Important: VSS, EVSS and VSSA/VREFL pins must be
connected together.
The HS output pins are a low RDS(ON) high side switches.
Each HS switch is protected against over-temperature and
over-current. The output is capable of limiting the inrush
current with an automatic PWM or feature a real PWM
capability using the PWM input.
The VDD pin is needed to place an external capacitor to
stabilize the regulated output voltage. The VDD pin is
intended to supply the embedded microcontroller.
VOLTAGE REGULATOR GROUND PIN (VSS)
RESET PIN (RST_A)
The HS1 has a lower RDS(ON), to run higher currents (e.g.
heater), than the HS2 and HS3 outputs.
RST_A is the bidirectional reset pin of the analog die. It is
an open drain with pullup resistor and must be connected to
the RST pin of the MCU.
For the HS1 two pins (HS1a:HS1b) are necessary for the
current capability and have to be connected externally.
INTERRUPT PIN (IRQ_A)
Important: The HS3 can be only used to drive resistive
loads.
IRQ_A is the interrupt output pin of the analog die
indicating errors or wake-up events. It is an open drain with
pullup resistor and must be connected to the IRQ pin of the
MCU.
908E621
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ADC SUPPLY/REFERENCE PINS (VDDA/VREFH
AND VSSA/VREFL)
VDDA and VSSA are the power supply pins for the analogto-digital converter (ADC).
VREFH and VREFL are the reference voltage pins for the
ADC.
The supply and reference signals are internally connected.
It is recommended that a high quality ceramic decoupling
capacitor be placed between these pins.
For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY PINS (EVDD AND EVSS)
EVDD and EVSS are the power supply and ground pins.
The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
VDDA/VREFH
EVDD
VDD
0,1µF
µC
Analog
Die
4,7µF
EVSS
TEST MODE PIN (TESTMODE)
This pin is for test purpose only. In the application this pin
has to be forced to GND.
For Programming/Test this pin has to be forced to VDD to
bring the analog die into Test mode. In Test mode the Reset
Timeout (80 ms) is disabled and the LIN receiver is disabled
NOTE: After detecting a RESET (internal or external), the
PSON bit needs to be set within 80 ms. If not, the device will
automatically enter sleep mode.
MCU TEST PIN (FLSVPP)
This pin is for test purposes only. This pin should either be
left open (not connected) or can be connected to GND.
NO CONNECT PINS (NC)
The NC pins are not connected internally.
Note: Each of the NC pins can be left open or connected
to ground (recommended).
EXPOSED PAD PIN
The exposed pad pin on the bottom side of the package
conducts heat from the chip to the PCB board. For thermal
performance, the pad must be soldered to the PCB board. It
is recommended that the pad be connected to the ground
potential.
VSS
VSSA/VREFL
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MM908E621 - Functional Block Diagram
SMARTMOS Analog Control IC
MC68HC908EY16 Core
Internal Regulators & Safety
M68HC08 CPU
w/ ALU, RAM, Flash ROM
Voltage Regulation
Reset, IRQ & Wake-up
Switched VDD
Power Module
w/Power-On Reset
Watchdog Timer
Internal Clock Module
Control & Interface
Hall Sensor Interface
Analog Multiplexer
LIN Interface
SPI Interface & PWM Control
10-Bit ADC Module
I/O Ports A, B, C, D, E
Analog Input w/Integrated Current Source
Outputs
Timer Modules
High Side Drivers & Diagnostics
Communication Modules
H-Bridge Drivers & Diagnostics
Reset & IRQ
Internal Regulators & Safety
Control & Interface
Outputs
MC68HC908EY16 Core
SMARTMOS ANALOG CONTROL IC
INTERNAL REGULATORS & SAFETY:
VOLTAGE REGULATION
The voltage regulator circuitry provides the regulated
voltage for the Analog IC as well as the VDD/VSS rails for the
core IC. The on-chip regulator consists of two elements, the
main regulator, and the low voltage reset circuit. The VDD
regulator accepts an unregulated input supply, and provides
a regulated VDD supply to all digital sections of the device.
The output of the regulator is also connected to the VDD pin,
to provide the 5.0 V to the microcontroller.
watchdog reset event will reset all registers in the SPI,
excluding the RSR.
RESET, IRQ & WAKE-UP
There are several functions on the Analog IC that can
generate a reset or wake-up signal to the core IC. There is a
pin that is used to detect an external wake-up event. The
Reset signal has many possible sources in the Analog IC
circuitry. The IRQ function on the Analog IC, will notify the
core IC of pending system critical conditions.
CONTROL & INTERFACE:
SWITCHED VDD
This function provides a switchable +5.0 V VDD rail for an
external load.
WATCHDOG TIMER
HALL SENSOR INTERFACE
This interface can be configured to support an input pin as
a general purpose input, or as a hall-effect sensor input, to be
able to read 3-pin / 2-pin hall sensors or switches.
The watchdog timer module generates a reset, in case of
a watchdog timeout or wrong watchdog timer reset. A
908E621
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
SPI INTERFACE & PWM CONTROL
The SPI and PWM interfaces are mastered by the core IC
(CPU), and are used to control the output functions of the
Analog IC, as well as to report status and failure information
of the Analog IC.
LIN INTERFACE
MM68HC908EY16 CORE IC
M68HC08 CPU W/ALU, RAM, FLASH ROM
This possesses the functionality of the CPU08
architecture, along with 512 bytes of RAM and 15,872 bytes
of FLASH memory, with in-circuit programming.
The LIN interface function supports the single wire bus
transmit and receive capabilities. It is suited for automotive
bus systems and is based on the LIN bus/physical layer
specification. The LIN driver is a low side MOSFET with slope
control, internal current limitation, and thermal shutdown.
POWER MODULE W/P0WER-ON-RESET
ANALOG MULTIPLEXER
INTERNAL CLOCK MODULE
To be able to have different sources for the MCU with one
single signal, an analog multiplexer is integrated in the analog
IC. This multiplexer has eleven different sources on the
Analog IC, which can be selected with the SS[3:0] bits
(through SPI communication) in the A0MUCTL register.
This module provides the clocks needed by the core IC
functions, without the need for external components.
Software selectable bus frequencies are available. It also
provides a clock monitor function.
This block of circuitry manages the power supplied to the
core IC, as well as providing POR, LVI, Watchdog timer, and
MCU supervision circuitry (COP).
10-BIT ADC MODULE
ANALOG INPUT W/INTEGRATED CURRENT
SOURCE
The terminal A0 provides a switchable current source, to
allow the reading of switches, NTC, etc., without the need for
an additional supply line for the sensor (single wire). There
are four different selectable current source values.
This module provides an 8-channel, 10-bit successive
approximation analog-to-digital converter (ADC).
I/O PORTS A, B, C, D, E
There are many I/O pins that are controlled by the CPU
through the several I/O ports of the core IC.
OUTPUTS:
TIMER MODULES
HIGH SIDE DRIVERS & DIAGNOSTICS
There are two 16-bit, 2 channel timer interface modules
with selectable input capture, output compare, and PWM
capabilities, for each channel.
The HS outputs are low RDS(ON) high side switches.
Each HS switch is protected against over-temperature and
over-current. The output is capable of limiting the inrush
current with an automatic PWM, or feature a real PWM
capability using the PWM input.
H-BRIDGE DRIVERS & DIAGNOSTICS
The device includes power MOSFETs configured as four
half-bridge driver outputs. These outputs are short-circuit and
over-temperature protected. Over-current protection is done
on both high side and low side MOSFETs.
COMMUNICATION MODULES
There are several communication functions supported by
the core IC, including an enhanced serial communication
interface module (ESCI) for the LIN communication, and an
SPI module for inter-IC communication.
RESET & IRQ
There are interrupt and reset connections between the
Analog IC and the core IC, for concise control and error/
exception management.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Power Up
RESET
VDD High and Reset Delay (tRST) expired
Normal
Request
PSON = 0 and Normal Request
timeout (tNORMREQ) expired
Reset (LVR, HTR, WDR, ext. Reset)
PSON = 1
VDD Low
NORMAL
SLEEP Command
Wake-Up Interrupt
Power
Down
TESTMODE = 1
The 908E621 offers three operating modes: Normal (Run),
Stop, and Sleep. In Normal mode, the device is active and is
operating under normal application conditions. The Stop and
Sleep modes are low power modes with wake-up capabilities.
The different modes can be selected by the STOP and
SLEEP bits in the System Control Register.
Figure 11 describes how transitions are done between the
different operating modes and Table 6, page 26, gives an
overview of the operating modes.
STOP Command
908E621 ANALOG DIE MODES OF OPERATION
Wake-up (Reset)
Reset (LVR, ext. Reset)
SLEEP
STOP
Reset (LVR, ext. Reset, (HTR))
Figure 11. Operating Modes and Transitions
Normal Mode
Stop Mode
This Mode is the normal operating mode of the device, all
functions and power stages are active and can be enabled/
disabled. The voltage regulator provides the +5.0 V VDD to
the MCU.
In Stop mode, the voltage regulator still supplies the MCU
with VDD (limited current capability). To enter the Stop mode,
the STOP bit in the System Control Register must be set, and
the MCU has to be stopped also (see 908EY16 datasheet for
details).
Wake-up from this mode is possible by the LIN bus activity
or the wake-up input L0. It is maskable with the LINIE and/or
L0IE bits in the Interrupt Mask Register. The analog die is
generating an interrupt on IRQ_A pin to wake-up the MCU.
The wake-up / interrupt source can be evaluated with the
L0IF and LINIF bits in the Interrupt Flag Register.
Stop mode has a higher current consumption than Sleep
mode, but allows a quicker wake-up. Additionally the wake-
After a reset (e.g. Power-On-Reset, Wake-up from Sleep),
the MCU has to set the PSON bit in the System Control
Register within 80 ms typical (tNORMREQ). This is to ensure
the MCU has started up and is operating correctly. If the
PSON bit is not set within the required time frame, the device
enters SLEEP mode to reduce power consumption (fail safe).
This MCU monitoring can be disabled (e.g. for
programming) by applying VDD on the TESTMODE pin.
908E621
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
up sources can be selected (maskable), which is not possible
in Sleep mode.
Figure 12 show the procedure to enter the Stop mode and
how the system is waking up.
MCU
Power Die
behaves like a power on reset. The wake-up / reset source
can be evaluated by the L0WF and/or LINWF bits in the
Reset Status Register.
Sleep mode has a lower current consumption than Stop
mode, but requires a longer time to wake-up. The wake-up
sources can not be selected (not maskable).
Figure 13 show the procedure to enter the Sleep mode
and how a wake-up is performed.
From Reset
MCU
Power Die
initialize
From Reset
operate
initialize
Enable/disable
LIN/L0 wakeup
SPI:
STOP =1
Switch to VREG
low current mode
operate
MCU STOP
Wake-up on
LIN or L0 ?
SPI:
SLEEP =1
Switch off VREG
VDD low, RST low
Assert IRQ
IRQ
interrupt
?
Switch to VREG
high current mode
Wake-up on
LIN or L0 ?
SPI: reason for
interrupt
Store Wake-up
Event
Figure 12. STOP Mode Wake-up Procedure
Sleep Mode
In Sleep mode, the voltage regulator is turned off and the
MCU is not supplied (VDD = 0 V), also the RST_A pin is pulled
low.
To enter the Sleep mode, the Sleep bit in the System
Control Register has to be set.
Wake-up from this mode is possible by LIN bus activity or
the wake-up input L0, and is not maskable. The wake-up
Start VREG
VDD high, RST
high
Figure 13. SLEEP Mode Wake-up Procedure
Table 6 summarized the Operating modes.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 6. Operating Modes Overview
RST_A
MCU monitoring/
Power Stages
Watchdog Function
LIN Interface
Device Mode
Voltage Regulator
Wake-up Capabilities
Reset
VDD ON
N/A
LOW
Disabled
Disabled
Disabled
Normal Request
VDD ON
N/A
HIGH
tNORMREQ (80 ms
typical) timeout to set
PSON bit in System
Control Register
Disabled
Disabled
Normal (Run)
VDD ON
N/A
HIGH
Window Watchdog
active if enabled
Enabled
Enabled
Stop
VDD ON with limited
current capability
LIN wake-up,
L0 state change
HIGH
Disabled
Disabled
Recessive state with
wake-up capability
LOW
Disabled
Disabled
Recessive state with
wake-up capability
Sleep
Output
(SPI PSON=1)(35)
VDD OFF
LIN wake-up
L0 state change
Notes
35. The SPI is still active in Stop mode. However, due to the limited current capability of the voltage regulator in Stop mode, the PSON bit
has to be set before the increased current caused from a running MCU causes an LVR.
OPERATING MODES OF THE MCU
For a detailed description of the operating modes of the
MCU, refer to the MC68HC908EY16 datasheet.
INTERRUPTS
The 908E621 has seven different interrupt sources. An
interrupt pulse on the IRQ_A pin is generated to report an
event or fault to the MCU. All interrupts are maskable and can
be enabled/disabled via the SPI (Interrupt Mask Register).
After reset, all interrupts are automatically disabled.
will be set. If the high temperature interrupt is enabled (HTIE
= 1), an interrupt will be initiated.
During Stop and Sleep mode, the HTI circuitry is disabled.
Low Voltage Interrupt
The LIN Interrupt is related to the Stop mode. If the LIN
interrupt is enabled (LINIE = 1) in Stop mode, an interrupt is
asserted if a rising edge is detected, and the bus was
dominant longer than TPROPWL. After the wake-up / interrupt,
the LINIF indicates the reason for the wake-up / interrupt.
Low voltage interrupt (LVI) is related to external supply
voltage VSUP. If this voltage falls below the LVI threshold, it
will set the LVIF bit in the Interrupt Flag Register. If the low
voltage interrupt is enabled (LVIE = 1), an interrupt will be
initiated.
During Sleep and Stop mode, the low voltage interrupt
circuitry is disabled.
High Voltage Interrupt
The High voltage Interrupt (HVI) is related to the external
supply voltage VSUP. If this voltage rises above the HVI
threshold, it will set the HVIF bit in the Interrupt Flag Register.
If the High voltage Interrupt is enabled (HVIE = 1), an
interrupt will be initiated.
During Stop and Sleep mode, the HVI circuitry is disabled.
High Temperature Interrupt
The high temperature interrupt (HTI) is generated by the
on chip temperature sensors. If the chip temperature is above
the HTI threshold, the HTIF bit in the Interrupt Flag Register
LIN Interrupt
Power Stage Fail Interrupt
The power stage fail flag indicates an error condition on
any of the power stages (see Figure 14, page 27). If the
power stage fail interrupt is enabled (PSFIE = 1), an interrupt
will be initiated if:
During Stop and Sleep mode, the PSFI circuitry is
disabled.
HO Input Interrupt
The H0 interrupt flag H0IF is set in run mode by a state
change of the H0F flag (rising or falling edge on the enabled
input). The interrupt function is available if the input is
selected as General Purpose, or as a 2-pin Hall sensor input.
The interrupt is maskable with the H0IE bit in the Interrupt
Mask Register.
During Stop and Sleep mode, the H0I circuitry is disabled.
908E621
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
L0 input Interrupt
The L0 interrupt flag L0IF is set in run mode by a state
change of the L0F flag (rising or falling edge). The interrupt is
maskable with the L0IE bit in the interrupt mask register.
INTERRUPT FLAG REGISTER (IFR)
HVIF - High Voltage Flag Bit
Register Name and Address: IFR - $0A
Bit7
6
5
4
3
2
1
L0IF
H0IF
LINIF
0
HTIF
LVIF
HVIF
0
0
0
0
0
0
0
Read
Bit0
PSFIF
Write
Reset
is still present while writing a logical one to LVIF, the writing
has no effect. Therefore, a low voltage interrupt cannot be
lost due to inadvertent clearing of LVIF. Reset clears the LVIF
bit. Writing a logic [0] to LVIF has no effect.
1 = low voltage condition has occurred
0 = low voltage condition has not occurred
0
This read/write flag is set on a high voltage condition.
Clear HVIF by writing a logic [1] to HVIF. If the high voltage
condition is still present while writing a logical one to HVIF,
the writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to inadvertent clearing of HVIF. Reset
clears the HVIF bit. Writing a logic [0] to HVIF has no effect.
1 = high voltage condition has occurred
0 = high voltage condition has not occurred
L0IF - L0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
L0 input. Clear L0IF by writing a logic [1] to L0IF. Reset clears
the L0IF bit. Writing a logic [0] to L0IF has no effect.
1 = rising or falling edge on L0 input detected
0 = no state change on L0 input detected
H0IF - H0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
H0 input. Clear H0IF by writing a logic [1] to H0IF. Reset
clears the H0IF bit. Writing a logic [0] to H0IF has no effect.
1 = state change on the hall-flags detected
0 = no state change on the hall-flags detected
LINIF - LIN Flag Bit
This read/write flag is set if a rising edge is detected and
the bus was dominant longer than TpropWL. Clear LINIF by
writing a logic [1] to LINIF. Reset clears the LINIF bit. Writing
a logic [0] to LINIF has no effect.
1 = LIN bus interrupt has occurred
0 = not LIN bus interrupt occurred since last clear
HTIF - High Temperature Flag Bit
This read/write flag is set on high temperature condition.
Clear HTIF by writing a logic [1] to HTIF. If high temperature
condition is still present while writing a logical one to HTIF,
the writing has no effect. Therefore, a high temperature
interrupt cannot be lost due to inadvertent clearing of HTIF.
Reset clears the HTIF bit. Writing a logic [0] to HTIF has no
effect.
1 = high temperature condition has occurred
0 = high temperature condition has not occurred
LVIF - Low Voltage Flag Bit
This read/write flag is set on low voltage condition. Clear
LVIF by writing a logic [1] to LVIF. If the low voltage condition
PSFIF - Power Stage Fail Bit
This read-only flag is set on a fail condition on one of the
power outputs (HBx, HSx, HVDD, H0). Reset clears the
PSFIF bit. Clear this flag by writing a logic [1] to the
appropriate fail flag.
1 = power stage fail condition has occurred
0 = power stage fail condition has not occurred
H0OCF
H0OCF
HVDDOCF
HVDDOCF
HB1OC
HB2OC
PSFIF
HBFF
HB3OC
HB4OC
HS1OC
HSFF
HS2OC
HS3OC
Figure 14. Principal Implementation of the PSFIF
INTERRUPT MASK REGISTER (IMR)
Register Name and Address: IMR - $09
Bit7
6
5
4
3
2
1
Bit0
L0IE
H0IE
LINIE
HTRD
HTIE
LVIE
HVIE
PSFIE
0
0
0
0
0
0
0
0
Read
Write
Reset
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
L0IE - L0 Input Interrupt Enable Bit
HTIE - High Temperature Interrupt Enable Bit
This read/write bit enables CPU interrupts by the L0 flag,
L0IF. Reset clears the L0IE bit.
1 = interrupt requests from L0IF flag enabled
0 = interrupt requests from L0IF flag disabled
This read/write bit enables CPU interrupts by the high
temperature flag, HTIF. Reset clears the HTIE bit.
1 = interrupt requests from HTIF flag enabled
0 = interrupt requests from HTIF flag disabled
H0IE - H0 Input Interrupt Enable Bit
LVIE - Low Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the Hallport
flag, H0IF. Reset clears the H0IE bit.
1 = interrupt requests from H0IF flag enabled
0 = interrupt requests from H0IF flag disabled
This read/write bit enables CPU interrupts by the low
voltage flag, LVIF.Reset clears the LVIE bit.
1 = interrupt requests from LVIF flag enabled
0 = interrupt requests from LVIF flag disabled
LINIE - LIN line Interrupt Enable Bit
HVIE - High Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the LIN flag,
LINIF. Reset clears the LINIE bit.
1 = interrupt requests from LINIF flag enabled
0 = interrupt requests from LINIF flag disabled
This read/write bit enables CPU interrupts by the high
voltage flag, HVIF.Reset clears the HVIE bit.
1 = interrupt requests from HVIF flag enabled
0 = interrupt requests from HVIF flag disabled
HTRD - High Temperature Reset Disable Bit
PSFIE - Power Stage Fail Interrupt Enable Bit
This read/write bit disables the high temperature reset
function. Reset clears the HTRD bit.
1 = high temperature reset is disabled
0 = high temperature reset is enabled
This read/write bit enables CPU interrupts by power stage
fail flag, PSFIF. Reset clears the PSFIE bit.
1 = interrupt requests from PSFIF flag enabled
0 = interrupt requests from PSFIF flag disabled
Note: Disabling of the high temperature reset can lead to
a destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
RESETS
The 908E621 has four internal and one external reset
source.
Each internal reset event will cause a reset pin low for tRST
(1.25 ms typical), after the reset event is gone.
SPI REGISTERS
WDRE
WD Reset Sensor
Reset SPI Register
(not RSR)
VDD
HTRD
HTR Reset Sensor
Clear RSR and set
POR Bit
RST_A
MONO FLOP
RSR
POR internal VREG
LVR Main VREG
Pulse Duration
after reset event is
removed
Figure 15. Internal Reset Routing
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET SOURCE
Register Name and Address: RSR - $0D
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by bit HTRD in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
The watchdog module generates a reset, because of a
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. If the voltage falls
below a certain threshold, it will pull down the RST_A pin.
Reset is flagged by the LVR bit in the Reset Status Register.
An LVR event will reset all register in the SPI excluding the
RSR.
Power On Reset
The POR is related to the internal 5.0 V supply. If the
device detects a power on, the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all register
in the SPI including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A pin low
for tRST after the VDD has reached its nominal value (above
LVR Threshold). Also see Figure 10, page 18).
Bit7
6
5
4
3
POR
PINR
WDR
HTR
LVR
1
0
0
0
0
Read
2
1
Bit0
0
LINWF LOWF
Write
POR
0
0
0
POR— Power On Reset bit
This read/write bit is set after power on. Bit is cleared by
writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing an
logic “1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to a watchdog timeout or
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
Reset Pin / External Reset
LVR— Low Voltage Reset Bit
An external reset can be applied by pulling down the
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
This read/write bit is set if the external VDD voltage coming
from the main voltage regulator falls below a certain value.
The bit is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
Reset Status Register
This register contains five flags that shows the source of
the last reset. A power-on-reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a poweron-reset or by software.
In addition, the register includes two flags which will
indicate the source of a wake-up from Sleep mode: Either LIN
bus activity, or an event on the L0 wake-up input pin.
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. The bit is cleared by writing a logic “1” to this
location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. The bit is cleared by writing a logic “1” to this
location.
908E621
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Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
1 = Wake-up due to L0 pin
0 = no Wake-up due to L0 pin
ANALOG DIE INPUTS/OUTPUTS
LIN PHYSICAL LAYER
The LIN pin offers high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
The LIN transmitter circuitry is enabled by setting the
PSON bit in the System Control Register (SYSCTL).
If the transmitter works in the current limitation region, the
LINCL bit in the System Status Register (SYSSTAT) is set
and the LIN transceiver is disabled after a certain time.
For improved performance and safe behavior, in case of
LIN bus short to Ground or LIN bus leakage during low power
mode, the internal pull-up resistor on the LIN pin is
disconnected from VSUP and a small current source keeps
the LIN bus at recessive level. In case of a LIN bus short to
GND, this feature will reduce the current consumption in
STOP and SLEEP modes.
The LIN bus pin provides a physical layer for single wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
The LIN driver is a low side MOSFET with internal current
limitation and thermal shutdown. An internal pull-up resistor
with a serial diode structure is integrated, so no external pullup components are required for the application in a slave
node. The fall time from dominant to recessive and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
The slew rate can be selected for optimized operation at
10 and 20 kBit/s as well as high baud rates for test and
programming. The slew rate can be adapted with 2 bits
SRS[1:0] in the System Control Register. The initial slew rate
is optimized for 20 kBit/s.
MODE
PSON
SRS[1:0]
VSUP
Wake-up
LINIF
Control
10µA
LINCL
30k
LIN bus
TXD
Slope
Control
Wake-up
Filter
GND
Receiver
TESTMODE
RXD
Figure 16. LIN Interface
TXD Pin
The TXD pin is the MCU interface to control the state of the
LIN transmitter (see Figure 2). When TXD is LOW, the LIN
pin is low (dominant state). When TXD is HIGH, the LIN
output MOSFET is turned off (recessive state). The TXD pin
has an internal pull-up current source to set the LIN bus to a
recessive state in the event, for instance, if the
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SLEEP Mode and Wake-up Feature
microcontroller could not control it during system power-up or
power-down.
During SLEEP mode operation the transmitter of the
physical layer is disabled, the internal pull-up resistor is
disconnected from VSUP, and a small current source keeps
the LIN pin in the recessive state. The receiver is still active
to be able to detect wake-up events on the LIN bus line.
A dominant level longer than TPROPWL followed by an
rising edge will generate a system wake-up (reset) and set
the LINWF flag in the Reset Status register (RSR). Also see
Figure 9, page 17).
RXD Pin
The RXD transceiver pin is the MCU interface, which
reports the state of the LIN bus voltage. LIN HIGH (recessive
state) is reported by a high level on RXD, LIN LOW (dominant
state) by a low level on RXD.
STOP Mode and Wake-up Feature
During STOP mode operation the transmitter of the
physical layer is disabled and the internal pull-up resistor is
disconnected from VSUP and a small current source keeps
the LIN pin in recessive state. The receiver is still active and
able to detect wake-up events on the LIN bus line.
If the LIN interrupt is enabled (LINIE bit in the Interrupt
Mask register is set), a dominant level longer than TPROPWL
followed by an rising edge will set the LINIF flag and generate
an interrupt which causes a system wake-up (see Figure 8,
page 17)
A0 INPUT AND ANALOG MULTIPLEXER
A0 - Analog Input
Input A0 is an analog input used for reading switches, or
as analog inputs for potentiometers, NTC, etc.
A0 is internally connected to the analog multiplexer. This
pin offers a switchable current source. To read the Analog
Input, the pin has to be selected with the SS[3:0] bits in the
A0MUCTL register.
Source Selection Bits
VDD
SSx
4
CSSEL
Selectable
Current
Source
PSON
ADOUT
CSON
Analog
Multiplexer
A0
SS[0:3]
Analog Port A0/A0CST
A0CST
1%
Figure 17. Analog Input and Multiplexer
A0 Current Source
The pin A0 provides a switchable current source, to be
able to read in switches, NTC, etc., without the need of an
additional supply line for the sensor. The overall enable of
this feature is done by setting the PSON bit in the System
Control register. In addition, the pin has to be selected with
the SS[3:0] bits. The current source can be enabled with the
CSON Bit and adjusted with the bits CSSEL[1:0].
With the CSSEL[1:0] bit’s, four different current values can
be selected (40, 120, 320, and 800 µA). This function is
halted during STOP and SLEEP mode operations.
The current source is derived from the VDD voltage, and is
constant up to an output voltage of ~4.75 V.
908E621
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31
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
A0 and Multiplexer Control Register (A0MUCTL)
IA0(UA0)
Register Name and Address: A0MUCTL - $08
Bit7
6
5
4
3
2
1
Bit0
CSON
CSSEL
1
CSSEL
0
CSA
SS3
SS2
SS1
SS0
0
0
0
0
0
0
0
0
100%
Read
Write
Reset
CSON — Current Source on/off
UA0[V]
4.75 5
To calibrate the current sources, an extra pin (A0CST) is
envisioned. On this pin, an accurate resistor can to be
connected. Switching the current sources to this resistor,
allows the user to measure the current and use the measured
value for calculating the current on A0.
Analog Multiplexer / ADOUT pin
The ADOUT pin is the analog output interface to the
Analog-to-digital converter of the MCU. To be able to have
different sources for the MCU with one single signal, an
analog multiplexer is integrated in the analog die. This
multiplexer has eleven different sources, which can be
selected with the SS[3:0] bits in the A0MUCTL register.
This read/write bit enables the current source for the A0 or
A0CST inputs. Reset clears CSON bit.
1 = Current Source enabled
0 = Current Source disabled
CSSEL[1:0] — Current Source Select Bits
These read/write bits select the current source values for
A0 or A0CST input. Reset clears CSSEL[1:0] bits.
Table 7. A0 Current Source Level Selection Bits
CSSEL1
CSSEL0
0
0
40 µA
0
1
120 µA
1
0
320 µA
1
1
800 µA
Half-bridge (HB1:HB4) Current Recopy
The multiplexer is connected to the four current sense
circuits on the low side FET of the half bridges. This sense
circuits offers a voltage proportional to the current through the
MOSFET. The resolution is depending on the CSA bit in the
A0 and Multiplexer control register (A0MUCTL).
High Side (HS1:HS3) Current Recopy
The multiplexer is connected to the three high side
switches. This sense circuit offers a voltage proportional to
the current through the transistor.
Analog Input A0 and A0CST
A0 and A0CST are directly connected to the analog
multiplexer. It offers the possibility to read analog values from
the periphery.
Current Source Enable (typ.)
CSA — H-bridges Current Sense Amplification Select Bit
This read/write bit selects the current sense amplification
of the H-Bridges HB1:HB4 current recopy. Reset clears the
CSA bit.
1 = low current sense amplification
0 = high current sense amplification
SS[3:0] — Analog Source Input Select Bits
These read/write bits selects the analog input source for
the ADOUT pin. Reset clears the SS[3:0] bits Analog
Multiplexer Configuration Bits.
SS3
SS2
SS1
SS0
Channel
0
0
0
0
current recopy HB1
0
0
0
1
current recopy HB2
0
0
1
0
current recopy HB3
0
0
1
1
current recopy HB4
VSUP Prescaler
0
1
0
0
current recopy HS1
The VSUP prescaler offers a possibility to measure the
external supply voltage. The output of this voltage is VSUP /
RATIOVSUP.
0
1
0
1
current recopy HS2
0
1
1
0
current recopy HS3
0
1
1
1
not used
Temperature Sensor
The analog die includes an on chip temperature sensor.
This sensor offers a voltage which is proportional to the
actual mean chip junction temperature.
908E621
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Hall-effect Sensor Input Pin H0
SS3
SS2
SS1
SS0
Channel
1
0
0
0
Chip temperature
1
0
0
1
VSUP prescaler
1
0
1
0
Pin A0
1
0
1
1
Pin A0CST
1
1
0
0
not used
1
1
0
1
not used
1
1
1
0
not used
1
1
1
1
not used
The H0 pin can be configured as general purpose input
(H0MS = 0) or as hall-effect sensor input (H0MS = 1) to be
able to read 3-pin / 2-pin hall sensors or switches.
VDD
10k
H0PD
VSUP
H0MS
H0MS
H0
H0EN
H0F
H0EN
Current
Sense
Figure 18. General purpose / Hall-effect Sensor Input (H0)
Current Coded Hallsensor Input
H0 is selected as “2-pin Hall-sensor input”, if the
corresponding H0MS bit in the H0/L0 Status and Control
Register (HLSCTL) is set. In this mode, the pin current to
GND is monitored by a special sense circuitry. Setting the
H0EN bit in the H0/L0 Status and Control Register, switches
the output to VSUP and enables the sense circuitry. The
result of the sense operation is given by the H0F flag. The
flag is low if the sensed current is higher than the sense
current threshold IHSCT. In this configuration, the HO pin is
protected (current limitation) against short-circuit to GND.
After switching on the hallport (H0EN = “1”), the Hallsensor needs some time to stabilize the output. In RUN
mode, the software has to take care about waiting for a few
µs (40) before sensing the hall-flags.
The hall-port output current is sensed. In case of an overcurrent (short to GND), the hall-port over-current flag
(H0OCF) is set and the current is limited. For proper
operation of the current limitation, an external capacitor
(>100 nF) close to the H0 pin is required.
908E621
Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VSUP
2 pin hall sensor
H0EN
H0
Current
Sense
>0.1uF
H0F
GND
V
Figure 19. H0 Used as 2-pin Hall-sensor Input
General Purpose Input
H0 is selected as a general purpose input, if the H0MS bit
in the H0/L0 Status and Control Register (HLSCTL) is
cleared. In this mode, the input is usable as a standard 5.0 V
VDD
input. The H0 input has a selectable internal pull-up resistor.
The pull-up can be switched off with the H0PD bit in the H0/
L0 Status and Control Register (HLSCTL). After reset, the
internal pull-up is enabled.
VDD
3 pin hall sensor
HVDD
Vs
10k
HVDDON
H0PD
H0F
H0
OUT
GND
GND
Figure 20. H0 Used as 3 Pin Hall-effect Sensor Input
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Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VDD
10k
H0PD
H0F
H0
GND
Figure 21. H0 Used to Read in Standard Switches
H0 Interrupt
The interrupt functionality on this pin is only available in
RUN mode. The H0 interrupt flag H0IF is set in run mode by
a state change of the H0 flag (rising or falling edge on the
enabled input). The interrupt function is available if the input
is selected as General Purpose or as 2-pin Hall-sensor input.
The interrupt can be masked with the H0IE bit in the interrupt
mask register.
Wake-up input L0
The device provides one wake-up capable input for
reading VSUP or VDD related signals.
RUN Mode
The actual input state is reflected in the L0F bit of the H0/
L0 Status and Control register (HLSCTL).
The L0 pin offers an interrupt capability on the rising and
falling edge. The interrupt can be enabled with the L0IE bit in
the Interrupt Mask register.
STOP/SLEEP Mode
During STOP and SLEEP mode, the pin can be used to
wake-up the device.
Before entering the STOP or SLEEP mode, the actual
state of the input is stored. If the state is changing during in
the STOP or SLEEP mode, a wake-up is initiated.
H0 / L0 Status and Control Register (HLSCTL)
Register Name and Address: HLSCTL - $07
Read
Bit7
6
5
L0F
0
0
4
3
2
1
Bit0
H0EN
H0PD
H0MS
0
0
0
H0F
H0OCF
Write
Reset
0
0
0
0
0
L0F — L0 Flag Bit
This read only flag reflects the state of the L0 input
1 = L0 input high
0 = L0 input low
H0OCF — H0 Over-current Flag Bit
This read/write flag is set at over-current condition on H0
during 2-pin hall-sensor mode. Clear H0OCF by writing a
logic [1] to H0OCF. Reset clears the H0OCF bit.
1 = over-current condition on H0 pin has occurred
0 = no over-current condition on H0 pin has occurred
H0F — H0 Flag Bit
This read only flag reflects the state of the H0 input
1 = Hall-port sensed high / current below threshold
detected
0 = Hall-port sensed low / current above threshold
detected
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
H0EN — H0 Input 2-pin Hall-effect sensor Enable Bit
Half-bridge Outputs
This read/write bit enables the 2-pin hall-effect sensor
sense circuitry. Reset clears H0EN bit.
1 = Hall-port H0 is switched on and sensed
0 = Hall-port H0 disabled
Outputs HB1:HB4 provide four low-resistive half-bridge
output stages. The half-bridges can be used in H-bridge, high
side or low side configurations.
Reset clears all bits in the H-bridge Output Register
(HBOUT) owing to the fact that all half-bridge outputs are
switched off.
HB1:HB4 output features
• Short-circuit (over-current) protection on high side and
low side MOSFETs
• Current recopy feature (low side MOSFET)
• Over-temperature protection
• Over-voltage and under-voltage protection
• Active clamp on low side MOSFET
H0PD — Hall-port Pull-up Disable Bit
This read/write bit disables the H0 Pull-up resistor. Reset
clears H0PD bit.
1 = Hall-port pull-up resistor on H0 disabled
0 = Hall-port pull-up resistor on H0 enabled
H0MS — H0 Mode Select
These read/write bits select the mode of the H0 input
Reset clears H0MS bit.
1 = H0 is 2-pin hall-sensor input
0 = H0 is general purpose input
VSUP
On/Off
Status
PWM
High Side Driver
Charge Pump
Over-temperature Protection
Over-current Protection
Control
HBx
On/Off
Status
PWM
Low Side Driver
Current Recopy
Current Limitation
Active Clamp
Over-current Protection
GND
Figure 22. Half-bridge Push-Pull Output Driver
Half-bridge Control
Each output MOSFET can be controlled individually. The
general enable of the circuitry is done by setting PSON in the
System Control Register (SYSCTL). The HBx_L and HBx_H
bits form one half-bridge. It is not possible to switch on both
MOSFETs in one half-bridge at the same time. If both bits are
set, the high side MOSFET is in PWM mode.
To avoid both MOSFETs (high side and low side) of one
half-bridge being on at the same time, a break-before-make
circuit exists. Switching the high side MOSFET on is inhibited
as long as the potential between gate and VSS is not below a
certain threshold. Switching the low side MOSFET on is
blocked as long as the potential between gate and source of
the high side MOSFET did not fall below a certain threshold.
908E621
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Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HALF-BRIDGE OUTPUT REGISTER (HBOUT)
CSA = “1”: low resolution selected
CSA = “0”: high resolution selected
Register Name and Address: HBOUT - $01
Half-bridge Over-temperature Protection
HBx_H
HBx_L
0
0
Low side and high side MOSFET off
0
1
High side MOSFET off,
low side MOSFET on
The outputs are protected against over-temperature
conditions. Each power output comprises two different
temperature thresholds.
The first threshold is the high temperature interrupt (HTI).
If the temperature reaches this threshold, the HTIF bit in the
Interrupt Flag Register (IFR) is set, and an interrupt will be
initiated if the HTIE bit in the Interrupt Mask register is set. In
addition, this interrupt can be used to automatically turn off
the power stages. This shutdown can be enabled/disabled by
the HTIS0-1 Bits in the System Control Register (SYSCTL).
The high temperature interrupts flag (HTIF) is cleared (and
the outputs reenabled) by writing a “1” to the HTIF flag in the
Interrupt Flag Register (IFR) or by a reset. Clearing this flag
has no effect as long as a high temperature condition is
present.
If the HTI shutdown is disabled, a second threshold high
temperature reset (HTR) will be used to turn off all power
stages (HB (all Fet’s), HS, HVDD, H0) in order to protect the
device.
1
0
High side MOSFET on,
low side MOSFET off
Half-Bridge Over-current Protection
1
1
High side MOSFET in PWM mode
Read
Write
Reset
Bit7
6
5
4
3
2
1
Bit0
HB4_
H
HB4_
L
HB3_
H
HB3_
L
HB2_
H
HB2_
L
HB1_
H
HB1_
L
0
0
0
0
0
0
0
0
HBx_H, HBx_L — Half-bridge Output Switches
These read/write bits select the output of each half-bridge
output according to Table . Reset clears all HBx_H, HBx_L
bits.
Table 8. Half-bridge Configuration
Mode
Half-bridge PWM mode
The PWM mode is selected by setting both HBxL and
HBxH of one half-bridge to “1”. In this mode, the high side
MOSFET is controlled by the incoming PWM signal on the
PWM pin (see Figure 2, page 2).
If the incoming signal is high, the high side MOSFET is
switched on.
If the incoming signal is low, the high side MOSFET is
switched off.
With the current recirculation mode control bit CRM in the
Half-bridge Status and Control Register (HBSCTL), the
recirculation behavior in PWM mode can be controlled. If
CRM is set, the corresponding low side MOSFET is switched
on, if the PWM controlled high side MOSFET is off.
Half-bridge Current Recopy
Each low side MOSFET has an additional sense output to
allow a current recopy feature. These sense sources are
internally amplified and switched to the Analog Multiplexer.
The factor for the Current Sense amplification can be
selected via the CSA bit in the A0MUCTL register (see
page 31)
The Half-bridges are protected against short to GND,
VSUP, and load shorts. The over-current protection is
implemented on each HB. If an over-current condition on the
high side MOSFET occurs, the high side MOSFET is
automatically switched off. An over-current condition on the
low side MOSFET will automatically turn off the low side
MOSFET. In both cases, the corresponding HBxOCF flag in
the Half-bridge Status and Control Register (HBSCTL) is set.
The over-current status flag is cleared (and the
corresponding half-bridge MOSFETs reenabled) by writing a
“1” to the HBxOCF in the Half-bridge Status and Control
Register (HBSCTL) or by a reset.
Half-bridge Over-voltage/Under-voltage Protection
The half-bridge outputs are protected against undervoltage and over-voltage conditions. This protection is done
by the low and high voltage interrupt circuitry. If one of these
flags (LVIF, HVIF) are set, the outputs are automatically
disabled when the VIS bit in the System Control Register
(SYSCTL) is cleared.
The over-voltage and under-voltage status flags are
cleared (and the outputs reenabled) by writing a “1” to the
LVIF / HVIF flags in the Interrupt Flag Register (IFR), or by a
reset. Clearing this flag has no effect as long as the high
voltage or low voltage condition is still present.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Half-bridge Status and Control Register (HBSCTL)
HBxOCF — Half-bridges Over-current Flag Bit
Register Name and Address: HBSCTL - $03
Bit7
Read
6
5
4
3
2
1
Bit0
0
0
0
HB4
OCF
HB3
OCF
HB2
OCF
HB1
OCF
0
0
0
0
0
0
0
CRM
Write
Reset
0
CRM — Current Recirculation Mode bit
This read/write bit selects the recirculation mode during
PWM. Reset clears the CRM bit.
1 = recirculation via switched on low side MOSFET
0 = recirculation via low side freewheeling diode
This read/write bit indicates that an over-current condition
on either the LS or the HS FET on HBx has occurred.
Clear HBxOCF and enable half-bridge by writing a logic [1]
to HBxOCF. Writing a logic [0] to HBxOCF has no effect.
Reset clears the HBxOCF bit.
1 = over-current condition on HBx occurred
0 = no over-current condition on HBx
High Side Drivers
The high side outputs are low resistive high side switches,
targeted for driving lamps. The high sides are protected
against over-temperature, over-current, and over-voltage/
under-voltage.
VSUP
PSON
on/off
HSxON
HSxPWM
Control
PWM
Status
Current
Limit
HS - Driver
charge pump
over-current protection
inrush current limiter
PWM
HSx
Figure 23. HS Circuitry
HIGH SIDE OPERATING MODES
The high side outputs are enabled if the PSON bit in the
System Control Register (SYSCTL) is set.
Each high side output is permanently switched on, if the
HSxON bit in the High Side Output Register (HSOUT) is set.
PWM control of the output is enabled, if the HSxPWM bit
High Side Output Register (HSOUT) is set. In this operating
mode, the high side MOSFET is on if the input PWM signal
(PWM pin) is high.
The following table shows the behavior of the high side
MOSFETs depending on the HSONx and PWMHSx bits.
908E621
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Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 9. High Side Configuration Bits
Mode
flags in the Interrupt Flag Register, or by reset. Clearing this
flag has no effect as long as a high or low voltage condition
is present.
HSxPWM
HSxON
0
0
High side MOSFET off
HIGH SIDE OVER-TEMPERATURE PROTECTION
0
1
High side MOSFET on if over-current, the
over-current flag (HSxOCF) is set, and the
high side MOSFET is turned off
1
0
In this mode, the PWM duty cycle is either
controlled by the PWM input signal, or if
the over-current shutdown value is
reached by the part itself.
The outputs are protected against over-temperature
conditions.
Each power output comprises two different temperature
thresholds.
The first threshold is the high temperature interrupt (HTI).
If the temperature reach this threshold, the HTI bit in the
interrupt flag register is set and an interrupt will be generated,
if the HTIE bit in the interrupt mask register is set. In addition,
this interrupt can be used to automatically turn off the power
stages (all high sides, on Half-bridges just the high side
FET’s). This shutdown can be enabled/disabled by the HTIS0
bit.
The high temperature interrupts flag (HTIE) is cleared (and
the outputs reenabled) by writing a logic [1] to the HTIF flag
in the Interrupt Status Register, or by reset. Clearing this flag
has no effect as long as a high temperature condition is
present.
If the HTIS shutdown is disabled, a second threshold
(HTR) will be used to turn off all power stages (HB (all Fet’s),
HS, HVDD, H0) in order to protect the device.
Without reaching the over-current
shutdown, the high side driver is directly
driven from the PWM input signal. If the
Input signal is high, the output is on. If low,
the output is off (PWM control).
If the current reaches the over-current
shutdown value, the high side will be
automatically turned off. With the next
rising edge of the PWM input signal, the
output will turn on again (current
limitation). The HSxOCF bit will be set.
The software has to distinguish between
an inrush current and a real short on the
output.
1
1
High side MOSFET is switched on and the
inrush current limitation is enabled. This
means the high side will start
automatically with a current limitation
around the over-current shutdown
threshold. (PWM signal must be applied,
see Figure 24)
If the high side enters current limitation,
the HSxOCF bit is set, but the output is not
disabled. The software needs to
distinguish between an inrush current and
a real short on the output.
High Side Over-voltage / Under-voltage Protection
The outputs are protected against under /over-voltage
conditions. This protection is done by the low and high
voltage interrupt circuitry. If an over /under-voltage condition
is detected (LVIF / HVIF), and Bit VIS in the High Side Status
Register is cleared, the output is disabled.
The over /under-voltage status flags are cleared (and the
output reenabled), by writing a logic [1] to the LVIF / HVIF
High Side Over-current Protection
The HS outputs are protected against over-current. When
the over-current limit is reached, the output will be
automatically switched off and the over-current flag is set.
Due to the high inrush current of bulbs, a special feature
was implemented to avoid a over-current shutdown during
this inrush current. If a PWM frequency will be supplied to the
PWM input during the switch on of a bulb, the inrush current
will be limited to the over-current shutdown limit. This means,
if the current reaches the over-current shutdown, the high
side will be switched off, but each rising edge on the PWM
input will enable the driver again. The duty cycle supplied by
the MCU has no influence on the switch-on time of the high
side driver.
In order to distinguish between a shutdown due to an
inrush current or a real shutdown, the software checks if the
over-current status flag (HSxOCF) in the High Side Status
register is set beyond a certain period of time.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HS Current
HS Over-current Shutdown Threshold
t
PWM Pin
t
Figure 24. Inrush Current Limitation on HS Outputs
High Side Current Recopy
HIGH SIDE OUT REGISTER (HSOUT)
Each High Side has an additional sense output to allow a
current recopy feature. This sense source is internally
connected to a shunt resistor. The drop voltage is amplified
and switched to the Analog Multiplexer.
Register Name and Address: HSOUT - $02
Bit7
Read
Switchable HVDD Outputs
The HVDD pin is a switchable 5.0 V output pin. It can be
used for driving external circuitry, which requires a 5.0 V
voltage. The output is enabled with the PSON bit in the
System Control register, and can be switched on / off with the
HVDD_ON bit in the High Side Out register. Low or high
voltage conditions (LVIF / HVIF) will have no influence on this
circuitry.
HVDD Over-temperature Protection
The output is protected against over-temperature
conditions.
HVDD Over-current Protection
The HVDD output is protected against over-current. In
case the current reaches the over-current limit, the output
current will be limited, and the HVDDOCF over-current flag in
the System Status register is set.
Write
Reset
HVDD
ON
0
6
0
0
5
4
3
2
1
Bit0
HS3P
WM
HS2P
WM
HS1P
WM
HS3O
N
HS2O
N
HS1O
N
0
0
0
0
0
0
HVDD-ON — HVDD On Bit
This read/write bit enables the HVDD output.
Reset clears HVDDON bit.
1 = HVDD enabled
0 = HVDD disabled
HSxON — High Side on/off Bits
These read/write bits turn on the High Side Fet’s
permanently. Reset clears the HSxON bits.
1 = High Side x is turned on
0 = High Side x is turned off
908E621
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HSxPWM — High Side PWM on/off Bits
STOP — Change to STOP Mode Bit
These read/write bits enable the PWM control of the High
Side Fet’s. Reset clears the HSxPWM bits.
1 = High Side x is controlled by PWM input signal
0 = High Side x is not controlled by PWM input signal
This write bit instructs the chip to enter Stop mode (See
Operational Modes on page 24). Reset or CPU interrupt
requests clear the STOP bit.
1 = go to Stop mode
0 = not in stop mode
In order to safely enter Stop mode, all other bits (Bit7-Bit2)
have to be “0”. Otherwise the STOP command will not
execute.
High Side Status Register (HSSTAT)
Register Name and Address: HSSTAT - $04
Bit7
Read
Write
Reset
HVDD
OCF
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
Bit0
HS3O
CF
HS2O
CF
HS1O
CF
0
0
0
HSxOCF — High Side Over-current Flag Bit
This read/write flag is set by an over-current condition at
the high side drivers x. Clear HSxOCF and enable the HS
Driver by writing a logic [1] to HSxOCF. Writing a logic [0] to
HSxOCF has no effect. Reset clears the HSxOCF bit.
1 = over-current condition on high side drivers has
occurred
0 = no over-current condition on high side drivers has
occurred
HVDDOCF — HVDD Output Over-current Flag Bit
This read/write flag is set by an over-current condition at
HVDD pin. Clear HVDDOCF and enable the output by writing
a logic [1] to the HVDDOCF Flag. Writing a logic [0] to
HVDDOCF has no effect. Reset clears the HVDDOCF bit.
1 = over-current condition on VDD output has occurred
0 = no over-current condition on VDD output has
occurred
System Control Register (SYSCTL)
Register Name and Address: SYSCTL - $00
Bit7
Read
5
0
0
PSON
4
3
HTIS1 HTIS0
2
1
Bit0
VIS
SRS1
SRS0
0
0
0
STOP SLEEP
Write
Reset
6
0
0
0
0
0
SLEEP — Change to SLEEP Mode Bit
This write bit instructs the chip to enter Sleep mode (See
Operational Modes on page 24). Reset or CPU interrupt
requests clear the SLEEP bit.
1 = go to Sleep mode
0 = not in sleep mode
In order to safely enter Sleep mode all other bits (Bit7-Bit2)
have to be “0”. Otherwise the SLEEP command will not
execute.
HTIS0-1 — High Temperature Interrupt Shutdown Bits
This read/write bit selects the power stage behavior at
High Temperature Interrupt (HTI). Reset clears the HTIS0-1
bits.
The HTIS0 bit selects the behavior of the high side HS1:3
and the high side FET of the half-bridges HB1:4.
1 = automatic HTI shutdown of the high side drivers
disabled
0 = automatic HTI shutdown of the high side drivers
enabled
The HTIS1 bit selects the behavior of the low side drivers
of the half-bridges HB1:4.
1 = automatic HTI shutdown of the low side drivers
disabled
0 = automatic HTI shutdown of the low side drivers
enabled
The user has to take care to protect the device against
thermal destruction!
VIS — Over/Under-voltage Interrupt Shutdown
This read/write bit selects the power stage behavior at LVI/
HVI. Reset clears the VIS bit.
1 = automatic LVI/HVI shutdown disabled
0 = automatic LVI/HVI shutdown enabled
PSON — Power Stages On Bit
SRS0-1 — LIN Slew Rate Select Bits
This read/write bit enables the power stages (half-bridges,
high sides, LIN transmitter, A0 Current Sources and HVDD
output). Reset clears the PSON bit.
1 = power stages enabled
0 = power stages disabled
These read/write bits enable the user to select the
appropriate LIN slew rate for different Baudrate
configurations. Reset clears the SRS1:0 bits.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HVDDF— HVDD Failure Bit
Table 10. LIN Slew Rate Selection Bits
SRS1
SRS0
Slew rate
0
0
Initial Slew Rate (20 kBaud)
0
1
High Speed II (8x)
1
0
Slow Slew Rate (10 kBaud)
1
1
High Speed I (4x)
This read only bit is a copy of the HVDDOCF bit in the High
Side Status register
1 = HVDD pin fail
0 = HVDD normal operating
HSF— HS1:3 Failure Bit
The high speed slew rates are used, for example, for
programming via the LIN, and are not intended for use in the
application.
This read only bit is set if a fail condition on one of the high
side outputs is present
1 = HS1:3 pin fail
0 = HS1:3 normal operating
System Status Register (SYSSTAT)
HS1OCF
Register Name and Address: SYSSTAT - $0C
Read
Bit7
6
5
4
3
2
1
Bit0
HS2OCF
LINC
L
HTIF
VF
H0F
HVD
DF
HSF
HBF
0
HS3OCF
Figure 26. HSF Flag Generation
Write
Reset
HSF
0
0
0
0
0
0
0
0
LINCL — LIN Current Limitation Bit
This read only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, the driver will be automatically turned off
after a certain time.
1 = transmitter operating in current limitation region
0 = transmitter not operating in current limitation region
HBF— HB1:4 Failure Bit
This read only bit is set if a fail condition on one of the halfbridge outputs is present.
1 = HB1:4 pin over-current fail
0 = HB1:4 normal operating
HB1OCF
HTIF— Over-temperature Status Bit
HB2OCF
This read only bit is a copy of the HTIF bit in the Interrupt
Flag register
1 = over-temperature condition
0 = no over-temperature condition
HB3OCF
HBF
HB4OCF
Figure 27. HBF Flag Generation
VF — Voltage Failure Bit
WINDOW WATCHDOG
This read only bit indicates that the supply voltage was out
of the allowed range. The bit is set if either the LVIF or the
HVIF in the Interrupt Flag register is set.
1 = low/high voltage condition detected
0 = no voltage failure condition detected
The window watchdog is used to supervise the device, and
to recover from, e.g. code runaways, or similar conditions.
The use of a window watchdog adds additional safety, as
the watchdog clear has not only to occur, but be done at a
certain time frame / window.
Normal mode
HVIF
LVIF
VF
Figure 25. VF Flag Generation
H0F — H0 Failure Bit
This read only bit is a copy of the H0OCF bit in the H0/L0
Status and Control Register (HLSCTL)
1 = over-current detected on H0
0 = no over-current on H0
The window watchdog function is only available in Normal
mode, and is halted in Stop and Sleep mode. On setting the
WDRE bit, the watchdog functionality is activated. Once this
function is enabled, it is not possible to disable it via software.
Reset clears the WDRE bit.
To prevent a Watchdog reset, the Watchdog timer has to
be cleared in the Window Open frame. This is done by writing
a logic “1” to the WDRST bit in the Watchdog Control register
(WDCTL). The actual reset of the watchdog counter occurs at
the end of the corresponding SPI transmission, with the rising
edge of the SS signal.
908E621
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
If the watchdog is enabled, it will generate a system reset,
if the timer has reached its end value, or if a watchdog reset
(WDRST) has occurred in the closed window.
The watchdog period can be selected with 2 bits in the
WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period.
Window closed
no watch dog clear allowed
WDP1:0 - Watchdog Period Select Bits
This read/write bit select the clock rate of the Watchdog.
Reset clears the WDP1:0 bits.
Table 11. Watchdog Period Selection Bits
Window open
for watch dog clear
WD timing x 50%
1 = Watchdog enabled
0 = Watchdog disabled
WD timing x 50%
WDP1
WDP0
Mode
0
0
80 ms window watchdog period
0
1
40 ms window watchdog period
1
0
20 ms window watchdog period
1
1
10 ms window watchdog period
WDRST - Watchdog Reset Bit
WD period ( timing selected by Bits WDP1:0)
This write only bit resets the Watchdog. Write a logic [1] to
reset the watchdog timer.
1 = Reset WD and restart timer
0 = no effect
Figure 28. Window Watchdog Period
Stop mode
Operations of the watchdog function is halted in stop mode
(counter/oscillator stopped). After wake-up, the watchdog
timer is automatically cleared, in order to give the MCU the
full time to reset the watchdog.
Sleep mode
Operations of the watchdog function is halted in sleep
mode. Because the main voltage regulator asserts an LVR
reset, the Watchdog functionality is disabled, and the WDRE
bit is cleared as soon as sleep mode is entered. To re-enable
this function bit WDRE has to be set after wake-up.
Voltage Regulator
The 908E621 contains a low power, low drop voltage
regulator, to provide internal power and external power for
the MCU. The on-chip regulator consist of two elements, the
main regulator and the low voltage reset circuit.
The VDD regulator accepts an unregulated input supply
and provides a regulated VDD supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0 V to the microcontroller.
Run mode
Watchdog Control Register (WDCTL)
During RUN mode the main voltage regulator is on. It will
provide a regulated supply to all digital sections.
Register Name and Address: WDCTL - $0B
Read
Bit7
6
5
4
3
2
1
Bit0
WDRE
WDP1
WDP0
0
0
0
0
0
Write
Reset
WDRST
0
0
0
0
0
0
0
0
STOP mode
During STOP mode, the Stop mode regulator will take care
of suppling a regulated output voltage. The Stop mode
regulator has a limited output current capability.
SLEEP mode
WDRE - Watchdog Reset Enable Bit
This read/write (write once) bit activates the watchdog.
The WDRE can only be set and can not be cleared by
software. Reset clears the WDRE bit.
In Sleep mode, the main voltage regulator external, VDD,
is turned off and the LVR circuitry will force the RST_A pin
low.
LOGIC COMMANDS AND REGISTERS
908E621 SERIAL PHERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) creates the
communication link between the MCU and the analog die.
The interface consists of four pins
• MOSI - Master Out Slave In (internal pulldown)
• MISO - Master In Slave Out
• SPSCK - Serial Clock (internal pulldown)
• SS - Slave Select (internal pullup)
A complete data transfer via the SPI, consists of 2 bytes.
The master sends address and data, the slave returns
system status and the data of the selected address.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SS
Read/Write, Address, Parity
MOSI
R/W
A4
A3
A2
A1
A0
Data (Register write)
P
X
D7
D6
D5
System Status Register
MISO
S7
S6
S5
S4
S3
D4
D3
D2
D1
D0
D2
D1
D0
Data (Register read)
S2
S1
S0
D7
D6
D5
D4
D3
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
Figure 29. SPI Protocol
• During the inactive phase of SS, the new data transfer
will be prepared. The falling edge on the SS line,
indicates the start of a new data transfer (framing), and
puts MISO in the low impedance mode. The first valid
data are moved to MISO with the rising edge of SPSCK.
• The MOSI, MISO will change data on a rising edge of
SPSCK.
• The MOSI, MISO will be sampled on a falling edge of
SPSCK.
• The data transfer is only valid, if exactly 16 sample clock
edges are present in the active phase of SS.
• After a write operation, the transmitted data will be
latched into the register by the rising edge of SS.
• Register read data is internally latched into the SPI at
the time when the parity bit is transferred
• SS high will force MISO to high-impedance
and the write data is latched in the SMARTMOS
registers on rising edge of SS.
Parity P
Completes the total number of 1 bits of (R/W,A[4-0]) to an
even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0.
The parity bit is only evaluated during a write operations
and ignored for read operations.
Bit X
Not used
Master Data Byte
This byte includes data to be written, or no valid data,
during a read operation.
Master Address Byte
Slave Status Byte
A4 - A0
This byte always includes the contents of the system
status register ($0C), independent if it is a write or read
operation, or which register was selected.
Includes the address of the desired register.
R/W
Includes the information, if it is a read or a write operation.
• If R/W = 1 (read operation), the second byte of master
contains no valid information, and the slave just
transmits back register data.
• If R/W = 0 (write operation), the master sends data to be
written in the second byte, the slave sends concurrently
contents of selected register prior to write operation,
Slave Data Byte
This byte includes the contents of selected register, during
a write operation, it includes the register content prior to the
write operation.
SPI REGISTER OVERVIEW
Table 12 summarizes the SPI Register addresses and the
bit names of each register.
908E621
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 12. SPI Register Overview
Addr
Register Name
R/W
System Control
(SYSCTL)
R
$00
$01
Half-bridge Output
(HBOUT)
$02
High Side Output
(HSOUT)
$03
Half-bridge Status and
Control (HBSCTL)
$04
High Side Status and
Control (HSSCTL)
$05
Reserved
$06
Reserved
$07
H0/L0 Status and
Control (HLSCTL)
$08
A0 and Multiplexer
Control (A0MUCTL)
$09
Interrupt Mask
(IMR)
$0A
Interrupt Flag
(IFR)
$0B
Watchdog Control
(WDCTL)
$0C
System Status
(SYSSTAT)
$0D
Reset Status
(RSR)
$0E
System Test
(SYSTEST)
$0F
System Trim 1
(SYSTRIM1)
$10
System Trim 2
(SYSTRIM2)
$11
System Trim 3
(SYSTRIM3)
Bit
7
PSON
W
R
HB4_H
W
R
W
HVDDON
R
CRM
W
R
W
HVDDOCF
6
5
4
3
2
1
0
0
0
STOP
SLEEP
HTIS1
HTIS0
VIS
SRS1
SRS0
HB4_L
HB3_H
HB3_L
HB2_H
HB2_L
HB1_H
HB1_L
HS3PWM
HS2PWM
HS1PWM
HS3ON
HS2ON
HS1ON
0
0
0
HB4OCF
HB3OCF
HB2OCF
HB1OCF
0
0
0
HS3OCF
HS2OCF
HS1OCF
H0EN
H0PD
H0MS
0
R
0
reserved
W
R
reserved
W
R
L0F
0
0
H0F
H0OCF
W
R
W
R
W
CSON
CSSEL1
CSSEL0
CSA
SS3
SS2
SS1
SS0
L0IE
H0IE
LINIE
HTRD
HTIE
LVIE
HVIE
PSFIE
L0IF
H0IF
LINIF
0
HTIF
LVIF
HVIF
WDRE
WDP1
WDP0
0
0
0
0
LINCL
HTIF
VF
H0F
HVDDF
HSF
HBF
0
POR
PINR
WDR
HTR
LVR
LINWF
L0WF
R
W
R
W
R
PSFIF
0
WDRST
W
R
W
R
reserved
W
R
W
HVDDT1
HVDDT0
reserved
reserved
itrim3
itrim2
itrim1
itrim0
0
0
0
0
0
0
0
0
CRHB5
CRHB4
CRHB3
CRHB2
CRHB1
CRHB0
0
0
0
0
0
0
CRHS5
CRHS4
CRHS3
CRHS2
CRHS1
CRHS0
R
W
CRHBHC1 CRHBHC0
R
W
0
0
0
CRHBHC3 CRHBHC2
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E621, various
parameters (e.g. ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the “empty” ($FF) state:
Watchdog Period Range Value (AWD Trim)
Trim Values
The window watchdog supervises device recovery (e.g.
from code runaways).
The application software has to clear the watchdog within
the open window. Due to the high variation of the watchdog
period, and therefore the reduced width of the watchdog
window, a value is stored at address $FDCF. This value
classifies the watchdog period into 3 ranges (Range 0, 1, 2).
This allows the application software to select one of three
time intervals to clear the watchdog, based on the stored
value. The classification is done, so that the application
software can have up to ±19% variations of the optimal clear
interval (e.g. caused by ICG variation).
The usage of the trim values located in the flash memory
are explained through the following:
Effective Open Window
• $FD80:$FDDF Trim and Calibration Values
• $FFFE:$FFFF Reset Vector
In the event the application uses these parameters, one
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
Internal Clock Generator (ICG) Trim Value
The internal clock generator (ICG) module is used to
create a stable clock source for the microcontroller without
using any external components. The untrimmed frequency of
the low frequency base clock (IBASE), will vary as much as
±25 percent due to process, temperature, and voltage
dependencies. To compensate these dependencies, an ICG
trim value is located at address $FDC2. After trimming, the
ICG has a typ. range of ±2% (±3% max.), at nominal
conditions (filtered (100nF), stabilized (4.7 μF) VDD = 5.0 V,
TAMBIENT~25 °C), and will vary over temperature and voltage
(VDD) as indicated in the 68HC908EY16 datasheet.
To trim the ICG, this value has to be copied to the ICG Trim
Register ICGTR at address $38 of the MCU.
Important: The value must be copied after every reset.
Having a variation in the watchdog period in conjunction
with a 50% open window, results in an effective open window,
which can be calculated by:
latest window open time: t_open = t_wd max / 2
earliest window closed time: t_closed = t_wd min
Optimal Clear Interval
The optimal clear interval, meaning the clear interval with
the biggest possible variation to latest window open time, and
to the earliest window closed time, can be calculated with the
following formula:
t_opt = t_open + (t_open+t_closed) / 2
See Table 13 to select the optimal clear interval for the
watchdog based on the Window No. and chosen period.
Table 13. Window Clear Interval
Window Range Period Select bits
$FDCF
0
1
2
Watchdog Period t_wd
WDP1:0
min.
max.
00
68
92
01
34
46
10
17
23
11
8.5
00
Unit
Effective Open Window
t_open
t_closed
46
68
23
34
11.5
17
11.5
5.75
8.5
7.125
92
124
62
92
77
01
46
62
31
46
10
23
31
15.5
23
11
11.5
15.5
7.75
11.5
9.625
00
52
68
34
52
43
01
26
34
17
26
10
13
17
8.5
13
11
6.5
8.5
4.25
6.5
ms
ms
ms
Unit
Optimal Clear Interval
t_opt
Unit
max.
variation
ms
±19.3%
ms
±19.5%
ms
±20.9%
57
ms
ms
ms
28.5
14.25
38.5
19.25
21.5
10.75
5.375
908E621
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Analog Die System Trim Values
ITRIM3:0 - IRef Trim Bits
For improved application performance, and to ensure the
outlined datasheet values, the analog die needs to be
trimmed. For this purpose, 3 trim values are stored in the
Flash memory at addresses $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
• copy $FDC4 into SYSTRIM1 register $0F
• copy $FDC5 into SYSTRIM2 register $10
• copy $FDC6 into SYSTRIM3 register $11
Note: These values must be copied to the respective SPI
register after a reset, to ensure proper trimming of the device.
These write only bits are for trimming the internal current
references IRef (also A0, A0CST). The provided trim values
have to be copied into these bits after every reset. Reset
clears the ITRIM3:0 bits.
System Test Register (SYSTEST)
Register Name and Address: SYSTEST - $0E
Bit7
6
5
4
3
2
1
Bit0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0
0
0
0
0
0
0
0
Read
Write
Reset
Note: do not write to the reserved bits
Table 15. IRef Trim Bits
itrim3
itrim2
itrim2
itrim0
Adjustment
0
0
0
0
0
0
0
0
1
2%
0
0
1
0
4%
0
0
1
1
8%
0
1
0
0
12%
0
1
0
1
-2%
0
1
1
0
-4%
0
1
1
1
-8%
1
0
0
0
-12%
System Trim Register 2 (SYSTRIM2)
The System Test Register is reserved for production
testing and is not allowed to be written to.
Register Name and Address: IFBHBTRIM - $10
Bit7
System Trim Register 1 (SYSTRIM1)
Register Name and Address: IBIAS - $0F
Bit7
6
HVDDT1
HVDDT0
0
0
Read
Write
Reset
5
4
3
2
1
Bit0
0
0
reserved
reserved
ITRIM3
ITRIM2
ITRIM1
ITRIM0
0
0
0
0
0
0
6
5
4
3
2
1
Bit0
0
0
Read
0
0
0
0
0
0
Write
CRHBHC1
CRHBHC0
CRHB5
CRHB4
CRHB3
CRHB2
Reset
0
0
0
0
0
0
CRHB1 CRHB0
0
0
CRHBHC1:0 - Current Recopy HB1:2 Trim Bits
Note: do not change (set) the reserved bits
These write only bits are for trimming the current recopy of
the half-bridge HB1 and HB2 (CSA=0). The provided trim
values have to be copied into these bits after every reset.
Reset clears the CRHBHC1:0 bits.
Table 16. Current Recopy Trim for HB1:2 (CSA=0)
HVDDT1:0 - HVDD Over-current Shutdown Delay Bits
These read/write bits allow changes to the filter time (for
capacitive load) for HVDD over-current detection. Reset
clears the HVDDT1:0 bits and sets the delay to the maximum
value.
Table 14. HVDD Over-current Shutdown Selection Bits
HVDDT1
HVDDT0
Typical Delay
0
0
950 μs
0
1
536 μs
1
0
234 μs
1
1
78 μs
CRHBHC1
CRHBHC0
Adjustment
0
0
0
0
1
-10%
1
0
5%
1
1
10%
CRHB5:3 - Current Recopy HB3:4 Trim Bits
These write only bits are for trimming the current recopy of
the half-bridge HB3 and HB4 (CSA=1). The provided trim
values have to be copied into these bits after every reset.
Reset clears the CRHB5:3 bits.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Current Recopy Trim for HB3:4 (CSA=0)
Table 17. Current Recopy Trim for HB3:4 (CSA=1)
CRHB5
CRHB4
CRHB3
Adjustment
0
0
0
0
0
0
1
-5%
0
1
0
-10%
0
1
1
-15%
1
0
0
reserved
1
0
1
5%
1
1
0
10%
1
1
1
15%
CRHBHC3
CRHBHC2
Adjustment
0
0
0
0
1
-10%
1
0
5%
1
1
10%
CRHS5:3 - Current Recopy HS2:3 Trim Bits
These write only bits are for trimming the current recopy of
the high side HS2 and HS3. The provided trim values have to
be copied into these bits after every reset. Reset clears the
CRHS5:3 bits.
CRHB2:0 - Current Recopy HB1:2 Trim Bits
Table 19. Current Recopy Trim for HS2:3
These write only bits are for trimming the current recopy of
the half-bridge HB1 and HB2 (CSA=1). The provided trim
values have to be copied into these bits after every reset.
Reset clears the CRHB2:0 bits.
Table 18. Current Recopy Trim for HB1:2 (CSA=1)
CRHB2
CRHB1
CRHB0
Adjustment
0
0
0
0
0
0
1
-5%
0
1
0
-10%
0
1
1
-15%
1
0
0
reserved
1
0
1
5%
1
1
0
10%
1
1
1
15%
CRHS5
CRHS4
CRHS3
Adjustment
0
0
0
0
0
0
1
-5%
0
1
0
-10%
0
1
1
-15%
1
0
0
reserved
1
0
1
5%
1
1
0
10%
1
1
1
15%
CRHS2:0 - Current Recopy HS1 Trim Bits
These write only bits are for trimming the current recopy of
the high side HS1. The provided Trim values have to be
copied into these bits after every reset. Reset clears the
CRHS2:0 bits.
Current Recopy Trim for HS1
System Trim Register 3 (SYSTRIM3)
Register Name and Address: IFBHSTRIM - $11
Bit7
6
5
4
3
2
1
Bit0
Read
0
0
0
0
0
0
0
0
Write
CRHBH
C3
CRHBH
C2
CRHS5
CRHS4
CRHS3
CRHS2
CRHS1
CRHS0
Reset
0
0
0
0
0
0
0
0
CRHBHC3:2 - Current Recopy HB3:4 Trim Bits
These write only bits are for trimming the current recopy of
the half-bridge HB3 and HB4 (CSA=0). The provided trim
values have to be copied into these bits after every reset.
Reset clears the CRHBHC3:2 bits.
CRHS2
CRHS1
CRHS0
Adjustment
0
0
0
0
0
0
1
-5%
0
1
0
-10%
0
1
1
-15%
1
0
0
reserved
1
0
1
5%
1
1
0
10%
1
1
1
15%
908E621
48
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
DEVELOPMENT SUPPORT
As the 908E621 has the MC68HC908EY16 MCU
embedded, typically all the development tools available for
the MCU also apply for this device. However, due to the
additional analog die circuitry and the nominal +12 V supply
voltage, some additional items have to be considered:
• nominal 12 V rather than the 5.0 or 3.0 V supply
• high voltage VTST might be applied not only to IRQ pin,
but IRQ_A pin
• MCU monitoring (Normal request timeout) has to be
disabled
For a detailed information on the MCU related
development support, see the MC68HC908EY16 datasheet section development support.
The programming is principally possible at two stages in
the manufacturing process, first on chip level, before the IC is
soldered onto a pcb board, and second after the IC is
soldered onto the pcb board.
Chip level programming
At the Chip level, the easiest way is to only power the MCU
with +5.0 V (see Figure 30), and not to provide the analog
chip with VSUP. In this setup, all the analog pins should be
left open (e.g. VSUP[1:8]), and interconnections between the
MCU and analog die have to be separated (e.g. IRQ - IRQ_A).
This mode is well described in the MC68HC908EY16
datasheet, section development support.
VSUP[1:8]
VDD
GND[1:4]
VSS
+5V
VDDA/VREFH
RST
EVDD
RST_A
+5V
1
1µF
+
+
3
4
1µF
GND
C1C2+
V+
+
5
RS232
DB-9
VCC
C1+
100nF
VTST
16
C2-
MAX232
V-
IRQ_A
1µF
15
7 T2OUT
3
8 R2IN
EVSS
+5V
9.8304MHz CLOCK
+5V
+
TESTMODE
CLK
PTB4/AD4
T2IN 10
6
10k
5
4
3
2
10k
PTC4/OSC1
1µF
74HC125
5
MM908E621
1µF
6
R2OUT 9
4.7µF
VSSA/VREFL
+
2
74HC125
2
IRQ
10k
DATA
PTA1/KBD1
PTA0/KBD0
10k
PTB3/AD3
1
Figure 30. Normal Monitor Mode Circuit (MCU only)
Of course it is also possible to supply the whole system
PCB level programming
with VSUP instead (12 V) as described in Figure 31, page 50.
If the IC is soldered onto the pcb board, it is typically not
possible to separately power the MCU with +5.0 V. The
whole system has to be powered up providing VSUP (see
Figure 31).
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
TYPICAL APPLICATIONS
.
VDD
VSUP
47µF
+
100nF
VSUP[1:8]
VDD
GND[1:4]
VSS
VDDA/VREFH
RST
EVDD
RST_A
100nF
VDD
1
1µF
16
+
+
3
4
1µF
VCC
C1+
VTST
C1-
GND
C2+
V+
+
5
RS232
DB-9
C2-
MAX232
V-
7 T2OUT
3
8 R2IN
EVSS
VDD
1µF
+
2
10k
9.8304MHz CLOCK
6
VDD
TESTMODE
CLK
10k
PTC4/OSC1
1µF
+
PTB4/AD4
T2IN 10
6
74HC125
R2OUT 9
MM908E621
IRQ_A
15
4.7µF
VSSA/VREFL
1µF
10k
74HC125
2
IRQ
10k
5
DATA
PTA1/KBD1
PTA0/KBD0
10k
4
PTB3/AD3
3
2
1
5
Figure 31. Normal Monitor Mode Circuit
Table 20 summarizes the possible configurations and the
necessary setups.
Table 20. Monitor Mode Signal Requirements and Options
Mode
IRQ RST TESTMODE
Normal
Monitor
Forced
Monitor
VTST
VDD
1
X
1
$FFFF
(blank)
VDD
VDD
Reset
Vector
Serial
Communication
Mode
Selection
PTA0
PTA1
PTB3
PTB4
1
0
0
1
1
0
X
VDD
VDD
0
not $FFFF
(not blank)
X
X
X
COP
OFF
disabled
disabled
9.8304
MHz
2.4576
MHz
9600
OFF
disabled
disabled
9.8304
MHz
2.4576
MHz
9600
ON
disabled
disabled
—
Nominal
1.6 MHz
Nominal
6300
ON
enabled
enabled
—
Nominal
1.6 MHz
Nominal
6300
X
GND
User
Communication Speed
Normal
Request
Baud
Bus
Time-out External
Clock Frequency Rate
ICG
X
Notes
36. PTA0 must have a pullup resistor to VDD in monitor mode
37.
38.
39.
40.
External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1
Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
X = don’t care
VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V
EMC/EMI RECOMMENDATIONS
VSUP Pins (VSUP[1:8])
This paragraph gives some device specific
recommendations to improve EMC/EMI performance.
Further generic design recommendations can be found on
the Freescale web site www.freescale.com.
It is recommended to place a high quality ceramic
decoupling capacitor close to the VSUP pins to improve
EMC/EMI behavior.
908E621
50
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
LIN Pin
For DPI (Direct Power Injection) and ESD (Electrostatic
Discharge), it is recommended to place a high quality ceramic
decoupling capacitor near the LIN pin. An additional varistor
will further increase the immunity against ESD. A ferrite in the
LIN line will suppress some of the noise induced.
Voltage Regulator Output Pins (VDD and VSS)
Use a high quality ceramic decoupling capacitor to
stabilize the regulated voltage.
MCU Digital Supply Pins (EVDD and EVSS)
Fast signal transitions on MCU pins place high, short
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU. It is recommended that a high quality
ceramic decoupling capacitor be placed between these pins.
MCU Analog Supply Pins (VREFH/VDDA and VREFL/
VSSA)
To avoid noise on the analog supply pins, it is important to
take special care on the layout. The MCU digital and analog
supplies should be tied to the same potential via separate
traces, and connected to the voltage regulator output.
Figure 32 and Figure 33 show the recommendations on
schematics and layout level, and Table 21 indicates
recommended external components and layout
considerations.
D1
VSUP[1:8]
VSUP
C1
+
VDD
C2
VSS
VDDA/VREFH
L1
LIN
LIN
EVDD
V1
C5
C3
MM908E621
C4
EVSS
GND[1:4]
VSSA/VREFL
Figure 32. EMC/EMI recommendations
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
TYPICAL APPLICATIONS
1
54
2
53
3
52
4
51
5
50
49
48
8
EVDD
47
9
EVSS
46
10
VSSA/VREFL
45
11
44
12
43
VDD
42
908E621
15
16
39
17
38
18
VSUP1
19
GND2
VSUP8
37
36
VSUP7
20
21
41
40
GND1
VSUP2
35
34
22
VSUP6
32
24
VSUP5
31
GND3
GND4
30
VSUP3
VSUP4
25
26
29
D1
28
VBAT
V1
27
GND
33
23
C1
14
LIN
VSS
C2
C5
13
C4
7
VDDA/VREFH
C3
6
LIN
L1
Figure 33. PCB Layout Recommendations
.
Table 21. Component Value Recommendation
Component
Recommended Value(41)
D1
Comments / Signal routing
reverse battery protection
C1
Bulk Capacitor
C2
100nF, SMD Ceramic, Low ESR
Close to VSUP pins with good ground return
C3
100nF, SMD Ceramic, Low ESR
Close (<3mm) to digital supply pins (EVDD, EVSS) with good ground
return.
The positive analog (VREFH/ VDDA) and the digital (EVDD) supply
should be connected right at the C3.
C4
4,7μF, SMD Ceramic, Low ESR
C5
180pF, SMD Ceramic, Low ESR
Bulk Capacitor
Close (<5mm) to LIN pin.
Total Capacitance on LIN has to be below 220pF.
(Ctotal = CLIN-Pin + C5 + CVaristor ~ 10pF + 180pF + 15pF)
V1(42)
Varistor Type TDK AVR-M1608C270MBAAB
Optional (close to LIN connector)
L1(42)
SMD Ferrite Bead Type TDK MMZ2012Y202B
Optional, (close to LIN connector)
Notes
41. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their
application.
42. Components are recommended to improve EMC and ESD performance.
908E621
52
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A
drawing number: 98ASA10712D.
EK SUFFIX (PB-FREE)
54-PIN SOICW-EP
98ASA10712D
ISSUE 0
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
53
PACKAGE DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN SOICW-EP
98ASA10712D
ISSUE 0
908E621
54
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGE DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN SOICW-EP
98ASA10712D
ISSUE 0
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL INFORMATION
908E621
THERMAL ADDENDUM (REV 1.0)
INTEGRATED QUAD H-BRIDGE AND TRIPLE HIGH-SIDE DRIVER
WITH EMBEDDED MCU AND LIN FOR MIRROR
Introduction
This thermal addendum is provided as a supplement to the MM908E621
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
Package and Thermal Considerations
This MM908E621 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
TJ1
TJ2
=
RθJA11 RθJA12
RθJA21 RθJA22
.
P1
P2
54-PIN
SOICW-EP
98ASA10712D
54-PIN SOICW-EP
Note For package dimensions, refer to the
908E621 device datasheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Table 22. Thermal Performance Comparison
1.0
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
Resistance
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
RθJAmn (1)(2)
23
20
24
RθJBmn
(2)(3)
9.0
6.0
10
RθJAmn
(1)(4)
52
47
52
1.0
0
2.0
RθJCmn (5)
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
Thermal vias
connected to top
buried plane
54 Terminal SOIC-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 34. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5
908E621
56
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
1
54
2
53
3
52
4
51
5
50
6
49
IRQ
RST
7
48
8
47
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
9
46
10
45
RST_A
IRQ_A
11
44
LIN
A0CST
A0
GND1
HB4
VSUP1
GND2
HB3
VSUP2
NC
NC
TESTMODE
GND3
HB2
VSUP3
13
12
14
15
43
42
Exposed
Pad
41
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
A
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
(PTE1/RXD <- RXD)
VSS
VDD
HVDD
L0
H0
HS3
VSUP8
HS2
VSUP7
HS1b
HS1a
VSUP6
VSUP5
GND4
HB1
VSUP4
908E621 Pin Connections
54-Pin SOICW-EP
0.65 mm Pitch
17.9mm x 7.5mm Body
10.3mm x 5.1mm Exposed Pad
Figure 35. Thermal Test Board
Device on Thermal Test Board
Material:
Outline:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
80 mm x 100 mm board area,
including edge connector for
thermal testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions:
Natural convection, still air
Table 23. Thermal Resistance Performance
Thermal
Resistance
RθJAmn
RθJSmn
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (°C/W)
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
0
53
48
53
300
39
34
38
600
35
30
34
0
21
16
20
300
15
11
15
600
14
9.0
13
RθJA is the thermal resistance between die junction and
ambient air.
RθJSmn is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package. This device is a dual die package. Index
m indicates the die that is heated. Index n refers to the
number of the die where the junction temperature is sensed.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
Thermal Resistance [ºC/W]
60
50
40
30
20
10
0
x
RθJA11
RθJA22
RθJA12 = RθJA21
0
300
600
Heat spreading area A [mm²]
Figure 36. Device on Thermal Test Board RθJA
Thermal Resistance [ºC/W]
100
10
1
x
0.1
1.00E-03
1.00E-02
RθJA11
RθJA22
RθJA12 = RθJA21
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 37. Transient Thermal Resistance RθJA (1.0 W Step Response)
Device on Thermal Test Board Area A = 600 (mm2)
908E621
58
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
3.0
DATE
2/2007
DESCRIPTION OF CHANGES
•
•
•
•
Implemented Revision History page
Changed Table 3, Statistic Electrical Characteristics, Hall-Effect Sensor Input H0 - 2pin Hall Sensor
Input Mode (H0MS = 1), Sense Current Hysteresis on page 13 from a Minimum of 800 to 600 and
Typical from 1100 to none.
Removed “Advance” watermark and updated to final Data Sheet.
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Electrical Characteristics on page 6. Added note with instructions from www.freescale.com.
4.0
6/2007
•
Updated to Final by removing “Advance Information” from page 1.
5.0
6/2008
•
•
•
•
•
•
Changed STOP Mode Total Output Current on page 9 from 850 to 1100μA
Changed Sense Current Hysteresis on page 13 from 800 to 650μA
Changed Normal Request Timeout on page 15 from 124 to 150ms
Updated Freescale form and style to the current format
Updated package drawing
Added Functional Internal Block Description section
6.0
4/2012
•
•
•
Added MM908E621ACPEK/R2 to the ordering information.
Removed MM908E621ACDWB/R2 from the data sheet
Updated Freescale form and style to the current format
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
59
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Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
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disclaims any and all liability, including without limitation consequential or incidental
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respective owners.
© 2012 Freescale Semiconductor, Inc.
Document Number: MM908E621
Rev. 6.0
4/2012
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