Data Sheet

74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Rev. 1 — 7 August 2012
Product data sheet
1. General description
The 74HC366-Q100; 74HCT366-Q100 is a hex inverter/line driver with 3-state outputs
controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs to
assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use
of current limiting resistors to interface inputs to voltages in excess of VCC.
The 74HC366-Q100; 74HCT366-Q100 is functionally identical to:
• 74HC365-Q100; 74HCT365-Q100, but has inverted outputs
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Inverting outputs
 Input levels:
 For 74HC366-Q100: CMOS level
 For 74HC366-Q100: TTL level
 Complies with JEDEC standard no. 7A
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC366D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HC366PW-Q100
40 C to +125 C
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT366D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HCT366PW-Q100
40 C to +125 C
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HC366-Q100
74HCT366-Q100
4. Functional diagram
2
4
6
10
12
1A
1Y
2A
2Y
3A
3Y
4A
4Y
5A
5Y
6A
14
6Y
3
1Y
2A
2Y
3A
3Y
4A
4Y
2
3
5A
5Y
4
5
6
7
6A
6Y
10
9
12
11
14
13
7
1
15
11
13
OE2
OE1
OE2
001aaf583
Functional diagram
74HC_HCT366_Q100
Product data sheet
&
EN
9
OE1
1
15
Fig 1.
1A
5
Fig 2.
001aaf581
Logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
001aaf582
Fig 3.
IEC logic symbol
© NXP B.V. 2012. All rights reserved.
2 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
buffer/line driver 1
VCC
1A
1Y
OE1
OE2
GND
2A
3A
4A
5A
6A
buffer/line driver 2
2Y
buffer/line driver 3
3Y
buffer/line driver 4
4Y
buffer/line driver 5
5Y
buffer/line driver 6
6Y
001aaf584
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
+&4
+&74
2(
9&&
$
2(
<
$
$
<
<
$
$
<
<
$
*1'
<
DDD
Fig 5.
Pin configuration
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
3 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
OE1
1
output enable input 1 (active LOW)
1A
2
data input 1
1Y
3
data output 1
2A
4
data input 2
2Y
5
data output 2
3A
6
data input 3
3Y
7
data output 3
GND
8
ground (0 V)
4Y
9
data output 4
4A
10
data input 4
5Y
11
data output 5
5A
12
data input 5
6Y
13
data output 6
6A
14
data input 6
OE2
15
output enable input 2 (active LOW)
VCC
16
supply voltage
6. Functional description
Table 3.
Function table[1]
Control
Input
Output
OE1
OE2
nA
nY
L
L
L
H
L
L
H
L
X
H
X
Z
H
X
X
Z
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
4 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
-
35
mA
ICC
supply current
-
70
mA
IGND
ground current
-
70
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
SO16 package
[1]
-
500
mW
TSSOP16 package
[2]
-
500
mW
[1]
For SO16 packages: Ptot derates linearly with 8 mW/K above 70 C.
[2]
For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC366-Q100
Min
Typ
74HCT366-Q100
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
5 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
9. Static characteristics
Table 6.
Static characteristics 74HC366-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
VCC = 2.0 V
1.5
1.2
-
V
VCC = 4.5 V
3.15
2.4
-
V
VCC = 6.0 V
4.2
3.2
-
V
VCC = 2.0 V
-
0.8
0.5
V
VCC = 4.5 V
-
2.1
1.35
V
VCC = 6.0 V
-
2.8
1.8
V
-
-
-
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
V
IO = 6.0 mA; VCC = 4.5 V
3.98
4.32
-
V
IO = 7.8 mA; VCC = 6.0 V
5.48
5.81
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
0.15
0.26
V
IO = 7.8 mA; VCC = 6.0 V
-
0.16
0.26
V
HIGH-level output voltage VI = VIH or VIL
LOW-level output voltage VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
0.1
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V
-
-
0.5
A
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
CI
input capacitance
-
-
8.0
A
-
3.5
-
pF
VCC = 2.0 V
1.5
-
-
V
Tamb = 40 C to +85 C
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
HIGH-level output voltage VI = VIH or VIL
74HC_HCT366_Q100
Product data sheet
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 6.0 mA; VCC = 4.5 V
3.84
-
-
V
IO = 7.8 mA; VCC = 6.0 V
5.34
-
-
V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
6 of 19
NXP Semiconductors
74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Table 6.
Static characteristics 74HC366-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
Conditions
Min
Typ
Max
Unit
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
-
0.33
V
IO = 7.8 mA; VCC = 6.0 V
-
-
0.33
V
LOW-level output voltage VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 6.0 V;
-
-
1.0
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V
-
-
5.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
-
-
80
A
Tamb = 40 C to +125 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 6.0 mA; VCC = 4.5 V
3.7
-
-
V
IO = 7.8 mA; VCC = 6.0 V
5.2
-
-
V
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
-
0.4
V
IO = 7.8 mA; VCC = 6.0 V
-
-
0.4
V
A
HIGH-level output voltage VI = VIH or VIL
LOW-level output voltage VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V
-
-
10.0 A
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
-
-
160
Min
Typ
Max
Unit
A
Table 7.
Static characteristics 74HCT366-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
VIH
HIGH-level input voltage VCC = 4.5 V to 5.5 V
2.0
1.6
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
V
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
74HC_HCT366_Q100
Product data sheet
IO = 20 A
4.4
4.5
-
V
IO = 6.0 mA
3.98
4.32
-
V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
7 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
Table 7.
Static characteristics 74HCT366-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
0
0.1
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
IO = 6.0 mA
-
0.16
0.26
V
-
-
0.1
A
IOZ
OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin; other
inputs at GND or VCC; IO = 0 A; VCC = 5.5 V
-
-
0.5
A
ICC
supply current
-
-
8.0
A
ICC
additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; IO = 0 A
pins nA
-
100
360
A
pin OE1
-
100
360
A
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
pin OE2
CI
input capacitance
-
90
320
A
-
3.5
-
pF
Tamb = 40 C to +85 C
VIH
HIGH-level input voltage VCC = 4.5 V to 5.5 V
2.0
-
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
-
-
V
IO = 6.0 mA
3.84
-
-
V
IO = 20 A
-
-
0.1
V
IO = 6.0 mA
-
-
0.33
V
-
-
1.0
A
5.0
A
VOL
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
IOZ
OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin; other
inputs at GND or VCC; IO = 0 A; VCC = 5.5 V
ICC
supply current
ICC
additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; IO = 0 A
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
-
-
80
A
pins nA
-
-
450
A
pin OE1
-
-
450
A
pin OE2
-
-
400
A
Tamb = 40 C to +125 C
VIH
HIGH-level input voltage VCC = 4.5 V to 5.5 V
2.0
-
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
VOH
HIGH-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
-
-
V
IO = 6.0 mA
3.7
-
-
V
LOW-level output
voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
0.1
V
IO = 6.0 mA
-
-
0.4
V
VOL
II
input leakage current
IOZ
OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin; other
inputs at GND or VCC; IO = 0 A; VCC = 5.5 V
74HC_HCT366_Q100
Product data sheet
VI = VCC or GND; VCC = 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
-
-
1.0
A
-
-
10.0
A
© NXP B.V. 2012. All rights reserved.
8 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
Table 7.
Static characteristics 74HCT366-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ICC
supply current
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
-
-
160
A
ICC
additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; IO = 0 A
pins nA
-
-
490
A
pin OE1
-
-
490
A
pin OE2
-
-
441
A
10. Dynamic characteristics
Table 8.
Dynamic characteristics 74HC366-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; see test circuit Figure 8.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
33
100
ns
VCC = 4.5 V
-
12
20
ns
VCC = 5 V; CL = 15 pF
-
10
-
ns
VCC = 6.0 V
-
10
17
ns
VCC = 2.0 V
-
44
150
ns
VCC = 4.5 V
-
16
30
ns
VCC = 6.0 V
-
13
26
ns
VCC = 2.0 V
-
55
150
ns
VCC = 4.5 V
-
20
30
ns
VCC = 6.0 V
-
16
26
ns
VCC = 2.0 V
-
14
60
ns
VCC = 4.5 V
-
5
12
ns
VCC = 6.0 V
-
4
10
ns
-
30
-
pF
VCC = 2.0 V
-
-
125
ns
VCC = 4.5 V
-
-
25
ns
-
-
21
ns
VCC = 2.0 V
-
-
190
ns
VCC = 4.5 V
-
-
38
ns
VCC = 6.0 V
-
-
33
ns
Tamb = 25 C
tpd
ten
tdis
tt
CPD
propagation delay
enable time
disable time
transition time
power dissipation
capacitance
nA to nY; see Figure 6
OEn to nY; see Figure 7
OEn to nY; see Figure 7
[1]
[2]
[3]
[4]
see Figure 6
per buffer; VI = GND to VCC
[5]
nA to nY; see Figure 6
[1]
Tamb = 40 C to +85 C
tpd
propagation delay
VCC = 6.0 V
ten
enable time
74HC_HCT366_Q100
Product data sheet
OEn to nY; see Figure 7
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
[2]
© NXP B.V. 2012. All rights reserved.
9 of 19
NXP Semiconductors
74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Table 8.
Dynamic characteristics 74HC366-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; see test circuit Figure 8.
Symbol Parameter
tdis
tt
disable time
transition time
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
-
190
ns
VCC = 4.5 V
-
-
38
ns
VCC = 6.0 V
-
-
33
ns
VCC = 2.0 V
-
-
75
ns
VCC = 4.5 V
-
-
15
ns
VCC = 6.0 V
-
-
13
ns
OEn to nY; see Figure 7
[3]
[4]
see Figure 6
Tamb = 40 C to +125 C
tpd
propagation delay
nA to nY; see Figure 6
[1]
VCC = 2.0 V
-
-
150
ns
VCC = 4.5 V
-
-
30
ns
-
-
26
ns
VCC = 6.0 V
ten
enable time
OEn to nY; see Figure 7
[2]
VCC = 2.0 V
-
-
225
ns
VCC = 4.5 V
-
-
45
ns
-
-
38
ns
VCC = 6.0 V
tdis
disable time
OEn to nY; see Figure 7
[3]
VCC = 2.0 V
-
-
225
ns
VCC = 4.5 V
-
-
45
ns
-
-
38
ns
VCC = 2.0 V
-
-
90
ns
VCC = 4.5 V
-
-
18
ns
VCC = 6.0 V
-
-
15
ns
VCC = 6.0 V
tt
[1]
transition time
[4]
see Figure 6
tpd is the same as tPHL and tPLH.
[2]
ten is the same as tPZH and tPZL.
[3]
tdis is the same as tPHZ and tPLZ.
[4]
tt is the same as tTHL and tTLH.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
10 of 19
NXP Semiconductors
74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
Table 9.
Dynamic characteristics 74HCT366-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; see test circuit Figure 8.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
-
13
24
ns
Tamb = 25 C
tpd
propagation delay
nA to nY; see Figure 6
[1]
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
-
11
-
ns
ten
enable time
OEn to nY; VCC = 4.5 V; see Figure 7
[2]
-
16
35
ns
tdis
disable time
OEn to nY; VCC = 4.5 V; see Figure 7
[3]
-
20
35
ns
transition time
VCC = 4.5 V; see Figure 6
[4]
-
5
12
ns
power dissipation
capacitance
per buffer; VI = GND to (VCC  1.5 V)
[5]
-
30
-
pF
nA to nY; VCC = 4.5 V; see Figure 6
[1]
-
-
30
ns
OEn to nY; VCC = 4.5 V; see Figure 7
[2]
-
-
44
ns
tt
CPD
Tamb = 40 C to +85 C
tpd
ten
propagation delay
enable time
tdis
disable time
OEn to nY; VCC = 4.5 V; see Figure 7
[3]
-
-
44
ns
tt
transition time
VCC = 4.5 V; see Figure 6
[4]
-
-
15
ns
nA to nY; VCC = 4.5 V; see Figure 6
[1]
-
-
36
ns
Tamb = 40 C to +125 C
tpd
propagation delay
ten
enable time
OEn to nY; VCC = 4.5 V; see Figure 7
[2]
-
-
53
ns
tdis
disable time
OEn to nY; VCC = 4.5 V; see Figure 7
[3]
-
-
53
ns
VCC = 4.5 V; see Figure 6
[4]
-
-
18
ns
tt
[1]
transition time
tpd is the same as tPHL and tPLH.
[2]
ten is the same as tPZH and tPZL.
[3]
tdis is the same as tPHZ and tPLZ.
[4]
tt is the same as tTHL and tTLH.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
11 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
11. Waveforms
VI
nA input
VM
VM
GND
t PHL
t PLH
VOH
nY output
VM
VM
VOL
t THL
t TLH
001aaf585
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Propagation delay data input (nA) to output (nY) and output transition time
VI
VM
VM
OEn input
GND
tPLZ
tPZL
VCC
nY output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
nY output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aaf586
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Table 10.
3-state enable and disable times
Measurement points
Type
Input
Output
VM
VM
VX
VY
74HC366-Q100
0.5VCC
0.5VCC
0.1  VCC
0.9  VCC
74HCT366-Q100
1.3 V
1.3 V
0.1  VCC
0.9  VCC
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
12 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 8.
Table 11.
Load circuitry for measuring switching times
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC366-Q100
VCC
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HCT366-Q100
3V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
13 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 9.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
14 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 10. Package outline SOT403-1 (TSSOP16)
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
15 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
13. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
Low-power Schottky Transistor-Transistor Logic
MM
Machine Model
MIL
Military
14. Revision history
Table 13.
Revision history
Document ID
Release date
74HC_HCT366_Q100 v.1 20120807
74HC_HCT366_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
16 of 19
74HC366-Q100; 74HCT366-Q100
NXP Semiconductors
Hex buffer/line driver; 3-state; inverting
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT366_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
17 of 19
NXP Semiconductors
74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT366_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
18 of 19
NXP Semiconductors
74HC366-Q100; 74HCT366-Q100
Hex buffer/line driver; 3-state; inverting
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 August 2012
Document identifier: 74HC_HCT366_Q100