C o ntrol In t eg ra t ed P Owe r Sys te m (C IPOS™) Reference Board for IGCMxxF60xA with 3-shunt AN-CIPOS mini-2-Reference Board-3 Authors: JunHo Song, JunBae Lee and DaeWoong Chung Application Note,. Preliminary For Power Management Application 1 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt Table of contents 1 Introduction............................................................................................................................................... 3 2 Schematic.................................................................................................................................................. 4 3 External Connection ................................................................................................................................ 5 3.1 Signal Connector (J1, 2.5mm pitch connector) .......................................................................................... 5 3.2 Signal Connector (J2, 2.5mm pitch connector) .......................................................................................... 5 3.3 Power Connector ........................................................................................................................................ 5 4 Key Parameters Design Guide ................................................................................................................ 6 4.1 Circuit of Input Signals (LIN, HIN) .............................................................................................................. 6 4.2 Bootstrap Capacitor .................................................................................................................................... 6 4.3 Internal Bootstrap Functionality Characteristics ......................................................................................... 7 4.4 Over Current Protection ............................................................................................................................. 8 4.4.1 Shunt Resistor Selection ............................................................................................................................ 8 4.4.2 Delay Time ................................................................................................................................................. 9 4.5 Temperature Monitor and Protection ....................................................................................................... 10 5 Part list .................................................................................................................................................... 11 6 PCB Design Guide .................................................................................................................................. 12 6.1 Layout of Reference Board ...................................................................................................................... 12 7 Reference ................................................................................................................................................ 13 Application Note,. Preliminary 2 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 1 Introduction This reference board is composed of the IGCMxxF60xA, its minimum peripheral components and three shunt resistors. It is designed for customers to evaluate the performance of CIPOSTM with simple connection of the control signals and power wires. Figure 1 shows the external view of reference board. This application note also describes how to design the key parameters and PCB layout. Figure 1. Reference board for IGCMxxF60xA Reference Board Power Connector CIPOSTM VS1 VS2 19 10 HO2 20 9 LIN3 21 8 LIN2 HO1 22 7 LIN1 VSS 12 LO3 HO3 17 13 LO2 VS3 16 14 LO1 Power Connectors 3~ 15 11 18 Thermistor (IGCMxxF60GA) VB1 23 6 HIN3 VB2 24 5 HIN2 25 4 HIN1 VB3 26 3 ITRIP 27 VFO 28 VDD 2 AC 1 Bridge Diode Power Connector Filters & Itrip, Fo & temperature monitor circuits Signal connectors to controller SMPS Controller Figure 2. Application example Application Note,. Preliminary 3 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 2 Schematic Figure 3 shows a circuitry of the reference board for IGCMxxF60xA. The reference board consists of interface circuit, bootstrap circuit, snubber capacitor, short-circuit protection, fault output circuit and three shunt resistors. CIPOSTM mini NC (24) (1) VS(U) (2) VB(U) R7 RBS1 (3) VS(V) (4) VB(V) VB2 C11 C8 D2 R8 RBS2 (5) VS(W) (6) VB(W) D3 (7) HIN(U) (3) WH (4) UL (9) HIN(W) HIN3 LIN1 (11) LIN(V) (6) WL (12) LIN(W) C16 Vctr (11) GND VDD C13 R12 C14 LIN2 V (21) V HO3 W W (20) VDD C18 R11 C15 C19 C20 LO1 NU (19) R13 NV (18) R14 NW (17) R15 LO2 LIN3 (13) VDD C1 ~ C6 Vctr VS2 HIN2 (10) LIN(U) (5) VL (10) VDD HIN1 (8) HIN(V) Vctr U HO2 VS3 (2) VH (7) /Fo UU(22) VS1 RBS3 R1 ~ R6 (1) UH (9) Vctr VB3 C12 C9 R9 J1 HO1 VB1 C10 C7 D1 P P (23) VDD (14) VFO VFO (15) ITRIP ITRIP (16) VSS VSS C17 N LO3 Thermistor (IGCMxxF60GA) R10 D4 R16 J2 R17 R18 D5 R19 D6 (1) NU (2) NV (3) NW C20 C21 C22 Figure 3. Circuit of the reference board Note: Vctr denotes the controller supply voltage such as 5V or 3.3V. It is optional to use external bootstrap circuit together with internal one as shown in dot line, in case that smaller bootstrap resistor is necessary. Application Note,. Preliminary 4 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 3 External Connection 3.1 Signal Connector (J1, 2.5mm pitch connector) 3.2 3.3 Pin Name Description 1 HIN(U) High side control signal input of U phase 2 HIN(V) High side control signal input of V phase 3 HIN(W) Low side control signal input of W phase 4 LIN(U) Low side control signal input of U phase 5 LIN(V) Low side control signal input of V phase 6 LIN(W) Low side control signal input of W phase 7 /Fo Fault output signal / Temperature monitor (IGCMxxF60GA) 8 NC No Connection 9 Vctr External control voltage (5V or 3.3V) 10 VDD External 15V supply voltage 11 GND Ground Signal Connector (J2, 2.5mm pitch connector) Pin Name Description 1 ISEN(NU) Current monitor output of NU 2 ISEN(NV) Current monitor output of NV 3 ISEN(NW) Current monitor output of NW Power Connector Pin Description U Output terminal of U phase V Output terminal of V phase W Output terminal of W phase P Positive terminal of DC link voltage N Negative terminal of DC link voltage Application Note,. Preliminary 5 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 4 Key Parameters Design Guide 4.1 Circuit of Input Signals (LIN, HIN) The input signals can be either TTL- or CMOS-compatible. The logic levels can go down to 3.3V. The maximum input voltage of the pins is internally clamped to 10.5V. However, the recommended voltage range of input voltage is up to 5V. The control pins LIN and HIN are active high. They have an internal pull-down structure with a pull-down resistor value of nominal 5kΩ. The input noise filter inside CIPOSTM suppresses short pulse and prevents the driven IGBT from unintentional operation. The input noise filter time (tFLIN) is typically 270ns. This means that an input signal must stay on more than 270ns so that the input signal can be processed correctly. CIPOSTM can be connected directly to controller without external input RC filter thanks to the internal pull down resistor and input noise filter as shown in Figure 4. Controller (MCU or DSP) HINx LINx 5kΩ Vz=10.5V Input Noise Filter tFILIN=270ns Figure 4. Filter of input signals and pull-down circuit 4.2 Bootstrap Capacitor Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this technique a supply voltage for the floating high side sections of the gate drive can be easily established according to Figure 5. It is only the effective circuit shown for one of the three half bridges. The bootstrap functionality is composed internally to limit current. Please refer to the datasheet and application note for bootstrapping method in detail. P VDD CDD VB HO Gate VS Drive IC LO VBS CBS VSS Figure 5. Bootstrap circuit for the supply of a high side gate drive Application Note,. Preliminary 6 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt A low leakage current of the high side section is very important in order to keep the bootstrap capacitors small. The CBS discharges mainly by the following mechanisms: - Quiescent current to the high side circuit in the IC - Gate charge for turning high side IGBT on - Level-shift charge required by level shifters in the IC - Leakage current in the bootstrap diode - CBS capacitor leakage current (ignored for non-electrolytic capacitor) - Bootstrap diode reverse recovery charge The calculation of the bootstrap capacitor results in C BS = Ileak × t P ΔVBS with Ileak being the maximum discharge current of CBS, tP the maximum on pulse width of high side IGBT and ∆ VBS the voltage drop at the bootstrap capacitor within a switching period. Practically, the recommended leakage current is 1mA of Ileak for CIPOSTM. Figure 6 shows the curve corresponding to above equation for a continuous sinusoidal modulation, if the voltage ripple ∆ VBS is 0.1V. The recommended bootstrap capacitance for a continuous sinusoidal modulation method is therefore in the range up to 4.7µF for most switching frequencies. In other PWM method case like a discontinuous sinusoidal modulation, tP must be set the longest period of the low side IGBT off. 5 CBS [uF] 4 3 2 1 0 0 5 10 15 20 fPWM [kHz] Figure 6. Size of the bootstrap capacitor as a function of the switching frequency fPWM 4.3 Internal Bootstrap Functionality Characteristics TM CIPOS includes three bootstrap functionalities in internal drive IC, which consist of three diodes and three resistors, as shown in Figure 5. Typical value of internal bootstrap resistor is 40Ω. For more information, please refer to the below table. It’s noted that RBS2 and RBS3 have same value to RBS1. Description Condition Repetitive peak reverse voltage Bootstrap resistance of U-phase VS2 or VS3=300V, TJ = 25°C VS2 and VS3=0V, TJ = 25°C VS2 or VS3=300V, TJ = 125°C VS2 and VS3=0V, TJ = 125°C Reverse recovery Forward voltage drop Symbol Min. VRRM 600 Typ. Max. Unit V RBS1 35 40 50 65 Ω IF = 0.6A, di/dt = 80A/µs trr_BS 50 ns IF = 20mA, VS2 and VS3 = 0V VF_BS 2.6 V Application Note,. Preliminary 7 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 4.4 Over Current Protection The OC (Over Current) protection level is decided by ITRIP positive going threshold voltage VIT,TH+ in CIPOSTM and shunt resistance. When ITRIP voltage exceeds VIT,TH+, CIPOSTM turns off 6 IGBTs and fault-output is activated during fault-output duration time, typically 65us. SC OC Low Side IGBT Collector Current RC circuit time constant delay Sensing Voltage of the shunt resistor SC Reference Voltage tITRIP tITRIP CIPOSTM All IGBTs don’t operate Fault Output Signal Typ. 65ms All IGBTs operate normally All IGBTs don’t operate Typ. 65ms Figure 7. Timing chart of OC protection 4.4.1 Shunt Resistor Selection The value of shunt resistor is calculated by the following equation. R SH = VIT, TH + + VFILTER, DIODE DROP I OC Where VIT,TH+ is the ITRIP positive going threshold voltage of CIPOSTM and IOC is the current of SC detection level. VIT,TH+ is 0.47Vtyp. VFILTER, DIODE is drop voltage between ITRIP and Rsh. VFILTER, DIODE is 0.62V. So the voltage of ITRIP is reached to 0.47V when voltage of RSH is 1.09V. The maximum value of OC protection level should be set less than the repetitive peak collector current in the datasheet considering the tolerance of shunt resistor. For example, the maximum peak collector current of IGCM10F60xA is 18Apeak, R SH(min) = 1.09 = 0.06Ω 18 So the recommended value of shunt resistor is over 60mΩ for IGCM10F60xA. For the power rating of the shunt resistor, the below lists should be considered. - Maximum load current of inverter (Irms) - Shunt resistor value at Tc=25°C (RSH) - Power derating ratio of shunt resistor at TSH=100°C - Safety margin Application Note,. Preliminary 8 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt And the power rating is calculated by following equation. PSH = 2 1 I rms R SH × marigin × Derating ratio 2 For example, In case of IGCM10F60xA and RSH = 60mΩ - Max. load current of inverter: 6Arms - Power derating ratio of shunt resistor at TSH = 100°C: 80% - Safety margin: 30% 1 6 2 × 0.06 × 1.3 × = 1.76W 2 0.8 So the proper power rating of shunt resistor is over 2W. Based on the previous equations, conditions and calculation method, minimum shunt resistance and resistor power according to all kinds of IGCMxxF60xA products are introduced as shown in below table. It’s noted that a proper resistance and its power over than minimum values should be chosen considering over-current protection level required in the application set. PSH = Product Maximum Peak Current Minimum Shunt Resistance, RSH Minimum Shunt Resistor Power, PSH IGCM06F60xA 12 91mΩ 1.5W IGCM10F60xA 18 60mΩ 2W IGCM15F60xA 30 37mΩ 3W IGCM20F60xA 45 25mΩ 5W 4.4.2 Delay Time The RC filter should be necessary in OC sensing circuit to prevent malfunction of OC protection from noise interference. The RC time constant is determined by applying time of noise and the withstand time capability of IGBT. When the current on shunt resistor exceeds OC protection level (IOC), this voltage is applied to the ITRIP pin of CIPOSTM via the RC filter. The filter delay time (tFilter) that the input voltage of ITRIP pin rises to the ITRIP positive threshold voltage is caused by RC filter time constant. In addition there is the shutdown propagation delay of Itrip (tITRIP). Please refer to the below table. Item Shut down propagation delay (tITRIP) Condition Min. Typ. Max. IGCM20F60xA Iout = 15A, from VIT,TH+to 10% Iout - 1540 - IGCM15F60xA Iout = 10A, from VIT,TH+to 10% Iout - 1340 - IGCM10F60xA Iout = 6A, from VIT,TH+to 10% Iout - 1260 - IGCM06x60xA Iout = 4A, from VIT,TH+to 10% Iout - 1300 - Unit ns Therefore, the total delay time from occurrence of OC to shutdown of the IGBT gate becomes t total = t Filter + t ITRIP Shut down propagation delay is in inverse proportion to the current range, therefore tITRIP is reduced at higher current condition than condition of table 14. The total delay must be less than 5ms of short circuit withstand time (tSC) in datasheet. Thus, RC time constant should be set in the range of 1~2µs. It is recommended that R10 of 1.8kΩ, R16~R18 of 100Ω, C17 of 1nF and C2~C22 of 1nF. Application Note,. Preliminary 9 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 4.5 Temperature Monitor and Protection In case of IGCMxxF60GA, built-in thermistor (85kΩ at 25°C) is connected between VFO and VSS. The typical application circuit is like Figure 8 where the VFO pin is used for both thermistor temperature detection and fault detection. The voltage of VFO pin decreases as the thermistor temperature increases due to external pull-up resistor. It is noted that the voltage variation of VFO pin due to temperature variation should be always higher than the fault detection level of micro controller. In this reference board, the pull-up resistor is set to 3.6kΩ so that the VFO voltage becomes 2.95V and 1.95V respectively for 5V and 3.3V control voltage (Vctr) when the temperature of thermistor is 100°C as shown in Figure 9. CIPOSTM IGCMxxF60GA Vctr Drive IC R11=3.6kΩ Micro Controller VFO Input to AD Converter VFO Thermistor VSS Input to Fault Detection Figure 8. Temperature monitor with built in thermistor and pull up resistor 5.0 Vctr=5V Vctr=3.3V 4.5 4.0 VFO [ V ] 3.5 3.0 2.5 OT set 100¡É : 2.95V at Vctr=5V 2.0 OT set 100¡É : 1.95V at Vctr=3.3V 1.5 1.0 0.5 0.0 0 10 20 30 40 50 60 70 80 90 o 100 Thermistor temperature [ C ] 110 120 Figure 9. Voltage of VFO according to the temperature Application Note,. Preliminary 10 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 5 Part list Symbol Components Note R1 ~ R6 100Ω, 1/8W, 5% R7 ~ R9 No Connection R10 1.8kΩ, 1/8W, 1% Series resistor for current sensing voltage R11 3.6kΩ, 1/8W, 1% Pull-up resistor for fault output voltage R12 1kΩ, 1/8W, 5% Series resistor for fault output voltage R13 ~ R15 Content 4.4.1 R16 3kΩ, 1/8W, 5% R17 ~ R19 100Ω, 1/8W, 1% C1 ~ C6 1nF, 25V C7 ~ C9 0.1uF, 25V Bypass capacitors for high side bias voltage C10 ~ C12 22uF, 35V Bootstrap capacitors C13 100uF, 35V Source capacitor for 5 or 3.3V supply voltage C14 0.1uF, 35V Bypass capacitor for 5 or 3.3V supply voltage C15 220uF, 35V Source capacitor for VDD supply voltage C16 0.1uF, 35V Bypass capacitor for VDD supply voltage C17 1nF, 25V Bypass capacitor for current sensing voltage C18 1nF, 16V Bypass capacitor for fault output voltage C19 1nF, 16V Bypass capacitor for fault output voltage C20 0.1uF, 630V C20 ~ C22 1nF, 25V D1 ~ D3 No Connection D4 ~ D6 1N4148 J1 SMW250-11P Signal & Power supply connector J2 SMW250-03P Current sensing connector U, V, W, P, N Fasten Tap Series resistors for input voltage Note 1 Current sensing resistor Pull-down resistor for ITRIP voltage Series resistor for current sensing voltage Bypass capacitors for input voltage Snubber capacitor Bypass capacitor for current sensing voltage Note 1 Series diode for current sensing voltage Power terminals Note 1: It is optional to use external bootstrap circuit together with internal one, in case that smaller bootstrap resistor is necessary. Application Note,. Preliminary 11 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 6 PCB Design Guide In general, there are several issues to be considered when designing an inverter board as below lists. - Low stray inductive connection - Isolation distance - Component placement This chapter explains above considerations and method for the layout design. Layout of Reference Board 102.5mm 6.1 64.0mm [ TOP ] [ Bottom ] Figure 10. Layout of reference board for IGCMxxF60xA Note. 2. The connection between emitters of CIPOSTM (NU, NV, NW) and shunt resistor should be as short and as wide as possible. 3. It is recommended that ground pin of micro-controller be directly connected to VSS pin. Signal ground and power ground should be as short as possible and connected at only one point via the capacitor (C16). 4. All of the bypass capacitors should be placed as close to the pins of CIPOSTM as possible. 5. The capacitor (C17) for shunt voltage sensing should be placed as close to ITRIP and VSS pins as possible. 6. In order to detect sensing voltage of the shunt resistor exactly, both sensing and ground patterns should be connected at pins of the shunt resistor and should not be overlapped with any patterns for load current as shown in Figure 10. 7. The snubber capacitor (C19) should be placed as close to the terminals as possible. 8. The power patterns of U, V, W, P, NU, NV and NW should be designed on both layer with via to cover the high current and there should be kept the isolation distance among the power patterns over 2.54mm. 9. There are milling profiles in blue line to keep the isolation distance 10. All components except IGCMxxF60xA are placed on the top layer. Application Note,. Preliminary 12 Ver. 0.4, 2010-06-01 Control Integrated POwer System (CIPOS™) Reference Board for CIPOS™ IGCMxxF60xA with 3-shunt 7 [1] Reference LS Power Semitech: CIPOSTM IGCM10F60HA; Preliminary Datasheet Ver. 0.2; LS Power Semitech, 2010 Revision History Previous Version: Ver. 0.3 Major changes since the last revision Page or Reference 12 Description of change Note 3 Application Note,. Preliminary 13 Ver. 0.4, 2010-06-01 Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBLADE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, i-Wafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. ANSI™ of American National Standards Institute. AUTOSAR™ of AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. 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