I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver BC68FB540 Revision: V1.10 Date: ����������������� December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 RF Transceiver Features.......................................................................................................... 7 General Description.......................................................................................... 7 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 8 Pin Descriptions............................................................................................... 9 Absolute Maximum Ratings............................................................................11 D.C. Characteristics........................................................................................ 12 A.C. Characteristics........................................................................................ 13 LVD/LVR Electrical Characteristics............................................................... 14 RF Transceiver Electrical Characteristics.................................................... 14 Power on Reset Electrical Characteristics................................................... 16 System Architecture....................................................................................... 16 Clocking and Pipelining.......................................................................................................... 16 Program Counter.................................................................................................................... 17 Stack...................................................................................................................................... 18 Arithmetic and Logic Unit – ALU............................................................................................ 18 Flash Program Memory.................................................................................. 19 Structure................................................................................................................................. 19 Special Vectors...................................................................................................................... 19 Look-up Table......................................................................................................................... 19 Table Program Example......................................................................................................... 20 In System Programming – ISP............................................................................................... 21 In Application Programming – IAP......................................................................................... 26 In Circuit Programming – ICP................................................................................................ 30 On-Chip Debug Support – OCDS.......................................................................................... 31 Data Memory................................................................................................... 32 Structure................................................................................................................................. 32 Special Function Register Description......................................................... 34 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 34 Memory Pointer – MP0, MP1................................................................................................. 34 Bank Pointer – BP.................................................................................................................. 35 Accumulator – ACC................................................................................................................ 35 Program Counter Low Register – PCL................................................................................... 35 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 35 Status Register – STATUS..................................................................................................... 36 Rev. 1.10 2 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Oscillator......................................................................................................... 38 Oscillator Overview................................................................................................................ 38 System Clock Configurations................................................................................................. 38 External Crystal Oscillator – HXT........................................................................................... 39 Internal PLL Frequency Generator......................................................................................... 40 Internal High Speed RC Oscillator – HIRC............................................................................ 42 Internal Low Speed 32kHz RC Oscillator – LIRC................................................................... 42 Supplementary Internal Clocks.............................................................................................. 42 Operating Modes and System Clocks.......................................................... 43 System Clocks....................................................................................................................... 43 System Operation Modes....................................................................................................... 43 Control Register..................................................................................................................... 45 Fast Wake-up......................................................................................................................... 46 Operating Mode Switching..................................................................................................... 47 Standby Current Considerations............................................................................................ 51 Wake-up................................................................................................................................. 51 Programming Considerations................................................................................................. 52 Watchdog Timer.............................................................................................. 52 Watchdog Timer Clock Source............................................................................................... 52 Watchdog Timer Control Register.......................................................................................... 52 Watchdog Timer Operation.................................................................................................... 54 Reset and Initialisation................................................................................... 55 Reset Overview...................................................................................................................... 55 Reset Functions..................................................................................................................... 56 Reset Initial Conditions.......................................................................................................... 59 Input/Output Ports.......................................................................................... 63 Pull-high Resistors................................................................................................................. 64 Port Wake-up......................................................................................................................... 65 Port A Wake-up Palarity Control Register.............................................................................. 65 I/O Port Control Registers...................................................................................................... 66 Port A Power Source Control Register................................................................................... 67 I/O Pin Structures................................................................................................................... 69 Programming Considerations................................................................................................. 69 Timer Modules – TM....................................................................................... 70 Introduction............................................................................................................................ 70 TM Operation......................................................................................................................... 70 TM Clock Source.................................................................................................................... 71 TM Interrupts.......................................................................................................................... 71 TM External Pins.................................................................................................................... 71 TM Input/Output Pin Control Registers.................................................................................. 72 Programming Considerations................................................................................................. 75 Rev. 1.10 3 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Compact Type TM – CTM............................................................................... 76 Compact Type TM Operation................................................................................................. 76 Compact Type TM Register Description................................................................................ 77 Compact Type TM Operation Modes..................................................................................... 81 Standard Type TM – STM............................................................................... 87 Standard Type TM Operation................................................................................................. 87 Standard Type TM Register Description................................................................................ 88 Standard Type TM Operation Modes..................................................................................... 94 Serial Interface Module – SIM...................................................................... 105 SPI Interface........................................................................................................................ 105 SPI Registers....................................................................................................................... 106 SPI Bus Enable/Disable....................................................................................................... 109 SPI Communication..............................................................................................................110 SPI Error Detection...............................................................................................................113 I2C Interface..........................................................................................................................113 I2C Registers.........................................................................................................................115 I2C Bus Communication........................................................................................................119 I2C Time-out Function........................................................................................................... 122 Peripheral ClockOutput................................................................................ 123 Peripheral Clock Operation.................................................................................................. 123 Serial Interface – SPIA.................................................................................. 125 SPIA Interface Operation..................................................................................................... 125 SPI Registers....................................................................................................................... 126 SPIA Bus Enable/Disable..................................................................................................... 129 SPIA Communication........................................................................................................... 129 Error Detection..................................................................................................................... 133 Interrupts....................................................................................................... 134 Interrupt Registers................................................................................................................ 134 Interrupt Operation............................................................................................................... 140 External Interrupt.................................................................................................................. 141 USB Interrupt....................................................................................................................... 142 Serial Interface Module Interrupt – SIM Interrupt................................................................. 142 Serial Peripheral Interface Interrupt – SPIA Interrupt........................................................... 142 Low Voltage Detect Interrupt – LVD Interrupt....................................................................... 142 Multi-function Interrupt......................................................................................................... 143 TM Interrupts........................................................................................................................ 143 Interrupt Wake-up Function.................................................................................................. 143 Programming Considerations............................................................................................... 144 Low Voltage Detector – LVD........................................................................ 145 LVD Register........................................................................................................................ 145 LVD Operation...................................................................................................................... 146 Rev. 1.10 4 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver USB Interface................................................................................................ 146 Power Planning.................................................................................................................... 146 USB Suspend Wake-up and Remote Wake-up................................................................... 147 USB Interface Operation...................................................................................................... 147 USB Interface Registers....................................................................................................... 148 RF Transceiver.............................................................................................. 158 RF Transceiver Abbreviations.............................................................................................. 158 RF Transceiver State Control............................................................................................... 159 RF Transceiver Packet Processing...................................................................................... 161 RF Transceiver Data and Control Interface.......................................................................... 165 RF Transceiver Register Map.............................................................................................. 168 Configuration Options.................................................................................. 184 Application Circuit........................................................................................ 184 Instruction Set............................................................................................... 185 Introduction.......................................................................................................................... 185 Instruction Timing................................................................................................................. 185 Moving and Transferring Data.............................................................................................. 185 Arithmetic Operations........................................................................................................... 185 Logical and Rotate Operation.............................................................................................. 186 Branches and Control Transfer............................................................................................ 186 Bit Operations...................................................................................................................... 186 Table Read Operations........................................................................................................ 186 Other Operations.................................................................................................................. 186 Instruction Set Summary............................................................................. 187 Table Conventions................................................................................................................ 187 Instruction Definition.................................................................................... 189 Package Information.................................................................................... 198 SAW type 46-pin (6.5mm×4.5mm) QFN Outline Dimensions.............................................. 199 Rev. 1.10 5 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Features CPU Features • Operating voltage ♦♦ fSYS = 6MHz/12MHz: 3.3V~5.5V • Up to 0.33μs instruction cycle with 12MHz system clock at VDD= 5V • Power down and wake-up functions to reduce power consumption • Three oscillators ♦♦ External Crystal – HXT ♦♦ Internal RC – HIRC ♦♦ Internal 32kHz RC – LIRC • Internal 12MHz RC OSC with 0.25% accuracy for all USB modes • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 62 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K×16 • RAM Data Memory: 256×8 • USB 2.0 Full Speed compatible • 4 endpoints supported including endpoint 0 • All endpoints except endpoint 0 can support interrupt and bulk transfer • All endpoints except endpoint 0 can be configured as 8, 16, 32, 64 bytes FIFO size • Endpoint 0 support control transfer • Endpoint 0 has 8 byte FIFO • Support 3.3V LDO and internal UDP 1.5K ohm pull-up resistor • 2 Compact type 10-bit Timer Module – CTM • 1 Standard type 10-bit Timer Module – STM • 1 Standard type 16-bit Timer Module – STM • Watchdog Timer function • Up to 8 bidirectional I/O lines • Dual pin-shared external interrupts • Multiple Timer Modules for time measurement, input capture, compare match output or PWM output or single pulse output function • Serial Interface Modules with both SPI and I2C interfaces • Single Serial SPI interface • Low voltage reset function • Low voltage detect function Rev. 1.10 6 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Support In System Programming function – ISP • Package type: 46-QFN • Flash program memory can be re-programmed up to 1,000,000 times • Flash program memory data retenton > 10 years RF Transceiver Features • Low Power High Performance 2.4GHz GFSK Transceiver • 2400-2483.5MHz ISM band operation • Support 250Kbps, 1Mbps and 2Mbps air data rate • Programmable output power • Variable payload length from 1 to 32 bytes • Automatic packet processing • 6 data pipes for 1:6 star networks General Description The device is a Flash Memory I/O with USB type 8-bit high performance RISC architecture microcontrollers, designed for applications that interface directly to which require an USB interface. Offering users the convenience of Flash Memory multiprogramming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI, I2C and USB interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The external interrupt can be triggered with falling edges or both falling and rising edges. A full choice of three oscillator functions are provided including two fully integrated system oscillators which requires no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimize microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features along with many other features ensure that the devices will find specific excellent use in a wide range of application possibilities such as motor driving, industrial control, consumer products, subsystem controllers, etc. The devices are fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast and efficient product development cycles. Rev. 1.10 7 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Block Diagram Reset Ci��uit Flash P�og�a��ing Ci��uit�y (ICP) Wat�hdog Ti�e� Flash P�og�a� Me�o�y Low Voltage Reset RAM Data Me�o�y Ti�e� Modules I/O Inte��upt Cont�olle� 8-�it RISC MCU Co�e HXT Os�illato� Low Voltage Dete�t SIM (SPI/I�C) Inte�nal RC Os�illato�s SPIA USB �.0 Full Speed Engine USB �.0 XCVR �.�GHz RF T�ans�eive� 3.3V Regulato� Pin Assignment NC RES/OCDSCK PA�/TP3_1/OSC� PA0/TCK1/OCDSDA NC PE0/VDDIO NC NC PA1/TP�_1/OSC1 NC XTALP NC XTALN NC �6 �5 �� �3 �� �1 �0 39 38 37 36 35 3� 33 VDDPA 1 3� NC RFP1 � 31 NC RFN1 3 30 NC �9 VSS �8 HVDD NC � VDD3RXRF 5 VDD3IF 6 �7 VDD VDD3B 7 �6 V33O CDVDD 8 �5 UDP/GPIO1 NC 9 �� UDN/GPIO0 BC68FB540 46 QFN-A 10 11 1� 13 1� 15 16 17 18 19 �0 �1 �� �3 PA�/SDOA/TP0_0/MOSI PA3/TCK� PA5/SDIA/TP1_0/MISO IRQ PA7/INT0/SCSA/CSN NC PA6/TCK0/SCKA NC NC NC NC RFSCK CE VSSRX� Note: If the MCU pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the “/” sign can be used for higher priority. Rev. 1.10 8 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Pin Descriptions Pin Name PA0/TCK1/ OCDSDA PA1/TP2_1/ OSC1 PA2/TP3_1/ OSC2 PA3/TCK2 PA4/SDOA/ TP0_0/MOSI PA5/SDIA/ TP1_0/MISO PA6/TCK0/ SCKA PA7/INT0/SCSA/ CSN PE0/VDDIO RES/OCDSCK UDN/GPIO0 Function OPT I/T PA0 PAPU PAWU ST O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up TCK1 — ST OCDSDA — ST CMOS On-Chip Debug Support data pin for OCDS EV chip only — PA1 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up TP2_1 TMPC1 ST CMOS TM2 I/O OSC1 CO HXT PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP3_1 TMPC1 ST CMOS TM3 I/O OSC2 CO — PA3 PAPU PAWU ST TCK2 — ST PA4 PAPU PAWU ST — HXT TM1 input HXT Pin Chip enable activates RX or TX mode CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM2 input CMOS General purpose I/O. Register enabled pull-up and wake-up. SDOA — — CMOS SPIA data output TP0_0 TMPC0 ST CMOS TM0 I/O MOSI — — PA5 PAPU PAWU ST SDIA — ST TP1_0 TMPC0 ST MISO — — PA6 PAPU PAWU ST — RF Transceiver SPI slave data input Internally connected to SDOA line. CMOS General purpose I/O. Register enabled pull-up and wake-up. — SPIA data input CMOS TM1 I/O — RF Transceiver SPI slave data output with tri-state option Internally connected to SDIA line. CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK0 — ST SCKA — ST CMOS SPIA Serial Clock — PA7 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM0 input INT0 — ST SCSA — ST External interrupt 0 CSN — — PE0 PXPU PXWU ST VDDIO CO PWR — RES — ST — Reset pin OCDSCK — ST — On-Chip Debug Support clock pin for OCDS EV chip only CMOS SPIA Slave Select — RF Transceiver SPI chip select, active low. Internally connected to SCSA line. CMOS General purpose I/O. Register enabled pull-up and wake-up. PA external power input UDN — ST CMOS USB UDN line GPIO0 — ST CMOS General purpose I/O UDP — ST CMOS USB UDP line GPIO1 — ST CMOS General purpose I/O V33O V33O — — PWR VDD VDD — PWR — Power supply HVDD — PWR — HIRC oscillator positive power supply UDP/GPIO1 HVDD Rev. 1.10 3.3V regulator output 9 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Pin Name VSS Function OPT I/T O/T VSS — PWR — Negative power supply, ground. Description RFP1 RFP1 — — — RF positive input/output port RFN1 RFN1 — — — RF negative input/output port CE — — — Chip enable activates RX or TX mode CE IRQ IRQ — — — Maskable interrupt pin, active low. RFSCK RFSCK — — — SPI clock XTALP XTALP — — — Crystal oscillator node P (inverter output) XTALN XTALN — — — Crystal oscillator node N (inverter input) VDDPA VDDPA — — — 1.8V regulator output for power amplifier VDD3RXRF — — PWR — RF transceiver positive power supply VDD3IF — — PWR — RF transceiver positive power supply VDD3B VDD3B — PWR — RF transceiver positive power supply CDVDD CDVDD — — — 1.8V regulator output decoupling capacitor pin VSSRX2 VSSRX2 — PWR — RF transceiver negative power supply, ground. NC — — — Not connected. NC Note: OPT: Optional by configuration option (CO) or register option I/T: Input type O/T: Output type CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output NMOS: NMOS output PWR: Power HXT: High frequency crystal oscillator For certain reason some I/O lines may be not bonded to external pins and should be properly configured to avoid a floating condition which will result in additional current leakage. MCU Control Pins Pin Name 2.4GHz RF Transceiver Pins Pin Type Pin Name Pin Type I PA0/TCK1 O CE PA7/INT0/SCSA O CSN I PA3/TCK2 I IRQ O PA5/SDIA/TP1_0 I MISO O PA4/SDOA/TP0_0 O MOSI I PA6/TCK0/SCKA O RFSCK I Connections between 2.4GHz RF Transceiver and MCU Pins Rev. 1.10 10 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver VDD3RXRF/ VDD3IF VDD VDD Interface Control Circuitry VDD3B VDD3RXRF/ VDD3IF SCSA CSN SDOA MOSI SDIA MISO SCKA RFSCK TCK� IRQ PA0 VDD3B VDDPA CDVDD 2.4G RF Transceiver RFP1 RFN1 CE XTALP XTALN VSS VSSRX� 2.4GHz RF Transceiver and MCU Connection Diagram Note: When communicating with the RF transceiver using the SPIA interface, care must be taken: 1. Set both PAPS0 and PAPS1 registers to “0xFFH”. 2. Set both SACKPOL and SACKEG bits in the SPIAC1 register to 1. 3. Set RUBUS bit in the SYSC register to 1 after power-on reset. 4. Set T0PC0 bit in the TMPC0 register to 0. Absolute Maximum Ratings Supply Voltage ..................................................................................................VSS-0.3V to VSS +6.0V Input Voltage ....................................................................................................VSS-0.3V to VDD +0.3V IOL Total....................................................................................................................................... 150mA IOH Total...................................................................................................................................... -100mA Total Power Dissipation..............................................................................................................500mV Storage Temperature ......................................................................................................-50°C to 125°C Operating Temperature . .................................................................................................. -40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 11 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver D.C. Characteristics Ta=25°C Symbol VDD Parameter Test Conditions 2.2 — 5.5 V fSYS = 12MHz 2.7 — 5.5 V fSYS = 12MHz 2.7 — 5.5 V 3V fSYS = fH = 6MHz, no load, WDT enable, All peripherals off — 1.0 2.0 mA — 2.5 5.0 mA fSYS = fH = 12MHz, no load, WDT enable, All peripherals off — 2.0 4.0 mA — 4.0 7.0 mA IDD 5V fSYS = fH = 6MHz, no load, WDT enable USB/PLL/V33O enable — 10 15 mA 5V fSYS = fH = 12MHz, no load, WDT enable USB/PLL/V33O enable — 11 16 mA fSYS = fH = 12MHz, no load, WDT enable All peripherals off — 2.0 4.0 mA — 4.0 7.0 mA fSYS = fH = 12MHz, no load, WDT enable USB/PLL/V33O enable — 5.5 10 mA — 11 16 mA fSYS = fL = fLIRC = 32kHz No load, WDT/LVR enable — 40 80 μA — 70 150 μA fSYS = fH or fL disabled, no load, All peripherals off, WDT enable — 1.5 3.0 μA — 3.0 6.0 μA fSYS = fH = fHXT or fHIRC enabled, no load, All peripherals off, WDT enable — 0.8 1.5 mA — 1.5 3.0 mA No load, all peripherals off, WDT disable — 0.1 1.0 μA — 0.3 2.0 μA No load, all peripherals off, WDT disable, LVD/LVR enable — 60 90 μA No load, all peripherals off, WDT disable, USB/V33O enable, SUSP2=0 — 360 420 μA No load, all peripherals off, WDT disable, USB/V33O enable, SUSP2=1 — 240 320 μA 3V Operating Current (HIRC) 5V 3V 5V Operating Current (LIRC) Standby Current (IDLE0 Mode) Standby Current (IDLE1 Mode) ISTB Standby Current (SLEEP0 Mode) Standby Current (SLEEP1 Mode) Suspend Current (SLEEP0 Mode) 3V 5V 3V 5V 3V 5V 3V 5V — 5V Input Low Voltage for I/O Ports or Input Pins — — 0 — 0.2VDD V Input Low Voltage for RES pin — — 0 — 0.4VDD V Input High Voltage for I/O Ports or Input Pins — — 0.8VDD — VDD V — Input High Voltage for RES pin Sink Current for I/O Port 0.9VDD — VDD V 3V — VOL = 0.1VDD 4 8 — mA 5V VOL = 0.1VDD 10 20 — mA 3V VOH = 0.9VDD -2 -4 — mA 5V VOH = 0.9VDD -5 -10 — mA IV33O = 70 mA 3.0 3.3 3.6 V 1.9 3.0 3.6 V IOH Source Current for I/O Port VV33O 3.3V Regulator Output 5V VDDIO I/O Port A supply power voltage — Rev. 1.10 fSYS = 6MHz — Operating Current (HXT) IOL Unit Operating Voltage (HIRC) 5V VIH Max. — 3V VIL Typ. Operating Voltage (HXT) 5V ISUS Min. Conditions VDD — 12 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Symbol Parameter Test Conditions VDD Conditions 3V — 5V — RPH Pull-high Resistance for I/O Ports RPL Pull-low Resistance for UBUS Pins RUDP Pull-high Resistance from UDP to 3.3V V33O SUSP2=1, RUBUS=0 5V — Min. Typ. Max. Unit 20 60 100 kΩ 10 30 50 kΩ 0.5 1 1.5 MΩ -5% 1.5 +5% kΩ A.C. Characteristics Ta=25°C Symbol Parameter System Clock (HXT) fSYS System Clock (HIRC) Test Condition VDD Condition Min. Typ. Max. Unit 3.3V~5.5V — 2 — 6 MHz 3.3V~5.5V — 2 — 12 MHz 3.3V~5.5V Non-USB mode, Ta = 25°C -3% 12 +3% MHz 3.3V~5.5V Non-USB mode, Ta = -40°C to 85°C -6% 12 +6% MHz 3.3V~5.5V Non-USB mode, Ta = -40°C to 85°C -10% 12 +10% MHz -0.25% 12 -10% 32 +10% kHz -50% 32 +60% kHz 3.3V~5.5V USB mode 5V Ta = 25°C +0.25% MHz fLIRC Low Speed RC oscillator Clock (LIRC) tTCK TCK pin Minimum Input Pulse Width — — 0.3 — — μs tINT Interrupt Pin Minimum Input Pulse Width — — 10 — — μs tRES External Reset Pin Minimum Input Pulse Width — — 10 — — μs — fSYS = fH =fHXT 1024 — — tSYS — fSYS = fH =fHIRC 1024 — — tSYS — fSYS = fL = fLIRC 2 — — tSYS System Start-up Timer period (Wake-up from power down mode, fSYS on) — — 2 — — tSYS System Start-up Timer period (Reset) — — 1024 — — tSYS System reset delay time (Power-on reset) — — 25 50 100 ms System reset delay time (Any reset except power-on reset) — — 8.3 16.7 33.3 ms Minimum Software Reset Pulse Width to Reset — — 45 90 120 μs System Start-up Timer Period (Wake-up from power down mode, fSYS off) (SLOW → NORMAL mode) tSST tRSTD tSRESET 2.2V~5.5V Ta = -40°C to 85°C Note: tSYS= 1/fSYS Rev. 1.10 13 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver LVD/LVR Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter Min. Typ. Max. Unit Conditions VDD LVR Enable, voltage select 2.1V VLVR VLVD Low Voltage Reset Voltage — Low Voltage Detector Voltage — 2.1 LVR Enable, voltage select 2.55V Typ. 2.55 Typ. LVR Enable, voltage select 3.15V -5% 3.15 +5% LVR Enable, voltage select 3.8V 3.8 LVD Enable, voltage select 2.0V 2.0 LVD Enable, voltage select 2.2V 2.2 LVD Enable, voltage select 2.4V 2.4 LVD Enable, voltage select 2.7V LVD Enable, voltage select 3.0V Typ. -5% 2.7 3.0 LVD Enable, voltage select 3.3V 3.3 LVD Enable, voltage select 3.6V 3.6 LVD Enable, voltage select 4.0V V Typ. +5% V 4.0 — 30 45 μA — 60 90 μA ILVD Additional Current Consumption if LVD/LVR is used 3V LVR Enable, 5V LVD Disable → Enable tBGS VBG Turn on Stable Time — No load — — 10 ms LVR Enable, LVD Disable → Enable — — 15 μs tLVDS LVDO stable time — tLVR Minimum Low Voltage Width to Reset — — 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt — — 60 120 240 μs RF Transceiver Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit 3.0 3.6 V VDDRF RF operating voltage (VDD3RXRF, VDD3IF, VDD3B) — — 1.9 VIHRF RF digital input high voltage — — 0.7VDDRF — 5.25 V VILRF RF digital input low voltage — — 0 — 0.3VDDRF V VOHRF RF digital output high voltage — I=-0.25mA VDDRF-0.3V — VDDRF V I=0.25mA VOLRF RF digital output low voltage — 0 — 0.3 V ISTBRF1 RF power down current — — — 4 — μA μA ISTBRF2 RF standby-I current — — — 90 — ISTBRF3 RF standby-II current — — — 330 — μA fOP RF Operating frequency — — 2400 — 2527 MHz RFSK Air data rate — — 250 — 2000 Kbps Rev. 1.10 14 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Symbol Parameter Test Conditions Conditions VDD Min. Typ. Max. Unit dBm Transmitter PRF PBW IDDTX Output power Modulation 20dB bandwidth Transmitter operating current — -40 0 3 — RFSK=2Mbps — — 2.5 — MHz — RFSK=1Mbps — 1.8 — MHz — RFSK=250Kbps — 1.6 — MHz — PRF=-40dBm — 8 — mA — PRF=-30dBm — 8.6 — mA — PRF=-20dBm — 10 — mA — PRF=-10dBm — 11.5 — mA — PRF=-6dBm — 12 — mA — PRF=-1dBm — 16.5 — mA — PRF=3dBm — 25 — mA — RFSK=2Mbps — 17 — mA — RFSK=1Mbps — 17 — mA — RFSK=250Kbps — 16 — mA — 20 — dBm Receiver IDDRX Receiver operating current MaxInput IE-3 BER RXSENS IE-3 BER sensitivity — — — RFSK=2Mbps — -87 — dBm — RFSK=1Mbps — -90 — dBm — RFSK=250Kbps — -96 — dBm 6 — dB dB C/I CO Co-channeL C/I (2Mbps) — — — C/I+1ST ACS C/I 2MHz (2Mbps) — — — 2 — C/I-1ST ACS C/I 2MHz (2Mbps) — — — -6 — dB C/I+2ND ACS C/I 4MHz (2Mbps) — — — -21 — dB C/I-2ND ACS C/I 4MHz (2Mbps) — — — -12 — dB C/I+3RD ACS C/I 6MHz (2Mbps) — — — -29 — dB C/I-3RD ACS C/I 6MHz (2Mbps) — — — -18 — dB C/I CO Co-channel C/I (1Mbps) — — — 6 — dB C/I+1ST ACS C/I 1MHz (1Mbps) — — — 4 — dB C/I-1ST ACS C/I 1MHz (1Mbps) — — — -6 — dB C/I+2ND ACS C/I 2MHz (1Mbps) — — — -24 — dB C/I-2ND ACS C/I 2MHz (1Mbps) — — — -12 — dB C/I+3RD ACS C/I 3MHz (1Mbps) — — — -28 — dB C/I-3RD ACS C/I 3MHz (1Mbps) — — — -16 — dB C/I CO Co-channel C/I (250Kbps) — — — 9 — dB C/I+1ST ACS C/I 1MHz (250Kbps) — — — -13 — dB C/I-1ST ACS C/I 1MHz (250Kbps) — — — -16 — dB C/I+2ND ACS C/I 2MHz (250Kbps) — — — -25 — dB C/I-2ND ACS C/I 2MHz (250Kbps) — — — -9 — dB C/I+3RD ACS C/I 3MHz (250Kbps) — — — -33 — dB C/I-3RD ACS C/I 3MHz (250Kbps) — — — -33 — dB Rev. 1.10 15 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Power on Reset Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. Rev. 1.10 16 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, which is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.10 17 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.10 18 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. 0000H Initialisation Ve�to� 000�H Inte��upt Ve�to�s 00�8H 00�CH n00H nFFH 0FFFH Look-up Ta�le 16 �its Program Memory Structure Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD[m]” instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as “0”. The accompanying diagram illustrates the addressing data flow of the look-up table. Rev. 1.10 19 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver A d d re s s T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is”0F00H” which refers to the start address of the last page within the 4K Program Memory of the device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “0F06H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,0Fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “0F06H” transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address “0F05H” transferred to tempreg2 and TBLH in this ; example the data “1AH” is transferred to tempreg1 and data “0FH” to ; register tempreg2 : : org 0F00h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.10 20 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver In System Programming – ISP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-system using a two-line USB interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Program Memory can be programmed serially in-system using the USB interface, namely using the UDN and UDP pins. The power is supplied by the UBUS pin. The technical details regarding the in-system programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. The Flash Program Memory Read/ Write function is implemented using a series of registers. Flash Memory Read/Write Page Size The 32 words page size is assigned for this device. The following diagram illustrates the Read/Write page and buffer assignment. The write buffer is controlled by the CLWB bit in the FRCR register. The CLWB bit can be set high to enable the Clear Write Buffer procedure, as the procedure is finished, this bit will be cleared to low by hardware. The Write Buffer is filled when the FWEN bit is set to high, when this bit is set high, the data in the Write buffer will be written to the Flash ROM, the FWT bit is used to indicate the writing procedure. Setting this bit high and check if the write procedure is finished, this bit will be cleared by hardware. The Read Byte can be assigned by the address. The FRDEN is used to enable the read function and the FRD is used to indicate the reading procedure. When the reading procedure is finished, this bit will be cleared by hardware. Flash Me�o�y W�ite Buffe� FARH FARL FD0H FD0L CLWB Write one word to FD0L/FD0H Flash Me�o�y FARH FARL FD0H FD0L Read one word to FD0L/FD0H Rev. 1.10 21 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Note: 1. Writing a data into high byte, which means the H/L Data is written into Write Buffer, will cause the Flash memory address increased by one automatically and the new address will be loaded to the FARH and FARL registers. However, the user can also fill the new address by filling the data into FARH and FARL registers in the same page, then the data will be written into the corresponding address. 2. If the address already reached the boundary of the flash memory, such as 11111b of the 32 words. At this moment, the address will not be increased and the address will stop at the last address of that page and the writing data is invalid. 3. At this point, the user has to set a new address again to fill a new data. 4. If the data is writing using the write buffer, the write buffer will be cleared by hardware automatically after the write procedure is ready in 2ms. 5. First time use the Write buffer or renew the data in the Write buffer, the user can use to Clear buffer bit (CLWB) to clear write buffer. ISP Bootloader The devices provide the ISP Bootloader function to upgrade the software in the Flash memory. The user can select to use the ISP Bootloader application software provided by Holtek IDE tool or to create the own Bootloader software. When the Holtek Bootloader software is selected, that will occupy 0.5K words area in the Flash memory. The accopanying diagram illustrates the Flash memory structure with Holtek Bootloader software. Bootloade� 0000H 0D00H 0DFFH Last Page Flash Program Memory Registers There are two address registers, four 16-bit data registers and two control register. The control register is located in Bank1 and the other registers are located in Bank0. Read and Write operations to the Flash memory are carried out in 16-bit data operations using the address and data registers and the control register. Several registers control the overall operation of the internal Flash Program Memory. The address registers are named FARL and FARH, the data registers are named FDnL and FDnH, and the control registers are named FCR and FRCR. As the FARL and FDnL registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The FARH, FDnH, FCR and FRCR registers however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Rev. 1.10 22 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit Register Name 7 6 5 4 3 2 1 0 A0 FARL A7 A6 A5 A4 A3 A2 A1 FARH — — — — A11 A10 A9 A8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 D0 FD2L D7 D6 D5 D4 D3 D2 D1 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD FRCR — — — FSWRST — — — CLWB ISP Registers List • FARL Register Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown Bit 7~0A7~A0: Flash Memory Address bit 7 ~ bit 0 • FARH Register Bit 7 6 5 4 3 2 1 0 Name — — — — A11 A10 A9 A8 R/W — — — — R/W R/W R/W R/W POR — — — — x x x x “x”: unknown Bit 7~4 Unimplemented, read as “0” Bit 3~0A11~A8: Flash Memory Address bit 11 ~ bit 0 • FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 The first Flash Memory data bit 7 ~ bit 0 23 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 15 ~ bit 8 • FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 The second Flash Memory data bit 7 ~ bit 0 • FD1H Register Bit 7 6 5 4 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 15 ~ bit 8 • FD2L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 7 ~ bit 0 • FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 The third Flash Memory data bit 15 ~ bit 8 • FD3L Register Bit 6 5 4 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 7 The fourth Flash Memory data bit 7 ~ bit 0 24 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 15 ~ bit 8 • FCR Register Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7CFWEN: Flash ROM Write Enable bit, FWEN, control bit 0: Disabled 1: Unimplemented This bit is used to control the FWEN bit enable or disable. When this bit is cleared to low by software, the Flash memory write enable control bit, FWEN will be cleared to low as well. It’s ineffective to set this bit to high. The user can check this bit to confirm the FWEN status. Bit 6~4FMOD2~FMOD0: Flash Program memory – Configuration option memory operating mode control bits 000: Write memory mode 001: Page erase mode 010: Reserved 011: Read memory mode 10x: Reserved 110: FWEN mode – Flash memory Write Enabled mode 111: Reserved Bit 3BWT: Mode cahnge control 0: Mode change cycle has finished 1: Activate a mode change cycle This bit will be automatically reset to zero by the hardware after the mode change cycle has hinished. Bit 2FWT: Flash memory Write control 0: Write cycle has finished 1: Activate a write cycle This bit is the Flash memory Write control bit and when set high by application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Bit 1FRDEN: Flash memory Read Enable control 0: Disable 1: Enable This bit is the Flash memory Read Enable control bit which must be set high before Flash memory read operations are carried out. Clearing this bit to zero will inhibit Flash memory read operations. Rev. 1.10 25 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit 0FRD: Flash memory Read control 0: Read cycle has finished 1: Activate a read cycle This is the Flash memory Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The FWT, FRDEN and FRD registers can not be set to “1” at the same time with a single instruction. • FRCR Register Bit 7 6 5 4 3 2 1 0 Name — — — FSWRST — — — CLWB R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 Unimplemented, read as “0” Bit 4FSWRST: Control bit This bit must be cleared to zero. Bit 3~1 Unimplemented, read as “0” Bit 0CLWB: Flash program memory Write Buffer Clear control bit 0: Do not initiate Clear Write Buffer process 1: Initiate Write Buffer Clear process This bit is used to control the Flash Program memory clear Write buffer process. It will be set by software and cleared by hardware. In Application Programming – IAP Offering users the convenience of Flash Memory multi-programming features, the device provides not only an ISP function, but also an additional IAP function. The convenience of the IAP function is that it can execute the updated program procedure using its internal firmware, without requiring an external Program Writer or PC. In addition, the IAP interface can also be any type of communication protocol, such as UART or CAN, using I/O pins. Designers can assign I/O pins to communicate with the external memory device, including the updated program. Regarding the internal firmware, the user can select versions provided by HOLTEK or create their own. The following section illustrates the procedures regarding how to implement IAP firmware. Enable Flash Write Control Procedure The first procedure to implement the IAP firmware is to enable the Flash Write control which includes the following steps. • Write data “110” to the Fmod [2:0] bits in the FCR register to enable the Flash write control bit, FWEN. • Set the BWT bit in the FCR register to “1”. • The device will start a 1ms counter. The user should write the correct data pattern into the Flash data registers, namely FD1L~FD3L and FD1H~FD3H, during this period of time. • Once the 1ms counter has overflowed or if the written pattern is incorrect, the enable Flash write control procedure will be invalid and the user should repeat the above procedure. • No matter whether the procedure is valid or not, the devices will clear the BWT bit automatically. Rev. 1.10 26 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • The enable Flash write pattern data is (00H 04H 0DH 09H C3H 40H) and it should be written into the Flash data registers. • Once the Flash write operation is enabled, the user can update the Flash memory using the Flash control registers. • To disable the Flash write procedure, the user can only clear the CFWEN bit in the FCR register. There is no need to execute the above procedure. Set FWEN F�od �~0=110 : Set FWEN �it BWT =1�Ha�dwa�e set a �ounte� W�tie the following patte�n to Flash Data �egiste� FD 1L = 00h � FD 1H = 0�h FD �L =0dh � FD �H = 09h FD 3L =C3h � FD 3H = �0h No Is �ounte� ove�flow? BWT=0? Yes Is patte�n is �o��e�t ? No Yes CFWEN=1 . Set FWEN �it su��ess CFWEN=0 Set FWEN �it fail END Enable Flash Write Procedure Rev. 1.10 27 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Flash Memory Write and Read Procedures The following flow charts illustrate the Write and Read Flash memory procedures. Write Flash ROM Set FWEN procedure Page Erase FAH=xxh, FAL=xxh Fmod2~0=001 FWT=1 No FWT=0 ? Yes Write Fmod2~0=000 Write data to Write Buffer [(ROM ≤ 8K → 1~32 Words data) or (ROM > 8K → 1~64 Words data)]: Flash address register: FAH=xxh, FAL=xxh Write the following data to register: FD0L=xxh, FD0H=xxh No Write Buffer Finish? Write next data Yes FWT=1 No FWT=0 ? Yes Write Finish ? No Write next Page Yes Clear CFWEN bit END Write Flash Program Memory Procedure Rev. 1.10 28 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Read Flash F�od�~0=011 FRDEN=1 flash add�ess �egiste�: FAH=xxh� FAL=xxh FRD=1 No FRD=0 ? Yes Read value: FD0L=xxh� FD0H=xxh No Read Finish ? Yes FRDEN=0 Clea� CFWEN �it END Read Flash Program Memory Procedure Rev. 1.10 29 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA UDN Programming Serial Data/Address ICPCK RES Programming Clock VDD VDD/HVDD VSS VSS Power Supply Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, user should take control of the UDN and RES pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Note: * may be resistor or capacitor. The resistance of * must be greater than 300W or the capacitance of * must be less than 1nF. Rev. 1.10 30 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver On-Chip Debug Support – OCDS There is an EV chip named BC68VB540 which is used to emulate the real MCU device named BC68FB540. This EV chip device also provides the “On-Chip Debug” function to debug the real MCU device during development process. The two devices, EV chip and real MCU, are almost functional compatible except the “On-Chip Debug” function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Rev. 1.10 Holtek e-Link Pins EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD/HVDD VSS VSS Power Supply Ground 31 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. Capacity Banks 256×8 0: 80H~FFH 1: 80H~FFH The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks, the structure of which depends upon the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the FRCR, FCR, FARH and FDnH registers at address from 40H to 46H, which are only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. 00H Spe�ial Pu�pose Data Me�o�y �0H �6H 7FH 80H Gene�al Pu�pose Data Me�o�y FFH Bank 0 Bank 1 Data Memory Structure Rev. 1.10 32 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bank 0� 1 IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC �0H �1H ��H �3H ��H �5H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH 50H INTC0 INTC1 51H INTC� 5�H 53H MFI0 5�H 55H MFI1 56H 57H 58H PAWU 59H PAPU 5AH PA PAC 5BH PADIR 5CH 5DH 5EH PXWU 5FH PXPU 60H 61H PB 6�H PBC 63H 6�H 65H 66H 67H PE 68H PEC 69H 6AH 6BH 6CH | 6DH | 6EH | 6FH 36H 70H I�CTOC 37H 71H 38H SIMC0 7�H SIMC1 39H 73H SIMD 3AH 7�H SIMA/SIMC� 3BH 75H SPIAC0 3CH 76H | SPIAC1 3DH 3EH SPIAD 79H 7AH 3FH SBSC 7BH 7CH : Unused� �ead as 00H 7DH 7EH 7FH 00H 01H 0�H 03H 0�H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 1�H 13H 1�H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH �0H �1H ��H �3H ��H �5H �6H �7H �8H �9H �AH | Bank 0 Bank 1 FRCR FCR FARL FARH FD0L FD0H FD1L FD1H FD�L FD�H FD3H FD3L TMPC0 TMPC1 TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH TM0RP TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH TM�C0 TM�C1 TM�DL TM�DH TM�AL TM�AH TM3C0 TM3C1 TM3DL TM3DH TM3AL TM3AH USB_STAT UINT USC USR UCC AWR STLI STLO SIES MISC UFIEN UFOEN UFC0 UFC1 FIFO0 FIFO1 FIFO� FIFO3 CTRL LVRC PAPS0 PAPS1 SYSC Special Purpose Data Memory Structure Rev. 1.10 33 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM registers space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data only from Bank 0 while the IAR1 and MP1 register pair can access data from any Data Memory bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointer – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Exanple adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.10 34 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bank Pointer – BP Depending upon which device is used, the Program and Data Memory are divided into several banks. Selecting the required Data Memory area is achieved using the Bank Pointer bits 0. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as “0” Bit 0DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.10 35 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.10 36 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x “x”: unknown Bit 7~6 Unimplemented, read as “0” Bit 5TO: Watchdog Time-out flag 0: After power up ow executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred Bit 4PDF: Power down flag 0: After power up ow executing the “CLR WDT” instruction 1: By executing the “HALT” instructin Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The “C” flag is also affected by a rotate through carry instruction. Rev. 1.10 37 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Oscillator Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through register programming. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Name Frequency Pins External High Speed Crystal Type HXT 6 or 12MHz OSC1/OSC2 Internal High Speed RC HIRC 12MHz — Internal Low Speed RC LIRC 32kHz — Oscillator Types Note: For USB applications, HXT must be connected a 6MHz or 12MHz crystal. System Clock Configurations There are several oscillator sources, two high speed oscillators and one low speed oscillator. The high speed system clocks are sourced from the external crystal/ ceramic oscillator, the PLL frequency generator and the internal 12MHz RC oscillator. The low speed oscillator is the internal 32 kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. In addition, the internal PLL frequency generator, whose clock source is supplied by an external crystal oscillator, can be enabled by a software control bit to generate various frequencies for the USB interface and system clock. Rev. 1.10 38 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver HXT fH USBCKEN Config. Option Sele�ts 6 o� 1�MHz XTAL To USBCK �i��uits HOSC 16MHz HOSC PLL HIRC SYSCLK SYSCLK P�es�ale� PLL 6MHz Configu�ation Option fH PLL �lo�k 1�MHz FSYS16MHZ fH/� fH/� fH/8 fH/16 fH/3� fH/6� fL LIRC fSYS PLL HLCLK� CKS�~CKS0 fL fSUB Fast Wake-up f�o� SLEEP o� IDLE �ode Cont�ol (fo� HXT only) WDT System Clock Configurations External Crystal Oscillator – HXT The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the default oscillator clock source after power on. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Crystal/Ceramic System Oscillator – HXT HXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0 pF 0 pF 8MHz 0 pF 0 pF 4MHz 0 pF 0 pF 12MHz 100 pF 100 pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Note: For USB applications, HXT must be connected a 6MHz or 12MHz crystal. Rev. 1.10 39 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Internal PLL Frequency Generator The internal PLL frequency generator is used to generate the frequency for the USB interface and the system clock. This PLL generator can be enabled or disabled by the PLL control bit in the USC register. After a power on reset, the PLL control bit will be set to “0” to turn on the PLL generator. The PLL generator will provide the fixed 48MHz frequency for the USB operating frequency and another frequency for the system clock source which can be 6MHz, 12MHz or 16MHz. The selection of this system frequency is implemented using the SYSCLK, Fsys16MHZ, and USBCKEN bits in the UCC register. In addition, the system clock can be selected as the HXT via these control bits. The CLK_ADJ bit is used to adjust the PLL clock automatically. SYSC Register Bit 7 6 5 4 3 2 1 0 Name CLK_ADJ USBdis RUBUS — — HFV — — R/W R/W R/W R/W — — R/W — — POR 0 0 0 — — 0 — — Bit 7CLK_ADJ: PLL Clock Automatic Adjustment function 0: Disable 1: Enable Note that if the user selects the HIRC as the system clock, the CLK_ADJ bit must be set to 1 to adjust the PLL frequency automatically. Bit 6USBdis: USB SUE control bit USB related control bit, described elsewhere. Bit 5RUBUS: UBUS pin pull low resistor USB related control bit, described elsewhere. Bit 4~3 Unimplemented, read as “0” Bit 2HFV: Non-USB mdoe high frequency voltage control 0: For USB mode – bit must be cleared to zero 1: For non-USB mode – bit must be set high to eusure that the higher freqyency can work at lower voltages. A high frequency means that the frequency is greater than 8MHz and is used as the system clock, fH. Bit 1~0 Rev. 1.10 Unimplemented, read as “0” 40 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver UCC Register Bit 7 Name Rctrl 6 5 4 R/W R/W R/W R/W POR 0 0 0 3 2 1 0 USBCKEN — EPS1 EPS0 R/W R/W — R/W R/W 0 0 — 0 0 SYSCLK Fsys16MHZ SUSP2 Bit 7Rctrl: 7.5kΩ resistor between UDP and UBUS control bit USB related control bit, described elsewhere. Bit 6SYSCLK: System clock frequency select bit 0: 12MHz 1: 6MHz Note: 1. If a 6MHz crystal or resonator is used for the MCU, this bit should be set to 1. 2. If a 12MHz crystal or resonator is used, then this bit should be set to 0. 3. If the 12MHz HIRC oscillator is selected, then this bit must be set to 0. Bit 5Fsys16MHZ: PLL 16MHz output control bit 0: From HXT 1: From PLL output – 16MHz frequency output Bit 4SUSP2: Reduce power consumption in suspend mode controlbit USB related control bit, described elsewhere. Bit 3USBCKEN: USB clock control bit 0: Disable 1: Enable Bit 2 Unimplemented, read as “0” Bit 1~0EPS1~EPS0: Accessing endpoint FIFO selection USB related control bit, described elsewhere. USC Register Bit 7 6 5 4 3 Name URD SELPS2 PLL R/W R/W R/W R/W R/W R POR 1 0 0 0 0 SELUSB RESUME 2 1 0 URST RMWK SUSP R/W R/W R 0 0 0 Bit 7URD: USB reset signal control function definition USB related control bit, described elsewhere. Bit 6SELPS2: PS2 mode selection bit USB related control bit, described elsewhere. Bit 5PLL: PLL control bit 0: Turn-on PLL 1: Turn-off PLL Bit 4SELUSB: USB mode selection bit USB related control bit, described elsewhere. Bit 3RESUME: USB resume indication bit USB related control bit, described elsewhere. Bit 2URST: USB reset indication bit USB related control bit, described elsewhere. Bit 1RMWK: USB remote wake-up control USB related control bit, described elsewhere. Bit 0SUSP: USB suspend indication USB related control bit, described elsewhere. Rev. 1.10 41 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver The following tableillustrates the PLL output frequency selected by the related control bits. PLL USBCKEN Fsys16MHZ 0 0 0 fH 0 0 1 fPLL – 16MHz fPLL – 6MHz or 12MHz, depending upon the “SYSCLK” bit in the UCC register HOSC (HXT or HIRC) 0 1 0 0 1 1 fPLL – 16MHz 1 x x HOSC (HXT or HIRC) “x” stands for “don’t care” High Frequency System Clock fH Selection Table Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3.3V or 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 3% (Non-USB mode). Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PA1 and PA2 are free for use as normal I/O pins. The HIRC has its own power supply pin, HVDD. The HVDD pin must be connected to VDD and an 0.1mF capacitor to ground. Internal Low Speed 32kHz RC Oscillator – LIRC The Internal 32kHz System Oscillator is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Supplementary Internal Clocks The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source, namely fSUB, to the Watchdog Timer Circuit. Rev. 1.10 42 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either a HXT or HIRC oscillator, selected via a configuration option. The low speed system clock source can be provided by internal clock fL, sourced by the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. The fSUB clock is used as the clock source for the Watchdog timer. HXT fH USBCKEN Config. Option Sele�ts 6 o� 1�MHz XTAL To USBCK �i��uits HOSC 16MHz HOSC PLL HIRC P�es�ale� PLL 6MHz Configu�ation Option fH PLL �lo�k 1�MHz SYSCLK FSYS16MHZ fH/� fH/� fH/8 fH/16 fH/3� fH/6� fSYS fL LIRC SYSCLK PLL fL fSUB HLCLK� CKS�~CKS0 WDT Fast Wake-up f�o� SLEEP o� IDLE �ode Cont�ol (fo� HXT only) System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillatoion will stop to conserve the power. Therefore there is no fH~fH/64 clock for peripheral circuit to use. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Rev. 1.10 43 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Operating Mode Description CPU fSYS fSUB NORMAL Mode on fH~fH/64 on SLOW Mode on fL on IDLE0 Mode off off on IDLE1 Mode off on on SLEEP0 Mode off off off SLEEP1 Mode off off on NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source is provided by the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fSUB, will be on. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fSUB, will be on. SLEEP0 Mode The SLEEP0 Mode is enteredwhen an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fL clock will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to “0”. If the LVDEN is set to “1”, it won’t enter the SLEEP0 Mode. SLEEP1 Mode The SLEEP1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However, the fSUB clock will continue to operate if the LVDEN is “1” or the Watchdog Timer function is enabled. Rev. 1.10 44 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Control Register A single register, SMOD is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0” 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fL clock source is initially used after the device wakes up. When the bit is high, the fL clock source can be used as a temporary system clock to provide a faster wake up time as the fL clock is available. Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1~2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 1024 clock cycles if the HIRC oscillator is used. Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Rev. 1.10 45 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit 0HLCLK: system clock selection 0: fH/2~fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system clock. When the bit is high the f H clock will be selected and if low the fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely the LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wakeup function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the LIRC oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 1024 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. Note that if the Watchdog Timer is disabled, which means that the LIRC is off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. System Oscillator FSTEN Bit Wake-up Time (SLEEP0 Mode) Wake-up Time (SLEEP1 Mode) 0 1024 HXT cycles 1024 HXT cycles 1 1024 HXT cycles 1~2 f SUB cycles (System runs with f SUB first for 1024 HXT cycles and 1~2 HXT cycles then switches over to wun with the HXT clock) HIRC x 1024 HIRC cycles 1024 HIRC cycles 1~2 HIRC cycles LIRC x 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cycles HXT Wake-up Time (SLEEP0 Mode) Wake-up Time (IDLE1 Mode) 1~2 HXT cycles Wake-up Times Rev. 1.10 46 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes. Rev. 1.10 47 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.10 48 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110”or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and WDT clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.10 49 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0”and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and fSUB clock will be on and the application program will stop at the”HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.10 50 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator is enabled. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external or USB reset • An external rising or falling edge on PA and a falling edge on PB~PE, except for PE1 • A system interrupt • A WDT overflow If the system is woken up by an external or USB reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Ports can be setup using the PAWU and PXWU registers to permit a negative transition on the pin to wake-up the system. When a Port pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.10 51 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Programming Considerations • If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is “1”. • If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC oscillator after wake up. • There are peripheral functions, such as WDT, TMs and SIM, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. • The on/off condition of fSUB depends upon whether the WDT is enabled or disabled as the WDT clock source is generated from fSUB. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fSUB, which is sourced from the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The WDT function is allowed to enable or disable by setting the WDTC register data. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. The WRF software reset flag will be indicated in the CTRL register. Rev. 1.10 52 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function enable control 10101: Disabled 01010: Enabled Other values: Reset MCU If these bits are changed to any other values due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three buts determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. CTRL Register Bit 7 6 5 4 3 2 Name FSYSON — — R/W R/W — — POR 0 — — — 1 0 — — — — LVRF LRF WRF R/W R/W — R/W x 0 0 “x”: unknown Bit 7FSYSON: fSYS control in IDLE Mode Described elsewhere. Bit 6~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR control register software reset flag Described elsewhere. Bit 0WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Rev. 1.10 53 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. WE4 ~ WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the Watchdog Timer contents. The first is a WDT reset, which means a value other than 01010B or 10101B is written into the WE4~WE0 bit locations, the second is to use the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer and that is to use the single “CLR WDT” instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC WE�~WE0 �its Registe� Reset MCU CLR “HALT”Inst�u�tion “CLR WDT”Inst�u�tion LIRC fLIRC 8-stage Divide� fLIRC/�8 WS�~WS0 (fLIRC/�8 ~ fLIRC/�18) WDT P�es�ale� 8-to-1 MUX WDT Ti�e-out (�8/fLIRC ~ �18/fLIRC) Watchdog timer Rev. 1.10 54 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. A hardware reset will of course be automatically implemented after the device is powered-on, however there are a number of other hardware and software reset sources that can be implemented dynamically when the device is running. Reset Overview The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program instructions commence execution. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. The devices provide several reset sources to generate the internal reset signal, providing extended MCU protection. The different types of resets are listed in the accompanying table. Reset Name Abbreviation Indication Bit Register Notes — Auto generated at power on Power-on Reset POR — Reset Pin RES — — Low Voltage reset LVR LVRF CTRL Watchdog reset Hardware reset Low VDD voltage WDT TO STATUS WDTC register setting software reset Watchdog Timer overflows — WRF CTRL Write to WDTC register LVRC register setting software reset — LRF CTRL Write to LVRC register Reset Souce Summary In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Rev. 1.10 55 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Note: tRSTD is power-on delay, typical time= 50ms Power-on Reset Timing Chart RES Pin Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. Note: "*" It is recommended that this component is added for added ESD protection "**" It is recommended that this component is added in environments where power line noise is significant. External RES Circuit Rev. 1.10 56 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. Note: tRSTD is power-on delay, typical time= 16.7ms RES Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an MCU reset should the value fall below a certain predefined level. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery in battery powered applications, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some different values by environmental noise, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Note: tRSTD is power-on delay, typical time= 16.7ms Low Voltage Reset Timing Chart Rev. 1.10 57 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage value above, an MCU reset will generated. The reset operation will be activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined register values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 “x”: unknown Bit 7FSYSON: fSYS control in IDLE Mode Described elsewhere. Bit 6~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program. The “x” means unknown. Bit 1LRF: LVR control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the LVRC control register contains any undefined LVR voltage register values. This in effect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program. Bit 0WRF: WDT control register software reset flag Described elsewhere. Rev. 1.10 58 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to “1”. Note: tRSTD is power-on delay, typical time= 16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC. The tSST is 1024 clock for HXT. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF Reset Function 0 0 Power-on reset u u RES, LVR or USB reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.10 Reset Function Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack pointer Stack pointer will point to the top of the stack 59 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Reset Register (Power On) WDT Timeout/WDTC Software Reset (Normal Operation) RES Reset/LVRC Software Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u ---- ---0 ---- ---0 SMOD 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 INTEG 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 LVDC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 INTC1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 uu-u uu-u 00-0 00-0 00-0 00-0 INTC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PB -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 PBC -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 PE ---- -101 ---- -101 ---- -101 ---- -101 ---- -uuu ---- -101 ---- -101 PEC - - - - - 111 - - - - - 111 - - - - - 111 - - - - - 111 ---- -uuu - - - - - 111 - - - - - 111 WDTC 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 FRCR ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0 FCR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FARH ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx FD0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx I2CTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMC0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx Rev. 1.10 60 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Reset Register (Power On) WDT Timeout/WDTC Software Reset (Normal Operation) RES Reset/LVRC Software Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) SIMA/ SIMC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu- --u- 111 - - - 0 - 111 - - - 0 - SPIAC1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 SPIAD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SBSC 0000 ---0 0000 ---0 0000 ---0 0000 ---0 uuuu ---u 0000 ---0 0000 ---0 PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PADIR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PXPU -0-- --00 -0-- --00 -0-- --00 -0-- --00 -u-- --uu -0-- --00 -0-- --00 PXWU -0-- --00 -0-- --00 -0-- --00 -0-- --00 -u-- --uu -0-- --00 -0-- --00 TMPC0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TMPC1 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TM0C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- TM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0RP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 USB_ STAT 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- UINT ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 USC 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 USR ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 UCC 0000 0-00 uuuu u-uu 0000 0-00 0000 0-00 uuuu u-uu 0uu0 u-00 0uu0 u-00 AWR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Rev. 1.10 61 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Reset Register (Power On) WDT Timeout/WDTC Software Reset (Normal Operation) RES Reset/LVRC Software Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) STLI ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 STLO ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 SIES 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 MISC 000- 0000 xxu- uuuu 000- 0000 000- 0000 xxu- uuuu 000- 0000 000- 0000 UFIEN ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 FIFO0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx UFOEN ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 UFC0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- PAPS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SYSC 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- CTRL 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 LVRC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 Note: "*" stands for "warm reset" "-" not implement "u" stands for "unchanged "x" stands for "unknown Rev. 1.10 62 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA, PB and PE. However, only the I/O lines on Port A are bonded to the external pins. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PADIR PADIR7 PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIR0 PB — PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC — PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PE — — — — — PE2 PE1 PE0 PEC — — — — — PEC2 PEC1 PEC0 PXWU — PELWU — — — — PBHWU PBLWU PXPU — PELPU — — — — PBHPU PBLPU PAPS0 PA3S1 PA3S0 PA2S1 PA2S0 PA1S1 PA1S0 PA0S1 PA0S0 PAPS1 PA7S1 PA7S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 I/O Registers List “—”: Unimplemented, read as “0” PAn/PBn/PEn: I/O Port Data bit 0: Data 0 1: Data 1 Rev. 1.10 63 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers, namely PAPU and PXPU, and are implemented using weak PMOS transistors. Note that the PA pull-high resistors are controlled by bits in the PAPU register, other than the PB and PE pull-high resistors are controlled by nibble in the PXPU register. PAPU Register Bit 7 6 5 4 3 2 1 0 Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAPU7~PAPU0: I/O pin PA7 ~ PA0 pull-high control 0: Disable 1: Enable PXPU Register Bit 7 6 5 4 3 2 1 0 Name — PELPU — — — — PBHPU PBLPU R/W — R/W — — — — R/W R/W POR — 0 — — — — 0 0 Bit 7 Unimplemented, read as “0” Bit 6PELPU: I/O pin PE2 ~ PE0 pull-high control 0: Disable 1: Enable Bit 5~2 Unimplemented, read as “0” Bit 1PBHPU: I/O pin PB7 ~ PB4 pull-high control 0: Disable 1: Enable Bit 0PBLPU: I/O pin PB3 ~ PB0 pull-high control 0: Disable 1: Enable Rev. 1.10 64 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Port Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the I/O pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on I/O Port can be selected by bits or nibble to have this wake-up feature using the PAWU and PXWU registers. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAWU7~PAWU0: I/O pin PA7 ~ PA0 wake-up control 0: Disable 1: Enable PXWU Register Bit 7 6 5 4 3 2 1 0 Name — PELWU — — — — PBHWU PBLWU R/W — R/W — — — — R/W R/W POR — 0 — — — — 0 0 Bit 7 Unimplemented, read as “0” Bit 6PELWU: I/O pin PE2 ~ PE0 wake-up control 0: Disable 1: Enable Bit 5~2 Unimplemented, read as “0” Bit 1PBHWU: I/O pin PB7 ~ PB4 wake-up control 0: Disable 1: Enable Bit 0PBLWU: I/O pin PB3 ~ PB0 wake-up control 0: Disable 1: Enable Port A Wake-up Palarity Control Register The I/O port, PA, can be setup to have a choice of wake-up polarity using specific register. Each pin on Port A can be selected individually to have this Wake-up polarity feature using the PADIR register. PADIR Register Bit 7 6 5 4 3 2 1 0 Name PADIR7 PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PADIR7~PADIR0: I/O pin PA7 ~ PA0 wake-up edge select 0: Rising edge 1: Falling edge Rev. 1.10 65 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I/O Port Control Registers Each I/O port has its own control register known as PAC, PBC and PEC, to control the input/ output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PAC7~PAC0: I/O pin PA7 ~ PA0 input/output control 0: Output 1: Input PBC Register Bit 7 6 5 4 3 2 1 0 Name — PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 1 1 1 1 1 1 1 Bit 7 Unimplemented, read as “0” Bit 6~0PBC6~PBC0: I/O pin PB6 ~ PB0 input/output control 0: Output 1: Input PEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — PEC2 PEC1 PEC0 R/W — — — — — R/W R/W R/W POR — — — — — 1 1 1 Bit 7~3 Unimplemented, read as “0” Bit 2~0PEC2~PEC0: I/O pin PE2 ~ PE0 input/output control 0: Output 1: Input Rev. 1.10 66 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Port A Power Source Control Register Port A can be setup to have a choice of two different power source using specific registers. Each pin on Port A can be selected individually to have various power sources using the PAPS0 and PAPS1 registers. PAPS0 Register Bit 7 6 5 4 3 2 1 0 Name PA3S1 PA3S0 PA2S1 PA2S0 PA1S1 PA1S0 PA0S1 PA0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PA3S1~PA3S0: PA3 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Bit 5~4PA2S1~PA2S0: PA2 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Bit 3~2PA1S1~PA1S0: PA1 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Bit 1~0PA0S1~PA0S0: PA0 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Rev. 1.10 67 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver PAPS1 Register Bit 7 6 5 4 3 2 1 0 Name PA7S1 PA7S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PA7S1~PA7S0: PA7 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Bit 5~4PA6S1~PA6S0: PA6 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Bit 3~2PA5S1~PA5S0: PA5 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Bit 1~0PA4S1~PA4S0: PA4 power supply control 00: From VDD pin 01: From VDD pin 10: From VDDIO pin 11: From V33O, 3.3V regulator output These bits should be set to “10” or “11” for the RF Transceiver applications. Rev. 1.10 68 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. All Ports provide the wake-up function which can be set by individual pin in the Port A while it has to be set by nibble pins in the Port B and Port E. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a voltage level transition on any of the Port pins. Single or multiple pins on Ports can be setup to have this function. Rev. 1.10 69 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Standard TM sections. Introduction The device contains four TMs having a reference name of TM0, TM1, TM2 and TM3. Each individual TM can be categorised as a certain type, namely Compact Type TM or Standard Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Standard TMs will be described in this section. The detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. CTM STM Timer/Counter TM Function √ √ Input Capture — √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output — 1 Edge Edge Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary The device contains a specific number of either Compact Type or Standard Type TM units which are shown in the table together with their individual reference name, TM0~TM3. TM0 TM1 TM2 TM3 16-bit STM 10-bit STM 10-bit CTM 10-bit CTM TM Name/Type Reference TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.10 70 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fL clock source or the external TCKn pin. Note that setting these bits to the value 101 will select an undefined clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have two output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type in this device is different, the details are provided in the accompanying table. All TM output pin names have a “_n” suffix. Pin names that include a “_0” or “_1” suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. CTM STM Registers TCK2, TP2_0, TP2_1; TCK3, TP3_0, TP3_1 TCK0, TP0_0, TP0_1; TCK1, TP1_0, TP1_1 TMPC0, TMPC1 TM External Pins Rev. 1.10 71 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function is implemented using two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Bit Register Name 7 6 5 4 3 2 1 0 TMPC0 — — T1CP1 T1CP0 — — T0CP1 T0CP0 TMPC1 — — T3CP1 T3CP0 — — T2CP1 T2CP0 TM Input/Output Pin Control Registers List TM0 Function Pin Control Block Diagram Rev. 1.10 72 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown in the diagram are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than ome TM input. 3. The PB4/TP0_1 and PB3/TP1_1 pins are not bonded to the external pins. TM2 Function Pin Control Block Diagram Rev. 1.10 73 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM3 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown in the diagram are used for TM output inversion control. 2. The PB6/TP2_0, PB5/TP3_0 amd PB2/TCK3 pins are not bonded to the external pins. TMPC0 Register Bit 7 6 5 4 3 2 1 0 Name — — T1CP1 T1CP0 — — T0CP1 T0CP0 R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T1CP1: TP1_1 pin control 0: Disable 1: Enable Bit 4T1CP0: TP1_0 pin control 0: Disable 1: Enable Bit 3~2 Unimplemented, read as “0” Bit 1T0CP1: TP0_1 pin control 0: Disable 1: Enable Bit 0T0CP0: TP0_0 pin control 0: Disable 1: Enable Rev. 1.10 74 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TMPC1 Register Bit 7 6 5 4 3 2 1 0 Name — — T3CP1 T3CP0 — — T2CP1 T2CP0 R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T3CP1: TP3_1 pin control 0: Disable 1: Enable Bit 4T3CP0: TP3_0 pin control 0: Disable 1: Enable Bit 3~2 Unimplemented, read as “0” Bit 1T2CP1: TP2_1 pin control 0: Disable 1: Enable Bit 0T2CP0: TP2_0 pin control 0: Disable 1: Enable Programming Considerations The TM Counter Registers and the Capture/Compare CCRA register, being either 10-bit or 16- bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA register implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA low byte register, named TMxAL, using the following access procedures. Accessing the CCRA low byte register without following these access procedures will result in unpredictable values. The following steps show the read and write procedures: • Writing Data to CCRA Rev. 1.10 ♦♦ Step 1. Write data to Low Byte TMxAL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. 75 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Reading Data from the Counter Registers and CCRA ♦♦ Step 1. Read data from the High Byte TMxDH or TMxAH ––here data is read directly from the high byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL or TMxAL ––this step reads data from the 8-bit buffer. Compact Type TM – CTM Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. TM Name TM No. TM Input Pin TM Output Pin 10-bit CTM 2 TCK2 TP2_0, TP2_1 10-bit CTM 3 TCK3 TP3_0, TP3_1 Compact Type TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Block Diagram – n = 2 or 3 Rev. 1.10 76 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 10-bit Compact TM Registers List (n = 2 or 3) TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 TMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0 TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register Rev. 1.10 Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 77 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TMnC0 Register Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TnPAU: TMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fL 101: Undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TMn. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fL are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the TMn. Setting the bit high enables the counter to run while clearing the bit disables the TMn. Clearing this bit to zero will stop the counter from counting and turn off the TMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TMn is in the Compare Match Output Mode then the TMn output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks Rev. 1.10 78 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TMn. To ensure reliable operation the TMn should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TMn output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TMn TPn_0, TPn_1 output function Comparator Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: Force inactive state 01: Force output active state 10: PWM Output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the TMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TMn is running. Rev. 1.10 79 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A. The TMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TMn output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TMn output pin when a compare match occurs. After the TMn output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TMn is running. Bit 3TnOC: TMn TPn_0, TPn_1 output control bit Comparator Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high Timer/Counter Mode Unused This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TMn TPn_0, TPn_1 output polarity control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty control 0: CCRP – Period; CCRA – Duty 1: CCRP – Duty; CCRA – Period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparator P match 1: TMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TMn contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM mode. Rev. 1.10 80 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Compact Type TM Operation Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to “00” respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.10 81 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� ove�flow Counte� Value CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 0x3FF CCRP > 0 TnCCLR = 0; TnM [1:0] = 00 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affe�ted �y TnAF flag. Re�ains High until �eset �y TnON �it Output Toggle with TnAF flag He�e TnIO [1:0] = 11 Toggle Output sele�t Note TnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when TnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compara Match Output Mode – TnCCLR = 0 (n = 2 or 3) Note: 1. With TnCCLR= 0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.10 82 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF Resu�e CCRA Pause CCRA=0 Stop Counte� Resta�t CCRP Ti�e TnON TnPAU TnPOL No TnAF flag gene�ated on CCRA ove�flow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not gene�ated Output does not �hange TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag He�e TnIO [1:0] = 11 Toggle Output sele�t Output not affe�ted �y TnAF flag. Re�ains High until �eset �y TnON �it Note TnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when TnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compara Match Output Mode – TnCCLR = 1 (n = 2 or 3) Note: 1. With TnCCLR= 1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.10 83 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128, The CTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 128 256 384 512 Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.10 84 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnDPX = 0; TnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when TnON �etu�ns high CCRP Pause Resu�e Counte� Stop if TnON �it low CCRA Ti�e TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when TnPOL = 1 PWM Output Mode – TnDXP = 0 (n = 2 or 3) Note: 1. Here TnDPX= 0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.10 85 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnDPX = 1; TnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when TnON �etu�ns high CCRA Pause Resu�e Counte� Stop if TnON �it low CCRP Ti�e TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when TnPOL = 1 PWM Output Mode – TnDXP = 1 (n = 2 or 3) Note: 1. Here TnDPX= 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.10 86 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. TM Name TM No. TM Input Pin TM Output Pin 16-bit STM 0 TCK0 TP0_0, TP0_1 10-bit STM 1 TCK1 TP1_0, TP1_1 Standard Type TM Operation There are two sizes of Standard TMs, one is 10-bit wide and the other is 16-bit wide. At the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits. The only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Standard Type TM Block Diagram (n = 0 for 16-bit STM; n = 1 for 10-bit STM) Rev. 1.10 87 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM0C0 T0PAU T0CK2 T0CK1 T0CK0 T0ON — — — TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0PX T0CLR TM0DL D7 D6 D5 D4 D3 D2 D1 D0 TM0DH D15 D14 D13 D12 D11 D10 D9 D8 TM0AL D7 D6 D5 D4 D3 D2 D1 D0 TM0AH D15 D14 D13 D12 D11 D10 D9 D8 TM0RP T0RP7 T0RP6 T0RP5 T0RP4 T0RP3 T0RP2 T0RP1 T0RP0 16-bit Standard TM Registers List Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH — — — — — — D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH — — — — — — D9 D8 10-bit Standard TM Registers List TM0DL/TM1DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0/TM1 Counter Low Byte Register bit 7 ~ bit 0 TM0/TM1 10 or 16-bit Counter bit 7 ~ bit 0 TM0DH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0 Counter High Byte Register bit 7 ~ bit 0 TM0 16-bit Counter bit 15 ~ bit 8 TM1DH Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 TM1 Counter High Byte Register bit 1 ~ bit 0 TM1 10-bit Counter bit 9 ~ bit 8 88 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM0AL/TM1AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0/TM1 CCRA Low Byte Register bit 7 ~ bit 0 TM0/TM1 10- or 16-bit CCRA bit 7 ~ bit 0 TM0AH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0 CCRA High Byte Register bit 7 ~ bit 0 TM0 16-bit CCRA bit 15 ~ bit 8 TM1AH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 TM1 CCRA High Byte Register bit 1 ~ bit 0 TM1 10-bit Counter bit 9 ~ bit 8 TM0RP Register Bit 7 6 5 4 3 2 1 0 Name T0RP7 T0RP6 T0RP5 T0RP4 T0RP3 T0RP2 T0RP1 T0RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0T0RP7~T0RP0: TM0 CCRP 8-bit register bit 7 ~ bit 0, compared with the TM0 counter bit 15~bit 8 Comparator P match period = 0: 65536 TM0 clocks 1~255: (1~255) × 256 TM0 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 1.10 89 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM0C0 Register Bit 7 6 5 4 3 2 1 0 Name T0PAU T0CK2 T0CK1 T0CK0 T0ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7T0PAU: TM0 Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4T0CK2~T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fL 101: Undefined 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fL are other internal clocks, the details of which can be found in the oscillator section. Bit 3T0ON: TM0 Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run while clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TMn output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high. Bit 2~0 Rev. 1.10 Unimplemented, read as “0” 90 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TM1C0 Register Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T1PAU: TM1 Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fL 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fL are other internal clocks, the details of which can be found in the oscillator section. Bit 3T1ON: TM1 Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run while clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 1.10 91 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TMnC1 Register – n = 0 or 1 Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TMn. To ensure reliable operation the TMn should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TMn output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TMn TPn_0, TPn_1 output function Comparator Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode / Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM Output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of TPn_0, TPn_1 01: Input capture at falling edge of TPn_0, TPn_1 10: Input capture at rising/falling edge of TPn_0, TPn_1 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the TMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TMn is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A. The TMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TMn output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TMn output pin when a compare match occurs. After the TMn output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TMn is running. Rev. 1.10 92 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit 3TnOC: TMn TPn_0, TPn_1 output control bit Comparator Match Output Mode 0: Initial low 1: Initial high PWM Mode / Single Pulse Output Mode 0: Active low 1: Active high Timer/Counter Mode Unused This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode or Single Pulse Output Mode it determines if the PWM or Single Pulse signal is active high or active low. Bit 2TnPOL: TMn TPn_0, TPn_1 output polarity control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty control 0: CCRP – Period; CCRA – Duty 1: CCRP – Duty; CCRA – Period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparator P match 1: TMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TMn contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM mode. Rev. 1.10 93 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.10 94 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� ove�flow Counte� Value CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 0xFFFF O� 0x3FF CCRP > 0 TnCCLR = 0; TnM [1:0] = 00 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affe�ted �y TnAF flag. Re�ains High until �eset �y TnON �it Output Toggle with TnAF flag He�e TnIO [1:0] = 11 Toggle Output sele�t Note TnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when TnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compara Match Output Mode – TnCCLR = 0 (n = 0 or 1) Note: 1. With TnCCLR= 0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. n = 0 for 16-bit STM; n = 1 for 10-bit STM Rev. 1.10 95 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0xFFFF o� 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e TnON TnPAU TnPOL No TnAF flag gene�ated on CCRA ove�flow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not gene�ated Output does not �hange TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affe�ted �y TnAF flag. Re�ains High until �eset �y TnON �it Output Toggle with TnAF flag He�e TnIO [1:0] = 11 Toggle Output sele�t Note TnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when TnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compara Match Output Mode – TnCCLR = 1 (n = 0 or 1) Note: 1. With TnCCLR= 1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 5. n = 0 for 16-bit STM; n = 1 for 10-bit STM Rev. 1.10 96 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. Rev. 1.10 97 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=0 CCRP 1~255 0 Period CCRP×256 65536 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA = 128, The STM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1 CCRP 1~255 Period 0 CCRA CCRP×256 Duty 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. • 10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128, The STM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.10 98 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnDPX = 0; TnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when TnON �etu�ns high CCRP Pause Resu�e Counte� Stop if TnON �it low CCRA Ti�e TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y othe� Output Inve�ts pin-sha�ed fun�tion when TnPOL = 1 PWM Output Mode – TnDXP = 0 (n = 0 or 1) Note: 1. Here TnDPX= 0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation 5. n = 0 for 16-bit STM; n = 1 for 10-bit STM Rev. 1.10 99 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnDPX = 1; TnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when TnON �etu�ns high CCRA Pause Resu�e Counte� Stop if TnON �it low CCRP Ti�e TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when TnPOL = 1 PWM Output Mode – TnDXP = 1 (n = 0 or 1) Note: 1. Here TnDPX= 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation 5. n = 0 for 16-bit STM; n = 1 for 10-bit STM Rev. 1.10 100 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Single Pulse Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. S/W Command SET“TnON” or TCKn Pin Transition CCRA Leading Edge CCRA Trailing Edge TnON bit 0→1 TnON bit 1→0 S/W Command CLR“TnON” or CCRA Compare Match TPn_x Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.10 101 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnM [1:0] = 10 ; TnIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when TnON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Ti�e TnON Softwa�e T�igge� Auto. set �y TCKn pin Clea�ed �y CCRA �at�h TCKn pin Softwa�e T�igge� Softwa�e Clea� Softwa�e T�igge� Softwa�e T�igge� TCKn pin T�igge� TnPAU TnPOL No CCRP Inte��upts gene�ated CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Output Inve�ts when TnPOL = 1 Pulse Width set �y CCRA Single Pulse Output Mode – n = 0 or 1 Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit hight 5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed. Rev. 1.10 102 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Rev. 1.10 103 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Counte� Value TnM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Stop Counte� Reset CCRP Resu�e YY Pause XX Ti�e TnON TnPAU A�tive edge A�tive edge TM �aptu�e pin TPn_x A�tive edge CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value XX 00 – Rising edge YY XX 01 – Falling edge 10 – Both edges YY 11 – Disa�le Captu�e Capture Input Mode – n = 0 or 1 Note: 1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function – TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.10 104 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected by software control. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. The pull-high resistors of the SIM pins can be selected using pull-high control registers and also if the SIM function is enabled. There is one control register associated with the serial interface control, namely SBSC. This is used to enable the SIM_WCOL bit function, SA_WCOL bit function and I2C debounce selection. The device provides two kinds of SPI function, namely SPI and SPIA, each of them has the corresponding WCOL control bits to enable the SIM WCOL and SPIA WCOL control bits, namely SIM_WCOL and SA_WCOL respectively. In addition, the I2CDB1 and I2CDB0 bits are used to select the I2C debounce time. SPI Interface This SPI interface function, which is part of the Serial Interface Module, should not be confused with the other independent SPI function, known as SPIA, which is described in another section of this datasheet. The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pinshared with other functions and with the I2C function pins, the SPI interface must first be selected by the correct bits in the SIMC0 and SIMC2 registers. After the SPI option has been selected, it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register. SPI Master/Slave Connection Rev. 1.10 105 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPI Block Diagram The SPI function in these devices offer the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge • WCOL bit enabled or disable select The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. SPI Registers There are four internal registers which control the overall operation of the SPI interface. These are the SIMD data register and three registers SIMC0, SIMC2 and SBSC. The SIM_WCOL bit in the SBSC register is used to control the SPI WCOL function. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL 0 SPI Registers List Rev. 1.10 106 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown There are also three control registers for the SPI interface, SIMC0 SIMC2 and SBSC. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/ disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fL 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from fL or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2PCKP1~PCKP0: Select PCK output pin freqyency 00: fSYS 01: fSYS /4 10: fSYS /8 11: TM0 CCRP match frequency/2 Rev. 1.10 107 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Unimplemented, read as “0” SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Rev. 1.10 108 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit 2CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. SBSC Register Bit 7 6 5 4 3 2 1 0 Name SIM_WCOL — I2CDB1B I2CDB0 — — — SA_WCOL R/W R/W — R/W R/W — — — R/W POR 0 — 0 0 — — — 0 Bit 7SIM_WCOL: SIM WCOL bit function control 0: Disable 1: Enable Bit 6 Unimplemented, read as “0” Bit 5~4I2CDB1~I2CDB0: I2C debounce selection bits Related to I2C function, described elsewhere Bit 3~1 Unimplemented, read as “0” Bit 0SA_WCOL: SPIA WCOL bit function control Related to SPIA function, described elsewhere SPI Bus Enable/Disable To enable the SPI bus, set CSEN= 1 and SCS = 0, then wait for data to be written into the SIMD (TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in.To disable the SPI bus, the SCK, SDI, SDO and SCS will become I/O pins or the other functions. Rev. 1.10 109 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 1.10 110 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.10 111 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver All communication is carried out using the 4-line interface for either Master or Slave Mode.The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be an I/O pin or the other functions and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode: Master Mode • Step 1 Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave device. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Rev. 1.10 112 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Slave Mode • Step 1 Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master device. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. SPI Error Detection The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is set by the SPI serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SIMD register takes place during a data transfer operation and will prevent the write operation from continuing. The overall function of the WCOL bit can be disabled or enabled by the SIM_WCOL bit in the SBSC register. I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection Rev. 1.10 113 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I2C interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data. However, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. The debounce time of the I2C interface can be determined by the I2CDB1 and I2CDB0 bits in the SBSC register. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. I2C Block Diagram S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r Rev. 1.10 114 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SBSC, one address register SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. The I2CDB0 and I2CDB1 in the SBSC register are used to select the I2C debounce time. Bit Register Name 7 SIMC0 SIMC1 6 5 4 3 2 1 0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — HCF HAAS HBB HTX TXAK SRW IAMWU RXAK D0 SIMD D7 D6 D5 D4 D3 D2 D1 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL I2C Registers List SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown Rev. 1.10 115 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fL 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from fL or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2PCKP1~PCKP0: Select PCK output pin freqyency 00: fSYS 01: fSYS /4 10: fSYS /8 11: TM0 CCRP match frequency/2 Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Rev. 1.10 Unimplemented, read as “0” 116 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. 2 Bit 6HAAS: I2C Bus address match flag 0: No address match 1: Address matched The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5HBB: I2C Bus busy flag 0: Bus not busy 1: Bus busy The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to “0” when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: Select I2C slave device is transmitter or reveicer 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C Bus transmit acknowledge flag 0: Send an acknowledge flag 1: Not send an acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data,this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to “0” before further data is received. Bit 2SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Wake-up control 0: Disable 1: Enable This bit should be set to “1” to enable I2C address match wake up from SLEEP or IDLE Mode. Rev. 1.10 117 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Bit 0RXAK: I2C Bus receive acknowledge flag 0: Receive an acknowledge flag 1: Not receive an acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown Bit 7~1IICA6~IICA0: I2C Slave Address bit 6 ~ bit 0 The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. SBSC Register Bit 7 6 Name SIM_WCOL — 5 R/W R/W — R/W POR 0 — 0 4 3 2 1 0 — — — SA_WCOL R/W — — — R/W 0 — — — 0 I2CDB1B I2CDB0 Bit 7SIM_WCOL: SIM WCOL bit function control Related to SPI function, described elsewhere Bit 6 Unimplemented, read as “0” Bit 5~4I2CDB1~I2CDB0: I2C debounce selection bits 00: No debounce 01: 1 system clock devounce 1x: 2 system clocks debounce Bit 3~1 Unimplemented, read as “0” Bit 0SA_WCOL: SPIA WCOL bit function control Related to SPIA function, described elsewhere Rev. 1.10 118 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus and the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to “1” to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt. I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Rev. 1.10 119 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I2C Bus Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to “0”. Rev. 1.10 120 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. I2C Communication Timing Diagram Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.10 121 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver I2C Bus ISR Flow Chart I2C Time-out Function The I2C interface provides a time-out scheme to prevent a locked situation which might take place by an unexpected clock timing generated by a noise input signal. When the I2C interface has been locked for a period of time, the I2C hardware and the register, SIMC1, will be initialized automatically and the I2CTOF bit in the I2CTOC register will be set high. The Time Out function enable/disable and the time-out period are managed by the I2CTOC register. I2C Time-out Operation The time-out counter will start counting when the I2C interface received the START bit and address match. After that the counter will be cleared on each falling edge of the SCL pin. If the time counter is larger than the selected time-out time, then the anti-locked protection scheme will take place and the time-out counter will be stopped by hardware automatically, the I2CTOF bit will be set high and an I2C interrupt will also take place. Note that this scheme can also be stopped when the I2C received the STOP bit. There are several time-out periods can be selected by the I2CTOS0~I2CTOS5 bits in the I2CTOC register. Rev. 1.10 122 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • I2CTOC Register Bit 7 6 Name I2CTOEN I2CTOF 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 Bit 7I2CTOEN: I C Time-out function enable control 0: Disable 1: Enable 2 Bit 6I2CTOF: I2C Time-out indication bit 0: Not occur 1: Occurred Bit 5~0I2CTOS5~I2CTOS0: I2C Time-out period selection The I2C time-out clock is provided by the fL/32. The time-out period can be calculated from the accompanying equation. I2C Time-out Period = ([I2CTOS5 : I2CTOS0] + 1) × (32/fL) Peripheral ClockOutput The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to “1” enables the Peripheral Clock and clearing PCKEN bit to “0” disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode, this will disable the Peripheral Clock output. SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fL 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function Rev. 1.10 123 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from fL or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2PCKP1~PCKP0: Select PCK output pin freqyency 00: fSYS 01: fSYS /4 10: fSYS /8 11: TM0 CCRP match frequency/2 Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Rev. 1.10 Unimplemented, read as “0” 124 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Serial Interface – SPIA The device contains an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. This SPIA interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, this device is provided only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with other functions, the SPIA interface pins must first be selected by configuring the corresponding selection bits in the pin-shared function selection registers. The SPIA interface function is disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The master also controls the clock/signal. As the device only contains a single SCSA pin only one slave device can be utilised. The SCSA pin is controlled by the application program, set the the SACSEN bit to “1” to enable the SCSA pin function and clear the SACSEN bit to “0” to place the SCSA pin into an I/O function. SPIA Master/Slave Connection The SPIA Serial Interface function includes the following features: • Full-duplex synchronous data transfer • Both Master and Slave mode • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN. Rev. 1.10 125 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPIA Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPIA interface. These are the SIMD data register and two registers SPIAC0 and SPIAC1. Bit Register Name 7 6 SPIAC0 SASPI2 SASPI1 SPIAC1 — — SPIAD D7 D6 D5 D4 D3 D2 D1 D0 SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL 5 4 3 2 1 SASPI0 — — — SPIAEN 0 — SACKPOL SACKEG SAMLS SACSEN SAWCOL SATRF SPIA Registers List SPIAD Register The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPIA bus must be made via the SPIA register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown There are also three control registers for the SPIA interface, SPIAC0, SPIAC1 and SBSC. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag, etc. Rev. 1.10 126 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPIAC0 Register Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — — SPIAEN — R/W R/W R/W R/W — — — R/W — POR 1 1 1 — — — 0 — Bit 7~5SASPI2~SASPI0: SPIA Master/Slave clock select 000: SPIA master mode with clock fSYS /4 001: SPIA master mode with clock fSYS /16 010: SPIA master mode with clock fSYS /64 011: SPIA master mode with clock fL 100: SPIA master mode with clock TM0 CCRP match frequency/2 101: SPIA slave mode 11x: Reserved These bits are used to control the SPIA Master/Slave selection and the SPIA Master clock frequency. The SPIA clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPIA Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4~2 Unimplemented, read as “0” Bit 1SPIAEN: SPIIA Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA lines will lose the SPI function and the SPIA operating current will be reduced to a minimum value. When the bit is high the SPIA interface is enabled. Bit 0 Rev. 1.10 Unimplemented, read as “0” 127 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPIAC1 Register Bit 7 6 Name — — R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 5 4 SACKPOL SACKEG 3 SAMLS 2 1 SACSEN SAWCOL 0 SATRF Unimplemented, read as “0” Bit 5SACKPOL: SPIA clock line base condition selection 0: The SCKA line will be high when the clock is inactive 1: The SCKA line will be low when the clock is inactive The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. Bit 4SACKEG: SPIA SCKA clock active edge type selection SACKPOL=0 0: SCKA is high base level and data capture at SCKA rising edge 1: SCKA is high base level and data capture at SCKA falling edge SACKPOL=1 0: SCKA is low base level and data capture at SCKA falling edge 1: SCKA is low base level and data capture at SCKA rising edge The SACKEG and SACKPOL bits are used to setup the way that the clock signal outputs and inputs data on the SPIA bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of SACKPOL bit. Bit 3SAMLS: SPIA data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2SACSEN: SPIA SCSA pin control 0: Disable 1: Enable The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin function will be disabled and can be placed into I/O pin or other pin-shared functions. If the bit is high, the SCSA pin will be enabled and used as a select pin. Bit 1SAWCOL: SPIA write collision flag 0: No collision 1: Collision The SAWCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SPIAD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0SATRF: SPIA Transmit/Receive complete flag 0: SPIA data is being transferred 1: SPIA data transfer is completed The SATRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPIA data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. Rev. 1.10 128 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SBSC Register Bit 7 6 5 4 3 2 1 0 Name SIM_WCOL — I2CDB1B I2CDB0 — — — SA_WCOL R/W R/W — R/W R/W — — — R/W POR 0 — 0 0 — — — 0 Bit 7SIM_WCOL: SIM WCOL bit function control Related to SPI function, described elsewhere Bit 6 Unimplemented, read as “0” Bit 5~4I2CDB1~I2CDB0: I2C debounce selection bits Related to I2C function, described elsewhere Bit 3~1 Unimplemented, read as “0” Bit 0SA_WCOL: SPIA WCOL bit function control 0: Disable 1: Enable SPIA Bus Enable/Disable To enable the SPIA bus, set SACSEN= 1 and SCSA=0, then wait for data to be written into the SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in. To disable the SPIA bus SCKA, SDIA, SDOA, SCSA will become I/O pins or the other functions. SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD registers. The master should output a SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCSA signal for various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function if the SPIA clock source is active. Rev. 1.10 129 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPIA Master Mode Timing SPIA Slave Mode Timing – SACKEG= 0 SPIA Slave Mode Timing – SACKEG= 1 Rev. 1.10 130 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPIA Transfer Control Flowchart All communication is carried out using the 4-line interface for either Master or Slave Mode. The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be an I/O pin or the other functions and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master Mode the SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOL in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode: Rev. 1.10 131 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Master Mode • Step 1 Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this must be same as the Slave device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Rev. 1.10 132 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Slave Mode • Step 1 Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this setting must be the same with the Master device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Error Detection The SAWCOL bit in the SPIAC1 register is provided to indicate errors during data transfer. The bit is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SPIAD register takes place during a data transfer operation and will prevent the write operation from continuing. The SAWCOL bit in the SPIAC register is provided to indicate errors during data transfer. The bit is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SPIAD register takes place during a data transfer operation and will prevent the write operation from continuing. The overall function of the SAWCOL bit can be disabled or enabled by the SA_WCOL bit in the SBSC register. Rev. 1.10 133 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, LVD, SIM, SPIA and USB. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/disable bit or “F” for request flag. Function Enable Bit Global Request Flag EMI — INTn Pins INTnE INTnF USB USBE USBF Multi-function MFnE MFnF Notes — n=0~1 — n=0~3 SIM SIME SIMF — SPIA SPIAE SPIAF — — LVD TM LVE LVF TnPE TnPF TnAE TnAF n=0~3 Interrupt Register Bit Naming Conventions Bit Register Name 7 INTEG — — INTC0 — USBF INTC1 MF1F MF0F INTC2 SPIAF MFI0 T1AF MFI1 T3AF T3PF 6 5 4 3 2 1 0 — — INT1S1 INT1S0 INT0S1 INT0S0 INT1F INT0F USBE INT1E INT0E EMI — LVF MF1E MF0E — LVE SIMF MF3F MF2F SPIAE SIME MF3E MF2E T1PF T0AF T0PF T1AE T1PE T0AE T0PE T2AF T2PF T3AE T3PE T2AE T2PE Interrupt Registers List Rev. 1.10 134 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 Name — USBF INT1F INT0F USBE INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6USBF: USB interrupt request flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3USBE: USB interrupt control 0: Disable 1: Enable Bit 2INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable Rev. 1.10 135 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver INTC1 Register Bit 7 6 5 4 3 2 1 0 Name MF1F MF0F — LVF MF1E MF0E — LVE R/W R/W R/W — R/W R/W R/W — R/W POR 0 0 — 0 0 0 — 0 Bit 7MF1F: Multi-function 1 interrupt request flag 0: No request 1: Interrupt request Bit 6MF0F: Multi-function 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 Unimplemented, read as “0” Bit 4LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3MF1E: Multi-function 1 interrupt control 0: Disable 1: Enable Bit 2MF0E: Multi-function 0 interrupt control 0: Disable 1: Enable Bit 1 Unimplemented, read as “0” Bit 0LVE: LVD Interrupt control 0: Disable 1: Enable Rev. 1.10 136 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver INTC2 Register Bit 7 6 5 4 3 2 1 0 Name SPIAF SIMF MF3F MF2F SPIAE SIME MF3E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7SPIAF: SPIA Interrupt request flag 0: No request 1: Interrupt request Bit 6SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 5MF3F: Multi-function 3 interrupt request flag 0: No request 1: Interrupt request Bit 4MF2F: Multi-function 2 interrupt request flag 0: No request 1: Interrupt request Bit 3SPIAE: SPIA Interrupt control 0: Disable 1: Enable Bit 2SIME: SIM Interrupt control 0: Disable 1: Enable Bit 1MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable Bit 0MF2E: Multi-function 2 interrupt control 0: Disable 1: Enable Rev. 1.10 137 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver MFI0 Register Bit 7 6 5 4 3 2 1 0 Name T1AF T1PF T0AF T0PF T1AE T1PE T0AE T0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T1AF: TM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6T1PF: TM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5T0AF: TM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4T0PF: TM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3T1AE: TM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 2T1PE: TM1 Comparator P match Interrupt control 0: Disable 1: Enable Bit 1T0AE: TM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0T0PE: TM0 Comparator P match Interrupt control 0: Disable 1: Enable Rev. 1.10 138 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver MFI1 Register Bit 7 6 5 4 3 2 1 0 Name T3AF T3PF T2AF T2PF T3AE T3PE T2AE T2PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T3AF: TM3 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6T3PF: TM3 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5T2AF: TM2 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4T2PF: TM2 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3T3AE: TM3 Comparator A match Interrupt control 0: Disable 1: Enable Bit 2T3PE: TM3 Comparator P match Interrupt control 0: Disable 1: Enable Bit 1T2AE: TM2 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0T2PE: TM2 Comparator P match Interrupt control 0: Disable 1: Enable Rev. 1.10 139 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Interrupt Operation When the conditions for an interrupt event occur, such as a TM Compare P, Compare A or Compare B match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI” , which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.10 140 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver EMI auto disa�led in ISR Legend xxF Request Flag� no auto �eset in ISR xxF Request Flag� auto �eset in ISR xxE Ena�le Bits Inte��upts �ontained within Multi-Fun�tion Inte��upts TM0 P T0PF T0PE TM0 A T0AF T0AE Inte��upt Na�e Request Flags Ena�le Bits Maste� Ena�le Vector P�io�ity INT0 Pin INT0F INT0E EMI 0�H High INT1 Pin INT1F USBE EMI 08H USB USBF INT1E EMI 0CH M. Fun�t. 0 MF0F MF0E EMI 10H M. Fun�t. 1 MF1F MF1E EMI 1�H M. Fun�t. � MF�F MF�E EMI 18H M. Fun�t. 3 MF3F MF3E EMI 1CH TM1 P T1PF T1PE TM1 A T1AF T1AE TM� P T�PF T�PE TM� A T�AF T�AE SIM SIMF SIME EMI �0H TM3 P T3PF T3PE SPIA SPIAF SPIAE EMI ��H TM3 A T3AF T3AE LVD LVF LVE EMI �8H Low Interrupt Scheme External Interrupt The external interrupts are controlled by signal transitions on the pins INT0 and INT1. An external interrupt request will take place when the external interrupt request flags, INT0F, INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E, INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F, INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Rev. 1.10 141 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver USB Interrupt A USB interrupt request will take place when the USB interrupt request flags, USBF, is set, a situation that will occur when an endpoint is accessed. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB interrupt enable bit, USBE, must first be set. When the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the USB interrupt vector, will take place. When the interrupt is serviced, the USB interrupt request flag, USBF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Serial Interface Module Interrupt – SIM Interrupt The Serial Interface Module interrupt, known as the SIM interrupt, will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the SIMF flag will be automatically cleared as well. Serial Peripheral Interface Interrupt – SPIA Interrupt The Serial Peripheral Interface Interrupt, also known as the SPIA interrupt, will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SPIAE, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPIA interface, a subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced, the Serial Interface Interrupt flag, SPIAF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Low Voltage Detect Interrupt – LVD Interrupt The Low Voltage Detector interrupt, known as the LVD interrupt, will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI and Low Voltage Interrupt enable bit, LVE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the LVF flag will be automatically cleared as well. Rev. 1.10 142 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Multi-function Interrupt Within this device there is various Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF3F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, interrupt will not be automatically reset and must be manually reset by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.10 143 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF3F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.10 144 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5LVDO: LVD output flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4LVDEN: Low Voltage Detector Enable control 0: Disable 1: Enable Bit 3 Unimplemented, read as “0” Bit 2~0VLVD2~VLVD0: LVD Voltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.10 145 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. The Low Voltage Detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however, if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. USB Interface The USB interface is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. A token based protocol method is used by the host device for communication control. Other advantages of the USB bus include live plugging and unplugging and dynamic device configuration. As the complexity of USB data protocol does not permit comprehensive USB operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed USB understanding. The device includes a USB interface function allowing for the convenient design of USB peripheral products. The USB disable/enable control bit “USBdis” is in the SYSC Register. If the USB is disabled, then V33O will be floating, the UDP/UDN lines will become I/O functions, and the USB SIE will be disabled. Power Planning The power sourced from the VDD pin is supplied to the MCU and USB SIE except the HIRC oscillator. For the HIRC oscillator, it is supplied by the HVDD pin. For the PA port, it can be configured using the PAPS1 and PAPS0 registers to define the pins PA0~PA7 are supplied by the MCU VDD, VDDIO or the V33O pin. Rev. 1.10 146 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver USB Suspend Wake-up and Remote Wake-up If there is no signal on the USB bus for over 3ms, the devices will go into a suspend mode. The Suspend flag, SUSP, in the USC register, will then be set high and an USB interrupt will be generated to indicate that the devices should jump to the suspend state to meet the requirements of the USB suspend current spec. In order to meet the requirements of the suspend current the firmware should disable the USB clock by clearing the USBCKEN bit to “0”. The suspend current can be further decreased by setting the SUSP2 bit in the UCC register. When the resume signal is sent out by the host, the device will be woken up the by the USB interrupt and the Resume bit in the USC register will be set. To ensure correct device operation, the program must set the USBCKEN bit in the UCC register high and clear the SUSP2 bit in the UCC register. The Resume signal will be cleared before the idle signal is sent out by the host and the Suspend line in the USC register will change to zero. So when the MCU detects the Suspend bit in the USC register, the condition of the Resume line should be noted and taken into consideration. SUSPEND Resu�e signal USB inte��upt Suspend Wake-up The device has a remote wake up function which can wake-up the USB Host by sending a wake-up pulse through RMWK in the USC register. Once the USB Host receives a wake-up signal from the device it will send a Resume signal to the device. SUSPEND �µs (Min.) RMWK Resu�e signal �.5�s (Min.) USB inte��upt Remote Wake-up USB Interface Operation The device has 4 Endpoints, EP0, EP1, EP2 and EP3. The EP0 supports Control transfer and other endpoints, EP1~EP3, support Interrupt or Bulk transfer. All endpoints except EP0 can be configure as 8, 16, 32, 64 FIFO size by the register UFC0 and UFC1. EP0 has 8-byte FIFO size. The Total FIFO size is 256+8 bytes for the device. As the USB FIFO is assigned from the last bank of the Data RAM and has a start address of nFFH to the upper address, dependent on the FIFO size, if the corresponding data RAM bank is used for both general purpose RAM and the USB FIFO, special care should be taken that the RAM “EQU” definition should not overlap with the USB FIFO RAM address. The URD in the USC register is the USB reset signal control function definition bit. The USB FIFO size definition for IN/OUT control depends on the UFC, UFIEN and UFOEN registers. If OUT 1 not used, then the OUT 1 FIFO will not be defined and IN 2 will be defined as IN 1 afterwards. Rev. 1.10 147 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver n80H Gene�al Pu�pose Data Me�o�y nBFH nC0H OUT 3 (8 �ytes) nC7H nC8H IN 3 (8 �ytes) nCFH nD0H OUT � (8 �ytes) nDFH nE0H IN � (8 �ytes) nEFH nF0H OUT 1 (8 �ytes) nF7H nF8H IN 1 (8 �ytes) nFFH “n”=Bank1~0� Last Bank is fi�st defined. USB FIFO Size Define USB Interface Registers The USB interface contains a series of registers which are used to control the overall USB operation. SYSC Register Bit 7 6 5 4 3 2 Name CLK_ADJ USBdis RUBUS R/W R/W R/W R/W POR 0 0 0 — 1 0 — — HFV — — — — R/W — — — 0 — — Bit 7CLK_ADJ: PLL Clock Automatic Adjustment function PLL related control bit, described elsewhere. Note that if the user selects the HIRC as the system clock, the CLK_ADJ bit must be set to 1 to adjust the PLL frequency automatically. Bit 6USBdis: USB SIE control bit 0: Enable 1: Disable Bit 5RUBUS: UBUS pin pull low resistor 0: Enable 1: Disable Bit 4~3 Unimplemented, read as “0” Bit 2HFV: Non-USB mdoe high frequency voltage control 0: For USB mode – bit must be cleared to zero 1: For non-USB mode – bit must be set high to eusure that the higher freqyency can work at lower voltages. A high frequency means that the frequency is greater than 8MHz and is used as the system clock, fH. Bit 1~0 Rev. 1.10 Unimplemented, read as “0” 148 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver USB_STAT Register Bit Name 7 6 5 4 PS2_CKO PS2_DAO PS2_CKI PS2_DAI 3 2 1 0 SE1 SE0 PU ESD R/W W W R R R/W R/W R/W R/W POR 1 1 0 0 0 0 0 0 Bit 7PS2_CKO: Output for driving UDP/GPIO1 pin, when operating under GPIO mode function. Default value is “1”. Bit 6PS2_DAO: Output for driving UDN/GPIO0 pin, when operating under GPIO mode function. Default value is “1”. Bit 5PS2_CKI: UDP/GPIO1 input Bit 4PS2_DAI: UDN/GPIO0 input Bit 3SE1: SE1 noise indication 0: No SE1 noise detected 1: SE1 noise detected This bit is used to indicate that the SIE has detected a SE1 noise on the USB bus or not. It is set to 1 by SIE hareware and cleared to 0 by application program. Bit 2SE0: SE0 noise indication 0: No SE0 noise detected 1: SE0 noise detected This bit is used to indicate that the SIE has detected a SE0 noise on the USB bus or not. It is set to 1 by SIE hareware and cleared to 0 by application program. Bit 1PU: UDP/UDN pins pull-high function control 0: Disable 1: Enable When this bit is set to 1, there will be a 600kΩ pull-high resistor connected to UDP and UDN pins respectively. Bit 0ESD: ESD issue indication 0: No ESD issue occurs 1: ESD issue occurred This bit will be set to 1 by SIE when an ESD issue occurs and cleared by application program. Rev. 1.10 149 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver UINT Register Bit 7 6 5 4 3 2 1 0 Name — — — — EP3EN EP2EN EP1EN EP0EN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3EP3EN: USB endpoint 3 interrupt control 0: Disable 1: Enable Bit 2EP2EN: USB endpoint 2 interrupt control 0: Disable 1: Enable Bit 1EP1EN: USB endpoint 1 interrupt control 0: Disable 1: Enable Bit 0EP0EN: USB endpoint 0 interrupt control 0: Disable 1: Enable USC Register Bit 7 6 5 Name URD SELPS2 PLL 4 R/W R/W R/W R/W R/W POR 1 0 0 0 3 2 1 0 URST RMWK SUSP R R/W R/W R 0 0 0 0 SELUSB RESUME Bit 7URD: USB reset signal control function definition 0: USB reset signal can not reset the MCU 1: USB reset signal will reset the MCU Bit 6SELPS2: PS2 mode selection bit 0: Not PS2 mode 1: PS2 mode When this bit is set to 1, the PS2 function is selected. The pin-shared pins, UDP/ GPIO1 and UDN/GPIO0, will be in the general purpose I/O function, GPIOP0 and GPIO1, which can be used as the DATA and CLK pins for PS2 function. Bit 5PLL: PLL control bit 0: Turn-on PLL 1: Turn-off PLL Bit 4SELUSB: USB mode selection bit 0: Not USB mode and turn off V33O 1: USB mode and turn on V33O When this bit is set to 1, the USB and V33O functions will both be enabled. The pinshared pins, UDP/GPIO1 and UDN/GPIO0, will be in the USB function, UDP and UDN, which are used as the USB pins for USB function. Rev. 1.10 150 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SELUSB 0 0 1 SELPS2 Mode Descriptions 0 No mode is supported. V33O pin not output and in a floating state. UDP/GPIO1 and UDN/GPIO0 pins are not output. 1 PS2 mode is selected. V33O pin output VDD voltage. The UDP/GPIO1 and UDN/GPIO0 pins are used as general purpose I/O pins, GPIO0 and GPIO1, which can output by application program. x USB mode is selected. V33O pin output 3.3V voltage. The UDP/GPIO1 and UDN/GPIO0 pins are used as USB functional pins, UDP and UDN, which can output by application program. “x”: don’t care Bit 3RESUME: USB resume indication 0: SUSP bit goes low 1: Leave Suspend mode When the USB leaves the suspend mode, the RESUME bit will be set to “1” by SIE and then an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set USBCKEN and clear the SUSP2 bit in the UCC register to enable the SIE detect function. The RESUME bit will be cleared to 0 when the SUSP goes low. When the MCU is detecting the SUSP, the RESUME state (causes the MCU to wake-up) should be noted and taken into consideration. Bit 2URST: USB reset indication bit 0: No USB reset occurs 1: USB reset occurred This bit is set and cleared by the USB SIE. This bit is used to indicate a USB reset event on the USB bus. When this bit is set to “1”, this indicates that a USB reset has occurred and that a USB interrupt will be initialized. Bit 1RMWK: USB remote wake-up control 0: No remote wake-up is asserted 1: Remote wake-up is asserted This bit is set by the MCU to inform the external USB host leaving the suspend mode. When this bit is set to 1, a high pulse with a pulse width of 4μs will be generatedand and sent to the USB host to ask for a USB remote wake-up to leave the suspend mode. Bit 0SUSP: USB suspend indication 0: Not in the suspend mode 1: Enter the suspend mode When this bit is set to 1, it indicates that the USB bus has entered the suspend mode. The USB interrupt will also be triggered when this bit changes state from low to high. Rev. 1.10 151 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver USR Register Bit 7 6 5 4 3 2 1 0 Name — — — — EP3F EP2F EP1F EP0F R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3EP3F: USB endpoint 3 accessed detection 0: Not accessed 1: Accessed Bit 2EP2F: USB endpoint 2 accessed detection 0: Not accessed 1: Accessed Bit 1EP1F: USB endpoint 1 accessed detection 0: Not accessed 1: Accessed Bit 0EP0F: USB endpoint 0 accessed detection 0: Not accessed 1: Accessed UCC Register Bit 7 Name Rctrl 6 R/W R/W R/W POR 0 0 5 4 3 2 1 0 SUSP2 USBCKEN — EPS1 EPS0 R/W R/W R/W — R/W R/W 0 0 0 — 0 0 SYSCLK Fsys16MHZ Bit 7Rctrl: 7.5kΩ resistor between UDP and UBUS control bit 0: No 7.5kΩ resistor connected between UDP and UBUS 1: 7.5kΩ resistor connected between UDP and UBUS Bit 6SYSCLK: System clock frequency select bit 0: 12MHz 1: 6MHz Note: If a 6MHz crystal or resonator is used for the MCU, this bit should be set to 1. If a 12MHz crystal or resonator is used, then this bit should be set to 0. If the 12MHz HIRC oscillator is selected, then this bit must be set to 0. Bit 5Fsys16MHZ: PLL 16MHz output control bit 0: From HXT 1: From PLL output – 16MHz frequency output Bit 4SUSP2: Reduce power consumption in suspend mode controlbit 0: Normal suspend mode 1: More power saving suspend mode If this bit is set to 1, the device will reduce more power consumption than the power consumption in the normal suspend mode. Bit 3USBCKEN: USB clock control bit 0: Disable 1: Enable Bit 2 Unimplemented, read as “0” Bit 1~0EPS1~EPS0: Accessing endpoint FIFO selection 00: Select endpoint 0 FIFO (control) 01: Select endpoint 1 FIFO 10: Select endpoint 2 FIFO 11: Select endpoint 3 FIFO Rev. 1.10 152 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver AWR Register Bit 7 6 5 4 3 2 1 0 Name AD6 AD6 AD6 AD6 AD6 AD6 AD6 WKEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1AD6~AD0: USB device address bit 6 ~ bit 0 The AWR register contains the current address with an initial value of “00H”. For the device address update, the address value extracted from the USB command has not to be loaded into this register until the SETUP stage is finished by setting the device address update control bit, ASET, in the SIES register to 1. Bit 0WKEN: USB remote wake-up control bit 0: Disable 1: Enable STLO Register Bit 7 6 5 4 3 2 1 0 Name — — — — STLO3 STLO2 STLO1 STLO0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0STLO3~STLO0: USB endpoint n FIFO OUT stall indication 0: Not stall 1: Stall The STLO register shows if the corresponding endpoint has worked properly or not. As soon as an endpoint improper operation occurs, the related bit in the STLO register will be set high. The STLO register bit will be cleared by a USB reset signal and a SETUP token event. STLI Register Bit 7 6 5 4 3 2 1 0 Name — — — — STLI3 STLI2 STLI1 STLI0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0STLI3~STLI0: USB endpoint n FIFO IN stall indication 0: Not stall 1: Stall The STLI register shows if the corresponding endpoint has worked properly or not. As soon as an endpoint improper operation occurs, the related bit in the STLI register will be set high. The STLI register bit will be cleared by a USB reset signal and a SETUP token event. Rev. 1.10 153 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SIES Register Bit 7 6 5 4 3 2 1 0 Name NMI CRCF — NAK IN OUT ERR ASET R/W R/W R/W — R R R/W R/W R/W POR 0 0 — 0 0 0 0 0 Bit 7NMI: NAK token interrupt mask control 0: Not masked 1: Masked This bit is available and used for all endpoints. If this bit is set to 1, an interrupt will be disabled when the device sends a NAK token to the host. Otherwise, if this bit is cleared to 0, an interrupt will be generated when the device sends a NAK token to the host. Bit 6CRCF: CRC error detection flag 0: No CRC error is detected 1: CRC error is detected This bit is used for all endpoints. This bit is set to 1 by SIE when a CRC error is detected and cleared to 0 by application program. Bit 5 Unimplemented, read as “0” Bit 4NAK: NAK signal indication flag 0: No ACK signal is transmitted 1: NAK error signal has been transmitted This bit is used to indicate that the SIE has transmitted a NAK signal to the USB host in response to the USB host IN or OUT token when the endpoint was accessed. Bit 3IN: IN token indication flag for Endpoint 0 0: The received token packet is not IN token 1: The received token packet is IN token This bit is used to indicate that the current received signal from the USB host is IN token for endpoint 0. Bit 2OUT: OUT token indication flag for Endpoint 0 0: The received token packet is not OUT token 1: The received token packet is OUT token This bit is used to indicate that the current received signal from the USB host is OUT token for endpoint 0. Bit 1ERR: FIFO access error indication flag 0: No FIFO access error occurs 1: FIFO access error occurred This bit is used to indicate that errors have occurred when the FIFO was accessed. This bit us set to 1 by SIE and should be cleared to 0 by application program. This ERR bit is used for all endpoint. Bit 0ASET: Device address update control 0: Device address is updated immediately when an address is writtn into the AWR register 1: Decive address is updated after the USB host reads out the data This bit is used to configure the SIE to automatically update the device address by the value stored in the AWR register. When this bit is set to 1 by application program, the SIE will update the device address with the value stored in the AWR register after the USB host has successfully read the data from the device by an IN token operation. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written into the AWR register. Therefore, in order to work properly, the application program has to clear this bit after the next value SETUP token is received. Rev. 1.10 154 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver MISC Register Bit 7 6 5 4 3 2 1 0 Name LEN0 READY SETCMD — E3IDF CLEAR TX REQUEST R/W R R R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7LEN0: 0-size packet indication flag 0: Not 0-sized oacket 1: 0-sized oacket This bit is used to show if the host sends a 0-sized packet to the MCU or not. It must be cleared by a read action to the corresponding FIFO. Bit 6READY: Desired endpoint FIFO ready indication flag 0: No ready 1: Ready Bit 5SETCMD: SETUP command indication flag 0: Not SETUP token in the endpoint 0 FIFO 1: SETUP token in the endpoint 0 FIFO This bit is used to indicate whether the data in the endpoint 0 FIFO is SETUP token or not. It is set by hardware and cleared by application program. Bit 4 Unimplemented, read as “0” Bit 3E3IDF: Endpoint 3 input FIFO selection 0: Single buffer 1: Double buffer This bit is used to indicate that the current received signal from the USB host is IN token for endpoint 0. Bit 2CLEAR: Clear FIFO function control 0: Disable 1: Enable This bit is used by the MCU to clear to the requested FIFO, even if the FIFO is not ready. After clearing the FIFO, the USB interface will send a force_tx_err signal to tell the USB host that the data under-run if the USB host wants to read data. Bit 1TX: Data transfer direction indication flag 0: Data transfer from the endpoint FIFO to the MCU 1: Data transfer from the MCU to the endpoint FIFO This bit is used to define the data transfer direction betweeb the MCU and the endpoint FIFO. When this bit is set high, it means that the MCU wants to write data to the endpoint FIFO. After the MCU write operation has been completed, this bit must be cleared to zero before terminating the FIFO request to indicate the end of data transfer. For a MCU read operation, this bit has to be cleared to zero to show that the MCU wants to read data from the endpoint FIFO and set high before terminating the FIFO request to indicate the end of data transfer after the completion of a MCU read operation. Bit 0REQUEST: Desired FIFO request control 0: No request or request conmple 1: Request the desired FIFO This bit is used to request the operation of the desired endpoint FIFO. After selecting the desired endpoint, the FIFO can be requested by setting this bit to high and it must be cleared to zero after request completion. Rev. 1.10 155 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver UFOEN Register Bit 7 6 5 4 3 2 1 0 Name — — — — SETO3 SETO2 SETO1 DATATG R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3SETO3: USB endpoint 3 output FIFO control 0: Disable 1: Enable Bit 2SETO2: USB endpoint 2 output FIFO control 0: Disable 1: Enable Bit 1SETO1: USB endpoint 1 output FIFO control 0: Disable 1: Enable Bit 0DATATG: DATA token toggle bit 0: Low 1: High UFIEN Register Bit 7 6 5 4 3 2 1 0 Name — — — — SETI3 SETI2 SETI1 FIFO_def R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3SETI3: USB endpoint 3 input FIFO control 0: Disable 1: Enable Bit 2SETI2: USB endpoint 2 input FIFO control 0: Disable 1: Enable Bit 1SETI1: USB endpoint 1 input FIFO control 0: Disable 1: Enable Bit 0FIFO_def: FIFO configuration redefined control 0: Disable 1: Enable This bit should be set to 1 to inform the SIE to redefine the relevant FIFO configurations including the UFOEN, UFIEN and UFC0 registers after the corresponding FIFO size is reconfigured. This bit will be automatically cleared by SIE. Rev. 1.10 156 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver UFC0 Register Bit 7 6 5 4 3 2 1 0 Name E3FS1 E3FS0 E2FS1 E2FS0 E1FS1 E1FS0 — — R/W R/W R/W R/W R/W R/W R/W — — POR 0 0 0 0 0 0 — — Bit 7~6E3FS1~E3FS0: USB endpoint 3 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 5~4E2FS1~E2FS0: USB endpoint 2 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 3~2E1FS1~E1FS0: USB endpoint 1 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 1~0 Unimplemented, read as “0” USB Endpoint FIFO Accessing Registers Bit Register Name 7 6 5 4 3 2 1 0 FIFO0 D7 D6 D5 D4 D3 D2 D1 D0 FIFO1 D7 D6 D5 D4 D3 D2 D1 D0 FIFO2 D7 D6 D5 D4 D3 D2 D1 D0 FIFO3 D7 D6 D5 D4 D3 D2 D1 D0 Endpoint FIFO Registers List Rev. 1.10 157 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver RF Transceiver The RF transceiver operates in the world wide ISM frequency band of 2400~2483.5 MHz. Burst mode transmission and up to 2Mbps air data rate make them suitable for applications requiring ultra low power consumption. It operates as either a transmitter or a receiver in the Time Division Duplex mode, abbreviated as TDD. The RF channel frequency determines the center of the channel used by the transceiver. The frequency is set by configuring the RF_CH register in register bank 0 according to the following formula: F0= 2400 + RF_CH (MHz). The resolution of the RF channel frequency is 1MHz. A transmitter and a receiver must be programmed with the same RF channel frequency to be able to communicate with each other. The output power of the transceiver is set by the RF_PWR bits in the RF_SETUP register. Demodulation is implemented with the embedded data slicer and bit recovery logic. The air data rate can be programmed to be 250Kbps, 1Mbps or 2Mbps by configuring the RF_ DR_HIGH and RF_DR_LOW registers. A transmitter and a receiver must be programmed with the same setting. Data Sli�e� RFP1 RFN1 XTALP XTALN Integ�ated TDD RF T�ans�eive� Pa�ket P�o�essing & State Cont�ol Powe� Manage�ent Gaussian Shaping TX FIFO CSN RFSCK MOSI MISO IRQ CE Registe� Banks FM Modulato� SPI Inte�fa�e RX FIFO FM De�odulato� RF Transceiver Block Diagram RF Transceiver Abbreviations ACK Acknowledgement ARC Auto Retransmission Count ARD Auto Retransmission Delay CD Carrier Detection CE Chip Enable CRC Cyclic Redundancy Check CSN Chip Select Not DPL Dynamic Payload Length FIFO First-In-First-Out GFSK Gaussian Frequency Shift Keying GHz Gigahertz LNA Low Noise Amplifier IRQ Interrupt Request ISM Industrial-Scientific-Medical LSB Least Significant Bit MAX_RT Maximum Retransmit Mbps Megabit per second MCU Microcontroller Unit MHz Megahertz MISO Master In Slave Out MOSI Master Out Slave In MSB Most Significant Bit PA Power Amplifier PID Packet Identity Bits Rev. 1.10 158 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver PLD Payload PRX Primary RX PTX Primary TX PWD_DWN Power Down PWD_UP Power Up RF_CH Radio Frequency Channel RSSI Received Signal Strength Indicator RX Receive RX_DR Receive Data Ready SCK SPI Clock SPI Serial Peripheral Interface TDD Time Division Duplex TX Transmit TX_DS Transmit Data Sent XTAL Crystal RF Transceiver State Control The RF transceiver block includes an integrated a state machine that controls the state transition between different modes. When the auto acknowledge feature is disabled, the state transition will be fully controlled by the MCU. • SPI register: PWR_UP, PRIM_RX, EN_AA, NO_ACK, ARC, ARD • System information: Time out, ACK received, ARD elapsed, ARC_CNT, TX FIFO empty, ACK packet transmitted, Packet received Primary Transmission State Control – PTX, PRIM_RX=0 VDD>1.9V Powe� Down PWR_UP=1 Sta�t up ti�e 1.5�s PWR_UP=0 Stand�y-I Ti�e out o� ACK �e�eived RX TX finished CE=0 Stand�y-II TX FIFO not e�pty CE=1 fo� �o�e than 15µs ARD elapsed and ARC_CNT<ARC TX setting 130µs TX FIFO not e�pty CE=1 TX setting 130µs TX TX FIFO e�pty CE=1 EN_AA=1 NO_ACK=0 RX setting 130µs Primary Transmission State Diagram Rev. 1.10 159 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Primary Reception State Control – PRX, PRIM_RX=1 VDD>1.9V Powe� Down PWR_UP=1 Sta�t up ti�e 1.5�s PWR_UP=0 Stand�y-I CE=0 CE=1 RX setting 130µs CE=0 RX TX ACK pa�ket t�ans�itted CE=1 RX setting 130µs Pa�ket �e�eived EN_AA=1 NO_ACK=0 TX setting 130µs Primary Reception State Diagram Power Down Mode The Power down mode of the RF Transceiver is entered by setting the PWR_UP bit in the CONFIG register to low. In the power down mode the transceiver block is in the sleep mode where it has minimal current consumption. However, the SPI interface is still active in this mode and all register values can be configured by the SPI interface. The MCU and RF Transceiver are powered down independently of each other. The method of powering down the MCU is covered in the previous MCU section of the datasheet. The RF Transceiver must be powered down before the MCU is powered down. This is implemented by first clearing the PWR_UP bit in the CONFIG register to disable the RF Transceiver circuitry and then pulling the line to high to disable the RF SPI interface circuitry. After the RF transceiver is completely powered down, the MCU can be powered down to minimise the power consumption. Standby-I Mode By setting the PWR_UP bit in the CONFIG register to 1 and de-asserting the CE signal to a low state, the device enters the Standby-I mode. The Standby-I mode is used to minimise the average current consumption and also to maintain a shorter start-up time. In this mode, the clock is still active. When the CE signal is set to a low state, the transceiver will return to the Standby-I mode regardless of whether it is in the TX or RX mode. Standby-II Mode In the Standby-II mode more RF Transceiver circuitry is active than in the Standby-I mode and therefore more current is consumed. The transceiver will enter the Standby-II mode from the TX mode when the CE signal is set to a high state and the TX FIFO is empty. If a new data packet is uploaded into the TX FIFO, the device will automatically return to the TX mode and the packet will be transmitted. Rev. 1.10 160 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TX Mode • Primary Transmit Device – PTX, PRIM_RX=0 The TX mode is an active mode where the PTX device transmits a data packet. To enter this mode from power down mode, the PTX device must set the PWR_UP bit to high, the PRIM_ RX bit to low, a payload in the TX FIFO and generate a high pulse on the CE line for more than 15μs. The PTX device stays in the TX mode until it finishes transmitting the current packet and then enters the Standby-II mode. If the CE signal is in a low state, it will return to Standby-I mode. If the CE signal is in a high state, the next action will be determined by the status of the TX FIFO. If the TX FIFO is not empty, the PTX device will enter the TX mode and then transmit the next packet. If the TX FIFO is empty, the PTX device will remain in the Standby-II mode. It is important to note that it never remains in the TX mode for more than 4ms during a transmit operation. If the auto retransmit is enabled by setting the EN_AA bit to 1 and an auto acknowledge is required by setting the NO_ACK bit to 0, the PTX device will enter the TX mode from the Standby-I mode when the ARD has elapsed and the number of retry is less than the ARC. The PTX device will enter the RX mode from the TX mode only when the EN_AA bit is set to 1 and the NO_ACK bit is cleared to 0 to receive the acknowledge packet. RX Mode • Primary Receive Device – PRX, PRIM_RX=1 The RX mode is an active mode where the transceiver is configured as a receiver. To enter this RX mode from the Standby-I mode, the PRX device must set the PWR_UP bit to high, the PRIM_RX bit to high and the CE signal to high. In this mode the receiver demodulates the signals from the RF channel, constantly presenting the demodulated data to the packet processing engine. The packet processing engine continuously searches for a valid packet. If a valid packet is found by a matching address and a valid CRC, the packet payload is presented to a vacant slot in the RX FIFO. If the RX FIFO is full, the received packet will be discarded. The PRX device remains in the RX mode until the MCU configures it to enter the Standby-I mode or Power Down mode. In the RX mode a carrier detection signal, CD, is made available. The CD signal is set high when an RF signal is detected on the receiving frequency channel. The internal CD signal is filtered before being written into the CD register. The RF signal must be present for at least 128 μs before the CD signal is set high. The PRX device will enter the TX mode from the RX mode only when the EN_AA bit is set to 1 and the NO_ACK bit is cleared to 0 in the received packet to transmit an acknowledge packet with a pending payload in the TX FIFO. RF Transceiver Packet Processing Packet Format The complete packet includes a preamble, 3~5 address bytes, a packet control field, 0~32 payload bytes and a CRC field. P�ea��le (1 �yte) Add�ess (3~5 �ytes) Pa�ket Cont�ol (9/0 �its) Payload Length (6 �its) PID (� �its) Payload (0~3� �ytes) CRC (�/1 �ytes) NO_ACK (1 �it) Packet Format Rev. 1.10 161 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Preamble The preamble is a bit sequence used to detect the “0” and “1” levels in the receiver. The preamble is one byte long whose value is either 01010101 or 10101010. If the first bit in the address is 1, the preamble is automatically set to 10101010 while if the first bit is 0, the preamble is automatically set to 01010101. This is done to ensure there are enough transitions in the preamble to stabilise the receiver. Address This field is the address for the receiver. An address ensures that the packet is detected by the target receiver. The address field can be configured to be 3, 4 or 5 bytes long by the AW register. The PRX device can open up to six data pipes to support up to six PTX devices with specific addresses. All six PTX device addresses are searched simultaneously. In the PRX device, the data pipes are enabled with the corresponding control bits in the EN_RXADDR register. The default status is that only data pipe 0 and pipe 1 are enabled. Each data pipe address can be configured in the RX_ADDR_PX registers. Each pipe can have up to a 5 byte configurable address. Data pipe 0 has a unique 5-byte address. Data pipes 1~5 share the 4 most significant address bytes. The least significant byte must be unique for all 6 pipes. To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX takes the data pipe address where it received the packet and uses it as the TX address when transmitting the ACK packet. On the PRX device the RX_ADDR_Pn defined as the pipe address must be unique. On the PTX device the TX_ADDR must be the same as the RX_ADDR_P0 on the PTX, and as the pipe address for the designated pipe on the PRX. No other data pipe can receive data until a complete packet is received by a data pipe that has detected its address. When multiple PTX devices are transmitting to a PRX, the ARD can be used to skew the auto retransmission so that they only block each other once. Packet Control When the Dynamic Payload Length function is enabled, the packet control field contains a 6-bit payload length field, a 2-bit Packet Identity, PID, field and a 1-bit NO_ACK flag. • Payload Length The payload length field is used to define the payload length and only used if the Dynamic Payload Length function is enabled. • PID The 2-bit PID field is used to detect whether the received packet is new or retransmitted. The PID prevents the PRX device from presenting the same payload more than once to the MCU. The PID field is incremented at the TX side for each new packet received through the SPI interface. The PID and CRC fields are used by the PRX device to determine whether a packet is old or new. When several data packets are lost on the link, the PID fields may become equal to the last received PID. If a packet has the same PID as the previous packet, the transceiver compares the CRC sums from both packets. If the CRC sums are also the same, the last received packet will be considered a copy of the previously received packet and be discarded. Rev. 1.10 162 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • NO_ACK The NO_ACK flag is used only when the auto acknowledgement feature is used. Setting the flag high informs the receiver that the packet is not to be auto acknowledged. The PTX device can set the NO_ACK flag bit in the Packet Control Field with the command: W_TX_PAYLOAD_ NOACK. However, the function must first be enabled in the FEATURE register by setting the EN_DYN_ACK bit. When the auto acknowledgement function is used, the PTX will directly enter to the Standby-I mode after the packet is transmitted and the PRX device does not transmit an ACK packet when it receives the PTX transmitted packet. Payload The payload field is used to define the contents of the packet. It can be from 0 to 32 bytes wide and transmitted on-air as it is uploaded (unmodified) to the device. The transceiver provides two alternatives for handling payload lengths, static and dynamic payload length. The static payload length of the six data pipes can be individually set. The default alternative is static payload length. With static payload length all packets between a transmitter and a receiver have the same length. The static payload length is set by the RX_PW_Pn registers. The payload length on the transmitter side is set by the number of bytes clocked into the TX_FIFO and must equal to the value in the RX_PW_Pn register on the receiver side. Each pipe has its own payload length. The Dynamic Payload Length, DPL, is an alternative to the static payload length. The DPL enables the transmitter to send packets with variable payload lengths to the receiver. This means that for a system with different payload lengths it is not necessary to scale the packet length to the longest payload. With the DPL feature the transceiver can decode the payload length of the received packet automatically instead of using the RX_PW_Pn registers. The MCU can read the length of the received payload using the command: R_RX_PL_WID. In order to enable the DPL function, the EN_DPL bit in the FEATURE register must be set. In the RX mode the DYNPD register has to be properly configured. A PTX device must set the DPL_P0 bit in the DYNPD register to transmit to a PRX with the DPL function being enabled. CRC The CRC is the error detection mechanism in the packet. The number of bytes in the CRC is set by the CRCO bit in the CONFIG register. It may be either 1 or 2 bytes and is calculated over the address, Packet Control Field and Payload. The polynomial for a1-byte CRC is X8 + X2 + X + 1 with an initial value of 0xFFH. The polynomial for a 2-byte CRC is X16 + X12 + X5 + 1 with an initial value of 0xFFFFH. No packet is accepted by the receiver side if the CRC fails. Rev. 1.10 163 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Packet Handling The transceiver circuitry uses burst mode for payload transmission and reception. The transmitter fetches the payload from the TX FIFO, automatically assembles it into a packet and transmits the packet in a very short burst period with a 1Mbps or 2Mbps air data rate. After a transmission, if the PTX packet has the NO_ACK flag set, the transceiver sets the TX_DS bit and gives an active low interrupt pulse on the IRQ line sent to the MCU. If the PTX is an ACK packet, the PTX needs to receive an ACK from the PRX and then assert the TX_DS IRQ. The receiver automatically validates and disassembles the received packet. If there is a valid packet within the new payload, it will write the payload into the RX FIFO, set the RX_DR bit and give an active low interrupt pulse on the IRQ line sent to the MCU. When the auto acknowledge function is enabled by setting the EN_AA bit to 1, the PTX device will automatically wait for an acknowledge packet after transmission and re-transmit the original packet after the ARD delay until an acknowledge packet is received or the number of re-transmission exceeds a threshold defined by the ARC field. If the number of re-transmissions exceeds a threshold defined by the ARC field, the transceiver will set the MAX_RT bit and give an active low interrupt pulse on the IRQ line sent to the MCU. Two packet loss counters, ARC_CNT and PLOS_CNT, are incremented by one each time a packet is lost. The ARC_CNT counter counts the number of retransmissions for the current transaction. The PLOS_CNT counter counts the total number of retransmissions since the last channel change. The ARC_CNT counter is reset by initiating a new transaction while the PLOS_CNT counter is reset by writing a value to the RF_CH register to change a RF channel. It is possible to use the information in the OBSERVE_TX register to make an overall assessment of the channel quality. The PTX device will retransmit if its RX FIFO is full but the received ACK frame has a payload. As an alternative for the PTX device to auto retransmit it is possible to manually set the transceiver to retransmit a packet a number of times. This is done using the REUSE_TX_PL command. When the auto acknowledge function is enabled, the PRX device will automatically check the NO_ACK field in the received packet, and if the NO_ACK bit is 0, it will automatically send an acknowledge packet to the PTX device. If the EN_ACK_PAY bit is set, the acknowledge packet can also be regarded as a pending payload in the TX FIFO. Rev. 1.10 164 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver RF Transceiver Data and Control Interface TX/RX FIFO The data FIFOs are used to store the payload that is to be transmitted in the TX FIFO or is received in the RX FIFO and ready to be clocked out. The FIFO is accessible in both the PTX mode and PRX modes. There is a three level 32 byte FIFO for both the TX and RX, supporting both the acknowledge mode or no acknowledge mode with up to six data pipes. • TX three levels, 32 bytes FIFO • RX three levels, 32 bytes FIFO Both the TX and RX FIFOs have a controller and are accessible through the SPI interface using dedicated SPI commands. A TX FIFO in PRX can store the payload for ACK packets for three different PTX devices. If the TX FIFO contains more than one payload for a pipe, the different payloads are handled using the first-in first-out principle. The TX FIFO in a PRX device is blocked if all pending payloads are addressed to pipes where the link to the PTX device is lost. In this case, the MCU can flush the TX FIFO using the FLUSH_TX command. The RX FIFO in the PRX device may contain a payload from up to three different PTX devices. A TX FIFO in the PTX devices can have up to three payloads stored. The TX FIFO can be written to by three commands, W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in the PTX mode and W_ACK_PAYLOAD in the PRX mode. All three commands give access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in both PTX and PRX modes. This command gives access to the RX_PLD register. The payload in the TX FIFO in a PTX device is NOT removed if the MAX_RT IRQ is asserted. In the FIFO_STATUS register it is possible to know whether the TX and RX FIFO are full or empty. The TX_REUSE bit is also available in the FIFO_STATUS register. The TX_REUSE bit is set by the SPI command, REUSE_TX_PL, and is reset by the SPI command, W_TX_PAYLOAD or FLUSH TX. Interrupt In the RF transceiver circuitry there is an active low interrupt line, IRQ, which is activated when the TX_DS IRQ, RX_DR IRQ or MAX_RT IRQ bit is set to high by the state machine in the STATUS register. The IRQ line is externally connected to the MCU TM clock input pin, TCK2. The detailed TM TCK configurations are described in the preceding section in this datasheet. The IRQ line is reset when the MCU writes a ‘1’ into the IRQ source bit in the STATUS register. The IRQ mask control bit in the CONFIG register is used to select which IRQ source is allowed to assert the IRQ line. By setting one of the MASK bits high, the corresponding IRQ source will be disabled. By default all IRQ sources are enabled. The 3-bit pipe information in the STATUS register is updated when the IRQ line changes state from high to low. If the STATUS register is read during a high to low transition of an IRQ line, the pipe information is not available. Rev. 1.10 165 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SPI Interface The SPI commands are shown in the following table. Every new command must be started by a high to low transition on the CSN line. In parallel to the SPI command byte applied on the MOSI line, the STATUS register bit, Sn, is serially shifted out on the MISO line. The RF Transceiver SPI interface is externally connected to the MCU SPIA interface. The detailed MCU SPIA interface operations are described in the corresponding SPIA interface section in this datasheet. The RF transceiver serial shifting SPI commands are in the following format: • Command byte: one byte command word from MSB to LSB • Data read operation: The data byte is shifted out from the least significant byte to the most significant byte and MSB first in each byte for all registers in all register banks. • Data write operation: The data byte is shifted in from the most significant byte to the least significant byte and MSB in each byte first for register 0 to register 8 in register bank 1. For other registers in all banks the data byte is shifted in from the least significant byte to the most significant byte. Command byte (Cn) Data bytes (Dn) R_REGISTER 000A AAAA 1 to 5 Read command and status registers AAAAA = 5-bit Register Map Address W_REGISTER 001A AAAA 1 to 5 Write command and status registers AAAAA = 5-bit Register Map Address Executable in power down or standby modes only R_RX_PAYLOAD Read RX-payload: 1 ~ 32 bytes, used in the RX mode 1 to 32 A read operation always starts at byte 0 0110 0001 LSB byte first The RX Payload is implemented in register bank 0 and is deleted from the FIFO after it is read W_TX_PAYLOAD 1010 0000 FLUSH_TX 1110 0001 Command name FLUSH_RX REUSE_TX_PL Rev. 1.10 1110 0010 1110 0011 Operation Write TX-payload: 1 ~ 32 bytes 1 to 32 A write operation always starts at byte 0 LSB byte first The TX Payload is implemented in register bank 0 and is used in the TX mode. 0 Flush TX FIFO, used in TX mode 0 Flush RX FIFO, used in RX mode. Should not be executed during transmission of acknowledge, that is, an acknowledge package will not be completed. 0 Used for a PTX device Reuse last transmitted payload Packets are repeatedly retransmitted as long as CE is high. The TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. The TX payload reuse must not be activated or deactivated during package transmission 166 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Command name Command byte (Cn) Data bytes (Dn) Operation 1 This write command followed by data 0x73 activates the following features: • R_RX_PL_WID • W_ACK_PAYLOAD • W_TX_PAYLOAD_NOACK A n e w A C T I VAT E c o mm a n d w i t h t h e s a m e d a t a deactivates them again. This is executable in power down or standby modes only. The features registers named as R_RX_PL_WID, W_ ACK_PAYLOAD, and W_TX_PAYLOAD_NOACK are initially in a deactivated state; a write operation has no effect, a read operation only results in zeros on MISO. To activate these registers, use the ACTIVATE command followed by data 0x73. Then they can be accessed just like any other registers. Using the same command and data will deactivate the registers again. This write command followed by data 0x53 toggles the register bank and the current register bank number can be read out from the STATUS register bit 7. ACTIVATE 0101 0000 R_RX_PL_WID 0110 0000 W_ACK_PAYLOAD Write ACK Payload: 1~ 32 bytes, used in the RX mode Write Payload to be transmitted together with ACK packet on PIPE “PPP” where the “PPP” ranges from 000 to 101. 1 to 32 Maximum three ACK packet payloads can be pending. 1010 1PPP LSB byte first Payloads with the same PPP are handled using first-infirst-out principle. A write operation to the ACK payload implemented in the register bank 0 always starts at byte 0. W_TX_PAYLOAD_NOACK 1011 0000 NOP Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO 1 to 32 Used in TX mode and implemented in the register bank 0 LSB byte first Disables AUTOACK on this specific packet. 1111 1111 0 No Operation. Might be used to read the STATUS register. CSN …… SCK MOSI C7 C6 C5 C� C3 C� C1 C0 MISO S7 S6 S5 S� S3 S� S1 S0 D7 D6 ……… D0 …… D15 ……… D8 …… …… D�3 ……… D16 D31 ……… Note: The data byte on the MISO line may be 1 byte, 4 bytes, 11 bytes or 32 bytes depending upon which register is accessed. SPI read operation – All registers in Bank 0 & Bank1 CSN …… SCK MOSI C7 C6 C5 C� C3 C� C1 C0 MISO S7 S6 S5 S� S3 S� S1 S0 D7 D6 ……… D0 …… D15 ……… D8 …… …… D�3 ……… D16 D31 ……… Note: The data byte on the MISO line may be 1 byte, 4 bytes, 11 bytes or 32 bytes depending upon which register is accessed. SPI write operation – All registers in Bank 0 & Register 9~14 in Bank1 Rev. 1.10 167 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver CSN SCK MOSI C7 C6 C5 C� C3 C� C1 C0 D15 D1�D13D1�D11D10 D9 D8 MISO S7 S6 S5 S� S3 S� S1 S0 D7 D6 D5 D� D3 D� D1 D0 SPI write operation – Register 0~8 in Bank1 RF Transceiver Register Map There are two register banks, which can be toggled by an SPI “ACTIVATE” command followed with 0x53 data byte and the bank status can be read from the STATUS register bit 7 in the Register Bank0. Register Bank 0 It is recommended that no access is executed on reserved or non defined registers. Otherwise, this may result in unpredictable conditions. • Address 00H – CONFIG Register This register is used to configure the primary setting of the RF Transceiver. Bit 7 6 5 4 3 2 1 0 Name — R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 1 0 0 0 Bit 7 MASK_RX_DR MASK_TX_DS MASK_MAX_RT EN_CRC CRCO PWR_UP PRIM_RX Reserved bit, only data “0” allowed. Bit 6MASK_RX_DR: RX_DR Mask interrupt control 0: RX_DR interrupt is reflected as an active low interrupt pulse on the IRQ line 1: RX_DR interrupt is not reflected on the IRQ line Bit 5MASK_TX_DS: TX_DS Mask interrupt control 0: TX_DS interrupt is reflected as an active low interrupt pulse on the IRQ line 1: TX_DS interrupt is not reflected on the IRQ line Bit 4MASK_MAX_RT: MAX_RT Mask interrupt control 0: MAX_RT interrupt is reflected as an active low interrupt pulse on the IRQ line 1: MAX_RT interrupt is not reflected on the IRQ line Bit 3EN_CRC: CRC function enable control 0: Disable 1: Enable This bit will be forced to high if one of the bits in the EN_AA register is high. Bit 2CRCO: CRC encoding scheme 0: 1 byte 1: 2 bytes Bit 1PWR_UP: RF Transceiver power control 0: Power up 1: Power down Bit 0PRIM_RX: RX/TX mode selection 0: Primary Transmit – PTX 1: Primary Receive – PRX Rev. 1.10 168 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 01H – EN_AA Register This register is used to enable the “Auto Acknowledgement” function of the individual data pipe. Bit 7 6 Name — — R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 1 1 1 1 1 Bit 7~6 5 4 3 2 1 0 ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 Reserved bits, only data “00” allowed. Bit 5ENAA_P5: Data Pipe 5 Auto Acknowledgement function enable control 0: Disable 1: Enable Bit 4ENAA_P4: Data Pipe 4 Auto Acknowledgement function enable control 0: Disable 1: Enable Bit 3ENAA_P3: Data Pipe 3 Auto Acknowledgement function enable control 0: Disable 1: Enable Bit 2ENAA_P2: Data Pipe 2 Auto Acknowledgement function enable control 0: Disable 1: Enable Bit 1ENAA_P1: Data Pipe 1 Auto Acknowledgement function enable control 0: Disable 1: Enable Bit 0ENAA_P0: Data Pipe 0 Auto Acknowledgement function enable control 0: Disable 1: Enable Rev. 1.10 169 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 02H – EN_RXADDR Register This register is used to enable the RX data pipe address. Bit 7 6 5 4 3 2 1 0 Name — — ERX_P5 ERX_P4 ERX_P3 ERX_P2 ERX_P1 ERX_P0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5ERX_P5: Data Pipe 5 enable control 0: Disable 1: Enable Bit 4ERX_P4: Data Pipe 4 enable control 0: Disable 1: Enable Bit 3ERX_P3: Data Pipe 3 enable control 0: Disable 1: Enable Bit 2ERX_P2: Data Pipe 2 enable control 0: Disable 1: Enable Bit 1ERX_P1: Data Pipe 1 enable control 0: Disable 1: Enable Bit 0ERX_P0: Data Pipe 0 enable control 0: Disable 1: Enable • Address 03H – SETUP_AW Register This register is used to specify the data pipe address field width. Bit 7 6 5 4 3 2 1 0 Name — — — — — — AW1 AW0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~2 Reserved bits, only data “000000” allowed. Bit 1~0AW1~AW0: Data pipe Address Field Width 00: Illegal, can not be used. 01: 3 bytes 10: 4 bytes 11: 5 bytes The field is used to specify the data pipe address field width which is the same for all data pipes. Rev. 1.10 170 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 04H – SETUP_RETR Register This register is used to set the number and delay of the automatic retransmission. Bit 7 6 5 4 3 2 1 0 Name ARD3 ARD2 ARD1 ARD0 ARC3 ARC2 ARC1 ARC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~4ARD3~ARD0: Automatic Retransmission Delay selection 0000: (1×250) μs 0001: (2×250) μs 0010: (3×250) μs : 1110: (15×250) μs 1111: (16×250) μs The Automatic Retransmission Delay is defined as the time from the end of the current transmission to the start of the next transmission. Bit 3~0ARC3~ARC0: Automatic Retransmission Number 0000: No retransmission when automatic acknowledgement failed 0001: 1 retransmission when automatic acknowledgement failed 0010: 2 retransmissions when automatic acknowledgement failed : 1110: 14 retransmissions when automatic acknowledgement failed 1111: 15 retransmissions when automatic acknowledgement failed • Address 05H – RF_CH Register This register is used to select the RF channel. Bit 7 6 5 4 3 2 1 0 Name — RF_CH6 RF_CH5 RF_CH4 RF_CH3 RF_CH2 RF_CH1 RF_CH0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 1 0 Bit 7 Reserved bits, only data “0” allowed. Bit 6~0RF_CH6~RF_CH0: RF Channel selection 0000000 ~ 1111111: RF channel 0 ~ RF channel 127 Rev. 1.10 171 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 06H – RF_SETUP Register This register is used to configure the RF channel. Bit 7 6 Name — — R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 1 1 1 1 Bit 7~6 5 4 3 2 1 0 RF_DR_LOW PLL_LOCK RF_DR_HIGH RF_PWR1 RF_PWR0 LNA_HCURR Reserved bits, only data “00” allowed. Bit 5RF_DR_LOW: Air Data Rate select bit This bit is used to select the air data rate together with the RF_DR_HIGH bit. Refer to RF_DR_HIGH bit definition for more details. Bit 4PLL_LOCK: PLL Signal Lock control 0: No effect 1: PLL signal is locked This bit is used to lock the PLL signal and only available in the test mode. Bit 3RF_DR_HIGH: Air Data Rate select bit [RF_DR_HIGH, RF_DR_LOW] = Air Data Rate 00: 1 Mbps 01: 2 Mbps 10: 250 Kbps 11: 2 Mbps Bit 2~1RF_PWR1~RF_PWR0: RF TX Output Power selection 00: -26 dBm 01: -14 dBm 10: -6 dBm 11: -1 dBm RF_PWR [1:0] Optimisation Register 4 [27:25] 00 01 10 11 -9 000 -40 -24 -16 001 -30 -17 -9 -3 010 -26 -14 -6 -1 011 -22 -10 -3 1 100 -20 -7 -2 2 101 -17 -5 0 3 Note: The Optimisation Register 4 is located at address 04H in the RF Bank 1. Bit 0LNA_HCURR: LNA Gain selection 0: Low gain 1: High gain Rev. 1.10 172 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 07H – STATUS Register This register is used to store the status during the RF data transfer. When the SPI command is committed to the RF Transceiver on the MOSI line, the content of the STATUS register will be serially shifted out from the RF Transceiver on the MISO line. Bit 7 6 5 4 3 2 1 0 Name RBANK RX_DR TX_DS R/W R R/W R/W R/W R R R R POR 0 0 0 0 1 1 1 0 MAX_RT RX_P_NO2 RX_P_NO1 RX_P_NO0 TX_FULL Bit 7RBANK: Register Bank Status 0: Register bank 0 1: Register bank 1 Bit 6RX_DR: RX FIFO Data Received Status 0: No data is received in RX FIFO 1: New data has been received in RX FIFO This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it. When a new data packet is received in the RX FIFO, this bit will be asserted. Bit 5TX_DS: TX FIFO Data Sent Status 0: No data is transmitted from TX FIFO 1: New data has been transmitted from TX FIFO This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it. When a new data packet is transmitted from the TX FIFO, this bit will be asserted. If the AUTO_ ACK function is enabled, this bit will be set to 1 after the ACK is received. Bit 4MAX_RT: Maximum TX retransmission Status 0: TX re-transmission number does not reach to the maximum retransmission number. 1: TX re-transmission number has reached to the maximum retransmission number. This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it. When the TX re-transmission number has reached to the maximum retransmission number, this bit will be asserted. If the MAX_RT bit is set to 1, it must be cleared to 0 by application program to enable further data communication. Bit 3~1RX_P_NO2~RX_P_NO0: Data pipe number in RX FIFO 000~101: Data pipe 0 ~ Data pipe 5. 110: Not used 111: RX FIFO empty This field is used to indicate the data pipe number for the available payload in the RX FIFO. When this field is “111”, it means that the RX FIFO is empty. Bit 0TX_FULL: TX FIFO full flag 0: TX FIFO is not full 1: TX FIFO is full This bit is set and cleared by hardware. When the TX FIFO is full, this bit will be asserted. If this bit is 0, it means that the TX FIFO is not full yet and still has available locations to be used. Rev. 1.10 173 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 08H – OBSERVE_TX Register This register includes two read-only counters and is used to indicate the status during the TX data transmission. Bit Name 7 6 5 4 3 2 1 0 PLOS_CNT3 PLOS_CNT2 PLOS_CNT1 PLOS_CNT0 ARC_CNT3 ARC_CNT2 ARC_CNT1 ARC_CNT0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~4 PLOS_CNT3 ~ PLOS_CNT0: TX lost data packet number 0000~1111: 0 TX lost data packet ~ 15 TX lost data packets This field is used to count the total lost data packets during the TX data transmission. The PLOS_CNT value will be incremented by one each time a TX data packet is lost and retransmitted. When the counter value is equal to “1111”, it will stop counting and remain the maximum value of 1111 instead of counter overflow until a reset condition occurs. This counter will be reset by a write operation to the RF_CH register. Bit 3~0 ARC_CNT3 ~ ARC_CNT0: Automatic Retransmission number This field is used to count the retransmitted data packets during the TX data transmission. The ARC_CNT value will be incremented by one each time a TX data packet is lost and retransmitted. This counter will be reset when a new TX data starts to be transmitted. • Address 09H – CD Register This register is used to indicate the carrier detect status. Bit 7 6 5 4 3 2 1 0 Name — — — — — — — CD R/W — — — — — — — R POR — — — — — — — 0 Bit 7~1 Unimplemented, read as “0” Bit 0CD: Carrier Detect status 0: No carrier is detected 1: Carrier has been detected • Address 0AH – RX_ADDR_P0 Register This register is used to specify the data pipe 0 RX address. Byte Name 4 3 2 1 0 RX_ADDR_P0 [39:32] RX_ADDR_P0 [31:24] RX_ADDR_P0 [23:16] RX_ADDR_P0 [15:8] RX_ADDR_P0 [7:0] R/W R/W R/W R/W R/W R/W POR E7 E7 E7 E7 E7 Bit 39~0RX_ADDR_P0: Data pipe0 receive address This field is used to define the data pipe 0 receive address. The address field width can be up to 5 bytes which is specified in the SETUP_AW register. This address field configuration is carried out in a specific way from the least significant byte to the most significant byte. Rev. 1.10 174 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 0BH – RX_ADDR_P1 Register This register is used to specify the data pipe 1 RX address. Byte Name 4 3 2 1 0 RX_ADDR_P1 [39:32] RX_ADDR_P1 [31:24] RX_ADDR_P1 [23:16] RX_ADDR_P1 [15:8] RX_ADDR_P1 [7:0] R/W R/W R/W R/W R/W R/W POR C2 C2 C2 C2 C2 Bit 39~0RX_ADDR_P1: Data pipe1 receive address This field is used to define the data pipe 1 receive address. The address field width can be up to 5 bytes which is specified in the SETUP_AW register. This address field configuration is carried out in a specific way from the least significant byte to the most significant byte. • Address 0CH – RX_ADDR_P2 Register This register is used to specify the data pipe 2 RX address. Byte Name 4 3 2 1 0 RX_ADDR_P1 [39:32] RX_ADDR_P1 [31:24] RX_ADDR_P1 [23:16] RX_ADDR_P1 [15:8] RX_ADDR_P2 [7:0] R/W R/W R/W R/W R/W R/W POR C2 C2 C2 C2 C3 Bit 39~8 RX_ADDR_P1 [39:8]: Data pipe1 receive address bit 39 ~ bit 8 Bit 7~0 RX_ADDR_P2 [7:0]: Data pipe 2 receive address bit 7 ~ bit 0 This field is used to define the data pipe 2 receive address. Note that only bit 7~ bit 0 of the address field can be configured and other 32 MSBs from bit 39 to bit 8 must be the same as the data pipe 1 address. • Address 0DH – RX_ADDR_P3 Register This register is used to specify the data pipe 3 RX address. Byte Name Rev. 1.10 4 3 2 1 0 RX_ADDR_P1 [39:32] RX_ADDR_P1 [31:24] RX_ADDR_P1 [23:16] RX_ADDR_P1 [15:8] RX_ADDR_P3 [7:0] R/W R/W R/W R/W R/W R/W POR C2 C2 C2 C2 C4 Bit 39~8 RX_ADDR_P1 [39:8]: Data pipe1 receive address bit 39 ~ bit 8 Bit 7~0 RX_ADDR_P3 [7:0]: Data pipe 3 receive address bit 7 ~ bit 0 This field is used to define the data pipe 3 receive address. Note that only bit 7~ bit 0 of the address field can be configured and other 32 MSBs from bit 39 to bit 8 must be the same as the data pipe 1 address. 175 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 0EH – RX_ADDR_P4 Register This register is used to specify the data pipe 4 RX address. Byte Name 4 3 2 1 0 RX_ADDR_P1 [39:32] RX_ADDR_P1 [31:24] RX_ADDR_P1 [23:16] RX_ADDR_P1 [15:8] RX_ADDR_P4 [7:0] R/W R/W R/W R/W R/W R/W POR C2 C2 C2 C2 C5 Bit 39~8 RX_ADDR_P1 [39:8]: Data pipe1 receive address bit 39 ~ bit 8 Bit 7~0 RX_ADDR_P4 [7:0]: Data pipe 4 receive address bit 7 ~ bit 0 This field is used to define the data pipe 4 receive address. Note that only bit 7~ bit 0 of the address field can be configured and other 32 MSBs from bit 39 to bit 8 must be the same as the data pipe 1 address. • Address 0FH – RX_ADDR_P5 Register This register is used to specify the data pipe 5 RX address. Byte Name 4 3 2 1 0 RX_ADDR_P1 [39:32] RX_ADDR_P1 [31:24] RX_ADDR_P1 [23:16] RX_ADDR_P1 [15:8] RX_ADDR_P5 [7:0] R/W R/W R/W R/W R/W R/W POR C2 C2 C2 C2 C6 Bit 39~8 RX_ADDR_P1 [39:8]: Data pipe1 receive address bit 39 ~ bit 8 Bit 7~0 RX_ADDR_P5 [7:0]: Data pipe 5 receive address bit 7 ~ bit 0 This field is used to define the data pipe 5 receive address. Note that only bit 7~ bit 0 of the address field can be configured and other 32 MSBs from bit 39 to bit 8 must be the same as the data pipe 1 address. • Address 10H – TX_ADDR Register This register is used to specify the TX address. Byte 4 3 2 1 0 Name TX_ADDR [39:32] TX_ADDR [31:24] TX_ADDR [23:16] TX_ADDR [15:8] TX_ADDR [7:0] R/W R/W R/W R/W R/W R/W POR E7 E7 E7 E7 E7 Bit 39~0TX_ADDR: TX Transmit address This field is only used for the PTX device to define the TX transmit address. The address field can be up to 5 bytes which is specified in the SETUP_AW register. This address field configuration is carried out in a specific way from the least significant byte to the most significant byte. It is recommended to specify the same address for both RX_ADDR_P0 and TX_ADDR address field to properly handle the automatic acknowledgement function. Rev. 1.10 176 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 11H – RX_PW_P0 Register This register is used to specify the data pipe 0 RX payload byte number. Bit 7 6 Name — — 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 RX_PW_P05 RX_PW_P04 RX_PW_P03 RX_PW_P02 RX_PW_P01 RX_PW_P00 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5~0 RX_PW_P0 [5:0]: Data Pipe 0 RX payload byte number 0: not used 1: 1 byte 2: 2 bytes : 32: 32 bytes Others: Can not be used • Address 12H – RX_PW_P1 Register This register is used to specify the data pipe 1 RX payload byte number. Bit 7 6 5 4 3 2 Name — — R/W R/W R/W RX_PW_P15 RX_PW_P14 RX_PW_P13 RX_PW_P12 RX_PW_P11 RX_PW_P10 R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5~0 RX_PW_P1 [5:0]: Data Pipe 1 RX payload byte number 0: not used 1: 1 byte 2: 2 bytes : 32: 32 bytes Others: Can not be used • Address 13H – RX_PW_P2 Register This register is used to specify the data pipe 2 RX payload byte number. Bit Rev. 1.10 7 6 5 4 3 2 Name — — R/W R/W R/W RX_PW_P25 RX_PW_P24 RX_PW_P23 RX_PW_P22 RX_PW_P21 RX_PW_P20 R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5~0 RX_PW_P2 [5:0]: Data Pipe 2 RX payload byte number 0: not used 1: 1 byte 2: 2 bytes : 32: 32 bytes Others: Can not be used 177 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 14H – RX_PW_P3 Register This register is used to specify the data pipe 3 RX payload byte number. Bit 7 6 Name — — 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 RX_PW_P35 RX_PW_P34 RX_PW_P33 RX_PW_P32 RX_PW_P31 RX_PW_P30 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5~0 RX_PW_P3 [5:0]: Data Pipe 3 RX payload byte number 0: not used 1: 1 byte 2: 2 bytes : : 32: 32 bytes Others: Can not be used • Address 15H – RX_PW_P4 Register This register is used to specify the data pipe 4 RX payload byte number. Bit 7 6 Name — — 5 4 3 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 RX_PW_P45 RX_PW_P44 RX_PW_P43 RX_PW_P42 RX_PW_P41 RX_PW_P40 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5~0 RX_PW_P4 [5:0]: Data Pipe 4 RX payload byte number 0: not used 1: 1 byte 2: 2 bytes : : 32: 32 bytes Others: Can not be used • Address 16H – RX_PW_P5 Register This register is used to specify the data pipe 5 RX payload byte number. Rev. 1.10 Bit 7 6 Name — — 5 4 3 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 RX_PW_P55 RX_PW_P54 RX_PW_P53 RX_PW_P52 RX_PW_P51 RX_PW_P50 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5~0 RX_PW_P5 [5:0]: Data Pipe 5 RX payload byte number 0: not used 1: 1 byte 2: 2 bytes : : 32: 32 bytes Others: Can not be used 178 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 17H – FIFO_STATUS Register This register is used to indicate the FIFO status during the data transfer. Bit 7 Name — R/W R/W R R POR 0 0 0 Bit 7 6 5 4 3 2 — — R R/W R/W R R 0 0 0 0 0 TX_REUSE TX_FULL TX_EMPTY 1 0 RX_FULL RX_EMPTY Reserved bits, only data “0” allowed. Bit 6TX_REUSE: Last Transmitted Data Packet Reuse status 0: Last transmitted data packet is not reused 1: Last transmitted data packet is reused This bit is used to indicate whether the last TX data packet is repeatedly transmitted or not. If the CE line is kept in a high state, the last data packet will be repeatedly retransmitted. This bit is set to 1 by the SPI command, REUSE_TX_PL, and cleared to 0 by the SPI command, W_TX_PAYLOAD or FLUSH_TX. Bit 5TX_FULL: TX FIFO Full Flag 0: TX FIFO is not full 1: TX FIFO is full This bit is used to indicate whether the TX FIFO is full or not. Bit 4TX_EMPTY: TX FIFO Empty Flag 0: TX FIFO is not empty 1: TX FIFO is empty This bit is used to indicate whether the TX FIFO is empty or not. Bit 3~2 Reserved bits, only data “00” allowed. Bit 1RX_FULL: RX FIFO Full Flag 0: RX FIFO is not full 1: RX FIFO is full This bit is used to indicate whether the RX FIFO is full or not. Bit 0RX_EMPTY: RX FIFO Empty Flag 0: RX FIFO is not empty 1: RX FIFO is empty This bit is used to indicate whether the RX FIFO is empty or not. Rev. 1.10 179 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 1CH – DYNPD Register This register is used to control the individual data pipe dynamic payload length function. Bit 7 6 5 4 3 2 1 0 Name — — DPL_P5 DPL_P4 DPL_P3 DPL_P2 DPL_P1 DPL_P0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Reserved bits, only data “00” allowed. Bit 5DPL_P5: Data Pipe 5 Dynamic Payload Length function enable control 0: Disable 1: Enable This bit is used to control the data pipe5 dynamic payload length function. It is only available when the EN_DPL and ENAA_P5 bits are both set to 1. Bit 4DPL_P4: Data Pipe 4 Dynamic Payload Length function enable control 0: Disable 1: Enable This bit is used to control the data pipe4 dynamic payload length function. It is only available when the EN_DPL and ENAA_P4 bits are both set to 1. Bit 3DPL_P3: Data Pipe 3 Dynamic Payload Length function enable control 0: Disable 1: Enable This bit is used to control the data pipe3 dynamic payload length function. It is only available when the EN_DPL and ENAA_P3 bits are both set to 1. Bit 2DPL_P2: Data Pipe 2 Dynamic Payload Length function enable control 0: Disable 1: Enable This bit is used to control the data pipe2 dynamic payload length function. It is only available when the EN_DPL and ENAA_P2 bits are both set to 1. Bit 1DPL_P1: Data Pipe 1 Dynamic Payload Length function enable control 0: Disable 1: Enable This bit is used to control the data pipe1 dynamic payload length function. It is only available when the EN_DPL and ENAA_P1 bits are both set to 1. Bit 0DPL_P0: Data Pipe 0 Dynamic Payload Length function enable control 0: Disable 1: Enable This bit is used to control the data pipe0 dynamic payload length function. It is only available when the EN_DPL and ENAA_P0 bits are both set to 1. Rev. 1.10 180 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 1DH – FEATURE Register This register is used to control several main features of the RF transceiver. Bit 7 6 5 4 3 Name — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~3 2 1 0 EN_DPL EN_ACK_PAY EN_DNY_ACK Reserved bits, only data “00000” allowed. Bit 2EN_DPL: RF Transceiver Dynamic Payload Length Function control 0: Disable 1: Enable This bit is used to control the RF Transceiver dynamic payload length function. If the EN_DPL bit is set to 1 and the corresponding ENAA_Pn bit is also set to 1, the dynamic payload length function of the relevant data pipe n will be available. Bit 1EN_ACK_PAY: RF Transceiver Payload with Acknowledgement control 0: Disable 1: Enable Bit 0EN_DNY_ACK: RF Transceiver “W_TX_PAYLOAD_NOACK” Command control 0: Disable the command 1: Enable the command Register Bank 1 It is recommended that no access is executed on reserved or non defined registers. Otherwise, this may result in unpredictable conditions. • Address 00H – Optimisation Register 0 Bit 31 30 ………… Name 1 0 Optimisation_Value_0 R/W W POR 0x0000_0000H This register is used to optimise the performance of the RF Transceiver by writing a specific value of 0x858A_C0C1H into this register. • Address 01H – Optimisation Register 1 Bit 31 30 ………… Name 1 0 Optimisation_Value_1 R/W W POR 0x0000_0000H This register is used to optimise the performance of the RF Transceiver by writing a specific value of 0x1103_C960H into this register. • Address 02H – Optimisation Register 2 Bit 31 30 ………… Name Optimisation_Value_2 R/W W POR 0x0000_0000H 1 0 This register is used to optimise the performance of the RF Transceiver by writing a specific value of 0x0000_0004H into this register. Rev. 1.10 181 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 03H – Optimisation Register 3 Bit 31 30 ………… Name 1 0 Optimisation_Value_3 R/W W POR 0x0300_1200H This register is used to optimise the performance of the RF Transceiver by writing a specific value of 0x0000_0004H into this register. • Address 04H – Optimisation Register 4 Bit 31 30 ………… Name 1 0 Optimisation_Value_4 R/W W POR 0x0000_0000H This register is used to optimise the performance of the RF Transceiver by writing a specific value into this register for different operating modes. For 1Mbps and 2Mbps: 0x447C_063FH For 250kbps: 0x447C_463FH • Address 05H – Optimisation Register 5 Bit 31 30 ………… Name 1 0 Optimisation_Value_5 R/W W POR 0x0000_0000H This register is used to optimise the performance of the RF Transceiver by writing a specific value into this register for different data rates. For 250kbps data rate: 0x7F00_6C87H For 1Mbps data rate: 0x0700_6C87H For 2Mbps data rate: 0x3000_6C87H • Address 07H – Status Register 1 Bit 31 30 8 7 6 ……… 1 Name Reserved bits RBANK Reserved bits R/W W R W POR 0 0 0 0 This register is reserved except for bit 7, RBANK. It is recommended the reserved bits are not accessed to prevent unpredictable results. Bit 7RBANK: Register Bank Status 0: Register bank 0 1: Register bank 1 Rev. 1.10 182 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver • Address 08H – Chip ID Register Bit 31 30 ………… Name 1 0 1 0 ID_Value R/W R POR 0x0000_0000H This register is a read-only register and is used to store the chip ID code. • Address 0CH – Initialization Register Bit 31 30 ………… Name Initialisation_Value R/W W POR 0x0000_0000H This register is used to initialise the RF Transceiver PLL Lock time by writing a specific value of 0x0573_1200H into this register. • Address 0DH – New_Feature Register Bit 31 30 ………… Name 1 0 New_Feature_Value R/W W POR 0x0000_0000H This register is used to configure the RF Transceiver features by writing a specific value of 0x0080_ B44EH into this register. • Address 0EH – RAMP Register Bit 87 86 ………… Name 1 0 RAMP_Value R/W W POR 0xuu_uuuu_ uuuu_uuuu_ uuuu_uuuuH This register is used to optimise the RF Transmitter output spectrum rate curve by writing a specific value of 0xCF_FFBD_F3CF_2080_8204_1041H into this register. Rev. 1.10 183 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Options 1 High Speed System Oscillator Selection – fH: HIRC or HXT Crystal Mode Frequency Options 2 HIRC Clock Frequency Selection – fHIRC: 12MHz or 6MHz I/O or VDDIO pin Option 3 I/O or VDDIO Pin Selection - VDDIO or I/O Application Circuit 33pF VBUS 16MHz 4.7pF 8.2nH 33pF 1M 100K 300R N.C VBUS 0.1uF N.C 2pF 3.9nH 1.2pF N.C N.C 1 2 3 4 5 6 7 8 9 3.3V 10R 10R 10R 33nF BC68FB540 10 11 12 13 14 15 16 17 18 19 20 21 22 23 100nF 100nF 100nF VDDPA RFP1 RFN1 NC VDD3RXRF VDD3IF VDD3B CDVDD NC 0R 0R Rev. 1.10 0.1uF 0.1uF 3.3V NC NC NC VSS HVDD VDD V33O UDP/GPIO1 UDN/GPIO0 32 31 30 29 28 27 26 25 24 0.1uF 33R 33R 33pF 33pF VBUS 0.1uF 10uF 1M 470pF VBUS DD+ VSS S-Case 3.9nH VSSRX2 RFSCK CE NC NC NC NC PA6/TCK0/SCKA PA7/INT0/*SCSA/CSN NC IRQ PA5/SDIA/TP1_0/MISO PA4/SDOA/TP0_0/MOSI PA3/TCK2 0R NC NC XTALN XTALP NC PA1/TP2_1/OSC1 NC NC NC PE0/VDDIO PA0/TCK1/OCDSDA PA2/TP3_1/OSC2 *RES/OCDSCK NC 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ANTENNA 10R 4.7R USB_CON 184 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.10 185 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.10 186 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.10 187 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 188 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.10 189 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.10 190 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.10 191 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.10 192 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.10 193 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.10 194 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.10 195 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.10 196 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.10 197 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.10 198 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver SAW type 46-pin (6.5mm×4.5mm) QFN Outline Dimensions Symbol Nom. A 0.031 0.033 0.035 A1 0.000 0.001 0.002 A3 — 0.008 BSC — b 0.006 0.008 0.010 D 0.254 0.256 0.258 E 0.175 0.177 0.179 e — 0.016 BSC — D2 0.197 0.201 0.205 E2 0.118 0.122 0.126 L 0.012 0.016 0.020 Symbol Rev. 1.10 Dimensions in inch Min. Max. Dimensions in mm Min. Nom. Max. A 0.80 0.85 0.90 0.04 A1 0.00 0.02 A3 — 0.20 BSC — b 0.15 0.20 0.25 D 6.45 6.50 6.55 E 4.45 4.50 4.55 e — 0.40 BSC — D2 5.00 5.10 5.20 E2 3.00 3.10 3.20 L 0.30 0.40 0.50 199 December 22, 2014 BC68FB540 I/O Flash USB 8-Bit MCU with 2.4GHz RF Transceiver Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 200 December 22, 2014