Data Sheet

74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
Rev. 1 — 7 November 2013
Product data sheet
1. General description
The 74HC2G00-Q100; 74HCT2G00-Q100 is a dual 2-input NAND gate. Inputs include
clamp diodes that enable the use of current limiting resistors to interface inputs to voltages
in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 2.0 V to 6.0 V
 Input levels:
 For 74HC2G00-Q100: CMOS level
 For 74HCT2G00-Q100: TTL level
 Symmetrical output impedance
 High noise immunity
 Low power dissipation
 Balanced propagation delays
 Multiple package options
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Ordering information
Table 1.
Ordering information
Type number
74HC2G00DP-Q100
Package
Temperature range
Name
Description
Version
40 C to +125 C
TSSOP8
plastic thin shrink small outline package;
8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
40 C to +125 C
VSSOP8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
74HCT2G00DP-Q100
74HC2G00DC-Q100
74HCT2G00DC-Q100
NXP Semiconductors
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
4. Marking
Table 2.
Marking code
Type number
Marking code[1]
74HC2G00DP-Q100
H00
74HCT2G00DP-Q100
T00
74HC2G00DC-Q100
H00
74HCT2G00DC-Q100
T00
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1
1A
2
1B
5
2A
6
2B
&
1Y
7
2Y
3
B
5
&
3
Y
6
mna712
Fig 1.
7
2
Logic symbol
A
mna713
Fig 2.
IEC logic symbol
Fig 3.
mna099
Logic diagram (one driver)
6. Pinning information
6.1 Pinning
+&*4
+&7*4
$ 9&&
% <
< %
*1' $
DDD
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1A, 2A
1, 5
data input
1B, 2B
2, 6
data input
GND
4
ground (0 V)
1Y, 2Y
7, 3
data output
VCC
8
supply voltage
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
7. Functional description
Table 4.
Function table[1]
Input
Output
nA
nB
L
L
H
L
H
H
H
L
H
H
H
L
[1]
nY
H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Min
Max
Unit
0.5
+7.0
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
-
20
mA
VO < 0.5 V or VO > VCC + 0.5 V
[1]
output clamping current
-
20
mA
VO = 0.5 V to (VCC + 0.5 V)
[1]
IO
output current
ICC
-
25
mA
supply current
[1]
-
50
mA
IGND
ground current
[1]
50
-
mA
Tstg
storage temperature
65
+150
C
-
300
mW
74HCT2G00-Q100
Unit
IOK
dynamic power dissipation
PD
[1]
[2]
Conditions
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC2G00-Q100
Min
Typ
Max
Min
Typ
Max
2.0
5.0
6.0
4.5
5.0
5.5
V
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
C
t/V
input transition rise
and fall rate
VCC
supply voltage
VI
74HC_HCT2G00_Q100
Product data sheet
40
+25
+125
40
+25
+125
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 13
NXP Semiconductors
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C.
Symbol
Parameter
40 C to +85 C
Conditions
40 C to +125 C
Unit
Min
Typ
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
V
74HC2G00-Q100
VIH
VIL
VOH
VOL
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
voltage
LOW-level output
voltage
VCC = 6.0 V
4.2
3.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
4.13
4.32
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.63
5.81
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.33
-
0.4
V
VI = VIH or VIL
VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
-
1.0
A
ICC
supply current
per input pin; VI = VCC or GND;
IO = 0 A; VCC = 6.0 V
-
-
10
-
20
A
CI
input capacitance
-
1.5
-
-
-
pF
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
4 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C.
Symbol
Parameter
40 C to +85 C
Conditions
40 C to +125 C
Min
Typ
Max
Min
Max
Unit
74HCT2G00-Q100
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
V
VIL
LOW-level input
voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
V
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
V
IO = 4.0 mA; VCC = 4.5 V
4.13
4.32
-
3.7
-
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.33
-
0.4
V
VOL
LOW-level output
voltage
VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
10
-
20
A
ICC
additional supply
current
per input; VCC = 4.5 V to 5.5 V;
VI = VCC  2.1 V; IO = 0 A
-
-
375
-
410
A
CI
input capacitance
-
1.5
-
-
-
pF
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 C; for test circuit, see Figure 6.
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Min
Max
VCC = 2.0 V
-
25
95
-
110
ns
VCC = 4.5 V
-
9
19
-
22
ns
-
7
16
-
20
ns
VCC = 2.0 V
-
18
95
-
125
ns
VCC = 4.5 V
-
6
19
-
25
ns
-
5
16
-
20
ns
-
10
-
-
-
pF
74HC2G00-Q100
tpd
propagation delay nA and nB to nY; see Figure 5
[1]
VCC = 6.0 V
tt
transition time
see Figure 5
[2]
VCC = 6.0 V
CPD
power dissipation VI = GND to VCC
capacitance
74HC_HCT2G00_Q100
Product data sheet
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
5 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 C; for test circuit, see Figure 6.
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Min
Max
74HCT2G00-Q100
propagation delay nA and nB to nY; see Figure 5
tpd
[1]
VCC = 4.5 V
tt
transition time
VCC = 4.5 V; see Figure 5
CPD
power dissipation VI = GND to VCC  1.5 V
capacitance
[1]
tpd is the same as tPLH and tPHL.
[2]
tt is the same as tTLH and tTHL.
[3]
-
12
24
-
29
ns
[2]
-
6
19
-
22
ns
[3]
-
10
-
-
-
pF
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
12. Waveforms
VI
VM
nA, nB input
VM
GND
tPHL
tPLH
VOH
90%
VM
nY output
VM
10%
VOL
tTHL
tTLH
001aae759
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Table 9.
Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY)
Measurement points
Type
Input
Output
VM
VM
74HC2G00-Q100
0.5  VCC
0.5  VCC
74HCT2G00-Q100
1.3 V
1.3 V
74HC_HCT2G00_Q100
Product data sheet
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Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
VI
tW
90 %
negative
pulse
VM
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
VI
G
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 6.
Table 10.
Test circuit for measuring switching times
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
VCC
 6 ns
50 pF
1 k
open
74HCT2G00-Q100 3 V
 6 ns
50 pF
1 k
open
74HC2G00-Q100
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
7 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
Fig 7.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Package outline SOT505-2 (TSSOP8)
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
Fig 8.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Package outline SOT765-1 (VSSOP8)
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
9 of 13
74HC2G00-Q100; 74HCT2G00-Q100
NXP Semiconductors
Dual 2-input NAND gate
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT2G00_Q100 v.1
20131107
Product data sheet
-
-
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
10 of 13
NXP Semiconductors
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT2G00_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
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representation or warranty that such applications will be suitable for the
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Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
11 of 13
NXP Semiconductors
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2013
© NXP B.V. 2013. All rights reserved.
12 of 13
NXP Semiconductors
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 November 2013
Document identifier: 74HC_HCT2G00_Q100