HT32F52342-52_Datasheetv100.pdf

HT32F52342/HT32F52352
Datasheet
32-Bit ARM® Cortex™-M0+ Microcontroller,
up to 128 KB Flash and 16 KB SRAM with 1 MSPS ADC,
USART, UART, SPI, I2C, I2S, MCTM, GPTM, BFTM,
SCI, CRC, RTC, WDT, PDMA, EBI and USB2.0 FS
Revision: V1.00
Date: January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller – FMC............................................................................................. 7
Reset Control Unit – RSTCU.................................................................................................. 8
Clock Control Unit – CKCU..................................................................................................... 8
Power Management – PWRCU.............................................................................................. 8
External Interrupt/Event Controller – EXTI............................................................................. 9
Analog to Digital Converter – ADC......................................................................................... 9
Analog Comparator – CMP..................................................................................................... 9
I/O Ports – GPIO................................................................................................................... 10
Motor Control Timer – MCTM............................................................................................... 10
PWM Generation and Capture Timers – GPTM................................................................... 11
Single Channel Generation and Capture Timers – SCTM.................................................... 11
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer – WDT........................................................................................................ 12
Real Time Clock – RTC........................................................................................................ 12
Inter-integrated Circuit – I2C................................................................................................. 12
Serial Peripheral Interface – SPI.......................................................................................... 13
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 13
Universal Asynchronous Receiver Transmitter – UART....................................................... 14
Smart Card Interface – SCI.................................................................................................. 14
Inter-IC Sound – I2S.............................................................................................................. 15
Cyclic Redundancy Check – CRC........................................................................................ 15
Peripheral Direct Memory Access – PDMA.......................................................................... 16
External Bus Interface – EBI................................................................................................. 16
Universal Serial Bus Device Controller – USB..................................................................... 17
Debug Support...................................................................................................................... 17
Package and Operation Temperature................................................................................... 17
3 Overview................................................................................................................. 18
Device Information................................................................................................................ 18
Block Diagram...................................................................................................................... 19
Memory Map......................................................................................................................... 20
Clock Structure..................................................................................................................... 23
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Table of Contents
On-chip Memory..................................................................................................................... 7
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
4 Pin Assignment...................................................................................................... 24
5 Electrical Characteristics...................................................................................... 30
Absolute Maximum Ratings.................................................................................................. 30
Recommended DC Operating Conditions............................................................................ 30
On-Chip LDO Voltage Regulator Characteristics.................................................................. 30
Reset and Supply Monitor Characteristics............................................................................ 32
External Clock Characteristics.............................................................................................. 33
Internal Clock Characteristics............................................................................................... 34
PLL Characteristics............................................................................................................... 35
Memory Characteristics........................................................................................................ 35
I/O Port Characteristics......................................................................................................... 35
ADC Characteristics............................................................................................................. 37
Comparator Characteristics.................................................................................................. 39
SCTM/GPTM/MCTM Characteristics.................................................................................... 39
I2C Characteristics................................................................................................................ 40
SPI Characteristics............................................................................................................... 41
I2S Characteristics................................................................................................................ 42
USB Characteristics.............................................................................................................. 44
6 Package Information............................................................................................. 45
48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 46
64-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 47
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Table of Contents
Power Consumption............................................................................................................. 31
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
List of Tables
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List of Tables
Table 1 HT32F52342/52352 Series Features and Peripheral List............................................................ 18
Table 2 HT32F52342/52352 Register Map............................................................................................... 21
Table 3 HT32F52342/52352 Series Pin Assignment for LQFP 64 / 48 Package...................................... 26
Table 4 HT32F52342/52352 Pin Description............................................................................................ 28
Table 5 Absolute Maximum Ratings.......................................................................................................... 30
Table 6 Recommended DC Operating Conditions.................................................................................... 30
Table 7 LDO Characteristics..................................................................................................................... 30
Table 8 Power Consumption Characteristics............................................................................................ 31
Table 9 VDD Power Reset Characteristics................................................................................................. 32
Table 10 LVD/BOD Characteristics........................................................................................................... 32
Table 11 High Speed External Clock (HSE) Characteristics..................................................................... 33
Table 12 Low Speed External Clock (LSE) Characteristics...................................................................... 33
Table 13 High Speed Internal Clock (HSI) Characteristics....................................................................... 34
Table 14 Low Speed Internal Clock (LSI) Characteristics......................................................................... 34
Table 15 PLL Characteristics.................................................................................................................... 35
Table 16 Flash Memory Characteristics.................................................................................................... 35
Table 17 I/O Port Characteristics.............................................................................................................. 35
Table 18 ADC Characteristics................................................................................................................... 37
Table 19 Comparator Characteristics....................................................................................................... 39
Table 20 SCTM/GPTM/MCTM Characteristics......................................................................................... 39
Table 21 I2C Characteristics...................................................................................................................... 40
Table 22 SPI Characteristics..................................................................................................................... 41
Table 23 I2S Characteristics...................................................................................................................... 42
Table 24 USB DC Electrical Characteristics............................................................................................. 44
Table 25 USB AC Electrical Characteristics.............................................................................................. 44
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
List of Figures
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List of Figures
Figure 1 HT32F52342/52352 Block Diagram........................................................................................... 19
Figure 2 HT32F52342/52352 Memory Map.............................................................................................. 20
Figure 3 HT32F52342/52352 Clock Structure.......................................................................................... 23
Figure 4 HT32F52342/52352 LQFP-48 Pin Assignment.......................................................................... 24
Figure 5 HT32F52342/52352 LQFP-64 Pin Assignment.......................................................................... 25
Figure 6 ADC Sampling Network Model................................................................................................... 38
Figure 7 I2C Timing Diagrams................................................................................................................... 40
Figure 8 SPI Timing Diagrams – SPI Master Mode.................................................................................. 41
Figure 9 SPI Timing Diagrams - SPI Slave Mode with CPHA=1.............................................................. 42
Figure 10 Timing of I2S Master Mode....................................................................................................... 43
Figure 11 Timing of I2S Slave Mode.......................................................................................................... 43
Figure 12 USB Signal Rise Time and Fall Time and Cross-Point Voltage (VCRS) Definition.................. 44
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
1
General Description
The HOLTEK HT32F52342/52352 devices are high performance, low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M0+ processor core. The Cortex™-M0+ is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and including advanced debug support.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.
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General Description
The devices operate at a frequency of up to 48 MHz with a Flash accelerator to obtain maximum
efficiency. It provides up to 128 KB of embedded Flash memory for code/data storage and 16 KB
of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as ADC, I2C, USART, UART, SPI, I2S, GPTM, MCTM, SCI, CRC-16/32, RTC,
WDT, PDMA, EBI, USB2.0 FS, SW-DP (Serial Wire Debug Port), etc., are also implemented in
the device series. Several power saving modes provide the flexibility for maximum optimisation
between wakeup latency and power consumption, an especially important consideration in low
power applications.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
2
Features
Core
■■ 32-bit ARM® Cortex™-M0+ processor core
■■ Up to 48 MHz operating frequency
Features
■■ 0.93 DMIPS/MHz (Dhrystone v2.1)
■■ Single-cycle multiplication
■■ Integrated Nested Vectored Interrupt Controller (NVIC)
■■ 24-bit SysTick timer
The Cortex™-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
On-chip Memory
■■ Up to 128 KB on-chip Flash memory for instruction/data and options storage
■■ 16 KB on-chip SRAM
■■ Supports multiple boot modes
The ARM® Cortex™-M0+ processor accesses and debug accesses share the single external
interface to external AHB peripherals. The processor accesses take priority over debug accesses.
The maximum address range of the Cortex™-M0+ is 4 GB since it has a 32-bit bus address
width. Additionally, a pre-defined memory map is provided by the Cortex™-M0+ processor to
reduce the software complexity of repeated implementation by different device vendors. However,
some regions are used by the ARM® Cortex™-M0+ system peripherals. Refer to the ARM®
Cortex™-M0+ Technical Reference Manual for more information. Figure 2 shows the memory
map of the HT32F52342/52352 series of devices, including code, SRAM, peripheral, and other predefined regions.
Flash Memory Controller – FMC
■■ Flash accelerator for maximum efficiency
■■ 32-Bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
■■ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
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32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Reset Control Unit – RSTCU
■■ Supply supervisor:
●● Power On Reset / Power Down Reset – POR/PDR
●● Brown-out Detector – BOD
●● Programmable Low Voltage Detector – LVD
Clock Control Unit – CKCU
■■ External 4 to 16 MHz crystal oscillator
■■ External 32,768 Hz crystal oscillator
■■ Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3V operating voltage and 25°C operating
temperature
■■ Internal 32 kHz RC oscillator
■■ Integrated system clock PLL
■■ Independent clock divider and gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers, APB clock divider and
gating circuitry. The AHB, APB and CortexTM-M0+ clocks are derived from the system clock (CK_
SYS) which can come from the LSI, LSE, HSI, HSE or PLL. The Watchdog Timer and Real Time
Clock (RTC) use either the LSI or LSE as their clock source.
Power Management – PWRCU
■■ Single VDD power supply : 2.0 V to 3.6 V
■■ Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply
■■ VBAT battery power supply for RTC and backup registers
■■ Three power domains: VDD, 1.5 V and Backup
■■ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
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Features
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
External Interrupt/Event Controller – EXTI
■■ Up to 16 EXTI lines with configurable trigger source and type
■■ All GPIO pins can be selected as EXTI trigger source
■■ Source trigger type includes high level, low level, negative edge, positive edge, or both edge
■■ Individual interrupt enable, wakeup enable and status bits for each EXTI line
■■ Integrated deglitch filter for short pulse blocking
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. Each EXTI line can also be masked
independently.
Analog to Digital Converter – ADC
■■ 12-bit SAR ADC engine
■■ Up to 1 Msps conversion rate
■■ Up to 12 external analog input channels
A 12-bit multi-channel ADC is integrated in the device. There are multiplexed channels, which
include 12 external analog signal channels and 2 internal channels which can be measured. If
the input voltage is required to remain within a specific threshold window, an Analog Watchdog
function will monitor and detect these signals. An interrupt will then be generated to inform the
device that the input voltage is not within the preset threshold levels. There are three conversion
modes to convert an analog signal to digital data. The ADC can be operated in one shot, continuous
and discontinuous conversion modes.
Analog Comparator – CMP
■■ Rail-to-rail comparator
■■ Each comparator has configurable negative inputs used for flexible voltage selection
■■ Dedicated I/O pin or internal voltage reference provided by 6-bit scaler
■■ Programmable hysteresis
■■ Programming speed and consumption
■■ Comparator output can be output to I/O or to timers or ADC trigger inputs
■■ 6-bit scaler can be configurable to dedicated I/O for voltage reference
■■ Comparator has interrupt generation capability with wakeup from Sleep or Deep Sleep modes
through the EXTI controller
The two general purpose comparators (CMP) are implemented within the device. They can be
configured either as standalone comparators or combined with the different kinds of peripheral IPs.
Each comparator is capable of asserting interrupts to the NVIC or waking up the MCU from sleep
or deep sleep mode through the EXTI wakeup event management unit.
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Features
■■ Software interrupt trigger mode for each EXTI line
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
I/O Ports – GPIO
■■ Up to 51 GPIOs
■■ Port A, B, C, D are mapped as 16 external interrupts - EXTI
■■ Almost all I/O pins have a configurable output driving current.
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins. The external
interrupts on the GPIO pins of the device have related control and configuration registers in the
External Interrupt Control Unit, EXTI.
Motor Control Timer – MCTM
■■ One 16-bit up, down, up/down auto-reload counter
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Complementary Outputs with programmable dead-time insertion
■■ Supports 3-phase motor control and hall sensor interface
■■ Brake input to force the timer’s output signals into a reset or fixed condition
The Motor Control Timer consists of a single 16-bit up/down counter, four 16-bit CCRs (Capture/
Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit repetition counter
and several control/status registers. It can be used for a variety of purposes including measuring
the pulse widths of input signals or generating output waveforms such as compare match outputs,
PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM is capable of
offering full functional support for motor control, hall sensor interfacing and brake input.
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Features
There are up to 51 General Purpose I/O pins, GPIO, named from PA0~PA15 to PD0~PD3 for the
implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximise flexibility and to meet the requirements of a wide
range of applications.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
PWM Generation and Capture Timers – GPTM
■■ One 16-bit up, down, up/down auto-reload counter
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Encoder interface controller with two inputs using quadrature decoder
The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare
Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.
They can be used for a variety of purposes including general time measurement, input signal pulse
width measurement, output waveform generation such as single pulse generation, or PWM output
generation. The GPTM supports an Encoder Interface using a decoder with two inputs.
Single Channel Generation and Capture Timers – SCTM
■■ One 16-bit up and auto-reload counter
■■ One channel for each timer
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned
■■ Single Pulse Mode Output
The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register
(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be
used for a variety of purposes including general timer, input signal pulse width measurement or
output waveform generation such as single pulse generation or PWM output.
Basic Function Timer – BFTM
■■ One 32-Bit compare/match count-up counter – no I/O control features
■■ One shot mode – counting stops after a match condition
■■ Repetitive mode – restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
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Features
■■ Compare Match Output
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Watchdog Timer – WDT
■■ 12-Bit down counter with 3-bit prescaler
■■ Reset event for the system
■■ Programmable watchdog timer window function
■■ Register write protection function
Real Time Clock – RTC
■■ 32-Bit up-counter with a programmable prescaler
■■ Alarm function
■■ Interrupt and Wake-up event
The Real Time Clock, RTC, includes an APB interface, a 32-bit count-up counter, a control
register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in
the Backup Domain except for the APB interface. The APB interface is located in the V DD15 power
domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the power
control unit when the V DD15 power domain is powered off, that is when the device enters the PowerDown mode. The RTC counter is used as a wakeup timer to generate a system resume signal from
the Power-Down mode.
Inter-integrated Circuit – I2C
■■ Supports both master and slave modes with a frequency of up to 1 MHz
■■ Provide an arbitration function and clock synchronisation
■■ Supports 7-bit and 10-bit addressing modes and general call addressing
■■ Supports slave multi-addressing mode with maskable address
The I2C is an internal circuit allowing communication with an external I2C interface which is an
industry standard two line serial interface used for connection to external hardware. These two
serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I 2C module
provides three data transfer rates: 1. 100 kHz in the Standard mode, 2. 400 kHz in the Fast mode
and 3. 1 MHz in the Fast plus mode. The SCL period generation register is used to setup different
kinds of duty cycle implementations for the SCL pulse.
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I 2C also has an
arbitration detect function and clock synchronisation to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
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Features
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due
to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value
register, WDT operation control circuitry and a WDT protection mechanism. If the software does
not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated
when the counter underflows. In addition, a reset is also generated if the software reloads the
counter when the counter value is greater than the WDT delta value. This means the counter must
be reloaded within a limited timing window using a specific method. The Watchdog Timer counter
can be stopped while the processor is in the debug mode. There is a register write protect function
which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Serial Peripheral Interface – SPI
■■ Supports both master and slave mode
■■ Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode
■■ FIFO Depth: 8 levels
■■ Multi-master and multi-slave operation
Universal Synchronous Asynchronous Receiver Transmitter – USART
■■ Supports both asynchronous and clocked synchronous serial communication modes
■■ Asynchronous operating baud rate up to (fPCLK/16) MHz and synchronous operating rate up to
(fPCLK/8) MHz
■■ Full duplex communication
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
■■ Auto hardware flow control mode – RTS, CTS
■■ IrDA SIR encoder and decoder
■■ RS485 mode with output enable control
■■ FIFO Depth: 8 x 9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full
duplex data exchange using synchronous or asynchronous data transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver
FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status
Register, LSR. The status includes the type and the condition of transfer operations as well as
several error conditions resulting from Parity, Overrun, Framing and Break events.
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Features
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines, MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Universal Asynchronous Receiver Transmitter – UART
■■ Asynchronous serial communication operating baud-rate up to (fPCLK/16) MHz
■■ Full duplex communication
Features
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports Line Status Interrupt. The software can detect a UART error status by reading
the Line Status Register, LSR. The status includes the type and the condition of transfer operations
as well as several error conditions resulting from Parity, Overrun, Framing and Break events.
Smart Card Interface – SCI
■■ Supports ISO 7816-3 standard
■■ Character mode
■■ Single transmit buffer and single receive buffer
■■ 11-bit ETU (elementary time unit) counter
■■ 9-bit guard time counter
■■ 24-bit general purpose waiting time counter
■■ Parity generation and checking
■■ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.
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32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Inter-IC Sound – I2S
■■ Master or slave mode
■■ Mono and stereo
■■ I2S-justified, Left-justified and Right-justified mode
■■ 8/16/24/32-bit sample size with 32-bit channel extended
■■ 8-bit Fractional Clock Divider with rate control
The I 2S is a synchronous communication interface that can be used as a master or slave to
exchange data with other audio peripherals, such as ADCs or DACs. The I2S supports a variety of
data formats. In addition to the stereo I2S-justified, Left-justified and Right-justified modes, there
are mono PCM modes with 8/16/24/32-bit sample size. When the I2S operates in the master mode,
then when using the fractional divider, it can provide an accurate sampling frequency output and
support the rate control function and fine-tuning of the output frequency to avoid system problems
caused by the cumulative frequency error between different devices.
Cyclic Redundancy Check – CRC
■■ Support CRC16 polynomial: 0x8005,
X16+X15+X2+1
■■ Support CCITT CRC16 polynomial: 0x1021,
X16+X12+X5+1
■■ Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7,
X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1
■■ Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
■■ Supports byte, half-word & word data size
■■ Programmable CRC initial seed value
■■ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32bit data
■■ Supports PDMA to complete a CRC computation of a block of memory
The CRC calculation unit is an error detection technique test algorithm which is used to verify data
transmission or storage data correctness. A CRC calculation takes a data stream or a block of data
as its input and generates a 16- or 32-bit output remainder. Ordinarily, a data stream is suffixed by
a CRC code and used as a checksum when being sent or stored. Therefore, the received or restored
data stream is calculated by the same generator polynomial as described above. If the new CRC
code result does not match the one calculated earlier, then this means that the data stream contains
a data error.
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January 25, 2016
Features
■■ 8 x 32-bit Tx & Rx FIFO with PDMA supported
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Peripheral Direct Memory Access – PDMA
■■ 6 channels with trigger source grouping
■■ 8-/16-/32-bit width data transfer
■■ Supports Address increment, decrement or fixed mode
■■ 4-level programmable channel priority
■■ Supports trigger source: ADC, SPI, USART, UART, I2C, I2S, GPTM, MCTM, SCI and software
request
The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals
and the system memory on the AHB bus. Each PDMA channel has a source address, destination
address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid
interrupt service routine execution. It improves system performance as the software does not need
to connect each data movement operation.
External Bus Interface – EBI
■■ Programmable interface for various memory types
■■ Translate the AHB transactions into the appropriate external device protocol
■■ Individual chip select signal for per memory bank
■■ Programmable timing to support a wide range of devices
■■ Automatic translation when AHB transaction width and external memory interface width is
different
■■ Write buffer to decrease the stalling of the AHB write burst transaction
■■ Multiplexed and non-multiplexed address and data line configurations
●● Up to 21 address lines
●● Up to 16-bit data bus width
The external bus interface is able to access external parallel interface devices such as SRAM, Flash
and LCD modules. The interface is memory mapped into the CPU internal address map. The data
and address lines are multiplexed in order to reduce the number of pins required to connect to the
external devices. The read/write timing of the bus can be adjusted to meet the timing specification
of the external devices. Note the interface only supports asynchronous 8 or 16-bit bus interface.
Rev. 1.00
16 of 48
January 25, 2016
Features
■■ Auto reload mode
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Universal Serial Bus Device Controller – USB
■■ Complies with USB 2.0 full-speed (12 Mbps) specification
■■ On-chip USB full-speed transceiver
■■ 1 control endpoint (EP0) for control transfer
■■ 3 single-buffered endpoints for bulk and interrupt transfer
■■ 1,024 bytes EP-SRAM used as the endpoint data buffers
The USB device controller is compliant with the USB 2.0 full-speed specification. There is one
control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM
is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding
registers, which provides maximum flexibility for various applications. The integrated USB fullspeed transceiver helps to minimise the overall system complexity and cost. The USB functional
block also contains the resume and suspend feature to meet the requirements of low-power
consumption.
Debug Support
■■ Serial Wire Debug Port – SW-DP
■■ 4 comparators for hardware breakpoint or code / literal patch
■■ 2 comparators for hardware watchpoints
Package and Operation Temperature
■■ 48/64-pin LQFP package
■■ Operation temperature range: -40°C to +85°C
Rev. 1.00
17 of 48
January 25, 2016
Features
■■ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
3
Overview
Device Information
Table 1 HT32F52342/52352 Series Features and Peripheral List
Peripherals
Option Bytes Flash (KB)
SRAM (KB)
Timers
Communication
HT32F52352
127.5
0.5
0.5
8
16
MCTM
1
GPTM
2
SCTM
2
BFTM
2
RTC
1
WDT
1
USB
1
SPI
2
USART
2
UART
2
I 2C
2
IS
1
SCI (ISO7816-3)
2
2
EBI
1
CRC-16/32
1
GPIO
Up to 51
EXTI
16
12-bit ADC
Number of channels
1
12 Channels
Comparator
2
CPU frequency
Up to 48 MHz
Operating voltage
Rev. 1.00
HT32F52342
64
2.0 V ~ 3.6 V
Operating temperature
-40° C ~ +85° C
Package
48/64-pin LQFP
18 of 48
January 25, 2016
Overview
Main Flash (KB)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Block Diagram
PA ~ PC[15:0], PD[3:0]
SWCLK SWDIO
BOOT
AF
AF
Powered by VDD15
PDMA
PDMA
SRAM
Controller
SRAM
CLDO
LDO
CAP.
1.5 V
BOD
LVD
Powered by VDD
USB
Device
PLL
fMax: 48 MHz
AF
AF
I2S
I2C0 ~ 1
AFIO
GPTM0 ~ 1
AF
AF
SPI1
SPI1~~00
AF
AF
SCTM0 ~ 1
SCI0
SCI0~~11
AF
AF
...
Analog
CMP
CMP
AF
ADC
RTCOUT
VBAT
VBAK
PWRCU
VDD33
VSS33
VBAK
Powered by VDD15
LSI
32 kHz
LSE
AF
PORB
BREG
Powered by VDDA
CLK, DIO,
DET
PWRSW
12-bit
SAR ADC
VDDA
VSSA
CH3 ~ CH0
Power control
MCTM
APB
AF
ADC_IN11
CN0, CP0
COUT0
CN1, CP1
COUT1
SDA
SCL
UART0
UART0~ 1
RTC
ADC_IN0
MOSI, MISO
SCK, SEL
WDT
BFTM0 ~ 1
AD0~AD15
A0~A20
CS0~CS3
OE, WR, ALE
DP
DM
USART0 ~ 1
EXTI
SCTM
USB
Control/Data
Registers
AF
DMA request
AHB to APB
Bridge
MCLK, BCLK
WS, SDO, SDI
CH0 ~CH2
CH0N ~ CH2N
CH3, BRK
8 MHz
External Bus
Interafce
6 Channels
XTALIN
XTALOUT
HSI
CKCU/RSTCU
Control Registers
AF
TX, RX
AHB
Peripherals
CRC
-16/32
AF
TX, RX
RTS/TXE
CTS/SCK
Control
Registers
HSE
4 ~ 16 MHz
Clock and reset control
Interrupt request
Bus Matrix
System
NVIC
FMC
Control
Registers
VSS
WAKEUP
32,768 Hz
nRST
Backup Domain
AF
X32KIN
X32KOUT
Power supply:
Bus:
Control signal:
Alternate function:
AF
Figure 1 HT32F52342/52352 Block Diagram
Rev. 1.00
19 of 48
January 25, 2016
Overview
IO Port
CortexTM-M0+
Processor
GPIO
Flash
Memory
AF
Flash Memory
Interface
SW-DP
VDD
POR
/PDR
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Memory Map
0x400F_FFFF
0xFFFF_FFFF
0xE010_0000
0xE000_0000
0x7000_0000
Private peripheral bus
Reserved
EBI Selection Bank
64 MB x 4
0x6000_0000
Reserved
0x4010_0000
Peripheral
0x4008_0000
0x4000_0000
AHB peripherals
512 KB
APB peripherals
512 KB
Reserved
SRAM
0x2000_4000
16 KB on-chip SRAM
16 KB
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_1000
Code
0x1F00_0000
0x0001_0000
Reserved
Option byte alias
1 KB
Reserved
Boot loader
4 KB
Reserved
Up to
128 KB on-chip Flash
Up to
128 KB
0x0000_0000
Reserved
GPIO A ～ D
Reserved
USB SRAM
USB
Reserved
EBI
Reserved
PDMA
Reserved
CRC
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM1
BFTM0
Reserved
SCTM1
Reserved
GPTM1
GPTM0
Reserved
RTC & PWRCU
Reserved
WDT
Reserved
CMP
Reserved
I2C1
I2C0
Reserved
SPI1
SCI0
Reserved
UART1
USART1
Reserved
SCI1
Reserved
SCTM0
Reserved
MCTM
Reserved
I2S
Reserved
EXTI
Reserved
AFIO
Reserved
ADC
Reserved
SPI0
Reserved
UART0
USART0
AHB
APB
Figure 2 HT32F52342/52352 Memory Map
Rev. 1.00
20 of 48
January 25, 2016
Overview
Reserved
0x400B_8000
0x400B_0000
0x400A_C000
0x400A_A000
0x400A_8000
0x4009_A000
0x4009_8000
0x4009_2000
0x4009_0000
0x4008_C000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
0x4007_8000
0x4007_7000
0x4007_6000
0x4007_5000
0x4007_4000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4005_9000
0x4005_8000
0x4004_A000
0x4004_9000
0x4004_8000
0x4004_5000
0x4004_4000
0x4004_3000
0x4004_2000
0x4004_1000
0x4004_0000
0x4003_B000
0x4003_A000
0x4003_5000
0x4003_4000
0x4002_D000
0x4002_C000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_2000
0x4000_1000
0x4000_0000
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Table 2 HT32F52342/52352 Register Map
Start Address
0x4000_0000
Peripheral
USART0
0x4000_1000
0x4000_1FFF
UART0
0x4000_2000
0x4000_3FFF
Reserved
0x4000_4000
0x4000_4FFF
SPI0
0x4000_5000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
ADC
0x4001_1000
0x4002_1FFF
Reserved
0x4002_2000
0x4002_2FFF
AFIO
0x4002_3000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
EXTI
0x4002_5000
0x4002_BFFF
Reserved
0x4002_6000
0x4002_6FFF
I2S
0x4002_7000
0x4002_BFFF
Reserved
0x4002_C000
0x4002_CFFF
MCTM
0x4002_D000
0x4003_3FFF
Reserved
0x4003_4000
0x4003_4FFF
SCTM0
Reserved
0x4003_5000
0x4003_9FFF
0x4003_A000
0x4003_AFFF
SCI1
0x4003_B000
0x4003_FFFF
Reserved
USART1
0x4004_0000
0x4004_0FFF
0x4004_1000
0x4004_1FFF
UART1
0x4004_2000
0x4004_2FFF
Reserved
0x4004_3000
0x4004_3FFF
SCI0
0x4004_4000
0x4004_4FFF
SPI1
0x4004_5000
0x4004_7FFF
Reserved
0x4004_8000
0x4004_8FFF
I2C0
0x4004_9000
0x4004_9FFF
I2C1
0x4004_A000
0x4005_7FFF
Reserved
0x4005_8000
0x4005_8FFF
Comparator
0x4005_9000
0x4006_7FFF
Reserved
0x4006_8000
0x4006_8FFF
WDT
0x4006_9000
0x4006_9FFF
Reserved
0x4006_A000
0x4006_AFFF
RTC/PWRCU
0x4006_B000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
GPTM0
0x4006_F000
0x4006_FFFF
GPTM1
0x4007_0000
0x4007_3FFF
Reserved
0x4007_4000
0x4007_4FFF
SCTM1
0x4007_5000
0x4007_5FFF
Reserved
0x4007_6000
0x4007_6FFF
BFTM0
0x4007_7000
0x4007_7FFF
BFTM1
0x4007_8000
0x4007_FFFF
Reserved
21 of 48
Bus
Overview
Rev. 1.00
End Address
0x4000_0FFF
APB
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
End Address
Peripheral
0x4008_0000
0x4008_1FFF
FMC
0x4008_2000
0x4008_7FFF
Reserved
0x4008_8000
0x4008_9FFF
CKCU/RSTCU
0x4008_A000
0x4008_BFFF
CRC
0x4008_C000
0x4008_FFFF
Reserved
0x4009_0000
0x4009_1FFF
PDMA Control Registers
0x4009_2000
0x4009_7FFF
Reserved
0x4009_8000
0x4009_9FFF
EBI Control Registers
0x4009_A000
0x400A_7FFF
Reserved
0x400A_8000
0x400A_BFFF
USB
0x400A_C000
0x400A_FFFF
Reserved
0x400B_0000
0x400B_1FFF
GPIOA
0x400B_2000
0x400B_3FFF
GPIOB
0x400B_4000
0x400B_5FFF
GPIOC
0x400B_6000
0x400B_7FFF
GPIOD
0x400B_8000
0x400F_FFFF
Reserved
22 of 48
Bus
AHB
January 25, 2016
Overview
Rev. 1.00
Start Address
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Clock Structure
Prescaler
1 ~ 32
CK_LSE
HSI Auto
Trimming
Controller
Divider
2
CK_REF
CKREFPRE
CKREFEN
USB REF Pulse
fCK_USB = 48 MHz
PLLSRC
8 MHz
HSI RC
1
HSIEN
PLLEN
f CK_PLL,max = 48 MHz
SW[2:0]
00x
CK_HSI
011
CK_HSE
GPIODEN
CK_SYS AHB Prescaler
1,2,4,8,16,32
FCLK
( free running clock)
010
110
Clock
Monitor
CK_LSE
LSEEN(Note1)
32 kHz
LSI RC
WDTSRC
1
0
CK_LSI
CK_WDT
HCLKC
( to CortexTM-M0+)
CM0PEN
(control by HW)
CK_AHB
111
32.768 kHz
LSE OSC
CK_GPIO
( to GPIO port)
GPIOAEN
fCK_SYS,max = 48 MHz
4-16 MHz
HSE XTAL
HSEEN
STCLK
(to SysTick)
8
CK_PLL
PLL
0
Overview
CK_USB
USBEN
DMAEN
HCLKD
( to PDMA)
EBIEN
CK_EBI
( to EBI)
CRCEN
CK_CRC
( to CRC)
HCLKF
( to Flash)
CM0PEN
FMCEN
WDTEN
RTCSRC(Note1)
HCLKS
( to SRAM)
LSIEN(Note1)
1
0
CK_RTC
CM0PEN
SRAMEN
RTCEN(Note1)
HCLKBM
( to Bus Matrix)
CM0PEN
CKOUTSRC[2:0]
BMEN
CKOUT
000
CK_REF
001
010
CK_AHB/16
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
HCLKAPB
( to APB Bridge)
CM0PEN
APBEN
PCLK
Peripherals
Clock
Prescaler
1,2,4,8
00
PCLK/2
01
PCLK/4
10
PCLK/8
11
PCLK ( CMPx, AFIO,
ADC, SPIx, USARTx,
UARTx, I2Cx, I2S,
GPTMx, MCTM,
BFTMx, SCTMx, EXTI,
RTC, SCIx, WDT)
SPIEN
SCIEN
ADC
Prescaler
1,2,3,4,8,...
CK_ADC IP
ADCEN
Figure 3 HT32F52342/52352 Clock Structure
Rev. 1.00
23 of 48
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
4
Pin Assignment
Holtek HT32F52342/HT32F52352
48 LQFP-A
5
33V
PA5
6
33V
PA6
7
33V
PA7
8
33V
PC4
9
33V
PC5
10
33V
11
USB
12
USB
USBDM
_PC6
USBDP
_PC7
47
46
45
44
43
42
41
40
39
38
37
AP
AP
AF0
(Default)
AF1
33V 33V 33V 33V 33V 33V 33V 33V 33V 33V
P33 3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15 1.5 V Power Pad
33V 3.3 V Digital & Analog IO Pad
33V 3.3 V Digital I/O Pad
USB USB PHY Pad
BAK
Backup Domain Pad
P33
36
VSS_2
P33
35
VDD_2
33V
34
PB1
33V
33
PB0
33V
32
PA15
33V
31
PA14
33V
30
SWDIO
PA13
33V
29
SWCLK
PA12
33V
28
PA11
33V
27
PA10
33V
26
PA9_
BOOT
33V
25
PA8
BAK BAK BAK BAK BAK
33V 33V 33V 33V
P33 33V 33V 33V
P15 P33 P33 33V
15
16
17
18
19
20
21
22
23
24
CLDO
VDD_1
VSS_1
nRST
VBAT
X32KIN
X32KOUT
RTCOUT
XTALIN
XTALOUT
PB15
PC0
PB10
PB11
PB12
PB13
PB14
AF1
14
AF0
(Default)
13
Figure 4 HT32F52342/52352 48-pin LQFP Pin Assignment
Rev. 1.00
24 of 48
January 25, 2016
Pin Assignment
PA4
48
AF0
(Default)
33V
PB2
4
PB3
PA3
PB4
33V
PB5
3
PC1
PA2
PC2
33V
PC3
2
PB6
PA1
PB7
33V
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Holtek HT32F52342/HT32F52352
64 LQFP-A
PB8
PB7
PB6
PC3
PC2
PC1
VSS_3
VDD_3
PC15
PC14
PB5
PB4
PB3
PB2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AP
AP
AF0
(Default)
33V 33V 33V 33V 33V 33V P33 P33 33V 33V 33V 33V 33V 33V
AF1
PA0
1
33V
33V
48
PD3
PA1
2
33V
33V
47
PD2
PA2
3
33V
33V
46
PD1
33V
45
PB1
33V
44
PB0
P33
43
VSS_2
P33
42
VDD_2
33V
41
PA15
33V
40
PA14
33V
39
SWDIO
PA13
33V
38
SWCLK
PA12
33V
37
PA11
33V
36
PA10
PA3
4
33V
PA4
5
33V
PA5
6
33V
PA6
7
33V
PA7
8
33V
VDD_4
9
P33
VSS_4
10
P33
PC4
11
33V
PC5
12
33V
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15 1.5 V Power Pad
33V 3.3 V Digital & Analog I/O Pad
33V 3.3 V Digital I/O Pad
USB USB PHY Pad
BAK Backup Domain Pad
PC8
13
33V
PC9
14
33V
33V
35
PA9_
BOOT
15
USB
33V
34
PA8
16
USB
33V
33
PC13
USBDM
/PC6
USBDP
/PC7
BAK BAK BAK BAK BAK
33V 33V 33V 33V 33V 33V 33V 33V
P33 33V 33V 33V
P18 P33 P33 33V
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLDO
VDD_1
VSS_1
nRST
VBAT
X32KIN
X32KOUT
RTCOUT
PD0
XTALIN
XTALOUT
PB15
PC0
PC10
PC11
PC12
PB10
PB11
PB12
PB13
PB14
AF1
18
AF0
(Default)
17
Figure 5 HT32F52342/52352 64-pin LQFP Pin Assignment
Rev. 1.00
25 of 48
January 25, 2016
Pin Assignment
VDDA
64
AF0
(Default)
VSSA
AF0
(Default)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Table 3 HT32F52342/52352 Series Pin Assignment for 48/64-pin LQFP Package
Package
64
48
LQFP LQFP
Alternate Function Mapping
AF0
System
Default
AF1
GPIO
AF2
ADC
AF3
AF4
AF5
AF6
MCTM
/GPTM
SPI
USART
/UART
CMP
AF7
AF8
AF9
I2C
SCI
GT1_
CH0
SPI1_
SCK
USR0_
RTS
I2C1_
SCL
SCI0_
CLK
I2S_
WS
I2C1_
SDA
SCI0_
DIO
I2S_
BCLK
EBI
AF10
I2S
AF11 AF12
N/A
N/A
AF13
SCTM
1
PA0
2
2
PA1
ADC_
IN1
GT1_
CH1
SPI1_
MOSI
USR0_
CTS
3
3
PA2
ADC_
IN2
GT1_
CH2
SPI1_
MISO
USR0_
TX
I2S_
SDO
4
4
PA3
ADC_
IN3
GT1_
CH3
SPI1_
SEL
USR0_
RX
I2S_
SDI
5
5
PA4
ADC_
IN4
GT0_
CH0
SPI0_
SCK
USR1_
TX
I2C0_
SCL
SCI1_
CLK
6
6
PA5
ADC_
IN5
GT0_
CH1
SPI0_
MOSI
USR1_
RX
I2C0_
SDA
SCI1_
DIO
7
7
PA6
ADC_
IN6
GT0_
CH2
SPI0_
MISO
USR1_
RTS
8
8
PA7
ADC_
IN7
GT0_
CH3
SPI0_
SEL
USR1_
CTS
PC4
ADC_
IN8
GT0_
CH0
SPI1_
SEL
UR0_
TX
I2C1_
SCL
EBI_
A19
SCTM0
PC5
ADC_
IN9
GT0_
CH1
SPI1_
SCK
UR0_
RX
I2C1_
SDA
EBI_
A20
SCTM1
PC8
ADC_
IN10
GT0_
CH2
SPI1_
MOSI
EBI_A0
PC9
ADC_
IN11
GT0_
CH3
SPI1_
MISO
EBI_A1
9
VDD_4
10
VSS_4
11
12
9
10
13
14
15
11
PC6
15
11
USBDM
16
12
USBDP
16
12
PC7
17
13
CLDO
18
14
VDD_1
19
15
VSS_1
20
16
nRST
21
17
VBAT
22
18
X32KIN
23
19
X32KOUT
PB11
24
20
RTCOUT
PB12
25
I2S_
MCLK
MT_
CH2
USR0_
TX
I2C0_
SCL
MT_
CH2N
USR0_
RX
I2C0_
SDA
PB10
WAKEUP
PD0
I2C0_
SDA
EBI_
A18
I2S_
SDI
I2S_
MCLK
21
XTALIN
PB13
27
22
XTALOUT
PB14
28
23
PB15
MT_
CH0
SPI0_
SEL
USR1_
TX
I2C1_
SCL
EBI_
A16
29
24
PC0
MT_
CH0N
SPI0_
SCK
USR1_
RX
I2C1_
SDA
EBI_
A17
30
PC10
GT1_
CH0
SPI1_
SEL
EBI_
AD13
I2S_
WS
31
PC11
GT1_
CH1
SPI1_
SCK
EBI_
AD14
I2S_
BCLK
32
PC12
GT1_
CH2
SPI1_
MOSI
UR1_
TX
I2C0_
SCL
EBI_
AD15
I2S_
SDO
33
PC13
GT1_
CH3
SPI1_
MISO
UR1_
RX
I2C0_
SDA
EBI_
CS3
I2S_
SDI
25
PA8
35
26
PA9
_BOOT
36
27
Rev. 1.00
PA10
N/A
SCI1_
DET
26
34
AF15
System
Other
Pin Assignment
1
ADC_
IN0
AF14
USR0_
TX
SPI0_
MOSI
MT_
CH1
SCI1_
CLK
SCI1_
DIO
USR0_
RX
26 of 48
SCTM0
I2S_
MCLK
EBI_A1
I2S_
WS
CKOUT
SCI0_
DET
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Package
Alternate Function Mapping
AF0
AF1
AF2
AF3
AF4
AF5
MT_
CH1N
SPI0_
MISO
AF6
AF7
AF9
AF10
SCI1_
DET
AF8
EBI_A0
I2S_
MCLK
37
28
PA11
38
29
SWCLK
PA12
39
30
SWDIO
PA13
40
31
PA14
MT_
CH0
SPI1_
SEL
USR1_
TX
I2C1_
SCL
SCI0_
CLK
EBI_
AD0
41
32
PA15
MT_
CH0N
SPI1_
SCK
USR1_
RX
I2C1_
SDA
SCI0_
DIO
EBI_
AD1
AF13
AF15
SCTM0
SCTM1
VDD_2
43
VSS_2
44
33
PB0
MT_
CH1
SPI1_
MOSI
USR0_
TX
I2C0_
SCL
EBI_
AD2
45
34
PB1
MT_
CH1N
SPI1_
MISO
USR0_
RX
I2C0_
SDA
EBI_
AD3
46
PD1
MT_
CH2
USR1_
RTS
SCI0_
CLK
EBI_
AD10
47
PD2
MT_
CH2N
USR1_
CTS
SCI0_
DIO
EBI_
AD11
48
PD3
MT_
CH3
SCI0_
DET
EBI_
AD12
35
VDD_2
36
VSS_2
49
37
PB2
MT_
CH2
SPI0_
SEL
UR0_
TX
EBI_
AD4
50
38
PB3
MT_
CH2N
SPI0_
SCK
UR0_
RX
EBI_
AD5
SCTM1
51
39
PB4
MT_
BRK
SPI0_
MOSI
UR1_
TX
EBI_
AD6
SCTM0
PB5
MT_
BRK
SPI0_
MISO
UR1_
RX
EBI_
AD7
53
PC14
MT_
CH3
54
PC15
55
VDD_3
56
VSS_3
52
AF14
Pin Assignment
42
AF11 AF12
40
57
41
PC1
CN0
MT_
CH0
SPI1_
SEL
58
42
PC2
CP0
MT_
CH0N
SPI1_
SCK
59
43
PC3
COUT0
60
44
PB6
CN1
MT_
CH2
61
45
PB7
CP1
MT_
CH2N
62
46
PB8
COUT1
MT_
CH3
63
47
VDDA
64
48
VSSA
Rev. 1.00
I2C0_
SCL
EBI_
AD8
I2C0_
SDA
EBI_
AD9
UR1_
TX
EBI_
OE
SCTM1
I2S_
MCLK
EBI_
CS0
SPI1_
MOSI
UR1_
RX
SPI1_
MISO
UR0_
TX
UR0_
RX
EBI_
WE
SCI1_
CLK
EBI_
ALE
I2S_
BCLK
I2C1_
SCL
SCI1_
DET
EBI_
CS1
I2S_
SDO
I2C1_
SDA
SCI1_
DIO
EBI_
CS2
I2S_
SDI
27 of 48
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Table 4 HT32F52342/52352 Pin Description
Pin Number
64LQFP 48LQFP
Pin Name
(Note1)
IO
Structure
Type
(Note2)
Description
Output
Driving
Default Function (AF0)
1
PA0
AI/O
33V
4/8/12/16 mA PA0
2
2
PA1
AI/O
33V
4/8/12/16 mA PA1
3
3
PA2
AI/O
33V
4/8/12/16 mA PA2
4
4
PA3
AI/O
33V
4/8/12/16 mA PA3
5
5
PA4
AI/O
33V
4/8/12/16 mA PA4
6
6
PA5
AI/O
33V
4/8/12/16 mA PA5
7
7
PA6
AI/O
33V
4/8/12/16 mA PA6
8
8
4/8/12/16 mA PA7
PA7
AI/O
33V
9
VDD_4
P
—
—
Voltage for digital I/O
10
VSS_4
P
—
—
Ground reference for digital I/O
11
9
PC4
AI/O
33V
4/8/12/16 mA PC4
12
10
PC5
AI/O
33V
4/8/12/16 mA PC5
13
PC8
AI/O
33V
4/8/12/16 mA PC8
14
PC9
AI/O
33V
4/8/12/16 mA PC9
4/8/12/16 mA PC6
15
11
PC6
I/O
33V
15
11
USBDM
AI/O
—
—
USB Differential data bus conforming to the
Universal Serial Bus standard.
16
12
USBDP
AI/O
—
—
USB Differential data bus conforming to the
Universal Serial Bus standard.
16
12
PC7
I/O
33V
4/8/12/16 mA PC7
17
13
CLDO
P
—
—
Core power LDO 1.5 V output.
It is recommended to connect a 1 uF
capacitor as close as possible between this
pin and VSS_1.
18
14
VDD_1
P
—
—
Voltage for digital I/O
19
15
VSS_1
P
—
—
Ground reference for digital I/O
20
16
nRST
I
(BK)
33V_PU
—
External reset pin and external wakeup pin
in the Power-Down mode
21
17
VBAT
P
—
—
Battery power input for the backup domain
33V
< 2 mA
X32KIN
22
18
PB10 Note 4
AI/O
(BK)
23
19
PB11 Note 4
AI/O
(BK)
33V
< 2 mA
X32KOUT
24
20
PB12 Note 4
I/O
(BK)
33V
< 2 mA
RTCOUT
PD0
I/O
33V
4/8/12/16 mA PD0
25
26
21
PB13
AI/O
33V
4/8/12/16 mA XTALIN
27
22
PB14
AI/O
33V
4/8/12/16 mA XTALOUT
28
23
PB15
I/O
33V
4/8/12/16 mA PB15
29
24
PC0
I/O
33V
4/8/12/16 mA PC0
PC10
I/O
33V
4/8/12/16 mA PC10
31
PC11
I/O
33V
4/8/12/16 mA PC11
32
PC12
I/O
33V
4/8/12/16 mA PC12
33
PC13
I/O
33V
4/8/12/16 mA PC13
30
Rev. 1.00
28 of 48
January 25, 2016
Pin Assignment
1
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Pin Number
64LQFP 48LQFP
Pin Name
(Note1)
IO
Structure
Type
(Note2)
Description
Output
Driving
Default Function (AF0)
25
PA8
I/O
33V_PU
4/8/12/16 mA PA8
35
26
PA9
I/O
33V_PU
4/8/12/16 mA PA9_BOOT
36
27
PA10
I/O
33V
4/8/12/16 mA PA10
37
28
PA11
I/O
33V
4/8/12/16 mA PA11
38
29
PA12
I/O
33V_PU
4/8/12/16 mA SWCLK
39
30
PA13
I/O
33V_PU
4/8/12/16 mA SWDIO
40
31
PA14
I/O
33V
4/8/12/16 mA PA14
41
32
PA15
I/O
33V
4/8/12/16 mA PA15
42
VDD_2
P
—
—
Voltage for digital I/O
43
VSS_2
P
—
—
Ground reference for digital I/O
44
33
PB0
I/O
33V
4/8/12/16 mA PB0
45
34
PB1
I/O
33V
4/8/12/16 mA PB1
46
PD1
I/O
33V
4/8/12/16 mA PD1
47
PD2
I/O
33V
4/8/12/16 mA PD2
48
PD3
I/O
33V
4/8/12/16 mA PD3
49
35
VDD_2
P
—
—
Voltage for digital I/O
36
VSS_2
P
—
—
Ground reference for digital I/O
37
PB2
I/O
33V
4/8/12/16 mA PB2
50
38
PB3
I/O
33V
4/8/12/16 mA PB3
51
39
PB4
I/O
33V
4/8/12/16 mA PB4
52
40
PB5
I/O
33V
4/8/12/16 mA PB5
53
PC14
I/O
33V
4/8/12/16 mA PC14
54
PC15
I/O
33V
4/8/12/16 mA PC15
55
VDD_3
P
—
—
Voltage for digital I/O
56
VSS_3
P
—
—
Ground reference for digital I/O
57
41
PC1
AI/O
33V
4/8/12/16 mA PC1
58
42
PC2
AI/O
33V
4/8/12/16 mA PC2
59
43
PC3
AI/O
33V
4/8/12/16 mA PC3
60
44
PB6
AI/O
33V
4/8/12/16 mA PB6
61
45
PB7
AI/O
33V
4/8/12/16 mA PB7
62
46
PB8
AI/O
33V
4/8/12/16 mA PB8
63
47
VDDA
P
—
—
Analog voltage for ADC and Comparator
64
48
VSSA
P
—
—
Ground reference for the ADC and Comparator
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, BK = Back-up domain
2. 33V = 3.3 V tolerant.
3. The GPIOs are in an AF0 state after a VDD15 power on reset (POR) except for the RTCOUT pin in the
Backup Domain I/O. The RTCOUT pin is reset by the Backup Domain power-on-reset (PORB) or by the
Backup Domain software reset (BAK_RST bit in BAK_CR register).
4. The backup domain of the I/O pins have a source current capability limitation of < 2 mA @ VDD = 3.3 V.
The typical sink current is 4/8 mA configurable @ VDD = 3.3 V.
Rev. 1.00
29 of 48
January 25, 2016
Pin Assignment
34
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
5
Electrical Characteristics
Absolute Maximum Ratings
Table 5 Absolute Maximum Ratings
Min
Max
VDD
Symbol
External main supply voltage
Parameter
VSS - 0.3
VSS + 3.6
Unit
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VIN
Input voltage on I/O
VSS - 0.3
VDD + 0.3
V
TA
Ambient operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
PD
Total power dissipation
—
500
mW
VESD
Electrostatic discharge voltage - human body mode
-4000
+4000
V
Recommended DC Operating Conditions
Table 6 Recommended DC Operating Conditions
Symbol
Parameter
I/O operating voltage
VDD
Conditions
TA = 25°C, unless otherwise specified.
Min
2.0
Typ
3.3
Max
3.6
Unit
V
VDDA
Analog operating voltage
2.5
3.3
3.6
V
VBAT
Battery supply operating voltage
2.0
3.3
3.6
V
On-Chip LDO Voltage Regulator Characteristics
Table 7 LDO Characteristics
Symbol
Rev. 1.00
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min Typ
VDD ≥ 2.0 V Regulator input @
ILDO = 35 mA and voltage
1.425 1.5
variant = ±5 %, after trimming.
VLDO
Internal regulator output
voltage
ILDO
Output current
CLDO
The capacitor value is
External filter capacitor value
dependent upon the core
for internal core power supply
power current consumption
VDD = 2.0 V Regulator input @
VLDO = 1.5 V
30 of 48
Max Unit
1.57
V
—
35
—
mA
—
2.2
—
μF
January 25, 2016
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Power Consumption
Table 8 Power Consumption Characteristics
Symbol
Parameter
Min Typ Max Unit
—
mA
VDD = VBAT = 3.3 V, HSE = 8 MHz,
PLL = 48 MHz, fHCLK = 48 MHz,
fPCLK = 48 MHz, All peripherals disabled
—
10
—
mA
VDD = VBAT = 3.3 V, HSE off, PLL off,
LSI on, fHCLK = 32 kHz, fPCLK = 32 kHz,
All peripherals enabled
—
51
—
μA
VDD = VBAT = 3.3 V, HSE off, PLL off,
LSI on, fHCLK = 32 kHz, fPCLK = 32 kHz,
All peripherals disabled
—
45
—
μA
VDD = VBAT = 3.3 V, HSE = 8 MHz,
PLL = 48 MHz, fHCLK = 0 MHz,
fPCLK = 48 MHz, All peripherals enabled
—
—
—
mA
VDD = VBAT = 3.3 V, HSE = 8 MHz,
PLL = 48 MHz, fHCLK = 0 MHz,
fPCLK = 48 MHz, All peripherals disabled
—
—
—
mA
Supply Current
(Deep-Sleep1 mode)
VDD = VBAT = 3.3 V, All clock off (HSE/PLL/
fHCLK), LDO in low power mode, LSI on,
RTC on
—
40
—
μA
Supply Current
(Deep-Sleep2 mode)
VDD = VBAT = 3.3 V, All clock off (HSE/PLL/
fHCLK), LDO off (DMOS on), LSI on, RTC on
—
12
—
μA
VDD = VBAT = 3.3 V, LDO off, LSE on,
LSI on, RTC on
—
—
—
μA
VDD = VBAT = 3.3 V, LDO off, LSE off,
LSI on, RTC off
—
2
—
μA
—
—
—
μA
—
1.5
—
μA
Supply Current
(Sleep mode)
VDD33 not present, VBAT = 3.3 V, LDO off,
Battery Supply Current LSE off, LSI on, RTC on
(Power-Down mode)
VDD not present, VBAT = 3.3 V, LDO off,
LSE off, LSI on, RTC off
Note: 1. HSE means high speed external oscillator. HSI means 8 MHz high speed internal oscillator.
2. LSE means 32.768 kHz low speed external oscillator. LSI means 32 kHz low speed internal
oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.
Rev. 1.00
31 of 48
January 25, 2016
Electrical Characteristics
20
Supply Current
(Power-Down mode)
IBAT
Conditions
VDD = VBAT = 3.3 V, HSE = 8 MHz,
PLL = 48 MHz, fHCLK = 48 MHz,
fPCLK = 48 MHz, All peripherals enabled
—
Supply Current
(Run mode)
IDD
TA = 25°C, unless otherwise specified.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Reset and Supply Monitor Characteristics
Table 9 VDD Power Reset Characteristics
Symbol
VPOR
Conditions
Power on reset threshold
(Rising Voltage on VDD)
Power down reset threshold
(Falling Voltage on VDD)
Min
Typ
Max
Unit
1.66
1.79
1.90
V
1.49
1.64
1.78
V
—
—
150
—
mV
VDD = 3.3 V
—
0.1
0.2
ms
TA = -40°C~ +85°C
VPORHYST POR hysteresis
tPOR
Reset delay time
Note: 1. Data based on characterisation results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. If the LDO is turned on, the VDD POR has to be in the de-assertion condition. When the
VDD POR is in the assertion state then the LDO will be turned off.
Table 10 LVD/BOD Characteristics
Symbol
VBOD
VLVD
Parameter
Voltage of Brown Out
Detection
TA = 25°C, unless otherwise specified.
—
Conditions
TA = -40°C~ 85°C
After factory-trimmed
(VDD Falling edge)
Min
Typ
Max
Unit
2.02
2.1
2.18
V
LVDS = 000
2.17
2.25
2.33
V
LVDS = 001
2.32
2.4
2.48
V
LVDS = 010
2.47
2.55
2.63
V
Voltage of Low Voltage TA = -40°C~ 85°C LVDS = 011
Detection
(VDD Falling edge) LVDS = 100
2.62
2.7
2.78
V
2.77
2.85
2.93
V
LVDS = 101
2.92
3.0
3.08
V
LVDS = 110
3.07
3.15
3.23
V
LVDS = 111
3.22
3.3
3.38
V
VLVDHTST
LVD hysteresis
VDD = 3.3 V
—
—
100
—
mV
tsuLVD
LVD Setup time
VDD = 3.3 V
—
—
—
5
μs
tatLVD
LVD active delay time
VDD = 3.3 V
—
—
—
—
μs
IDDLVD
Operation current
VDD = 3.3 V
—
—
5
15
μA
NOTE3
Note: 1. Data based on characterisation results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. Bandgap current is not included.
4. LVDS field is in the PWRCU LVDCSR register
Rev. 1.00
32 of 48
January 25, 2016
Electrical Characteristics
VPDR
Parameter
TA = 25°C, unless otherwise specified.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
External Clock Characteristics
Table 11 High Speed External Clock (HSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operation Range
VDD
High Speed External oscillator
frequency (HSE)
CLHSE
Load capacitance
RFHSE
Internal feedback resistor between
XTALIN and XTALOUT pins
RESR
Equivalent Series Resistance*
Min
2.0
Typ
—
—
4
—
16
MHz
VDD = 3.3 V, RESR = 100 Ω
@ 16 MHz
—
—
22
pF
—
—
1
—
MΩ
—
—
160
Ω
VDD = 3.3 V, CL = 12 pF
@ 16 MHz, HSEDR = 0
VDD = 2.4 V, CL = 12 pF
@ 16 MHz, HSEDR = 1
—
Max Unit
3.6
V
DHSE
HSE oscillator Duty cycle
40
—
60
%
IDDHSE
HSE oscillator current consumption VDD = 3.3 V @ 16 MHz
—
TBD
—
mA
IPWDHSE
HSE oscillator power down current VDD = 3.3 V
—
—
0.01
μA
tSUHSE
HSE oscillator startup time
—
—
4
ms
VDD = 3.3 V
Table 12 Low Speed External Clock (LSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operation Range
VBAK
Conditions
—
Typ
—
Max
3.6
Unit
V
—
32.768
—
kHz
—
10
—
MΩ
fCK_LSE
LSE Frequency
RF
Internal feedback resistor
RESR
Equivalent Series
Resistance
VBAK = 3.3 V
30
—
TBD
KΩ
CL
Recommended load
capacitances
VBAK = 3.3 V
6
—
TBD
pF
fCK_LSE = 32.768 kHz,
Oscillator supply current RESR = 50 KΩ, CL ≥ 7 pF
(High current mode)
VBAK = 2.0 V ~ 2.7 V
TA = -40°C ~ +85°C
—
3.3
6.3
μA
fCK_LSE = 32.768 kHz,
Oscillator supply current RESR = 50 KΩ, CL < 7 pF
VBAK = 2.0 V ~ 3.6 V
(Low current mode)
TA = -40°C ~ +85°C
—
1.8
3.3
μA
Power down current
—
—
0.01
μA
500
—
—
ms
IDDLSE
tsuLSE
Startup time
( Low current mode)
VBAK = 2.0 V ~ 3.6 V
Min
2.0
—
—
fCK_LSE = 32.768 kHz,
VBAK = 2.0 V ~ 3.6 V
Note: The following guidelines are recommended to increase the stability of the crystal circuit of the
HSE / LSE clock in the PCB layout:
■■ The crystal oscillator should be located as close as possible to the MCU to keep the trace lengths
as short as possible to reduce any parasitic capacitance.
■■ Shield lines in the vicinity of the crystal by using a ground plane to isolate signals and reduce noise.
■■ Keep any high frequencysignal lines away from the crystal area to prevent any crosstalk adverse effects.
Rev. 1.00
33 of 48
January 25, 2016
Electrical Characteristics
fHSE
Conditions
—
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Internal Clock Characteristics
Table 13 High Speed Internal Clock (HSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operation Range
VDD
fHSI
Duty
IDDHSI
tsuHSI
Min
2.0
Typ
Max
3.6
Unit
V
VDD = 3.3 V @ 25°C
—
8
—
MHz
VDD = 3.3 V, TA = 25°C
-2
—
2
%
-3
—
3
%
-4
—
4
%
35
—
65
%
VDD = 2.5 V ~ 3.6 V,
Factory calibrated HSI
T
oscillator frequency accuracy A = -40°C ~ +85°C
VDD = 2.0 V ~ 3.6 V
TA = -40°C ~ +85°C
Duty cycle
Oscillator supply current
Power down current
Startup time
fHSI = 8 MHz
300
fHSI = 8 MHz
fHSI = 8 MHz
-
-
500
μA
0.05
μA
10
μs
Table 14 Low Speed Internal Clock (LSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Low Speed Internal
Oscillator Frequency (LSI)
Conditions
VDD = 3.3 V,
TA = -40°C ~ +85°C
ACCLSI
LSI Frequency accuracy
IDDLSI
tSULSI
fLSI
Rev. 1.00
Min
Typ
Max
Unit
21
32
43
kHz
After factory-trimmed,
VDD = 3.3 V, TA = 25°C
-10
—
+10
%
LSI Oscillator Operating
current
VDD = 3.3 V, TA = 25°C
—
0.4
0.8
μA
LSI Oscillator startup time
VDD = 3.3 V, TA = 25°C
—
—
100
μs
34 of 48
January 25, 2016
Electrical Characteristics
ACCHSI
HSI Frequency
Conditions
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
PLL Characteristics
Table 15 PLL Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
PLL input clock
fPLLIN
Conditions
—
Min
4
Typ
—
Max
16
Unit
MHz
PLL output clock
—
16
—
48
MHz
tLOCK
PLL lock time
—
—
200
—
μs
Memory Characteristics
Table 16 Flash Memory Characteristics
Symbol
NENDU
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Number of guaranteed
program/erase cycles before TA = -40°C ~ +85°C
failure. (Endurance)
Min
Typ
Max
Unit
100
—
—
K cycles
Years
tRET
Data retention time
TA = -40°C ~ +85°C
10
—
—
tPROG
Word programming time
TA = -40°C ~ +85°C
20
—
—
μs
tERASE
Page erase time
TA = -40°C ~ +85°C
2
—
—
ms
tMERASE
Mass erase time
TA = -40°C ~ +85°C
10
—
—
ms
I/O Port Characteristics
Table 17 I/O Port Characteristics
Symbol
Parameter
Conditions
Min
Typ
VI = VSS, On-chip pull-up
resister disabled.
—
—
3
μA
—
—
3
μA
VI = VDD, On-chip pulldown resister disabled.
—
—
3
μA
—
—
3
μA
3.3 V IO
- 0.5
—
VDD *
0.35
V
Reset pin
- 0.5
—
VDD *
0.35
V
3.3 V IO
VDD *
0.65
—
VDD +
0.5
V
Reset pin
VDD *
0.65
—
VDD +
0.5
V
3.3 V IO
—
0.12
* VDD
—
mV
Reset pin
—
0.12
* VDD
—
mV
IIL
Low level input
current
3.3 V IO
IIH
High level input
current
3.3 V IO
VIL
Low level input
voltage
VIH
VHYS
Rev. 1.00
TA = 25°C, unless otherwise specified.
High level input
voltage
Schmitt trigger input
voltage hysteresis
Reset pin
Reset pin
35 of 48
Max Unit
January 25, 2016
Electrical Characteristics
fCK_PLL
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Symbol
Parameter
Conditions
3.3 V IO 4 mA drive, VOL = 0.4 V
IOL
VOL
VOH
High level output
current
(GPIO Source
current)
Low level output
voltage
High level output
voltage
—
Max Unit
—
mA
8
—
—
mA
12
—
—
mA
16
—
—
mA
4
—
—
mA
3.3 V I/O 4 mA drive, VOH = VDD - 0.4 V
4
—
—
mA
3.3 V I/O 8 mA drive, VOH = VDD - 0.4 V
8
—
—
mA
3.3 V I/O 12 mA drive, VOH = VDD - 0.4 V
12
—
—
mA
3.3 V I/O 16 mA drive, VOH = VDD - 0.4 V
16
—
—
mA
Backup Domain IO drive @ VDD = 3.3 V,
VOH = VDD - 0.4 V, PB10, PB11, PB12.
—
—
2
mA
3.3 V 4 mA drive IO, IOL = 4 mA
—
—
0.4
V
3.3 V 8 mA drive IO, IOL = 8 mA
—
—
0.4
V
3.3 V 12 mA drive IO, IOL = 12 mA
—
—
0.4
V
3.3 V 16 mA drive IO, IOL = 16 mA
—
—
0.4
V
VDD = 2.7 V~3.6 V
—
—
0.4
V
VDD = 2.0 V~2.7 V
—
—
0.6
V
Backup Domain IO
VDD = 2.7 V~3.6 V
Sink Current = 8 mA
(High driving strength) VDD = 2.0 V~2.7 V
—
—
0.4
V
—
—
0.6
V
3.3 V 4 mA drive IO, IOH = 4 mA
VDD 0.4
—
—
V
3.3 V 8 mA drive IO, IOH = 8 mA
VDD 0.4
—
—
V
3.3 V 12 mA drive IO, IOL = 12 mA
VDD 0.4
—
—
V
3.3 V 16 mA drive IO, IOL = 16 mA
VDD 0.4
—
—
V
2.4
—
—
V
VDD Backup Domain IO
VDD = 2.0 V~2.7 V
0.4
Source Current = 1mA
—
—
V
Backup Domain IO
Sink Current = 4 mA
(Low driving strength)
Backup Domain IO
VDD = 2.7 V~3.6 V
Source Current = 2mA
Rev. 1.00
Typ
4
RPU
Internal pull-up
resistor
3.3 V I/O
—
46
—
kΩ
RPD
Internal pull-down
resistor
3.3 V I/O
—
46
—
kΩ
36 of 48
January 25, 2016
Electrical Characteristics
IOH
3.3 V IO 8 mA drive, VOL = 0.4 V
Low level output
3.3 V IO 12 mA drive, VOL = 0.4 V
current
(GPIO Sink current) 3.3 V IO 16 mA drive, VOL = 0.4 V
Backup Domain IO drive @ VDD = 3.3 V,
VOL = 0.4 V, PB10, PB11, PB12
Min
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
ADC Characteristics
Table 18 ADC Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operating voltage
VDDA
Min
2.7
Typ
3.3
Max
3.6
Unit
V
—
VREF+
V
VDDA VDDA
V
VADCIN
A/D Converter input voltage
range
—
0
VREF+
A/D Converter Reference
voltage
—
—
IADC
Current consumption
VDDA = 3.3 V
—
1
TBD
mA
IADC_DN
Power down current
consumption
VDDA = 3.3 V
—
—
0.1
μA
fADC
A/D Converter clock
—
0.7
—
16
MHz
fS
Sampling rate
—
0.05
—
1
MHz
tDL
Data latency
—
—
12.5
—
1/fADC
Cycles
tS&H
Sampling & hold time
—
—
3.5
—
1/fADC
Cycles
tADCCONV
A/D Converter conversion time
—
—
16
—
1/fADC
Cycles
RI
Input sampling switch resistance
—
—
—
1
kΩ
—
16
—
pF
—
—
—
1
μs
CI
Input sampling capacitance
tSU
Startup up time
No pin/pad capacitance
included
N
Resolution
—
—
12
—
bits
INL
Integral Non-linearity error
fS = 750 kHz, VDDA = 3.3 V
—
±2
±5
LSB
DNL
Differential Non-linearity error
fS = 750 kHz, VDDA = 3.3 V
—
±1
EO
Offset error
—
—
—
±10
LSB
EG
Gain error
—
—
—
±10
LSB
LSB
Note: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input
stage where CI is the storage capacitor, RI is the resistance of the sampling switch and RS
is the output impedance of the signal source VS. Normally the sampling phase duration is
approximately, 3.5/fADC. The capacitance, CI, must be charged within this time frame and it
must be ensured that the voltage at its terminals becomes sufficiently close to VS for accuracy. To guarantee this, RS is not allowed to have an arbitrarily large value.
Rev. 1.00
37 of 48
January 25, 2016
Electrical Characteristics
Conditions
—
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
SAR ADC
sample
RS
CI
RI
Figure 6 ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and V REF ) are sampled
consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following
equation:
RS <
3.5
− RI
f ADCCI ln( 2N + 2 )
Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, RS may be larger than the value indicated by the equation
above.
Rev. 1.00
38 of 48
January 25, 2016
Electrical Characteristics
VS
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
Comparator Characteristics
Table 19 Comparator Characteristics
TA = 25°C, unless otherwise specified.
Parameter
Operating voltage
Conditions
Comparator mode
Min
2.4
Typ
3.3
Max
3.6
Unit
V
VIN
Input Common Mode
Voltage Range
CP or CN
VSSA
—
VDDA
V
VIOS
Input offset voltage(1)
TA = 25°C
-15
—
15
mV
No hysteresis
(CMPnHM [1:0] = 00)
—
0
—
mV
Low hysteresis
(CMPnHM [1:0] = 01)
—
30
—
mV
Middle hysteresis
(CMPnHM [1:0] = 10)
—
70
—
mV
High hysteresis
(CMPnHM [1:0] = 11)
—
100
—
mV
—
50
100
—
100
250
Vhys
tRT
ICMP
Input Hysteresis
VDDA ≥ 2.7 V
High Speed
Response time
mode
VDDA < 2.7 V
Input Overdrive = ±100mV
Low Speed mode
Current Consumption
VDDA = 3.3 V
ns
—
2
5
μs
High Speed mode
—
130
—
μA
Low Speed mode
—
30
—
μA
—
—
50
μs
—
—
0.1
μA
VSSA
—
VDDA
V
tCMPST
Comparator Startup Time
Comparator enabled to output
valid.
ICMP_DN
Power Down Supply
Current
CMPEN = 0
CVREFEN = 0
CVREFOE=0
Comparator Voltage Reference (CVR)
VCVR
Output Range
NBits
CVR Scaler Resolution
tCVRST
Setting Time
ICVR
Current Consumption
VDDA = 3.3 V
6
bits
CVR scaler setting time from
CVREF = “000000” to “111111”
—
—
100
μs
CVREFEN=1, CMPREFOE=0
—
65
—
μA
CVREFEN=1, CVREFOE=1
—
80
110
μA
Min
—
Typ
—
Max
48
Unit
MHz
Note: Guaranteed by design, not tested in production.
SCTM/GPTM/MCTM Characteristics
Table 20 SCTM/GPTM/MCTM Characteristics
Symbol
Rev. 1.00
fTM
Parameter
Timer clock source for GPTM and MCTM
Conditions
—
tRES
Timer resolution time
—
1
—
—
fTM
fEXT
External single frequency on channel 1 ~ 4
—
—
—
1/2
fTM
RES
Timer resolution
—
—
—
16
bits
39 of 48
January 25, 2016
Electrical Characteristics
Symbol
VDDA
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
I2C Characteristics
Table 21 I2C Characteristics
Symbol
Standard
mode
Parameter
Fast mode
Fast mode
plus
Max
100
Min
—
Max
400
Min
—
Max
1000
Unit
fSCL
SCL clock frequency
Min
—
tSCL(H)
SCL clock high time
4.5
—
1.125
—
0.45
—
μs
tSCL(L)
SCL clock low time
4.5
—
1.125
—
0.45
—
μs
tFALL
SCL and SDA fall time
—
1.3
—
0.34
—
0.135
μs
tRISE
SCL and SDA rise time
tSU(SDA)
SDA data setup time
tH(SDA)
SDA data hold time
tSU(STA)
START condition setup time
tH(STA)
START condition hold time
tSU(STO)
STOP condition setup time
kHz
1.3
—
0.34
—
0.135
μs
—
125
—
50
—
ns
0
—
0
—
0
—
ns
500
—
125
—
50
—
ns
0
—
0
—
0
—
ns
500
—
125
—
50
—
ns
Note: 1. Guaranteed by design, not tested in production.
2. To achieve 100kHz standard mode, the peripheral clock frequency must be higher than
2MHz.
3. To achieve 400kHz fast mode, the peripheral clock frequency must be higher than 8MHz.
4. To achieve 1MHz fast mode plus, the peripheral clock frequency must be higher than
20MHz.
5. The above characteristic parameters of the I2C bus timing are based on: SEQ_FILTER = 01
and COMB_FILTER_En is disabled.
tFALL
tRISE
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 7 I2C Timing Diagrams
Rev. 1.00
40 of 48
January 25, 2016
Electrical Characteristics
—
500
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
SPI Characteristics
Table 22 SPI Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode, SPI peripheral
clock frequency fPCLK
—
—
fPCLK/2
MHz
tSCK/2
-2
—
tSCK/2
+1
ns
SPI Master Mode
SPI master output SCK
clock frequency
tSCK(H)
tSCK(L)
SCK clock high and low time
tV(MO)
Data output valid time
—
—
—
5
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
—
—
fPCLK/3
MHz
30
—
70
%
SPI Slave Mode
fSCK
(1/tSCK)
SPI master output SCK
clock frequency
Slave mode, SPI peripheral
clock frequency fPCLK
DutySCK
SPI slave input SCK clock
duty cycle
tSU(SEL)
SEL enable setup time
—
3 tPCLK
—
—
ns
tH(SEL)
SEL enable hold time
—
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
Note: tSCK= 1/fSCK; tPCLK= 1/fPCLK. SPI output (input) clock frequency fSCK; SPI peripheral clock frequency fPCLK.
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
tV(MO)
MOSI
DATA VALID
tSU(MI )
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI )
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
tSU(MI )
tH(MO)
DATA VALID
DATA VALID
DATA VALID
tH(MI )
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 8 SPI Timing Diagrams – SPI Master Mode
Rev. 1.00
41 of 48
January 25, 2016
Electrical Characteristics
fSCK
(1/tSCK)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
SEL
tSU(SEL)
tH(SEL)
tSCK
tSCK(H)
Electrical Characteristics
SCK
(CPOL=0)
tSCK(L)
SCK
(CPOL=1)
tSU(SI)
MOSI
tH(SI)
LSB/MSB IN
MSB/LSB IN
tA(SO)
tV(SO)
tDIS(SO)
tH(SO)
LSB/MSB OUT
MSB/LSB OUT
MISO
Figure 9 SPI Timing Diagrams - SPI Slave Mode with CPHA=1
I2S Characteristics
Table 23 I2S Characteristics
Symbol
I2S Master mode
Parameter
Conditions
Min
Typ
Max
Unit
tWSD(MO)
WS output to BCLK delay
—
—
TBD
—
ns
tDOD(MO)
Data output to BCLK delay
—
—
TBD
—
ns
tDIS(MI)
Data input setup time
—
—
TBD
—
ns
tDIH(MI)
Data input hold time
—
—
TBD
—
ns
I2S Slave mode
Rev. 1.00
tBCH(SI)
BCLK high pulse width
—
—
TBD
—
ns
tBCL(SI)
BCLK low pulse width
—
—
TBD
—
ns
tWSS(SI)
WS input setup time
—
—
TBD
—
ns
tDOD(SO)
Data output to BCLK delay
—
—
TBD
—
ns
tDIS(SI)
Data input setup time
—
—
TBD
—
ns
tDIH(SI)
Data input hold time
—
—
TBD
—
ns
42 of 48
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
BCLK
tWSD(MO)
WS
Electrical Characteristics
tDOD(MO)
SDO
tDIS(MI )
tDIH(MI )
SDI
Figure 10 Timing of I2S Master Mode
tBCH(SI)
tBCL(SI)
BCLK
tWSS(SI)
WS
tDOD(SO)
SDO
tDIS(SI)
tDIH(SI)
SDI
Figure 11 Timing of I2S Slave Mode
Rev. 1.00
43 of 48
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
USB Characteristics
The USB interface is USB-IF certified - Full Speed.
Table 24 USB DC Electrical Characteristics
Symbol
Parameter
USB operating voltage
VDD33
Conditions
—
Min
3.0
|USBDP-USBDM|
Typ
—
Max Unit
3.6
V
Differential input sensitivity
0.2
—
—
V
VCM
Common mode voltage range
—
0.8
—
2.5
V
VSE
Single-ended receiver threshold
—
0.8
—
2.0
V
VOL
Pad output low voltage
0
—
0.3
V
VOH
Pad output high voltage
2.8
—
3.6
V
VCRS
Differential output signal cross-point
voltage
1.3
—
2.0
V
ZDRV
Driver output resistance
—
—
10
—
Ω
CIN
Transceiver pad capacitance
—
—
—
20
pF
RL of 1.5 kΩ to VDD33
Note: 1. Guaranteed by design, not tested in production.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP pin should
be pulled up with a 1.5 kΩ external resistor to a 3.0-to-3.6 V voltage supply.
3. The USB functionality is ensured down to 2.7 V but not for the full USB electrical characteristics
which will experience degradation in the 2.7-to-3.0 V VDD33 voltage range.
4. RL is the load connected to the USB driver USBDP.
Rise Time
Fall Time
tr
tf
90%
90%
VCRS
10%
10%
Figure 12 USB Signal Rise Time and Fall Time and Cross-Point Voltage (VCRS) Definition
Table 25 USB AC Electrical Characteristics
Symbol
Parameter
Rise time
tr
Rev. 1.00
Conditions
CL = 50 pF
Min
4
Typ
—
Max
20
Unit
ns
tf
Fall time
CL = 50 pF
4
—
20
ns
tr/f
Rise time / fall time matching
tr/f = tr / tf
90
—
110
%
44 of 48
January 25, 2016
Electrical Characteristics
VDI
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
6
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the package information.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.00
45 of 48
January 25, 2016
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
48-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.0197 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
9.0 BSC
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.5 BSC
—
F
0.17
0.22
0.27
G
1.35
1.4
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
46 of 48
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352
64-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Min.
Nom.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
Max.
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
—
9.0 BSC
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.4 BSC
—
F
0.13
0.18
0.23
G
1.35
1.4
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
47 of 48
January 25, 2016
32-Bit ARM® Cortex™-M0+ MCU
HT32F52342/HT32F52352

Copyright© 2016 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
48 of 48
January 25, 2016