HT32F1656/HT32F1655 Series DataSheet

32-bit ARM® Cortex™-M3 Microcontroller,up to 256KB Flash and
32KB SRAM with 1 MSPS ADC, USART, UART, SPI, I2C, I2S, MCTM,
GPTM, BFTM, PDMA, SCI, CRC, EBI and USB2.0 FS
HT32F1656/HT32F1655 Series
DataSheet
Revision: V1.00
Date: �������������
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller........................................................................................................ 7
Reset Control Unit.................................................................................................................. 8
Clock Control Unit................................................................................................................... 8
Power Management................................................................................................................ 8
External Interrupt/Event Controller......................................................................................... 9
Analog to Digital Converter..................................................................................................... 9
Analog Operational Amplifier/Comparator.............................................................................. 9
I/O Ports................................................................................................................................ 10
PWM Generation and Capture Timers – GPTM................................................................... 10
Motor Control Timer – MCTM............................................................................................... 10
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer.................................................................................................................... 11
Real Time Clock.................................................................................................................... 11
Inter-integrated Circuit – I2C................................................................................................. 12
Serial Peripheral Interface – SPI.......................................................................................... 12
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 12
Universal Asynchronous Receiver Transmitter – UART....................................................... 13
Smart Card Interface – SCI.................................................................................................. 13
Inter-IC Sound – I2S............................................................................................................. 14
Cyclic Redundancy Check – CRC........................................................................................ 14
Peripheral Direct Memory Access – PDMA.......................................................................... 15
External Bus Interface – EBI................................................................................................. 15
Universal Serial Bus Device Controller – USB..................................................................... 16
Debug Support...................................................................................................................... 16
Package and Operation Temperature................................................................................... 16
3 Overview................................................................................................................. 17
Device Information................................................................................................................ 17
Block Diagram...................................................................................................................... 18
Memory Map......................................................................................................................... 19
Clock Structure..................................................................................................................... 20
Pin Assignment..................................................................................................................... 21
Rev. 1.00
2 of 48
July 24, 2014
Table of Contents
On-chip Memory..................................................................................................................... 7
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
4 Electrical Characteristics...................................................................................... 30
Absolute Maximum Ratings.................................................................................................. 30
Recommended DC Operating Conditions............................................................................ 30
On-Chip LDO Voltage Regulator Characteristics.................................................................. 30
Power Consumption............................................................................................................. 31
External Clock Characteristics.............................................................................................. 32
Internal Clock Characteristics............................................................................................... 33
PLL Characteristics............................................................................................................... 34
Memory Characteristics........................................................................................................ 34
I/O Port Characteristics......................................................................................................... 34
ADC Characteristics............................................................................................................. 36
Operational Amplifier/Comparator Characteristics................................................................ 38
GPTM/MCTM Characteristics............................................................................................... 38
I2C Characteristics................................................................................................................ 39
SPI Characteristics............................................................................................................... 40
I2S Characteristics................................................................................................................ 41
USB Characteristics.............................................................................................................. 43
5 Package Information............................................................................................. 44
48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 45
64-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 46
100-pin LQFP (14mm×14mm) Outline Dimensions.............................................................. 47
Rev. 1.00
3 of 48
July 24, 2014
Table of Contents
Reset and Supply Monitor Characteristics............................................................................ 32
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
List of Tables
Rev. 1.00
4 of 48
July 24, 2014
List of Tables
Table 1. HT32F1656/1655 Series Features and Peripheral List............................................................... 17
Table 2. HT32F1656/55 Series Pin Assignment for LQFP100 / 64 / 48 Package..................................... 24
Table 3. HT32F1656/55 Pin Description................................................................................................... 27
Table 4. Absolute Maximum Ratings......................................................................................................... 30
Table 5. Recommended DC Operating Conditions................................................................................... 30
Table 6. LDO Characteristics.................................................................................................................... 30
Table 7. Power Consumption Characteristics........................................................................................... 31
Table 8. LVD/BOD Characteristics............................................................................................................ 32
Table 9. High Speed External Clock (HSE) Characteristics...................................................................... 32
Table 10. Low Speed External Clock (LSE) Characteristics..................................................................... 32
Table 11. High Speed Internal Clock (HSI) Characteristics...................................................................... 33
Table 12. Low Speed Internal Clock (LSI) Characteristics........................................................................ 33
Table 13. PLL Characteristics................................................................................................................... 33
Table 14. Flash Memory Characteristics................................................................................................... 33
Table 15. I/O Port Characteristics............................................................................................................. 34
Table 16. ADC Characteristics.................................................................................................................. 35
Table 17. OPA/CMP Characteristics......................................................................................................... 37
Table 18. GPTM/MCTM Characteristics................................................................................................... 37
Table 19. I2C Characteristics..................................................................................................................... 38
Table 20. SPI Characteristics.................................................................................................................... 39
Table 21. I2S Characteristics..................................................................................................................... 40
Table 22. USB DC Electrical Characteristics............................................................................................ 42
Table 23 USB AC Electrical Characteristics.............................................................................................. 42
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
List of Figures
Rev. 1.00
5 of 48
July 24, 2014
List of Figures
Figure 1. HT32F1656/1655 Block Diagram.............................................................................................. 18
Figure 2. HT32F1656/1655 Memory Map................................................................................................. 19
Figure 3. HT32F1656/1655 Clock Structure............................................................................................. 20
Figure 4. HT32F1656/1655 LQFP-48 Pin Assignment............................................................................. 21
Figure 5. HT32F1656/1655 LQFP-64 Pin Assignment............................................................................. 22
Figure 6. HT32F1656/1655 LQFP-100 Pin Assignment........................................................................... 23
Figure 7. ADC Sampling Network Model.................................................................................................. 36
Figure 8. I2C Timing Diagrams.................................................................................................................. 38
Figure 9. SPI Timing Diagrams - SPI Master Mode.................................................................................. 39
Figure 10. SPI Timing Diagrams - SPI Slave Mode with CPHA=1........................................................... 40
Figure 11. Timing of I2S Master Mode....................................................................................................... 41
Figure 12. Timing of I2S Slave Mode........................................................................................................ 41
Figure 13. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition..................... 42
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
1
General Description
The Holtek HT32F1656/1655 devices are high performance, low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M3 processor core. The Cortex™-M3 is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and includes advanced debug support.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control, fingerprint
recognition and so on.
Rev. 1.00
6 of 48
July 24, 2014
General Description
The devices operate at a frequency of up to 72 MHz with a Flash accelerator to obtain maximum
efficiency. They provide up to 256 KB of embedded Flash memory for code/data storage and 32
KB of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as ADC, I2C, USART, UART, SPI, I2S, PDMA, GPTM, MCTM, SCI, EBI, CRC16/32, USB2.0 FS, SW-DP (Serial Wire Debug Port), etc., are also implemented in the devices.
Several power saving modes provide the flexibility for maximum optimisation between wakeup
latency and power consumption, an especially important consideration in low power applications.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
2
Features
Core
On-chip Memory
▀ Up to 256 KB on-chip Flash memory for instruction/data and option storage
▀ 32 KB on-chip SRAM
▀ Supports multiple boot modes
The ARM® Cortex™-M3 processor is structured using Harvard architecture which uses a separate
bus structure to fetch instructions and load/store data. The instruction code and data are both
located in the same memory address space but in different address ranges. The maximum address
range of the Cortex™-M3 is 4 GB due to its 32-bit bus address width. Additionally, a pre-defined
memory map is provided by the Cortex™-M3 processor to reduce the software complexity of
repeated implementation for different device vendors. However, some regions are used by the
ARM® Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference
Manual for more information. Figure 2 shows the memory map of the HT32F1656/55 series of
devices, including Code, SRAM, peripheral, and other pre-defined regions.
Flash Memory Controller
▀ Flash accelerator for maximum efficiency
▀ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
▀ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
Rev. 1.00
7 of 48
July 24, 2014
Features
®
▀ 32-bit ARM Cortex™-M3 processor core
▀ Up to 72 MHz operating frequency
▀ 1.25 DMIPS/MHz (Dhrystone 2.1)
▀ Single-cycle multiplication and hardware division
▀ Integrated Nested Vectored Interrupt Controller (NVIC)
▀ 24-bit SysTick timer
The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for
products requiring high performance and low power consumption microcontrollers. It offers many
special features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Reset Control Unit
▀ Supply supervisor:
● Power-on Reset - POR
● Brown-out Detector - BOD
● Programmable Low Voltage Detector - LVD
Clock Control Unit
▀ External 4 to 16 MHz crystal oscillator
▀ External 32,768 Hz crystal oscillator
▀ Internal 8MHz RC oscillator trimmed to ±2% accuracy at 3.3V operating voltage and 25°C operating
temperature
▀ Internal 32 kHz RC oscillator
▀ Integrated system clock PLL
▀ Independent clock gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers and clock gating circuitry.
The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock (CK_SYS)
which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use
either the LSI or LSE as their clock source. The maximum operating frequency of the system core
clock (CK_AHB) can be up to 72 MHz.
Power Management
▀ Single 3.3 V power supply: 2.7 V to 3.6 V
▀ Integrated 1.8 V LDO regulator for core and peripheral power supply
▀ VBAT battery power supply for RTC and backup registers
▀ Three power domains: 3.3 V, 1.8 V and Backup
▀ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
Rev. 1.00
8 of 48
July 24, 2014
Features
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
External Interrupt/Event Controller
Analog to Digital Converter
▀ 12-bit SAR ADC engine
▀ Up to 1 Msps conversion rate - 1 μs at 56 MHz, 1.17 μs at 72 MHz
▀ Up to 16 external analog input channels
▀ Supply voltage range: 2.7 V ~ 3.6 V
▀ Conversion range: VREF+ ~ VREFA 12-bit multi-channel ADC is integrated in the device. There are up to 16 multiplexed channels,
which include external channels on which the external analog signals can be measured, and 2
internal channels. If the input voltage is required to remain within a specific threshold window,
an Analog Watchdog function will monitor and detect these signals. An interrupt will then be
generated to inform the device that the input voltage is not within the preset threshold levels. There
are three conversion modes to convert an analog signal to digital data. The ADC can be operated in
one shot, continuous and discontinuous conversion modes.
Analog Operational Amplifier/Comparator
▀ Two Operational Amplifiers or Comparator functions which are software configurable
▀ Supply voltage range: 2.7 V ~ 3.6 V
Two Operational Amplifiers/Comparators (OPA/CMP) are implemented within the devices. They
can be configured either as Operational Amplifiers or as Analog Comparators. When configured as
comparators, they are capable of generating interrupts to the NVIC.
Rev. 1.00
9 of 48
July 24, 2014
Features
▀ Up to 16 EXTI lines with configurable trigger source and type
▀ All GPIO pins can be selected as EXTI trigger source
▀ Source trigger type includes high level, low level, negative edge, positive edge, or both edge
▀ Individual interrupt enable, wakeup enable and status bits for each EXTI line
▀ Software interrupt trigger mode for each EXTI line
▀ Integrated deglitch filter for short pulse blocking
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. Each EXTI line can also be masked
independently.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
I/O Ports
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins.
The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit, EXTI.
PWM Generation and Capture Timers – GPTM
▀ Two 16-bit General-Purpose Timers - GPTM
▀ Up to 4-channel with PWM, Compare Output or Input Capture function for each GPTM
▀ External trigger input
The General Purpose Timers, known as GPTM0 and GPTM1, consist of one 16-bit up/downcounter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter Reload Register (CRR)
and several control/status registers. They can be used for a variety of purposes including general
time measurement, input signal pulse width measurement, output waveform generation such as
single pulse generation, or PWM output generation. The GPTM supports an Encoder Interface
using a decoder with two inputs.
Motor Control Timer – MCTM
▀ Two 16-bit up, down, up/down auto-reload counters
▀ 16-bit programmable prescaler allowing division of the counter clock frequency by any factor
between 1 and 65536
▀ Input Capture function
▀ Compare Match Output
▀ PWM waveform generation with edge aligned and centre-aligned Counting Modes
▀ Single Pulse Mode Output
▀ Complementary Outputs with programmable dead-time insertion
▀ Encoder interface controller with two inputs using quadrature decoder
▀ Supports 3-phase motor control and hall sensor interface
▀ Brake input to force the timer’s output signals into a reset or fixed condition
The Motor Control Timer consists of a single 16-bit up/down counter; four 16-bit CCRs (Capture/
Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit repetition counter
and several control/status registers. It can be used for a variety of purposes including measuring
the pulse widths of input signals or generating output waveforms such as compare match outputs,
PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM supports an
Encoder interface controller to an incremental encoder with two inputs. The MCTM is capable of
offering full functional support for motor control, hall sensor interfacing and brake input.
Rev. 1.00
10 of 48
July 24, 2014
Features
▀ Up to 80 GPIOs
▀ Port A, B, C, D, E are mapped as 16 external interrupts - EXTI
▀ Almost all I/O pins are 5 V-tolerant except for pins shared with analog inputs
There are up to 80 General Purpose I/O pins, GPIO, named from PA0~PA15 to PE0~PE15 for
the implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximise flexibility and to meet the requirements of a wide
range of applications.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Basic Function Timer – BFTM
Watchdog Timer
▀ 12-bit down counter with 3-bit prescaler
▀ Interrupt or reset event for the system
▀ Programmable watchdog timer window function
▀ Register write protection function
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to
software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value
register, a WDT delta value register, interrupt related circuits, WDT operation control circuitry
and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or
a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts
down and reaches a zero value. If the software does not reload the counter value before a Watchdog
Timer underflow occurs, an interrupt or a reset will be generated when the counter underflows. In
addition, an interrupt or reset is also generated if the software reloads the counter when the counter
value is greater than or equal to the WDT delta value. This means the counter must be reloaded
within a limited timing window using a specific method. The Watchdog Timer counter can be
stopped while the processor is in the debug mode. There is a register write protect function which
can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
Real Time Clock
▀ 32-bit up-counter with a programmable prescaler
▀ Alarm function
▀ Interrupt and Wake-up event
The Real Time Clock, RTC for short, includes an APB interface, a 32-bit count-up counter, a
control register, a prescaler, a compare register and a status register. Most of the RTC circuits are
located in the Backup Domain except for the APB interface. The APB interface is located in the
VDD18 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from
the power control unit when the V DD18 power domain is powered off, that is when the device enters
the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume
signal from the Power-Down mode.
Rev. 1.00
11 of 48
July 24, 2014
Features
▀ Two 32-bit compare/match count-up counters - no I/O control features
▀ One shot mode - counting stops after a match condition
▀ Repetitive mode - restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Inter-integrated Circuit – I2C
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I2C module also has
an arbitration detect function and clock synchronisation to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
Serial Peripheral Interface – SPI
▀ Supports both master and slave mode
▀ Frequency of up to 36 MHz for master mode and 24MHz for slave mode
▀ FIFO Depth: 8 levels
▀ Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
Universal Synchronous Asynchronous Receiver Transmitter – USART
▀
▀
▀
▀
▀
▀
▀
▀
▀
Rev. 1.00
Supports both asynchronous and clocked synchronous serial communication modes
Asynchronous operating baud rate up to 4.5 MHz and synchronous operating rate up to 9 MHz
Full duplex communication
Fully programmable serial communication characteristics including:
● Word length: 7, 8, or 9-bit character
● Parity: Even, odd, or no-parity bit generation and detection
● Stop bit: 1 or 2 stop bit generation
● Bit order: LSB-first or MSB-first transfer
Error detection: Parity, overrun, and frame error
Auto hardware flow control mode - RTS, CTS
IrDA SIR encoder and decoder
RS485 mode with output enable control
FIFO Depth: 16 x 9 bits for both receiver and transmitter
12 of 48
July 24, 2014
Features
▀ Supports both master and slave modes with a frequency of up to 1 MHz
▀ Provide an arbitration function and clock synchronisation
▀ Supports 7-bit and 10-bit addressing modes and general call addressing
▀ Supports slave multi-addressing mode with maskable address
The I2C Module is an internal circuit allowing communication with an external I2C interface which
is an industry standard two line serial interface used for connection to external hardware. These
two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
provides three data transfer rates: 1. 100 kHz in the Standard mode, 2. 400 kHz in the Fast mode
and 3. 1 MHz in the Fast mode plus mode. The SCL period generation register is used to setup
different kinds of duty cycle implementations for the SCL pulse.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Universal Asynchronous Receiver Transmitter – UART
▀ Asynchronous serial communication operating baud-rate up to 4.5 MHz
▀ Full duplex communication
▀ Fully programmable serial communication characteristics including:
● Word length: 7, 8, or 9-bit character
● Parity: Even, odd, or no-parity bit generation and detection
● Stop bit: 1 or 2 stop bit generation
● Bit order: LSB-first or MSB-first transfer
▀ Error detection: Parity, overrun, and frame error
▀ FIFO Depth: 16 x 9 bits for both receiver and transmitter
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports four types of interrupt including Line Status Interrupt, Transmitter FIFO Empty
Interrupt, Receiver Threshold Level Reaching Interrupt and Time Out Interrupt. The UART
module includes a 16-byte transmitter FIFO, (TX_FIFO) and a 16-byte receiver FIFO (RX_
FIFO). The software can detect a UART error status by reading the Line Status Register, LSR. The
status includes the type and the condition of transfer operations as well as several error conditions
resulting from Parity, Overrun, Framing and Break events.
Smart Card Interface – SCI
▀ Supports ISO 7816-3 standard
▀ Character mode
▀ Single transmit buffer and single receive buffer
▀ 11-bit ETU (elementary time unit) counter
▀ 9-bit guard time counter
▀ 24-bit general purpose waiting time counter
▀ Parity generation and checking
▀ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.
Rev. 1.00
13 of 48
July 24, 2014
Features
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a 16-byte transmitter FIFO, (TX_FIFO) and
a 16-byte receiver FIFO (RX_FIFO). The software can detect a USART error status by reading the
Line Status Register, LSR. The status includes the type and the condition of transfer operations as
well as several error conditions resulting from Parity, Overrun, Framing and Break events.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Inter-IC Sound – I2S
Cyclic Redundancy Check – CRC
▀ Supports CRC16 polynomial: 0x8005,
X16+X15+X2+1
▀ Supports CCITT CRC16 polynomial: 0x1021,
X16+X12+X5+1
▀ Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7,
X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1
▀ Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
▀ Supports byte, half-word & word data size
▀ Programmable CRC initial seed value
▀ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32bit data
Supports
PDMA to complete a CRC computation of a block of memory
▀
The CRC calculation unit is an error detection technique test algorithm which is used to verify data
transmission or storage data correctness. A CRC calculation takes a data stream or a block of data
as input and generates a 16- or 32-bit output remainder. Ordinarily, a data stream is suffixed by a
CRC code and used as a checksum when being sent or stored. Therefore, the received or restored
data stream is calculated by the same generator polynomial as described above. If the new CRC
code result does not match the one calculated earlier, that means data stream contains a data error.
Rev. 1.00
14 of 48
July 24, 2014
Features
▀ Master or slave mode
▀ Mono and stereo
2
▀ I S-justified, Left-justified, and Right-justified mode
▀ 8/16/24/32-bit sample size with 32-bit channel extended
▀ 8 x 32-bit Tx & Rx FIFO with PDMA supported
▀ 8-bit Fractional Clock Divider with rate control
The I2S is a synchronous communication interface that can be used as a master or slave to
exchange data with other audio peripherals, such as ADCs or DACs. The I2S supports a variety of
data formats. In addition to the stereo I2S-justified, Left-justified and Right-justified modes, there
are mono PCM modes with 8/16/24/32-bit sample size. When the I2S operates in the master mode,
then when using the fractional divider, it can provide an accurate sampling frequency output and
support the rate control function and fine-tuning of the output frequency to avoid system problems
caused by the cumulative frequency error between different devices.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Peripheral Direct Memory Access – PDMA
8 channels with trigger source grouping
8-/16-/32-bit width data transfer
Supports Address increment, decrement or fixed mode
4-level programmable channel priority
Auto reload mode
Supports trigger source: ADC, SPI, USART, UART, I2C, I2S, EBI, GPTM, MCTM, SCI and
software request
The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals
and the system memory on the AHB bus. Each PDMA channel has a source address, destination
address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid
interrupt service routine execution. It improves system performance as the software does not need
to join each data movement operation.
External Bus Interface – EBI
▀
▀
▀
▀
▀
▀
Programmable interface for various memory types
Translate the AHB transactions into the appropriate external device protocol
Memory bank regions and independent chip select control for each memory bank
Programmable timings to support a wide range of devices
Includes page read mode
Automatic translation when the AHB transaction width and external memory interface width is
different
Write buffer to decrease the stalling of the AHB write burst transaction
Supports multiplexed and non-multiplexed address and data line configurations
Up to 25 address lines
Up to 16-bit data bus width
▀
▀
▀
▀
The external bus interface is able to access external parallel interface devices such as SRAM,
Flash and LCD modules. The interface is memory mapped into the internal address map of
the Cortex-M3. The data and address lines can be multiplexed in order to reduce the number
of pins required to connect to the external devices. Tthe read/write timing of the bus can be
adjusted to meet the timing specification of the external devices. Note the interface only supports
asynchronous 8 or 16-bit bus interface.
Rev. 1.00
15 of 48
July 24, 2014
Features
▀
▀
▀
▀
▀
▀
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Universal Serial Bus Device Controller – USB
Debug Support
▀ Serial Wire Debug Port - SW-DP
▀ 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal
patches
▀ 4 comparators for hardware watchpoints
▀ 1-bit asynchronous trace (TRACESWO)
Package and Operation Temperature
▀ 48/64/100-pin LQFP package
▀ Operation temperature range: -40°C to +85°C
Rev. 1.00
16 of 48
July 24, 2014
Features
▀ Complies with USB 2.0 full-speed (12Mbps) specification
▀ On-chip USB full-speed transceiver
▀ 1 control endpoint (EP0) for control transfer
▀ 3 single-buffered endpoints for bulk and interrupt transfer
▀ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
▀ 1,024 bytes EP-SRAM used as the endpoint data buffers
The USB device controller is compliant with the USB 2.0 full-speed specification. There is one
control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM
is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding
registers, which provides maximum flexibility for various applications. The integrated USB fullspeed transceiver helps to minimise the overall system complexity and cost. The USB functional
block also contains the resume and suspend feature to meet the requirements of low-power
consumption.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
3
Overview
Device Information
Table 1. HT32F1656/1655 Series Features and Peripheral List
Peripherals
HT32F1655
128
Option Bytes Flash
1
1
SRAM (KB)
32
32
Communication
Timers
255
MCTM
2
GPTM
2
BFTM
2
RTC
1
WDT
1
USB
1
SPI
2
USART
2
UART
2
IC
2
IS
1
SCI
1
2
2
EBI
1
CRC-16/32
1
EXTI
16
12-bit ADC
Number of channels
1
OPA/Comparator
2
Overview
Rev. 1.00
HT32F1656
Main Flash (KB)
16 Channels
GPIO
Up to 80
CPU frequency
Up to 72 MHz
Operating voltage
2.7V ~ 3.6V
Operating temperature
-40℃ ~ +85℃
Packages
48/64/100-pin LQFP
17 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Block Diagram
TRACESWO
BOOT0
BOOT1
SWCLK SWDIO
AF
Powered b� V DD18
SW-DP
MPU
F�ash Memor�
Interface
fMax: 7� MHz
PDMA
Contro�
Registers
VSS33
VLDOOUT
LDO
1.8 V
VDD18
BOD
LVD
USB
Device
Powered b� VDD33
AF
WDT
UART0
USART1
AF
SPI0
UART1
AF
I�C 0 ~ 1
BFTM 0 ~ 1
AF
AF
...
AF
Ana�og
OPA/CMP
RTC
ADC
CH3 ~ CH0
ETI
AF
SCI
1�-bit
SAR ADC
SDA
SCL
Power contro�
APB1
AF
MCTM1
GPTM 0 ~ 1
APB0
MCTM0
TX� RX
MOSI� MISO
SCK� SEL
AF
AFIO
TX� RX
RTS/TXE
CTS/SCK
AF
SPI1
AD0~AD15
A0~A��
CS0~CS3
OE� WR
ALE� RDY
BL0~BL1
DP
DM
AF
I�S
XTALIN
XTALOUT
VDD33
HSI
8 MHz
USART0
ADC_IN15
CN0� CP0
AOUT0
CN1� CP1
AOUT1
VDDA
VSSA
� ~ 16 MHz
AF
DMA req�est
AHB to APB
Bridge
AF
ADC_IN0
SRAM
AF
8 Channe�s
EXTI
CH0 ~CH�
CH0N ~ CH�N
CH3� ETI� BRK
HSE
Externa� B�s
Interafce
PDMA
MCLK� BCLK
WS� SDO� SDI
CH0 ~CH�
CH0N ~ CH�N
CH3� ETI� BRK
USB
Contro�/Data
Registers
AF
MOSI� MISO
SCK� SEL
CKCU/RSTCU
Contro� Registers
CRC
-16/3�
C�ock and reset contro�
Interr�pt req�est
SRAM
Contro��er
GPIO
A~E
AF
TX� RX
PLL
AF
TX� RX
RTS/TXE
CTS/SCK
FMC
Contro�
Registers
AHB
Periphera�s
B�s Matrix
NVIC
1.8 V
fMax: 1�� MHz
DCode S�stem
CortexTM-M3
Processor
POR
F�ash
Memor�
CLK� DIO�
DET
RTCOUT
PWRSW
VBAT
VBAK
PWRCU
OPA/CMP
VDD33
VSS33
PORB
Powered b� V DDA
BREG
3� kHz
LSE
WAKEUP
3��768 Hz
nRST
Back�p Domain
Powered b� V DD18
AF
VBAK 3.3 V
LSI
AF
XTAL3�KIN
XTAL3�KOUT
Power s�pp��:
B�s:
Contro� signa�:
A�ternate f�nction:
AF
Figure 1. HT32F1656/1655 Block Diagram
Rev. 1.00
18 of 48
July 24, 2014
Overview
ICode
TPIU
PA ~ PE[15:0]
AF
AF
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Memory Map
0xFFFF_FFFF
Reserved
0xE010_0000
0x7000_0000
Private peripheral bus
Reserved
EBI Selection Bank
64 MB x 4
0x6000_0000
0x4400_0000
Peripheral
0x4200_0000
0x4010_0000
0x4008_0000
0x4000_0000
0x2220_0000
Reserved
APB/AHB bit band alias
32 MB
Reserved
AHB peripherals
512 KB
APB peripherals
512 KB
Reserved
SRAM bit band alias
SRAM
2 MB
0x2200_0000
0x2000_8000
Reserved
32 KB on-chip SRAM
32 KB
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_2000
0x1F00_0000
Code
0x0004_0000
Reserved
Option byte alias
1 KB
Reserved
Boot loader
8 KB
Reserved
Up to
256 KB on-chip Flash
Up to
256 KB
0x0000_0000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_2000
0x4000_1000
0x4000_0000
Reserved
GPIOA,B,C,D,E
Reserved
USB SRAM
USB
Reserved
EBI
Reserved
PDMA
Reserved
CRC
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM1
BFTM0
Reserved
GPTM1
GPTM0
Reserved
RTC/PWRCU
Reserved
WDT
Reserved
I2C1
I2C0
Reserved
SPI1
SCI
Reserved
UART1
USART1
Reserved
MCTM1
MCTM0
Reserved
I2S
Reserved
EXTI
Reserved
AFIO
Reserved
OPA/CMP
Reserved
ADC
Reserved
SPI0
Reserved
UART0
USART0
AHB
APB1
APB0
Figure 2. HT32F1656/1655 Memory Map
Rev. 1.00
19 of 48
July 24, 2014
Overview
0xE000_0000
0x400F_FFFF
0x400B_A000
0x400B_0000
0x400A_C000
0x400A_A000
0x400A_8000
0x4009_A000
0x4009_8000
0x4009_2000
0x4009_0000
0x4008_C000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
0x4007_8000
0x4007_7000
0x4007_6000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_A000
0x4004_9000
0x4004_8000
0x4004_5000
0x4004_4000
0x4004_3000
0x4004_2000
0x4004_1000
0x4004_0000
0x4002_E000
0x4002_D000
0x4002_C000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_9000
0x4001_8000
0x4001_1000
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Clock Structure
Divider
÷2
Prescaler
÷ 1~32
CK_REF
CKREFPRE
CKREFEN
Prescaler
÷ 1,2,3
fCK_USB,max = 48MHz
CK_USB
USBEN
PLLSRC
8 MHz
HSI RC
1
HSIEN
PLLEN
f CK_PLL,max = 144MHz
URnEN
CK_PLL
PLL
0
÷8
fCK_SYS,max = 144MHz
0x
CK_HSI
11
CK_HSE
CK_SYS
CK_LSE
LSEEN(Note1)
32 kHz
LSI RC
STCLK
(to SysTick)
CK_GPIO
( to GPIO port)
GPIOAEN
GPIOEEN
AHB
Prescaler
÷ 1,2,4,8
FCLK
( free running clock)
10
HCLKC
( to CortexTM-M3)
CM3EN
(control by HW)
CK_AHB
Clock
Monitor
32.768 kHz
LSE OSC
fCK_USARTn,max = 72MHz
CK_USART0
CK_USART1
CK_UART0
CK_UART1
SW[1:0]
4-16 MHz
HSE XTAL
HSEEN
Prescaler
÷ 1,2
PDMAEN
HCLKD
( to PDMA)
EBIEN
CK_EBI
( to EBI)
CRCEN
CK_CRC
( to CRC)
WDTSRC
1
0
CK_LSI
CK_WDT
WDTEN
RTCSRC(Note1)
LSIEN(Note1)
HCLKF
( to Flash)
CM3EN
1
0
FMCEN
CK_RTC
HCLKS
( to SRAM)
RTCEN
(Note1)
CM3EN
SRAMEN
CKOUTSRC[2:0]
CKOUT
HCLKBM
( to Bus Matrix)
000
CK_REF
001
010
CK_AHB/16
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
CM3EN
BMEN
HCLKAPB0
( to APB0 Bridge)
CM3EN
APB0EN
HCLKAPB1
( to APB1 Bridge)
CM3EN
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
APB1EN
PCLK ( OPAx, AFIO,
ADC, SPIx, USARTx,
UARTx, I2Cx, I2S,
GPTMx, MCTMx,
BFTMx, EXTI, RTC,
SCI, WDT)
OPA0EN
Note 1: Those control bits are located at RTC Control Register
(RTC_CTRL)
WDTREN
ADC
Prescaler
÷ 2,4,6,8,16...
CK_ADC
ADCEN
Figure 3. HT32F1656/1655 Clock Structure
Rev. 1.00
20 of 48
July 24, 2014
Overview
fCK_AHB,max = 72MHz
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Pin Assignment
Holtek HT32F1656/1655
LQFP-48
5
33V
PA5
6
33V
PA6
7
33V
PA7
8
33V
VDD33_1
9
P33
VSS33_1
10
P33
USBDM
/PB12
USBDP
/PB13
11
1�
�7
�6
�5
��
�3
��
�1
�0
39
38
37
AP
AP
33V
33V
33V
33V
33V
33V
5VT
5VT
5VT
5VT
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P18
1.8 V Power Pad
33V
3.3 V I/O Pad
5VT
5 V Tolerance I/O Pad
5VT
High Current Output
5 V Tolerance I/O Pad
USB
USB PHY Pad
USB
USB
BAK
Backup Domain Pad
P33
BAK
5VT
BAK BAK
P33 33V
BAK
33V
BAK
5VT
33V
33V
P33
P33
13
1�
15
16
17
19
�0
�1
��
�3
��
VLDOOUT
VLDOIN
VSSLDO
nRST
VBAT
RTCOUT
XTALIN
XTALOUT
VDD33_2
VSS33_2
PC15
PB14
PB15
18
P33
36
VSS33_3
P33
35
VDD33_3
5VT
3�
PB1
5VT
33
PB0
5VT
3�
PA15
5VT
31
PA14
5VT
30
SWDIO
PA13
5VT
�9
SWCLK
PA12
5VT
�8 TRACESWO
5VT
�7
5VT
�6
5VT
�5
PA11
PA10
PA9_
BOOT1
PA8_
BOOT0
XTAL32K
OUT
XTAL32K
IN
PC14
PC13
AF1
P33
AF1
AF0
(Default)
P18
AF0
(Default)
Figure 4. HT32F1656/1655 LQFP-48 Pin Assignment
Rev. 1.00
21 of 48
July 24, 2014
Overview
PA4
�8
AF0
(Default)
33V
PB2
�
PB3
PA3
PB4
33V
PB5
3
PB6
PA2
PB7
33V
PB8
�
PB9
PA1
PB10
33V
PB11
1
VDDA
PA0
VSSA
AF0
(Default)
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Holtek HT32F1656/1655
LQFP-64
PB11
PB10
PB9
PB8
PB7
PB6
VSS33_4
VDD33_4
PC8
PC7
PB5
PB4
PB3
PB2
63
6�
61
60
59
58
57
56
55
5�
53
5�
51
50
�9
AP
AP
33V
33V
33V
33V
33V
33V
P33
P33
5VT
5VT
5VT
5VT
5VT
5VT
AF0
(Default)
PA0
1
33V
5VT
�8
PC6
PA1
�
33V
5VT
�7
PC5
PA2
3
33V
5VT
�6
PC4
PA3
�
33V
5VT
�5
PB1
PA4
5
33V
5VT
��
PB0
PA5
6
33V
P33
�3
VSS33_3
PA6
7
33V
P33
��
VDD33_3
PA7
8
33V
5VT
�1
PA15
VDD33_1
9
P33
VSS33_1
10
P33
PC9
11
33V
PC10
1�
33V
PC11
13
33V
1�
33V
15
USB
16
USB
PC12
USBDM
/PB12
USBDP
/PB13
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P18
1.8 V Power Pad
33V
3.3 V I/O Pad
AF1
5VT
5 V Tolerance I/O Pad
5VT
�0
PA14
High Current Output
5 V Tolerance I/O Pad
5VT
5VT
39
SWDIO
PA13
5VT
38
SWCLK
PA12
USB
USB PHY Pad
5VT
37 TRACESWO
Backup Domain Pad
5VT
BAK
36
5VT
35
5VT
3�
5VT
33
5VT
5VT
5VT
�3
��
�5
�6
�7
�8
�9
30
31
3�
VDD33_2
VSS33_2
PC0
PC1
PC2
PB15
�0
�1
��
PA9_
BOOT1
PA8_
BOOT0
PC3
PC14
PC13
AF1
P33
PA10
AF0
(Default)
P33
PC15
33V
XTALOUT
19
VBAT
33V
PB14
18
nRST
5VT
XTALIN
17
VSSLDO
BAK
5VT
PD0
P33
VLDOIN
BAK
33V
RTCOUT
P33
VLDOOUT
BAK BAK
P33 33V
XTAL32K
OUT
XTAL32K
IN
P18
BAK
5VT
PA11
Figure 5. HT32F1656/1655 LQFP-64 Pin Assignment
Rev. 1.00
22 of 48
July 24, 2014
Overview
VDDA
6�
AF0
(Default)
VSSA
AF0
(Default)
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Holtek HT32F1656/1655
LQFP-100
78
77
76
5VT
5VT
5VT
5VT
AF0
(Default)
PA0
1
33V
5VT
75
PE0
PA1
�
33V
5VT
7�
PD15
PA2
3
33V
5VT
73
PD14
PA3
�
33V
5VT
7�
PD13
PA4
5
33V
5VT
71
PD12
PA5
6
33V
5VT
70
PD11
PA6
7
33V
5VT
69
PD10
PA7
8
33V
5VT
68
PD9
PE8
9
33V
5 V Tolerance I/O Pad
5VT
67
PC6
PE9
10
33V
66
PC5
PE10
11
33V
High Current Output
5 V Tolerance I/O Pad
5VT
5VT
65
PC4
PE11
1�
33V
USB PHY Pad
5VT
6�
PB1
PE12
13
33V
5VT
63
PB0
VDD33_1
1�
P33
P33
6�
VSS33_3
P33
AP
P18
33V
5VT
5VT
USB
BAK
3.3 V Digital Power Pad
3.3 V Analog Power Pad
1.8 V Power Pad
3.3 V I/O Pad
Backup Domain Pad
AF1
VSS33_1
15
P33
P33
61
VDD33_3
PC9
16
33V
5VT
60
PA15
PC10
17
33V
5VT
59
PA14
PC11
18
33V
5VT
58
SWDIO
PA13
PC12
19
33V
5VT
57
SWCLK
PA12
PD6
�0
33V
5VT
56 TRACESWO
PB12
�1
33V
5VT
55
USBDM
��
USB
5VT
5�
USBDP
�3
USB
5VT
53
PB13
��
33V
5VT
5�
PD8
NC
�5
5VT
51
PD7
33V
33V
P33
P33
5VT
5VT
5VT
5VT
5VT
5VT
5VT
5VT
5VT
35
36
37
38
39
�0
�1
��
�3
��
�5
�6
�7
�8
�9
50
PE13
PE14
PE15
XTALIN
XTALOUT
VDD33_2
VSS33_2
PD1
PD2
PD3
PD4
PD5
PC0
PC1
PC2
PC3
PB14
PB15
AF1
5VT
3�
PA9_
BOOT1
PA8_
BOOT0
AF0
(Default)
5VT
33
PC15
nRST
VBAT
5VT
3�
PD0
VLDOIN
VSSLDO
5VT
31
PC14
30
RTCOUT
�9
PC13
BAK BAK BAK BAK BAK
5VT P33 33V 33V 5VT
�8
XTAL32KIN
P33
�7
XTAL32KOUT
P33
�6
VLDOOUT
P18
PA11
PA10
Figure 6. HT32F1656/1655 LQFP-100 Pin Assignment
Rev. 1.00
23 of 48
July 24, 2014
Overview
79
5VT
PB2
80
5VT
PB3
81
5VT
PB4
8�
5VT
PC7
83
5VT
PB5
8�
P33
PC8
85
P33
PE1
86
5VT
PE2
87
5VT
PE3
88
5VT
AF0
(Default)
VSS33_4
VDD33_4
89
5VT
PE4
90
33V
PE5
91
33V
PE6
9�
33V
PE7
93
33V
PB6
9�
33V
PB7
95
33V
PB8
96
AP
PB9
97
AP
AP
PB10
VDDA
98
AP
PB11
VREF-
VREF+
100 99
VSSA
AF0
(Default)
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Table 2. HT32F1656/55 Series Pin Assignment for LQFP100 / 64 / 48 Package
Alternate function number
Package
AF0
LQFP LQFP LQFP
-100
-64
-48
System
Default
AF1
GPIO
AF2
ADC
AF3
AF4
CMP
MCTM
/GPTM
AF5
AF6
SPI
USART
/UART
AF7
I2C
AF8
SMC
AF9
EBI
AF10
I2S
1
1
PA0
ADC_IN0
GT1_CH0
USR0_RTS I2C1_SCL
SCI_CLK
I2S_WS
2
2
2
PA1
ADC_IN1
GT1_CH1
USR0_CTS I2C1_SDA
SCI_DIO
I2S_
BCLK
3
3
3
PA2
ADC_IN2
GT1_CH2
USR0_TX
I2S_
SDO
4
4
4
PA3
ADC_IN3
GT1_CH3
USR0_RX
I2S_SDI
5
5
5
PA4
ADC_IN4
GT0_CH0
SPI0_SCK
USR1_TX
I2C0_SCL
6
6
6
PA5
ADC_IN5
GT0_CH1
SPI0_MOSI USR1_RX
I2C0_SDA
7
7
7
PA6
ADC_IN6
GT0_CH2
SPI0_MISO USR1_RTS
8
8
8
PA7
ADC_IN7
GT0_CH3
SPI0_SEL
USR1_CTS
9
PE8
ADC_IN8
SPI1_SEL
USR0_RTS
10
PE9
ADC_IN9
SPI1_SCK
USR0_CTS
11
PE10
ADC_IN10
SPI1_MOSI USR0_TX
12
PE11
ADC_IN11
SPI1_MISO USR0_RX
13
PE12
ADC_IN12
14
9
9
VDD33_1
15
10
10
VSS33_1
16
11
PC9
ADC_IN13
GT0_CH0
SPI1_SEL
UR0_TX
I2C1_SCL
12
PC10
ADC_IN14
GT0_CH1
SPI1_SCK
UR0_RX
I2C1_SDA
18
13
PC11
ADC_IN15
GT0_CH2
SPI1_MOSI
19
14
PC12
GT0_CH3
SPI1_MISO
PD6
GT0_ETI
MT1_CH2
I2C0_SCL
MT1_
CH2N
I2C0_SDA
MT1_ETI
I2C0_SDA
EBI_
A18
I2S_SDI
I2C0_SCL
EBI_
A19
I2S_
MCLK
EBI_
A20
I2S_WS
21
15
11
PB12
22
15
11
USBDM
23
16
12
USBDP
24
16
12
PB13
26
17
13
VLDOOUT
27
18
14
VLDOIN
28
19
15
VSSLDO
29
20
16
nRST
30
21
17
VBAT
31
22
18
XTAL32KIN
32
23
19
XTAL32KOUT PC14
33
24
20
RTCOUT
34
25
25
N/A
N/A
AF15
N/A
System
Other
I2S_
MCLK
17
20
N/A
AF14
Overview
1
AF11 AF12 AF13
EBI_
ARDY
N.C.
PC13
PC15_
WAKEUP
PD0
35
PE13
36
PE14
GT1_ETI
37
PE15
GT1_CH0
38
26
21
XTALIN
PB14
39
27
22
XTALOUT
PB15
40
28
23
VDD33_2
Rev. 1.00
UR0_TX
24 of 48
EBI_
A21
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Alternate function number
Package
AF0
LQFP LQFP LQFP
-100
-64
-48
41
29
24
System
Default
AF1
GPIO
AF2
ADC
AF3
AF4
CMP
MCTM
/GPTM
AF5
AF6
AF7
AF8
AF9
AF10
SPI
USART
/UART
IC
SMC
EBI
IS
EBI_
A22
I2S_
BCLK
2
2
GT1_CH1
43
PD2
GT1_CH2
EBI_
A23
I2S_
SDO
GT1_CH3
EBI_
A24
I2S_SDI
PD4
MT1_CH0 SPI0_SEL
I2C1_SCL
EBI_
A16
I2S_
MCLK
PD5
MT1_
CH0N
SPI0_SCK
I2C1_SDA
EBI_
A17
PD3
46
UR0_RX
47
30
PC0
GT1_CH0
SPI1_SEL
EBI_
AD13
I2S_WS
48
31
PC1
GT1_CH1
SPI1_SCK
EBI_
AD14
I2S_
BCLK
49
32
PC2
GT1_CH2
SPI1_MOSI UR1_TX
I2C0_SCL
EBI_
AD15
I2S_
SDO
50
33
PC3
GT1_CH3
SPI1_MISO UR1_RX
I2C0_SDA
EBI_
CS3
I2S_SDI
51
PD7
I2C1_SCL
EBI_
SCI_CLK
A2
52
PD8
I2C1_SDA
SCI_DIO
53
34
25
PA8_BOOT0
I2S_
MCLK
USR0_TX
I2S_WS
EBI_
A0
I2S_
MCLK
35
26
PA9_BOOT1
36
27
PA10
56
37
28
TRACESWO
PA11
57
38
29
SWCLK
PA12
58
39
30
SWDIO
PA13
59
40
31
PA14
MT0_CH0 SPI1_SEL
USR1_TX
SCI_CLK
EBI_
AD0
PA15
MT0_
CH0N
USR1_RX
SCI_DIO
EBI_
AD1
61
42
62
43
63
44
64
45
65
46
32
SPI0_MOSI
EBI_
A1
55
41
N/A
N/A
EBI_
A0
54
60
N/A
AF15
System
Other
MT1_CH1
MT1_
CH1N
USR0_RX
CKOUT
SCI_DET
SPI0_MISO
SPI1_SCK
Overview
PD1
45
N/A
AF14
VSS33_2
42
44
AF11 AF12 AF13
TRACESWO
VDD33_3
VSS33_3
33
34
PB0
MT0_CH1 SPI1_MOSI USR0_TX
I2C0_SCL
EBI_
AD2
PB1
MT0_
CH1N
I2C0_SDA
EBI_
AD3
PC4
MT1_CH2
USR1_RTS
SCI_CLK
EBI_
AD10
USR1_CTS
SCI_DIO
EBI_
AD11
SCI_DET
EBI_
AD12
66
47
PC5
MT1_
CH2N
67
48
PC6
MT1_CH3
SPI1_MISO USR0_RX
68
PD9
SPI0_SEL
EBI_
A3
69
PD10
SPI0_SCK
EBI_
A4
70
PD11
SPI0_MOSI
EBI_
A5
71
PD12
SPI0_MISO
EBI_
A6
72
PD13
SPI1_SEL
EBI_
A7
73
PD14
SPI1_SCK
EBI_
A8
74
PD15
SPI1_MOSI
EBI_
A9
SPI1_MISO
EBI_
A10
75
PE0
35
VDD33_3
36
VSS33_3
EBI_
AD4
76
49
37
PB2
MT0_CH2 SPI0_SEL
UR0_TX
77
50
38
PB3
MT0_
CH2N
UR0_RX
EBI_
AD5
SPI0_SCK
78
51
39
PB4
MT0_BRK SPI0_MOSI UR1_TX
EBI_
AD6
79
52
40
PB5
MT1_BRK SPI0_MISO UR1_RX
EBI_
AD7
Rev. 1.00
25 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Alternate function number
Package
AF0
LQFP LQFP LQFP
-100
-64
-48
System
Default
AF1
GPIO
AF2
ADC
AF3
AF4
CMP
MCTM
/GPTM
AF5
AF6
AF7
AF8
AF9
AF10
SPI
USART
/UART
IC
SMC
EBI
IS
2
80
53
PC7
MT0_CH3
I2C0_SCL
EBI_
AD8
81
54
PC8
MT0_ETI
I2C0_SDA
EBI_
AD9
82
MT1_CH0
83
PE2
MT1_
CH0N
84
PE3
MT1_CH1
85
55
VDD33_4
86
56
VSS33_4
USR1_TX
SCI_CLK
EBI_
A11
SCI_DIO
EBI_
A12
PE4
MT1_
CH1N
88
PE5
MT1_CH2
USR1_RX
89
PE6
MT1_
CH2N
USR1_RTS
EBI_
BL0
I2S_
BCLK
MT1_BRK
USR1_CTS
EBI_
BL1
I2S_
MCLK
CN0
MT1_CH0 SPI1_SEL
UR1_TX
EBI_
OE
I2S_
MCLK
MT1_
CH0N
91
PE7
57
41
PB6
CN1
MT1_CH2 SPI1_MISO UR0_TX
EBI_
ALE
I2S_
BCLK
CP1
MT1_
CH2N
I2C1_SCL
EBI_
CS1
I2S_
SDO
I2C1_SDA
EBI_
CS2
I2S_SDI
CP0
93
59
43
PB8
COUT0
94
60
44
PB9
95
61
45
PB10
PB11
97
63
47
VDDA
98
63
47
VREF+
99
64
48
VREF-
100
64
48
VSSA
Rev. 1.00
EBI_
A15
EBI_
WE
PB7
46
I2C1_SDA
SPI1_MOSI UR1_RX
42
62
EBI_
A14
SPI1_SCK
58
96
I2C1_SCL
EBI_
CS0
92
COUT1
MT1_CH3
N/A
N/A
N/A
AF14
AF15
N/A
System
Other
EBI_
A13
87
90
AF11 AF12 AF13
Overview
PE1
2
UR0_RX
26 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Table 3. HT32F1656/55 Pin Description
Pin Number
LQFP LQFP LQFP
100
64
48
1
1
Pin
Name
Type
IO
Output
Structure
Driving
(Note2)
(Note1)
Description
Default Function (AF0)
1
PA0
AI/O
33V
4/8mA
PA0
2
2
2
PA1
AI/O
33V
4/8mA
PA1
3
3
3
PA2
AI/O
33V
4/8mA
PA2
4
4
PA3
AI/O
33V
4/8mA
PA3
5
5
PA4
AI/O
33V
4/8mA
PA4
6
6
6
PA5
AI/O
33V
4/8mA
PA5
7
7
7
PA6
AI/O
33V
4/8mA
PA6
8
8
8
PA7
AI/O
33V
4/8mA
PA7
9
—
PE8
AI/O
33V
4/8mA
PE8
10
—
PE9
AI/O
33V
4/8mA
PE9
11
—
PE10
AI/O
33V
4/8mA
PE10
12
—
PE11
AI/O
33V
4/8mA
PE11
33V
4/8mA
PE12
PE12
AI/O
14
9
9
VDD33_1
P
15
10
10
VSS33_1
P
16
11
PC9
AI/O
13
—
—
—
3.3 V voltage for digital I/O
—
Ground reference for digital I/O
33V
4/8mA
PC9
17
12
PC10
AI/O
33V
4/8mA
PC10
18
13
—
PC11
AI/O
33V
4/8mA
PC11
19
14
—
PC12
I/O
33V
4/8mA
PC12
20
Overview
4
5
PD6
I/O
33V
4/8mA
PD6
21
15
11
PB12
I/O
5VT
8mA
22
15
11
USBDM
AI/O
—
—
23
16
12
USBDP
AI/O
—
—
24
16
12
PB13
I/O
PB12
USB Differential data bus conforming to
the Universal Serial Bus standard.
USB Differential data bus conforming to
the Universal Serial Bus standard.
PB13
25
5VT
8mA
NC
26
17
13
VLDOOUT P
—
—
27
18
14
VLDOIN
P
—
—
28
19
15
VSSLDO
P
—
—
29
20
16
nRST
I(BK) 5VT_PU
—
30
21
17
VBAT
—
31
22
18
PC13
32
23
19
PC14
33
24
20
PC15
34
25
P
AI/O
(BK)
AI/O
(BK)
I/O
(BK)
I/O
Rev. 1.00
PD0
—
No connection
LDO power 1.8 V output
It is recommended to connect a capacitor,
denoted as CLDO, as close as possible
between this pin and VSSLDO.
LDO power 3.3 V input
Connected to the power switch circuitry
for the internal backup domain.
LDO ground reference
External reset pin and external wakeup
pin in the Power-Down mode
Battery power input for the backup domain
33V
1mA
XTAL32KIN
33V
1mA
XTAL32KOUT
5VT
1mA
RTCOUT
5VT
8mA
PD0
27 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Pin Number
LQFP LQFP LQFP
100
64
48
Pin
Name
Type
IO
Output
Structure
Driving
(Note2)
I/O
5VT
(Note1)
8mA
Description
Default Function (AF0)
35
PE13
PE13
36
PE14
I/O
5VT
8mA
PE14
37
PE15
I/O
5VT
8mA
PE15
26
21
PB14
AI/O
33V
4/8mA
XTALIN
39
27
22
PB15
AI/O
33V
4/8mA
XTALOUT
40
28
23
VDD33_2
P
—
—
3.3 V voltage for digital I/O
41
29
24
VSS33_2
P
—
—
Ground reference for digital I/O
42
PD1
I/O
5VT
8mA
PD1
43
PD2
I/O
5VT
8mA
PD2
44
PD3
I/O
5VT
8mA
PD3
45
PD4
I/O
5VT
8mA
PD4
46
PD5
I/O
5VT
8mA
PD5
47
30
PC0
I/O
5VT
12mA
PC0
48
31
PC1
I/O
5VT
12mA
PC1
49
32
PC2
I/O
5VT
12mA
PC2
50
33
PC3
I/O
5VT
12mA
PC3
51
PD7
I/O
5VT
8mA
PD7
52
PD8
I/O
5VT
8mA
PD8
53
34
25
PA8
I/O
5VT_PU
12mA
PA8
54
35
26
PA9
I/O
5VT_PU
12mA
PA9
55
36
27
PA10
I/O
5VT
8mA
PA10
56
37
28
PA11
I/O
5VT
8mA
TRACESWO
57
38
29
PA12
I/O
5VT_PU
8mA
SWCLK
58
39
30
PA13
I/O
5VT_PU
8mA
SWDIO
59
40
31
PA14
I/O
5VT_PU
12mA
PA14
32
PA15
I/O
5VT_PU
12mA
PA15
VDD33_3
P
60
41
61
42
62
43
VSS33_3
P
63
44
33
PB0
I/O
5VT
34
—
—
—
3.3 V voltage for digital I/O
—
Ground reference for digital I/O
12mA
PB0
64
45
PB1
I/O
5VT
12mA
PB1
65
46
PC4
I/O
5VT
8mA
PC4
66
47
PC5
I/O
5VT
8mA
PC5
67
48
PC6
I/O
5VT
8mA
PC6
68
PD9
I/O
5VT
8mA
PD9
69
PD10
I/O
5VT
8mA
PD10
70
PD11
I/O
5VT
8mA
PD11
71
PD12
I/O
5VT
8mA
PD12
72
PD13
I/O
5VT
8mA
PD13
73
PD14
I/O
5VT
8mA
PD14
74
PD15
I/O
5VT
8mA
PD15
75
PE0
I/O
5VT
8mA
PE0
Rev. 1.00
28 of 48
July 24, 2014
Overview
38
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Pin Number
LQFP LQFP LQFP
100
64
48
76
49
Pin
Name
Type
(Note1)
Description
IO
Output
Structure
Driving
(Note2)
—
Default Function (AF0)
35
VDD33_3
P
36
VSS33_3
P
37
PB2
I/O
5VT
12mA
PB2
—
—
3.3 V voltage for digital I/O
—
Ground reference for digital I/O
50
38
PB3
I/O
5VT
12mA
PB3
51
39
PB4
I/O
5VT
12mA
PB4
40
79
52
PB5
I/O
5VT
12mA
PB5
80
53
PC7
I/O
5VT
8mA
PC7
81
54
PC8
I/O
5VT
8mA
PC8
82
PE1
I/O
5VT
8mA
PE1
83
PE2
I/O
5VT
8mA
PE2
84
PE3
I/O
5VT
8mA
PE3
85
55
VDD33_4
P
86
56
VSS33_4
P
PE4
I/O
87
—
—
5VT
—
3.3 V voltage for digital I/O
—
Ground reference for digital I/O
8mA
PE4
88
PE5
I/O
5VT
8mA
PE5
89
PE6
I/O
5VT
8mA
PE6
90
PE7
I/O
5VT
8mA
PE7
57
41
PB6
AI/O
33V
4/8mA
PB6
92
58
42
PB7
AI/O
33V
4/8mA
PB7
93
59
43
PB8
AI/O
33V
4/8mA
PB8
91
Overview
77
78
94
60
44
PB9
AI/O
33V
4/8mA
PB9
95
61
45
PB10
AI/O
33V
4/8mA
PB10
96
62
46
PB11
AI/O
33V
4/8mA
PB11
97
63
47
VDDA
P
—
—
3.3 V analog voltage for ADC and OPA/
Comparator
98
VREF+
P
—
—
ADC positive reference voltage has to be
lower or equal to VDDA
99
VREF-
P
—
—
ADC negative reference voltage has to be
directly connected to VSSA
VSSA
P
—
—
Ground reference for the ADC and OPA/
Comparator
100
64
48
Note: 1. I = Input, O = Output, A = Analog port, P = Power supply, PU = Pull-up, BK = Back-up domain
2. 5VT = 5 V tolerant; 33V = 3.3 V tolerant.
3. The GPIOs are in an AF0 state after a VDD18 power on reset (POR) except for the RTCOUT pin in the
Backup Domain I/O. The RTCOUT pin is reset by the Backup Domain power-on-reset (PORB) or by the
Backup Domain software reset (BAK_RST bit in BAK_CR register).
4. The backup domain of the I/O pins have a source current capability limitation of < 1mA @ VBAT = 3.3V.
Rev. 1.00
29 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
4
Electrical Characteristics
Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings
Min
Max
Unit
VDD33
Symbol
External main supply voltage
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VLDOIN
External LDO supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5 V-tolerant I/O
VSS - 0.3
VSS + 5.5
V
Input voltage on other I/O
VSS - 0.3
VDD33 + 0.3
V
VIN
Parameter
TA
Ambient operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
PD
Total power dissipation
—
500
mW
VESD
Electrostatic discharge voltage - human body mode
-4000
+4000
V
Recommended DC Operating Conditions
Table 5. Recommended DC Operating Conditions
Symbol
VDD33
VDDA
Parameter
I/O operating voltage
Analog operating voltage
VBAT
Battery supply operating voltage
VLDOIN
LDO operating voltage
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
—
2.7
3.3
3.6
V
—
2.7
3.3
3.6
V
—
2.7
3.3
3.6
V
—
2.7
3.3
3.6
V
On-Chip LDO Voltage Regulator Characteristics
Table 6. LDO Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
VLDOOUT
Internal regulator output voltage
VLDOIN = 3.3V Regulator input
1.71
1.8
1.89
V
ILDOOUT
Output current
VLDOIN = 2.7V Regulator input
—
—
200
mA
CLDO
External filter capacitor value for
internal core power supply
The capacitor value is dependent
on the core power current
consumption
2.2
—
10
μF
Rev. 1.00
30 of 48
July 24, 2014
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Power Consumption
Table 7. Power Consumption Characteristics
Symbol
Parameter
Supply current
(Run mode)
IDD
Supply current
(Deep-Sleep1
mode)
Supply current
(Deep-Sleep2
mode)
Supply current
(Power-Down
mode)
IBAT
Conditions
Min
Typ
Max
Unit
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144MHz,
fHCLK = 72MHz, fPCLK = 72MHz, All peripherals enabled
—
62
72
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144MHz,
fHCLK = 72MHz, fPCLK = 72MHz, All peripherals disabled
—
29
34
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144 MHz,
fHCLK = 0MHz, fPCLK = 72MHz, All peripherals enabled
—
43
50
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144MHz,
fHCLK = 0MHz, fPCLK = 72MHz, All peripherals disabled
—
8.5
12
mA
VDD33 = VBAT = 3.3 V, All clock off (HSE/PLL/fHCLK), LDO
in low power mode, LSI on, RTC on
—
63
90
μA
VDD33 = VBAT = 3.3 V, All clock off (HSE/PLL/fHCLK), LDO
off (DMOS on), LSI on, RTC on
—
20
25
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE on, LSI off, RTC on
—
—
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE on, LSI off, RTC off
—
—
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE off, LSI on, RTC on
—
—
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE off, LSI on, RTC off
—
5
6
μA
—
4
—
μA
—
3.9
—
μA
VDD33 not present, VBAT = 3.3 V, LDO off, LSE off, LSI
Battery supply on, RTC on
current (PowerVDD33 not present, VBAT = 3.3 V, LDO off, LSE off, LSI
Down mode)
on, RTC off
Note: 1. HSE means high speed external oscillator. HSI means 8MHz high speed internal oscillator.
2. LSE means low speed external oscillator. LSI means 32.768KHz low speed internal oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.
Rev. 1.00
31 of 48
July 24, 2014
Electrical Characteristics
Supply current
(Sleep mode)
TA = 25°C, unless otherwise specified.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Reset and Supply Monitor Characteristics
Table 8. LVD/BOD Characteristics
Symbol
VBOD
Parameter
Min
Typ
Max
Unit
—
—
2.6
—
V
Voltage of Low Voltage Detector
LVDS
(Note1)
= ‘000’
—
2.7
—
V
LVDS
(Note1)
= ‘001’
—
2.8
—
V
LVDS (Note1) = ‘010’
—
2.9
—
V
= ‘011’
—
3.0
—
V
LVDS (Note1) = ‘100’
—
3.1
—
V
LVDS
(Note1)
= ‘101’
—
3.2
—
V
LVDS (Note1) = ‘110’
—
3.4
—
V
= ‘111’
—
3.5
—
V
—
1.36
—
V
LVDS
LVDS
VPOR
Conditions
Brown Out Detector Voltage
(Note1)
(Note1)
Power On Reset Voltage
—
Note: LVDS field is in PWRCU LVDCSR register
External Clock Characteristics
Table 9. High Speed External Clock (HSE) Characteristics
Symbol
Parameter
fHSE
High Speed External oscillator
frequency (HSE)
CHSE
Recommended load capacitance on
XTALIN and XTALOUT pins
Conditions
VDD33 = 3.3 V
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
4
—
16
MHz
—
TBD
—
pF
—
1.0
—
MΩ
40
—
60
%
DHSE
Recommended external feedback
resistor between XTALIN and
XTALOUT pins
HSE oscillator Duty cycle
IDDHSE
HSE oscillator current consumption
VDD33 = 3.3 V, TA = 25°C
—
0.96
—
mA
ISTBHSE
HSE oscillator standby current
VDD33 = 3.3 V, TA = 25°C
—
—
0.1
μA
tSUHSE
HSE oscillator startup time
VDD33 = 3.3 V, TA = 25°C
—
—
4
ms
RFHSE
Rev. 1.00
32 of 48
July 24, 2014
Electrical Characteristics
VLVD
TA = 25°C, unless otherwise specified.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Table 10. Low Speed External Clock (LSE) Characteristics
Symbol
Parameter
IDDLSE
LSE Oscillator Operating current
ISTBLSE
LSE Oscillator Standby current
tSULSE
LSE Oscillator Startup time
fLSE
CLSE
RFLSE
Conditions
VDD33 = VBAT = 3.3 V
VDD33 = VBAT = 3.3 V, LSESM
= 0 (Normal startup mode)
VDD33 = VBAT = 3.3 V, LSESM
= 1 (Fast startup mode)
VDD33 = VBAT = 3.3 V, LSESM
= 1 (Fast startup mode)
Min
Typ
Max Unit
—
32.768
—
kHz
—
TBD
—
pF
—
10
—
MΩ
40
—
60
%
—
1.7
—
μA
—
3
8
μA
—
200
—
ms
Note: The following PCB layout guidelines are recommended to increase the stability of the crystal circuit for the
HSE/LSE clock:
1. The crystal oscillator should be located as close as possible to the MCU to minimise trace length thus
reducing parasitic capacitance.
2. Use a ground plane as a shield under the crystal circuit to reduce the effects of noise interference.
3. Route high frequency signals away from crystal oscillator area to prevent crosstalk.
Internal Clock Characteristics
Table 11. High Speed Internal Clock (HSI) Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min Typ Max Unit
fHSI
High Speed Internal Oscillator
Frequency (HSI)
VDD33 = 3.3 V, TA = -40°C ~ +85°C
—
8
—
MHz
ACCHSI
HSI Oscillator Frequency
accuracy
Factory-trimmed,
VDD33 = 3.3 V, TA = -40°C ~+85°C
-5
—
+5
%
DHSI
HSI Oscillator Duty cycle
VDD33 = 3.3 V, fHSI = 8 MHz
35
—
65
%
IDDHSI
HSI Oscillator current
VDD33 = 3.3 V, fHSI = 8 MHz
—
0.92
—
mA
tSUHSI
HSI Oscillator Startup time
VDD33 = 3.3 V, fHSI = 8 MHz, HSIRCBL = 0
(HSI Ready Counter Bits Length 7 Bits )
—
17
—
μs
Note: HSIRCBL field is in PWRCU HSIRCR register
Table 12. Low Speed Internal Clock (LSI) Characteristics
Symbol
Parameter
fLSI
Low Speed Internal Oscillator
Frequency (LSI)
IDDLSI
tSULSI
Rev. 1.00
TA = 25°C, unless otherwise specified.
Conditions
VDD33 = VBAT = 3.3 V, TA = -40°C ~ +85°C
Min Typ Max Unit
25
32
43
kHz
LSI Oscillator Operating current VDD33 = VBAT = 3.3 V, TA = 25°C
—
1.0
2
μA
LSI Oscillator startup time
—
35
—
ms
VDD33 = VBAT = 3.3 V, TA = 25°C
33 of 48
July 24, 2014
Electrical Characteristics
DLSE
Low Speed External oscillator frequency (LSE)
Recommended load capacitance on
XTAL32KIN and XTAL32KOUT pins
Recommended external feedback
resistor between XTAL32KIN and
XTAL32KOUT pins
LSE oscillator Duty cycle
TA = 25°C, unless otherwise specified.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
PLL Characteristics
Table 13. PLL Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
4
—
16
MHz
fCK_PLL
PLL output clock
8
—
144
MHz
tLOCK
PLL lock time
—
TBD
—
ms
Memory Characteristics
Table 14. Flash Memory Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
—
K cycles
NENDU
Number of guaranteed program/erase
cycles before failure. (Endurance)
TA = -40°C ~ +85°C
20
—
TRET
Data retention time
TA = 25°C
100
—
—
Years
tPROG
Word programming time
TA = -40°C ~ +85°C
20
—
40
μs
tERASE
Page erase time
TA = -40°C ~ +85°C
20
—
40
ms
tMERASE
Mass erase time
TA = -40°C ~ +85°C
20
—
40
ms
I/O Port Characteristics
Table 15. I/O Port Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
3.3 V IO
IIL
Low level input current
5 V-tolerant IO
Reset pin
High level input current
VIH
VHYS
Rev. 1.00
Low level input voltage
High level input voltage
Schmitt trigger input
voltage hysteresis
—
3
μA
—
—
3
μA
—
—
3
μA
—
3
μA
—
—
3
μA
—
—
3
μA
3.3 V IO
-0.3
—
0.8
V
5 V-tolerant IO
-0.3
—
0.8
V
Reset pin
-0.3
—
0.8
V
3.3 V IO
2
—
3.6
V
5 V-tolerant IO
2
—
5.5
V
Reset pin
2
—
5.5
V
3.3 V IO
—
400
—
mV
5 V-tolerant IO
—
400
—
mV
Reset pin
—
400
—
mV
5 V-tolerant IO
Reset pin
VIL
Typ Max Unit
—
—
3.3 V IO
IIH
VI = 0 V, On-chip pullup resister disabled.
Min
34 of 48
VI = VDD33, On-chip pulldown resister disabled.
July 24, 2014
Electrical Characteristics
fPLLIN
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Symbol
IOL
VOL
VOH
RPU
RPD
Rev. 1.00
Low level output current
(GPIO Sink current)
High level output current
(GPIO Source current)
Low level output voltage
Conditions
Internal pull-down resistor
Typ Max Unit
3.3 V IO 4 mA drive, VOL = 0.4 V
4
—
—
mA
3.3 V IO 8 mA drive, VOL = 0.4 V
8
—
—
mA
5 V-tolerant IO 8 mA drive, VOL = 0.4 V
8
—
—
mA
5 V-tolerant IO 12 mA drive, VOL = 0.4 V
12
—
—
mA
Backup Domain IO drive @ VBAT = 3.3 V,
VOL = 0.4 V, PC13, PC14, PC15
—
4
—
mA
3.3 V I/O 4 mA drive, VOH = VDD33 - 0.4 V
4
—
—
mA
3.3 V I/O 8 mA drive, VOH = VDD33 - 0.4 V
8
—
—
mA
5 V-tolerant I/O 8 mA drive,
VOH = VDD33 - 0.4 V
8
—
—
mA
5 V-tolerant I/O 12 mA drive,
VOH = VDD33 - 0.4 V
12
—
—
mA
Backup Domain IO drive @ VBAT = 3.3 V,
VOL = VDD33 - 0.4 V, PC13, PC14, PC15
—
—
1
mA
3.3 V 4 mA drive IO, IOL = 4 mA
—
—
0.4
V
3.3 V 8 mA drive IO, IOL = 8 mA
—
—
0.4
V
5 V-tolerant 8 mA drive IO, IOL = 8 mA
—
—
0.4
V
5 V-tolerant 12 mA drive IO, IOL = 12 mA
—
—
0.4
V
3.3 V 4 mA drive IO, IOH = 4 mA
VDD33 0.4 V
—
—
V
3.3 V 8 mA drive IO, IOH = 8 mA
VDD33 0.4 V
—
—
V
5 V-tolerant 8 mA drive IO, IOH = 8 mA
VDD33 0.4 V
—
—
V
5 V-tolerant 12 mA drive IO, IOH = 12 mA
VDD33 0.4 V
—
—
V
High level output voltage
Internal pull-up resistor
Min
3.3 V I/O
34
74
kΩ
5 V-tolerant I/O
38
89
kΩ
3.3 V I/O
29
86
kΩ
5 V-tolerant I/O
35
107
kΩ
35 of 48
July 24, 2014
Electrical Characteristics
IOH
Parameter
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
ADC Characteristics
Table 16. ADC Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Operating voltage
VADCIN
A/D Converter input voltage range
VREF+
A/D Converter Reference voltage
IADC
Current consumption
VDDA = 3.3 V
VDDA = 3.3 V
Min Typ Max
Unit
2.7
3.3
3.6
V
0
—
VREF+
V
VDDA VDDA
—
1
TBD
V
mA
IADC_DN
Power down current consumption
—
1
10
μA
fADC
A/D Converter clock
0.7
—
14
MHz
fS
Sampling rate
0.05
—
1
fADCCONV
A/D Converter conversion time
—
14
—
RI
Input sampling switch resistance
—
—
1
MHz
1/fADC
Cycles
kΩ
CI
Input sampling capacitance
—
—
5
pF
tSU
Startup up time
—
—
1
μs
N
Resolution
—
12
—
bits
INL
Integral Non-linearity error
fS = 1 MHz, VDDA = 3.3 V
—
±2
±5
LSB
DNL
Differential Non-linearity error
fS = 1 MHz, VDDA = 3.3 V
—
—
±1
LSB
EO
Offset error
—
—
±10
LSB
EG
Gain error
—
—
±10
LSB
No pin/pad capacitance included
Note: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input stage where CI
is the storage capacitor, RI is the resistance of the sampling switch and RS is the output impedance of the
signal source VS. Normally the sampling phase duration is approximately, 1.5/fADC. The capacitance, CI,
must be charged within this time frame and it must be ensured that the voltage at its terminals becomes
sufficiently close to VS for accuracy. To guarantee this, RS may not have an arbitrarily large value.
Rev. 1.00
36 of 48
July 24, 2014
Electrical Characteristics
VDDA
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
SAR ADC
sample
RS
RI
Figure 7. ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and VREF) are sampled
consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following
equation:
RS <
1.5
− RI
f ADC C I ln(2 N + 2 )
where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, Rs may be larger than the value indicated by the equation
above.
Rev. 1.00
37 of 48
July 24, 2014
Electrical Characteristics
CI
VS
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
Operational Amplifier/Comparator Characteristics
Table 17. OPA/CMP Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Operating voltage
2.7
3.3
3.6
V
IOPA/CMP
Typical operating current
—
230
—
μA
VIOS
Input offset voltage
VIOS_DRIFT
Input offset voltage drift
Assign registers OPAEN = 0 and
EN_OPAOP = 0
VDDA = 3.3 V, AnOF[5:0] = ‘100000’
—
—
0.1
μA
-15
—
15
mV
VDDA = 3.3 V, After calibration
-1
—
TA = -40°C ~ +85°C
RINPUT
Input resistance
GV
Voltage Gain
Ut
Unit-Gain Bandwidth
VCM
OPA common mode voltage
range
VDDA = 3.3 V
VSSA
VOV
OPA output voltage swing
VDDA = 3.3 V
VSSA +
0.3
SR
Slew Rate
tRT
Comparator response time
60
mV
mV/°C
10
MΩ
100
dB
RL=100KΩ
1,3
RL=100KΩ, CL=100pF
1.24
VDDA = 3.3 V;
Output capacitor load CL=100pF
VDDA = 3.3 V;
Input Overdrive = ±10mV
1
0.04
—
MHz
VDDA –
1.2
VDDA –
0.5
1.6
—
V
V
V/μs
1
—
μs
Note: Guaranteed by design, not tested in production.
GPTM/MCTM Characteristics
Table 18. GPTM/MCTM Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fTM
Timer clock source for GPTM and MCTM
—
—
—
72
MHz
tRES
Timer resolution time
—
1
—
—
fTM
fEXT
External single frequency on channel 1 ~ 4
—
—
—
1/2
fTM
RES
Timer resolution
—
—
—
16
bits
Rev. 1.00
38 of 48
July 24, 2014
Electrical Characteristics
IOPA/CMP_DN Power down supply current
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
I2C Characteristics
Table 19. I2C Characteristics
Symbol
fSCL
Standard mode
Min
Max
Parameter
SCL clock frequency
—
Fast mode
Min
Max
100
Fast mode plus
Min
Max
400
1000
Unit
kHz
SCL clock high time
4.5
1.125
0.45
μs
SCL clock low time
4.5
1.125
0.45
μs
tFALL
SCL and SDA fall time
1.3
0.34
0.135
μs
tRISE
SCL and SDA rise time
1.3
0.34
0.135
μs
tSU(SDA)
SDA data setup time
tH(SDA)
SDA data hold time
tSU(STA)
START condition setup time
500
125
50
ns
0
0
0
ns
500
125
50
ns
tH(STA)
START condition hold time
0
0
0
ns
tSU(STO)
STOP condition setup time
500
125
50
ns
Note: 1. Guaranteed by design, not tested in production.
2. To achieve 100kHz standard mode, the peripheral clock frequency must be higher than 2MHz.
3. To achieve 400kHz fast mode, the peripheral clock frequency must be higher than 8MHz.
4. To achieve 1MHz fast mode plus, the peripheral clock frequency must be higher than 20MHz.
5. The above characteristic parameters of the I2C bus timing are based on: SEQ_FILTER = 01 and COMB_
FILTER_En is disabled.
tRISE
tFALL
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 8. I2C Timing Diagrams
Rev. 1.00
39 of 48
July 24, 2014
Electrical Characteristics
tSCL(H)
tSCL(L)
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
SPI Characteristics
Table 20. SPI Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
fPCLK/2
MHz
tSCK(H)
SCK clock high time
fPCLK/8
—
—
ns
tSCK(L)
SCK clock low time
fPCLK/8
—
—
ns
tV(MO)
Data output valid time
—
—
5
ns
tH(MO)
Data output hold time
2
—
—
ns
tSU(MI)
Data input setup time
5
—
—
ns
tH(MI)
Data input hold time
5
—
—
ns
SPI Slave mode
tSU(SEL)
SEL enable setup time
4 tPCLK
—
—
ns
tH(SEL)
SEL enable hold time
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
10
ns
tV(SO)
Data output valid time
—
—
25
ns
tH(SO)
Data output hold time
15
—
—
ns
tSU(SI)
Data input setup time
5
—
—
ns
tH(SI)
Data input hold time
4
—
—
ns
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
tV(MO)
MOSI
DATA VALID
tSU(MI)
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI)
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
tSU(MI)
tH(MO)
DATA VALID
DATA VALID
DATA VALID
tH(MI)
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 9. SPI Timing Diagrams - SPI Master Mode
Rev. 1.00
40 of 48
July 24, 2014
Electrical Characteristics
SPI Master mode
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
SEL
tSU(SEL)
tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(L)
Electrical Characteristics
tSCK(H)
SCK
(CPOL=1)
tSU(SI)
MOSI
tH(SI)
LSB/MSB IN
MSB/LSB IN
tA(SO)
tV(SO)
tDIS(SO)
tH(SO)
LSB/MSB OUT
MSB/LSB OUT
MISO
Figure 10. SPI Timing Diagrams - SPI Slave Mode with CPHA=1
I2S Characteristics
Table 21. I2S Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I2S Master mode
tWSD(MO)
WS output to BCLK delay
TBD
ns
tDOD(MO)
Data output to BCLK delay
TBD
ns
tDIS(MI)
Data input setup time
TBD
ns
tDIH(MI)
Data input hold time
TBD
ns
I S Slave mode
2
tBCH(SI)
BCLK high pulse width
TBD
ns
tBCL(SI)
BCLK low pulse width
TBD
ns
tWSS(SI)
WS input setup time
TBD
ns
tDOD(SO)
Data output to BCLK delay
TBD
ns
tDIS(SI)
Data input setup time
TBD
ns
tDIH(SI)
Data input hold time
TBD
ns
Rev. 1.00
41 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
BCLK
tWSD(MO)
WS
Electrical Characteristics
tDOD(MO)
SDO
tDIS(MI)
tDIH(MI)
SDI
Figure 11. Timing of I2S Master Mode
tBCH(SI)
tBCL(SI)
BCLK
tWSS(SI)
WS
tDOD(SO)
SDO
tDIS(SI)
tDIH(SI)
SDI
Figure 12. Timing of I2S Slave Mode
Rev. 1.00
42 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
USB Characteristics
The USB interface is USB-IF certified – Full Speed.
Table 22. USB DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Max
3.0
—
3.6
V
0.2
—
—
V
—
2.5
V
2.0
V
VDD33
USB operating voltage
VDI
Differential input sensitivity
VCM
Common mode voltage range
0.8
VSE
Single-ended receiver threshold
0.8
|USBDP-USBDM|
VOL
Pad output low voltage
VOH
Pad output high voltage
VCRS
Differential output signal cross-point voltage
1.3
ZDRV
Driver output resistance
—
CIN
Transceiver pad capacitance
RL of 1.5kΩ to VDD33
Unit
0
—
0.3
V
2.8
—
3.6
V
2.0
V
10
—
Ω
—
20
pF
Note: 1. Guaranteed by design, not tested in production.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP pin should be pulled up
with a 1.5kΩ external resistor to a 3.0-to-3.6 V voltage supply.
3. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which will
experience degradation in the 2.7-to-3.0 V VDD33 voltage range.
4. RL is the load connected to the USB driver USBDP.
Rise Time
Fall Time
Tr
Tf
90%
90%
VCRS
10%
10%
Figure 13. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition
Table 23 USB AC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Tr
Rise time
CL = 50 pF
4
—
20
ns
Tf
Fall time
CL = 50 pF
4
—
20
ns
Tr/f
Rise time / fall time matching
Tr/f = Tr / Tf
90
—
110
%
Rev. 1.00
43 of 48
July 24, 2014
Electrical Characteristics
Typ
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
5
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the package information.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.00
44 of 48
July 24, 2014
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
48-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
9.0 BSC
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.5 BSC
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
45 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
64-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.40 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
46 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655
100-pin LQFP (14mm×14mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.630 BSC
—
B
—
0.551 BSC
—
C
—
0.630 BSC
—
D
—
0.551 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
16.00 BSC
—
B
—
14.00 BSC
—
C
—
16.00 BSC
—
D
—
14.00 BSC
—
E
—
0.50 BSC
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
―
―
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
47 of 48
July 24, 2014
32-bit ARM® Cortex™-M3 MCU
HT32F1656/HT32F1655

Copyright© 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
48 of 48
July 24, 2014