HOLTEK HT32F1765

Holtek 32-bit Microcontroller with ARM® Cortex™-M3 Core
HT32F1755/HT32F1765/HT32F2755
Datasheet
Revision: V1.00
Date: ���������������
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller........................................................................................................ 8
Reset Control Unit.................................................................................................................. 8
Clock Control Unit................................................................................................................... 8
Power Management................................................................................................................ 9
Analog to Digital Converter..................................................................................................... 9
Analog Operational Amplifier/Comparator.............................................................................. 9
I/O Ports................................................................................................................................ 10
PWM Generation and Capture Timers – GPTM................................................................... 10
Motor Control Timer – MCTM............................................................................................... 11
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer.................................................................................................................... 12
Real Time Clock.................................................................................................................... 12
Inter-integrated Circuit – I2C................................................................................................. 13
Serial Peripheral Interface – SPI.......................................................................................... 13
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 14
Smart Card Interface – SCI.................................................................................................. 14
Peripheral Direct Memory Access – PDMA.......................................................................... 15
Universal Serial Bus Device Controller – USB..................................................................... 15
CMOS Sensor Interface – CSIF (HT32F2755 only)............................................................. 16
Debug Support...................................................................................................................... 16
Package and Operation Temperature................................................................................... 16
3 Overview................................................................................................................. 17
Device Information................................................................................................................ 17
Block Diagram...................................................................................................................... 18
Memory Map......................................................................................................................... 19
Clock Structure..................................................................................................................... 20
Pin Assignment..................................................................................................................... 21
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Table of Contents
On-chip Memory..................................................................................................................... 7
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
4 Electrical Characteristics...................................................................................... 28
Absolute Maximum Ratings.................................................................................................. 28
Recommended DC Characteristics...................................................................................... 28
On-Chip LDO Voltage Regulator Characteristics.................................................................. 28
Power Consumption............................................................................................................. 29
External Clock Characteristics.............................................................................................. 30
Internal Clock Characteristics............................................................................................... 31
PLL Characteristics............................................................................................................... 31
Memory Characteristics........................................................................................................ 31
I/O Port Characteristics......................................................................................................... 32
ADC Characteristics............................................................................................................. 33
Operation Amplifier/Comparator Characteristics.................................................................. 35
GPTM/MCTM Characteristics............................................................................................... 35
I2C Characteristics................................................................................................................ 36
SPI Characteristics............................................................................................................... 37
CSIF Characteristics............................................................................................................. 38
USB Characteristics.............................................................................................................. 39
5 Package Information............................................................................................. 41
48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 41
64-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 43
100-pin LQFP (14mm×14mm) Outline Dimensions.............................................................. 44
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August 13, 2012
Table of Contents
Reset and Supply Monitor Characteristics............................................................................ 29
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
List of Tables
Rev. 1.00
1. HT32F1755/1765/2755 Series Features and Peripheral List.................................................... 17
2. HT32F1755/1765/2755 Pin Descriptions.................................................................................. 24
3. Absolute Maximum Ratings....................................................................................................... 28
4. Recommended DC Operating Conditions................................................................................. 28
5. LDO Characteristics.................................................................................................................. 28
6. Power Consumption Characteristics......................................................................................... 29
7. LVD/BOD Characteristics.......................................................................................................... 29
8. High Speed External Clock (HSE) Characteristics.................................................................... 30
9. Low Speed External Clock (LSE) Characteristics..................................................................... 30
10. High Speed Internal Clock (HSI) Characteristics.................................................................... 31
11. Low Speed Internal Clock (LSI) Characteristics...................................................................... 31
12. PLL Characteristics................................................................................................................. 31
13. Flash Memory Characteristics................................................................................................. 31
14. I/O Port Characteristics........................................................................................................... 32
15. ADC Characteristics................................................................................................................ 33
16. OPA/CMP Characteristics....................................................................................................... 35
17. GPTM/MCTM Characteristics................................................................................................. 35
18. I2C Characteristics................................................................................................................... 36
19. SPI Characteristics.................................................................................................................. 37
20. CSIF Characteristics............................................................................................................... 38
21. USB DC Electrical Characteristics.......................................................................................... 39
22. USB AC Electrical Characteristics........................................................................................... 40
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
List of Figures
Rev. 1.00
1. HT32F1755/1765/2755 Block Diagram................................................................................... 18
2. HT32F1755/1765/2755 Memory Map...................................................................................... 19
3. HT32F1755/1765/2755 Clock Structure.................................................................................. 20
4. HT32F1755/1765/2755 48-LQFP Pin Assignment.................................................................. 21
5. HT32F1755/1765/2755 64-LQFP Pin Assignment.................................................................. 22
6. HT32F1755/1765/2755 100-LQFP Pin Assignment................................................................ 23
7. ADC Sampling Network Model................................................................................................ 34
8. I2C Timing Diagrams................................................................................................................ 36
9. SPI Timing Diagrams – SPI Master Mode............................................................................... 37
10. SPI Timing Diagrams – SPI Slave Mode and CPHA=1......................................................... 38
11. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition.................... 40
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List of Figures
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
1
General Description
The Holtek HT32F1755/1765/2755 devices are high performance and low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M3 processor core. The Cortex™-M3 is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and including advanced debug support.
The above features ensure that the HT32F1755/1765/2755 devices are suitable for use in a wide
range of applications, especially in areas such as white goods application control, power monitors,
alarm systems, consumer products, handheld equipment, data logging applications, motor control,
fingerprint recognition and so on.
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General Description
The HT32F1755/1765/2755 devices operate at a frequency of up to 72MHz with a Flash accelerator
to obtain maximum efficiency. It provides 128KB of embedded Flash memory for code/data storage
and up to 64KB of embedded SRAM memory for system operation and application program usage.
A variety of peripherals, such as ADC, I 2C, USART, SPI, PDMA, GPTM, MCTM, SCI, CSIF,
USB2.0 FS, SWJ-DP (Serial Wire and JTAG Debug Port), etc., are also implemented in the device
series. Several power saving modes provide the flexibility for maximum optimisation between
wakeup latency and power consumption, an especially important consideration in low power
applications.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
2
Features
Core
On-chip Memory
▀ 128KB on-chip Flash memory for instruction/data and options storage
▀ up to 64KB on-chip SRAM
▀ Supports multiple boot modes
The ARM® Cortex™-M3 processor is structured using a Harvard architecture which uses separate
busses to fetch instructions and load/store data. The instruction code and data are both located in
the same memory address space but in different address ranges. The maximum address range of
the Cortex™-M3 is 4GB due to its 32-bit bus address width. Additionally, a pre-defined memory
map is provided by the Cortex™-M3 processor to reduce the software complexity of repeated
implementation for different device vendors. However, some regions are used by the ARM®
Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference Manual
for more information. The Figure 2. shows the memory map of the HT32F1755/1765/2755 series of
devices, including Code, SRAM, peripheral, and other pre-defined regions.
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Features
®
▀ 32-bit ARM Cortex™-M3 processor core
▀ Up to 72MHz operation frequency
▀ 1.25 DMIPS/MHz (Dhrystone 2.1)
▀ Single-cycle multiplication and hardware division
▀ Integrated Nested Vectored Interrupt Controller (NVIC)
▀ 24-bit SysTick timer
The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for
products requiring high performance and low power consumption microcontrollers. It offers many
new features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Memory Controller
▀ Flash accelerator for maximum efficiency
▀ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
▀ Flash protection capability to prevent illegal access
Reset Control Unit
▀ Supply supervisor:
● Power-on Reset – POR
● Brown-out Detector – BOD
● Programmable Low Voltage Detector – LVD
The Reset Control Unit (RSTCU) has three kinds of reset, the power on reset, system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SWJ-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
Clock Control Unit
▀ External 4 to 16MHz crystal oscillator
▀ External 32,768Hz crystal oscillator
▀ Internal 8MHz RC oscillator trimmed to ±2% accuracy at 3.3V operating voltage and 25°C
operating temperature
▀ Internal 32kHz RC oscillator
▀ Integrated system clock PLL
▀ Independent clock gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers and clock gating circuitry.
The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock (CK_SYS)
which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use
either the LSI or LSE as their clock source. The maximum operating frequency of the system core
clock (CK_AHB) can be up to 72MHz.
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Features
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for
the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than
the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order
to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory
word program/page erase functions are also provided.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Power Management
Analog to Digital Converter
▀ 12-bit SAR ADC engine
▀ Up to 1Msps conversion rate – 1μs at 56MHz, 1.17μs at 72MHz
▀ 8 external analog input channels
▀ Supply voltage range: 2.7V ~ 3.6V
▀ Conversion range: VREF+ ~ VREFA 12-bit multi-channel ADC is integrated in the device. There are a total of 10 multiplexed
channels, which include 8 external channels on which the external analog signals can be measured,
and 2 internal channels. If the input voltage is required to remain within a specific threshold
window, an Analog Watchdog function will monitor and detect these signals. An interrupt will
then be generated to inform the device that the input voltage is not within the preset threshold
levels. There are three conversion modes to convert an analog signal to digital data. The ADC can
be operated in one shot, continuous and discontinuous conversion modes.
Analog Operational Amplifier/Comparator
▀ Two Operational Amplifiers or Comparator functions which are software configurable
▀ Supply voltage range: 2.7V ~ 3.6V
Two Operational Amplifiers/Comparators (OPA/CMP) are implemented within the devices. They
can be configured either as Operational Amplifiers or as Analog Comparators. When configured as
comparators, they are capable of generating interrupts to the NVIC.
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Features
▀ Single 3.3V power supply: 2.7V to 3.6V
▀ Integrated 1.8V LDO regulator for core and peripheral power supply
▀ VBAT battery power supply for RTC and backup registers
▀ Three power domains: 3.3V, 1.8V and Backup
▀ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
The Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
I/O Ports
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins.
The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit, EXTI.
PWM Generation and Capture Timers – GPTM
▀ Two 16-bit General-Purpose Timers – GPTM
▀ Up to 4-channel PWM Compare Output or Input Capture function for each GPTM
▀ External trigger input
T he General-P u r pose Timers, k now n as GPTM0 and GPTM1, consist of one 16 -bit
up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload
Register (CRR) and several control/status registers. They can be used for a variety of purposes
including general time measurement, input signal pulse width measurement, output waveform
generation such as single pulse generation, or PWM output generation. The GPTM supports an
Encoder Interface using a decoder with two inputs.
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Features
▀ Up to 80 GPIOs
▀ Port A, B, C, D, E are mapped as 16 external interrupts – EXTI
▀ Almost all I/O pins are 5V-tolerant except for pins shared with analog inputs
There are up to 80 General Purpose I/O pins, (GPIO), named PA0 ~ PA15 to PE0 ~ PE15 for the
implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximise flexibility and to meet the requirements of a wide
range of applications.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Motor Control Timer – MCTM
The Motor Control Timer consists of a single 16-bit up/down counter, four 16-bit CCRs
(Capture/Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit
repetition counter and several control/status registers. It can be used for a variety of purposes
including measuring the pulse widths of input signals or generating output waveforms such as
compare match outputs, PWM outputs or complementary PWM outputs with dead-time insertion.
The MCTM supports an Encoder interface controller to an incremental encoder with two inputs.
The MCTM is capable of offering full functional support for motor control, hall sensor interfacing
and brake input.
Basic Function Timer – BFTM
▀ Two 32-bit compare/match count-up counters – no I/O control features
▀ One shot mode – counting stops after a match condition
▀ Repetitive mode – restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
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Features
▀ Single 16-bit up, down, up/down auto-reload counter
▀ 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor
between 1 and 65536
▀ Input Capture function
▀ Compare Match Output
▀ PWM waveform generation with Edge and Centre-aligned Modes
▀ Single Pulse Mode Output
▀ Complementary Outputs with programmable dead-time insertion
▀ Encoder interface controller with two inputs using quadrature decoder
▀ Support 3-phase motor control and hall sensor interface
▀ Brake input to force the timer’s output signals into a reset or fixed condition
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Watchdog Timer
Real Time Clock
▀ 32-bit up-counter with a programmable prescaler
▀ Alarm function
▀ Interrupt and Wake-up event
The Real Time Clock, RTC, circuitry includes the APB interface, a 32-bit count-up counter, a
control register, a prescaler, a compare register and a status register. Most of the RTC circuits are
located in the Backup Domain except for the APB interface. The APB interface is located in the
VDD18 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from
the power control unit when the V DD18 power domain is powered off, that is when the device enters
the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume
signal from the Power-Down mode.
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Features
▀ 12-bit down counter with 3-bit prescaler
▀ Interrupt or reset event for the system
▀ Programmable watchdog timer window function
▀ Registers write protection function
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to
software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value
register, a WDT delta value register, interrupt related circuits, WDT operation control circuitry
and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or
a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts
down and reaches a zero value. If the software does not reload the counter value before a Watchdog
Timer underflow occurs, an interrupt or a reset will be generated when the counter underflows. In
addition, an interrupt or reset is also generated if the software reloads the counter when the counter
value is greater than or equal to the WDT delta value. This means the counter must be reloaded
within a limited timing window using a specific method. The Watchdog Timer counter can be
stopped while the processor is in the debug mode. There is a register write protect function which
can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Inter-integrated Circuit – I2C
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I2C module also has
an arbitration detect function and clock synchronization to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
Serial Peripheral Interface – SPI
▀ Supports both master and slave mode
▀ Frequency of up to 36MHz for master mode and 18MHz for slave mode
▀ FIFO Depth: 8 levels
▀ Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried in a similar way but with a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
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Features
▀ Support both master and slave mode with a frequency of up to 1MHz
▀ Provide an arbitration function and clock synchronization
▀ Supports 7-bit and 10-bit addressing mode and general call addressing
▀ Supports slave multi-addressing mode with maskable address
The I2C Module is an internal circuit allowing communication with an external I2C interface which
is an industry standard two line serial interface used for connection to external hardware. These
two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
provides three data transfer rates: (1). 100kHz in the Standard mode, (2). 400kHz in the Fast mode
and, (3). 1MHz in the Fast mode plus. The SCL period generation register is used to setup different
kinds of duty cycle implementation for the SCL pulse.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Universal Synchronous Asynchronous Receiver Transmitter – USART
The USART includes a programmable baud rate generator which is capable of dividing the
CK_AHB to produce a clock for the USART transmitter and receiver.
Smart Card Interface – SCI
▀ Support ISO 7816-3 standard
▀ Character mode
▀ Single transmit buffer and single receive buffer
▀ 11-bit ETU (Elementary Time Unit) counter
▀ 9-bit guard time counter
▀ 24-bit general purpose waiting time counter
▀ Parity generation and checking
▀ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.
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Features
▀ Operating frequency up to 4.5MHz
▀ Supports both asynchronous and clocked synchronous serial communication modes
▀ IrDA SIR encoder and decoder
▀ RS485 mode with output enable control
▀ Full Modem function for USART0
▀ Auto hardware flow control mode – RTS, CTS
▀ FIFO Depth: 16×9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. The USART is used to
translate data between parallel and serial interfaces, and is also commonly used for RS232 standard
communication. The USART peripheral function supports five types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt,
Time Out Interrupt and MODEM Status Interrupt. The USART module includes a 16-byte
transmitter FIFO (TX_FIFO) and a 16-byte receiver FIFO (RX_FIFO). The software can detect a
USART error status by reading the Line Status Register, LSR. The status includes the type and the
condition of transfer operations as well as several error conditions resulting from Parity, Overrun,
Framing and Break events.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Peripheral Direct Memory Access – PDMA
Universal Serial Bus Device Controller – USB
▀ Complies with USB 2.0 full-speed (12Mbps) specification
▀ On-chip USB full-speed transceiver
▀ 1 control endpoint (EP0) for control transfer
▀ 3 single-buffered endpoints for bulk and interrupt transfer
▀ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
▀ 1024 bytes EP-SRAM used as the endpoint data buffers
The USB device controller is compliant with USB 2.0 full-speed specification. There is one control
endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM is used as the
endpoint buffers. Each endpoint buffer size is programmable using corresponding registers, which
provides maximum flexibility for various applications. The integrated USB full-speed transceiver
helps to minimise the overall system complexity and cost. The USB functional block also contains
the resume and suspend features to meet the requirements of low-power consumption.
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Features
▀ 12 channels with trigger source grouping
▀ Supports Single and block transfer mode
▀ 8/16/32-bit width data transfer
▀ Supports Address increment, decrement or fixed mode
▀ 4-level programmable channel priority
▀ Auto reload mode
2
▀ Supports trigger source: CSIF, ADC, SPI, USART, I C, GPTM, MCTM, SCI and software
The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals
(USART, SPI, ADC, GPTM, MCTM, CSIF, I2C and SCI, CPU for software mode) and the system
memory on the AHB bus. Each PDMA channel has a source address, destination address, block
length and transfer count. The PDMA can exclude the CPU intervention and avoid interrupt service
routine execution. It improves system performance as the software does not need to join each data
movement operation.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
CMOS Sensor Interface – CSIF (HT32F2755 only)
Debug Support
▀
▀
▀
▀
Serial Wire or JTAG Debug Port SWJ-DP
6 instruction comparators and 2 literal comparators for hardware breakpoint or code/literal patch
4 comparators for hardware watchpoints
1-bit asynchronous trace – TRACESWO
Package and Operation Temperature
▀ 48/64/100-pin LQFP packages
▀ Operation temperature range: -40°C to +85°C
Rev. 1.00
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Features
▀ Up to 2048×2048 input resolution
▀ Supports 8-bit YUV422 and Raw RGB formats
▀ Up to 24MHz input pixel clock frequency
▀ Multi VSYNC and HSYNC settings for image capture
▀ Hardware window capture function
▀ Fractional hardware sub-sample function
▀ Dual FIFOs each with a capacity of 8×32 bits which can be read by the PDMA or CPU
The CMOS Sensor Interface, otherwise known as the CSIF, provides an interface for image
capture from CMOS sensors. The device can be connected to the CMOS sensor directly using its
CMOS Sensor Interface. The CSIF supports both Vertical SYNC and Horizontal SYNC modes for
image capture implementation. The CSIF consists of window capture and sub-sampling functions
together with dual FIFOs, each with a capacity of 8×32 bits, to store data which can be moved to
the internal SRAM via the Peripheral Direct Memory Access circuitry, PDMA. The CSIF does
not support image data conversion or decode but rather transfers the image data received from the
CMOS sensor to the internal SRAM transparently.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
3
Overview
Device Information
Table 1. HT32F1755/1765/2755 Series Features and Peripheral List
Peripherals
HT32F1755
HT32F2755
127
127
Option Bytes Flash (KB)
1
1
1
SRAM (KB)
32
64
64
Timers
MCTM
1
GPTM
2
BFTM
2
RTC
1
WDT
1
—
Communication
USB
1
SCI
1
USART
2
SPI
2
I2C
2
GPIO
Up to 80
EXTI
16
12-bit ADC
Number of channels
1
8 Channels
OPA/Comparator
2
CPU frequency
Up to 72MHz
Operating voltage
2.7V ~ 3.6V
Operating temperature
-40℃ ~ +85℃
Package
48/64/100-pin LQFP
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—
Overview
127
CSIF
Rev. 1.00
HT32F1765
Main Flash (KB)
1
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Block Diagram
JTRST, JTDI, JTDO,
JTCK_SWCLK,
JTMS_SWDIO
TRACESWO
AF
BOOT0
BOOT1
AF
CSIF_VSYNC, CSIF_HSYNC,
CSIF_MCK, CSIF_PCK,
CSIF_D[7:0]
AF
AF
Powered by VDD18
SWJ-DP
ICode
TPIU
Control
Registers
VSS33_1~4
Control
Registers
Control/Data
Registers
1.8 V
CKCU/RSTCU
Control
Registers
PLL
HSE
4 ~ 16 MHz
AF
Interrupt request
SRAM Controller
PDMA
fMax: 144 MHz
Clock and reset control
AHB Peripherals
XTALIN
XTALOUT
HSI
SRAM
8 MHz
VLDOIN
PDMA request
LDO
AHB to APB
AHB
to APB
Bridge
Bridge
VLDOOUT
1.8 V
VSSLDO
BOD
LVD
Powered by VLDOIN
USART1
SPI1
AF
SPI0
OPA/CMP
WDT
Powered by VDDA
AF
Analog
OPA/CMP
USB Device
Power control
AF
ADC
GPIOC
PD [15:0]
GPIOD
PE [15:0]
GPIOE
SCI
RTC
AF
PC [15:0]
BFTM 0 ~ 1
AF
GPIOB
APB1
PB [15:0]
APB0
GPIOA
AF
GPTM 0 ~ 1
PA [15:0]
SPI1_MOSI,
SPI1_MISO,
SPI1_SCK,
SPI1_SEL
AF
AF
I2C 0 ~ 1
12-bit
SAR ADC
UR1_TX,
UR1_RX,
UR1_RTS/TXE,
UR1_CTS/SCK
AF
USART0
AF
VDD18
AF
VDDA
VSSA
I2C0_SDA,
I2C0_SCL
I2C1_SDA,
I2C1_SCL
USBDP
USBDM
GT0_CH0~
GT0_CH3,
GT0_ETI
GT1_CH0~
GT1_CH3,
GT1_ETI
SCI_CLK,
SCI_DIO,
SCI_DET
RTCOUT
PWRSW
VBAT
VBAK
AFIO
PWRCU
VLDOIN
EXTI
PORB
MCTM
AF
VBAK 3.3 V
BREG
LSI
32 kHz
LSE
WAKEUP
32,768 Hz
nRST
Backup Domain VBAK
Powered by VDD18
AF
MT_CH0~
MT_CH3 ,
MT_CH0N~
MT_CH2N ,
MT_CH3 ,
MT_ETI ,
MT_BRK .
CSIF
FMC
12 Channels
VREF+, VREFCN0, CP0
AOUT0
CN1, CP1
AOUT1
PDMA
Bus Matrix
NVIC
ADC_IN0
:
ADC_IN7
VDD33_1~4
AF
XTAL32KIN
XTAL32KOUT
Power supply:
Bus:
Control signal:
Alternate function:
AF
NOTE: The AHB peripheral function, CSIF, is only available in the HT32F2755 device.
Figure 1. HT32F1755/1765/2755 Block Diagram
Rev. 1.00
18 of 45
August 13, 2012
Overview
fMax: 72 MHz
SPI0_MOSI,
SPI0_MISO,
SPI0_SCK,
SPI0_SEL
Flash Memory
POR
DCode System
Cortex -M3
Processor
UR0_TX,
UR0_RX,
UR0_DCD,
UR0_DSR,
UR0_DTR,
UR0_RI
UR0_RTS/TXE
UR0_CTS/SCK
Flash Memory Interface
MPU
TM
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Memory Map
0xFFFF_FFFF
Reserved
0x400F_FFFF
0xE010_0000
0x4400_0000
Reserved
APB/AHB bit band alias
Peripheral
32 Mbytes
0x4200_0000
0x4010_0000
0x4008_0000
0x4000_0000
0x2220_0000
Reserved
AHB peripherals
512 kbytes
APB peripherals
512 kbytes
Reserved
SRAM bit band alias
2 Mbytes
SRAM
0x2200_0000
0x2001_0000
Reserved
64 kbytes
(HT32F1765/
HT32F2755)
32 kB on-chip SRAM
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
0x1F00_0000
Code
0x0002_0000
32 kB on-chip SRAM
32 kbytes
(HT32F1755)
Reserved
Option bytes alias
1 kbytes
Reserved
Boot loader
2 kbytes
Reserved
128 kbytes
128 kB on-chip Flash
0x0000_0000
0x4007_8000
0x4007_7000
0x4007_6000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_F000
0x4004_E000
0x4004_A000
0x4004_9000
0x4004_8000
0x4004_5000
0x4004_4000
0x4004_3000
0x4004_1000
0x4004_0000
0x4002_D000
0x4002_C000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_F000
0x4001_E000
0x4001_D000
0x4001_C000
0x4001_B000
0x4001_A000
0x4001_9000
0x4001_8000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_1000
0x4000_0000
Reserved
CSIF
Reserved
PDMA
Reserved
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM1
BFTM0
Reserved
GPTM1
GPTM0
Reserved
RTC/PWRCU
Reserved
WDT
Reserved
USB
Reserved
I2C1
I2C0
Reserved
SPI1
SCI
Reserved
USART1
Reserved
MCTM
Reserved
EXTI
Reserved
AFIO
Reserved
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
OPA/CMP
Reserved
ADC
Reserved
SPI0
Reserved
USART0
AHB
APB1
APB0
Figure 2. HT32F1755/1765/2755 Memory Map
Rev. 1.00
19 of 45
August 13, 2012
Overview
0xE000_0000
Private peripheral bus
0x400C_E000
0x400C_C000
0x4009_2000
0x4009_0000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Clock Structure
fCSIF_MCK,max = 24MHz
CK_MCK
CSIF_MCK
( to CSIF clock output)
1
HSIEN
f CK_PLL,max = 144MHz
CK_PLL
PLL
0
0x
CK_HSE
CK_SYS
AHB
Prescaler
÷ 1,2,4,8
32.768 kHz CK_LSE
LSE OSC
LSEEN(Note1)
STCLK
(to SysTick)
FCLK
( free running clock)
10
Clock
Monitor
32 kHz
LSI RC
÷8
WDTSRC
1
0
CK_LSI
HCLKC
( to CortexTM-M3)
CM3EN
(control by HW)
CK_AHB
HSEEN
11
CK_USART0
CK_USART1
URnEN
fCK_SYS,max = 144MHz
CK_HSI
fCK_USARTn,max = 72MHz
Prescaler
÷1, 2
SW[1:0]
4-16 MHz
HSE XTAL
CK_USB
USBEN
fCK_AHB,max = 72MHz
PLLEN
fCK_USB,max = 48MHz
Prescaler
÷1, 2, 3
CSIFMPRE
CSIFMEN
PLLSRC
CK_PLL
Prescaler
÷1 ~ 32
CK_WDT
DMAEN
HCLKD
( to DMA)
CSIFEN
CK_CSIF
( to CSIF)
WDTEN
RTCSRC(Note1)
HCLKF
( to Flash)
CM3EN
LSIEN(Note1)
FMCEN
1
0
HCLKS
( to SRAM)
CK_RTC
CM3EN
RTCEN(Note1)
SRAMEN
HCLKBM
( to Bus Matrix)
CKOUTSRC[2:0]
CM3EN
CKOUT
000
CK_MCK
001
CK_AHB/16
010
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
BMEN
HCLKAPB0
( to APB0 Bridge)
CM3EN
APB0EN
HCLKAPB1
( to APB1 Bridge)
CM3EN
APB1EN
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
OPA0EN
WDTEN
Note 1: Those control bits are located at RTC Control Register
(RTC_CTRL)
ADC
Prescaler
÷ 1,2,4,6,8...
PCLK
(OPA, AFIO,
GPIO Port,
ADC, SPI,
USART, I2C,
GPTM, MCTM,
BFTM, EXTI,
RTC, SCI,
Watchdog Timer)
CK_ADC
ADCEN
Figure 3. HT32F1755/1765/2755 Clock Structure
Rev. 1.00
20 of 45
August 13, 2012
Overview
8 MHz
HSI RC
Divider
÷2
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Pin Assignment
MT_CH2
AF2
SPI0-SEL
AF1
PD8
AF0
(Default)
5VT
5VT
5VT
5VT
3.3 V Digital Power Pad
P18
33V
3.3 V Analog Power Pad
1.8 V Power Pad
3.3 V I/O Pad
5VT
5 V Tolerance I/O Pad
5VT
High Current Output
5 V Tolerance I/O Pad
USB
USB PHY Pad
33V
33V
P33
P33
13
14
15
16
17
21
22
23
24
VSS33_2
19
20
AF3
AF3*
(HT32F1755)
(HT32F2755)
(HT32F1765)
36
VSS33_3
P33
35
VDD33_3
5VT
34
PC12
I2C0_SDA
MT_CH1N
UR0_CTS
5VT
33
PC11
I2C0_SCL
MT_CH1
UR0_RTS
CSIF_PCK
5VT
32
JTRST
PE15
MT_CH0N
UR1_RX
CSIF_VSYNC
5VT
31
JTDI
PE14
MT_CH0
UR1_TX
CSIF_HSYNC
5VT
30
JTMS_
SWDIO
JTCK_
29
SWCLK
JTDO_
28
TRACESWO
5VT
27
5VT
26
5VT
25
PC10
PC9_
BOOT1
PC8_
BOOT0
CSIF_MCK
PE13
PE12
PE11
SCI_DET
MT_ETI
UR0_RX
CKOUT
--
UR0_TX
XTAL32K
OUT
XTAL32K
IN
PB5
PB4
AF1
BAK BAK BAK BAK BAK
5VT P33 33V 33V 5VT
AF2
AF0
(Default)
Backup Domain Pad
P33
VLDOOUT
BAK
AF1
P33
5VT
P33
18
AF0
(Default)
5VT
P18
Overview
GT1_CH0
33V
AP
AF3
AF3*
(HT32F1755)
(HT32F2755)
(HT32F1765)
CSIF_D0
33V
PB12
USB
33V
VDD33_2
12
PD9
USBDM
SPI0_SCK
USB
MT_CH2N
11
GT1_CH1
USBDP
CSIF_D1
P33
33V
PB11
10
33V
AP
XTALIN
VSS33_1
33V
P33
AP
XTALOUT
P33
PD10
9
PD11
VDD33_1
SPI0_MOSI
33V
SPI0_MISO
8
MT_CH3
PA7
MT_BRK
ADC_IN7
GT1_CH2
UR1_RX
GT1_CH3
SPI1_MISO
37
PB6_
WAKEUP
33V
38
RTCOUT
7
39
nRST
PA6
40
VBAT
ADC_IN6
41
47
VLDOIN
UR1_TX
42
46
48
VSSLDO
SPI1_MOSI
CSIF_D2
33V
CSIF_D3
6
PE5
PA5
CN0
ADC_IN5
SPI1_SCK
GT0_CH0
33V
SPI1-SEL
5
CSIF_D4
PA4
PE6
ADC_IN4
UR1_RTS
/ TXE
UR1_CTS
/ SCK
SPI1_SEL
CP0
33V
GT0_CH1
33V
4
SPI1_SCK
3
PA3
CSIF_D5
PA2
ADC_IN3
PE7
ADC_IN2
UR0_RX
AOUT0
UR0_TX
GT1_CH3
GT0_CH2
GT1_CH2
SPI1_MOSI
33V
CSIF_D6
2
PE8
PA1
PE9
ADC_IN1
CP1
SCI_DIO
CN1
GT1_CH1
GT0_ETI
33V
GT0_CH3
1
SPI1_MISO
PA0
43
I2C1_SCL
ADC_IN0
CSIF_D7
SCI_CLK
44
PE10
GT1_CH0
45
AOUT1
AF0
(Default)
GT1_ETI
AF1
VSSA
AF2
VDDA
AF3
I2C1_SDA
Holtek
HT32F1755/1765/2755
48 LQFP
Figure 4. HT32F1755/1765/2755 48-LQFP Pin Assignment
Rev. 1.00
21 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GT1_CH0
GT1_CH1
GT1_CH2
GT1_CH3
AF3
AF3*
(HT32F1755)
(HT32F2755)
(HT32F1765)
CSIF_D0
CSIF_D1
CSIF_D2
CSIF_D3
GT1_ETI
SPI1-SEL
SPI1_SCK
SPI1_MOSI
GT0_ETI
CSIF_D4
CSIF_D5
CSIF_D6
SPI1_MISO
AF1
AF0
(Default)
53
52
51
50
49
5VT
5VT
5VT
5VT
5VT
5VT
PD9
54
P33
PD10
55
P33
PD11
56
33V
PD12
57
33V
PD13
58
33V
PE5
59
33V
PE6
60
33V
PE7
61
33V
PE8
62
AP
PE9
63
AP
PE10
64
Overview
AF2
PD8
VSS33_4
VDD33_4
SPI0-SEL
SPI0_SCK
SPI0_MOSI
SPI0_MISO
MT_CH0
MT_CH0N
CN0
CP0
AOUT0
CP1
CN1
MT_CH2
MT_CH2N
MT_CH3
MT_BRK
I2C0_SCL
I2C0_SDA
GT0_CH0
GT0_CH1
GT0_CH2
GT0_ETI
GT0_CH3
AOUT1
AF0
(Default)
I2C1_SCL
GT1_ETI
AF1
VSSA
AF2
VDDA
AF3
CSIF_D7
I2C1_SDA
Holtek
HT32F1755/1765/2755
64 LQFP
AF0
(Default)
AF1
AF3
AF3*
(HT32F1755)
(HT32F2755)
(HT32F1765)
AF2
GT1_CH0
SCI_CLK
ADC_IN0
PA0
1
33V
5VT
48
PC15
SCI_DET
GT0_ETI
UR0_DSR
GT1_CH1
SCI_DIO
ADC_IN1
PA1
2
33V
5VT
47
PC14
SCI_DIO
MT_CH0N
UR1_CTS
GT1_CH2
UR0_TX
ADC_IN2
PA2
3
33V
5VT
46
PC13
SCI_CLK
MT_CH0
GT1_CH3
UR0_RX
ADC_IN3
PA3
4
33V
5VT
45
PC12
I2C0_SDA
MT_CH1N
UR0_CTS
CSIF_MCK
SPI1_SEL
UR1_RTS
ADC_IN4
PA4
5
33V
5VT
44
PC11
I2C0_SCL
MT_CH1
UR0_RTS
CSIF_PCK
SPI1_SCK
UR1_CTS
ADC_IN5
PA5
6
33V
P33
43
VSS33_3
SPI1_MOSI
UR1_TX
ADC_IN6
PA6
7
33V
SPI1_MISO
UR1_RX
ADC_IN7
PA7
8
33V
VDD33_1
9
P33
VSS33_1
10
P33
USBDP
11
USB
USBDM
12
USB
P33
AP
SPI0_SEL
UR1_RTS
GT0_CH0
PB0
13
5VT
SPI0_SCK
UR1_CTS
GT0_CH1
PB1
14
5VT
SPI0_MOSI
UR1_TX
GT0_CH2
PB2
15
SPI0_MISO
UR1_RX
GT0_CH3
PB3
16
3.3 V Digital Power Pad
3.3 V Analog Power Pad
P18
1.8 V Power Pad
33V
3.3 V I/O Pad
P33
42
VDD33_3
5VT
41
JTRST
PE15
MT_CH0N
UR1_RX
CSIF_VSYNC
JTDI
PE14
MT_CH0
UR1_TX
CSIF_HSYNC
5VT
5 V Tolerance I/O Pad
5VT
40
5VT
5VT
High Current Output
5 V Tolerance I/O Pad
39
USB
USB PHY Pad
5VT
5VT
JTMS_
SWDIO
JTCK_
38
SWCLK
JTDO_
37
TRACESWO
5VT
36
5VT
35
5VT
5VT
34
5VT
5VT
33
BAK
Backup Domain Pad
PC10
PC9_
BOOT1
PC8_
BOOT0
PC3
P33
P33
BAK BAK BAK BAK BAK
5VT P33 33V 33V 5VT
5VT
33V
33V
P33
P33
5VT
5VT
5VT
17
18
19
20
21
25
26
27
28
29
30
31
32
VLDOIN
VSSLDO
nRST
VBAT
PB7
XTALIN
XTALOUT
VDD33_2
VSS33_2
PC0
PC1
PC2
AF0
(Default)
GT0_ETI
PB11
PB12
SPI1_SEL
SPI1_SCK
SPI1_MOSI
AF1
GT1_CH0
GT1_CH1
GT1_CH2
AF2
I2C1_SCL
I2C1_SDA
UR0_RI
AF3
23
24
RTCOUT
XTAL32K
OUT
XTAL32K
IN
VLDOOUT
P18
22
UR1_RTS
PE13
PE12
PE11
SCI_DET
MT_ETI
UR0_RX
CKOUT
--
UR0_TX
SPI1_MISO
GT1_CH3
UR0_DCD
PB5
PB6_
WAKEUP
PB4
I2C1_SDA
UR0_DTR
Figure 5. HT32F1755/1765/2755 64-LQFP Pin Assignment
Rev. 1.00
22 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GT1_CH0
GT1_CH1
GT1_CH2
GT1_CH3
76
5VT
5VT
AF0
(Default)
AF1
AF2
AF3
AF3*
(HT32F1755)
(HT32F2755)
(HT32F1765)
GT1_CH0
SCI_CLK
ADC_IN0
PA0
1
33V
5VT
75
PD7
SPI1_MISO
GT1_CH1
SCI_DIO
ADC_IN1
PA1
2
33V
5VT
74
PD6
SPI1_MOSI
GT1_CH2
UR0_TX
ADC_IN2
PA2
3
33V
5VT
73
PD5
SPI1_SCK
GT1_CH3
UR0_RX
ADC_IN3
PA3
4
33V
5VT
72
PD4
SPI1_SEL
SPI1_SEL
UR1_RTS
ADC_IN4
PA4
5
33V
5VT
71
PD3
GT0_CH3
SPI0_MISO
SPI1_SCK
UR1_CTS
ADC_IN5
PA5
6
33V
5VT
70
PD2
GT0_CH2
SPI0_MOSI
SPI1_MOSI
UR1_TX
ADC_IN6
PA6
7
33V
5VT
69
PD1
GT0_CH1
SPI0_SCK
UR0_RI
SPI1_MISO
UR1_RX
ADC_IN7
PA7
8
33V
5VT
68
PD0
GT0_CH0
SPI0_SEL
UR0_DTR
UR0_RTS
SPI1_SEL
PA8
9
5VT
UR0_CTS
SPI1_SCK
PA9
10
5VT
UR0_TX
SPI1_MOSI
PA10
11
5VT
UR0_RX
SPI1_MISO
PA11
12
5VT
GT1_CH0
PA12
13
5VT
P33
AP
3.3 V Digital Power Pad
3.3 V Analog Power Pad
P18
1.8 V Power Pad
33V
3.3 V I/O Pad
UR0_DCD
5VT
5 V Tolerance I/O Pad
5VT
67
PC15
SCI_DET
GT0_ETI
UR0_DSR
High Current Output
5 V Tolerance I/O Pad
5VT
5VT
66
PC14
SCI_DIO
MT_CH0N
UR1_CTS
5VT
65
PC13
SCI_CLK
MT_CH0
USB
USB PHY Pad
5VT
64
PC12
I2C0_SDA
MT_CH1N
UR0_CTS
CSIF_MCK
Backup Domain Pad
5VT
63
PC11
I2C0_SCL
MT_CH1
UR0_RTS
CSIF_PCK
BAK
P33
62
VSS33_3
UR1_RTS
VDD33_1
14
VSS33_1
15
P33
P33
61
VDD33_3
USBDP
16
USB
5VT
60
JTRST
PE15
MT_CH0N
UR1_RX
CSIF_VSYNC
USBDM
17
USB
5VT
59
JTDI
PE14
MT_CH0
UR1_TX
CSIF_HSYNC
GT1_CH1
PA13
18
5VT
5VT
58
GT1_CH2
PA14
19
5VT
5VT
GT1_CH3
PA15
20
5VT
5VT
P33
JTMS_
SWDIO
JTCK_
57
SWCLK
JTDO_
56
TRACESWO
PC10
PE13
PE12
PE11
SPI0_SEL
UR1_RTS
GT0_CH0
PB0
21
5VT
5VT
55
SPI0_SCK
UR1_CTS
GT0_CH1
PB1
22
5VT
5VT
54
SPI0_MOSI
UR1_TX
GT0_CH2
PB2
23
5VT
5VT
53
SPI0_MISO
UR1_RX
GT0_CH3
PB3
24
5VT
5VT
52
PC7
NC
25
5VT
5VT
51
PC6
I2C1_SCL
SCI_CLK
PC9_
BOOT1
PC8_
BOOT0
5VT
5VT
5VT
5VT
5VT
5VT
26
27
28
29
30
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VLDOIN
VSSLDO
nRST
VBAT
XTALIN
XTALOUT
VDD33_2
VSS33_2
PB13
PB14
PB15
PC0
PC1
PC2
PC3
PC4
PC5
AF0
(Default)
PB11
PB12
UR0_RX
UR1_CTS
UR1_RTS
SPI1_SEL
SPI1_SCK
SPI1_MOSI
SPI1_MISO
UR1_TX
UR1_RX
AF1
GT1_CH0
GT1_CH1
GT1_CH2
GT1_CH3
I2C0_SCL
I2C0_SDA
AF2
I2C1_SCL
I2C1_SDA
UR0_RI
UR0_DCD
32
33
34
35
PB4
31
MT_ETI
UR0_RX
CKOUT
--
UR0_TX
I2C1_SDA
SCI_DIO
GT1_ETI
I2C1_SDA
UR0_DTR
AF3
5VT
UR0_TX
5VT
UR0_CTS
5VT
PB9
P33
PB10
P33
GT0_ETI
33V
UR0_RTS
33V
PB8
5VT
PB7
5VT
PB5
5VT
PB6_
WAKEUP
5VT
RTCOUT
BAK BAK BAK BAK BAK
5VT P33 33V 33V 5VT
XTAL32KIN
P33
XTAL32KOUT
P33
VLDOOUT
P18
SCI_DET
Figure 6. HT32F1755/1765/2755 100-LQFP Pin Assignment
Rev. 1.00
23 of 45
August 13, 2012
Overview
77
5VT
PD8
78
5VT
PD9
79
5VT
PD10
80
5VT
PD11
81
5VT
PD12
82
5VT
PD13
83
5VT
PD14
84
P33
PD15
85
P33
PE0
86
5VT
AF0
(Default)
VDD33_4
VSS33_4
87
5VT
PE1
88
5VT
PE2
89
5VT
PE3
90
33V
PE4
91
33V
PE5
92
33V
PE6
93
33V
PE7
94
33V
AF1
SPI0-SEL
SPI0_SCK
SPI0_MOSI
SPI0_MISO
MT_CH0
MT_CH0N
MT_CH1
MT_CH1N
MT_CH2
MT_CH2N
MT_CH3
MT_ETI
MT_BRK
CP0
CN0
AOUT0
95
33V
PE8
96
AP
PE9
97
AP
AP
AF2
MT_CH2
MT_CH2N
MT_CH3
MT_BRK
I2C0_SCL
I2C0_SDA
SCI_CLK
SCI_DIO
GT0_CH0
GT0_CH1
GT0_CH2
CP1
CN1
98
AP
AF3
AF3*
(HT32F1755)
(HT32F2755)
(HT32F1765)
CSIF_D0
CSIF_D1
CSIF_D2
CSIF_D3
GT1_ETI
SPI1-SEL
SPI1_SCK
SPI1_MOSI
GT0_ETI
CSIF_D4
CSIF_D5
CSIF_D6
GT0_ETI
GT0_CH3
AF0
(Default)
PE10
VDDA
AF1
SPI1_MISO
AOUT1
AF2
I2C1_SCL
GT1_ETI
VREF+
100 99
VSSA
VREF-
AF3
CSIF_D7
I2C1_SDA
Holtek
HT32F1755/1765/2755
100 LQFP
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table 2. HT32F1755/1765/2755 Pin Descriptions
Pins
Description
(Note1)
IO
Level
1
AI/O
—
PA0
ADC_IN0
SCI_CLK GT1_CH0
GT1_CH0
2
AI/O
—
PA1
ADC_IN1
SCI_DIO GT1_CH1
GT1_CH1
3
3
AI/O
—
PA2
ADC_IN2
UR0_TX GT1_CH2
GT1_CH2
4
4
AI/O
—
PA3
ADC_IN3
UR0_RX GT1_CH3
GT1_CH3
5
5
5
AI/O
—
PA4
ADC_IN4
UR1_RTS
SPI1_SEL
/TXE
SPI1_SEL
PA5
6
6
6
AI/O
—
PA5
ADC_IN5
UR1_CTS
SPI1_SCK
/SCK
SPI1_SCK
PA6
7
7
7
AI/O
—
PA6
ADC_IN6
UR1_TX SPI1_MOSI SPI1_MOSI
PA7
8
8
8
AI/O
—
PA7
ADC_IN7
UR1_RX SPI1_MISO SPI1_MISO
48
64
100
LQFP LQFP LQFP
PA0
1
1
PA1
2
2
PA2
3
PA3
4
PA4
(Note2)
Main
function
(AF0)
AF1
AF2
AF3
AF3
(HT32F1755)
(HT32F2755)
(HT32F1765)
PA8
—
—
9
I/O
5V-T
PA8
SPI1_SEL
UR0_RTS
/TXE
—
—
PA9
—
—
10
I/O
5V-T
PA9
SPI1_SCK
UR0_CTS
/SCK
—
—
PA10
—
—
11
I/O
5V-T
PA10
SPI1_MOSI UR0_TX
—
—
PA11
—
—
12
I/O
5V-T
PA11
SPI1_MISO UR0_RX
—
—
—
5V-T
PA12
GT1_CH0
—
—
PA12
13
I/O
VDD33_1
9
—
9
14
P
—
3.3V voltage for digital I/O
—
VSS33_1
10
10
15
P
—
Ground reference for digital I/O
USBDP
11
11
16
AI/O
—
USB Differential data bus conforming to the Universal Serial Bus
standard
USBDM
12
12
17
AI/O
—
USB Differential data bus conforming to the Universal Serial Bus
standard
PA13
—
—
18
I/O
5V-T
PA13
GT1_CH1
—
—
—
PA14
—
—
19
I/O
5V-T
PA14
GT1_CH2
—
—
—
PA15
—
—
20
I/O
5V-T
PA15
GT1_CH3
—
—
—
SPI0_SEL
UR1_CTS
SPI0_SCK
/SCK
SPI0_SCK
PB0
—
13
21
I/O
5V-T
PB0
UR1_RTS
GT0_CH0
SPI0_SEL
/TXE
PB1
—
14
22
I/O
5V-T
PB1
GT0_CH1
PB2
—
15
23
I/O
5V-T
PB2
GT0_CH2 UR1_TX
SPI0_MOSI SPI0_MOSI
PB3
—
16
24
I/O
5V-T
PB3
GT0_CH3 UR1_RX
SPI0_MISO SPI0_MISO
NC
—
25
—
—
No connection
—
VLDOOUT 13
17
26
P
—
LDO 1.8V output
It is recommended to connect a capacitor, denoted as CLDO, as
close as possible between this pin and VSSLDO
VLDOIN
14
18
27
P
—
LDO 3.3V power input
Connected to the power switch circuitry for the internal backup
domain
VSSLDO
15
19
28
P
—
LDO ground reference
nRST
16
20
29
I
5V(BK) T_PU
External reset pin and external wakeup pin in Power-Down mode
VBAT
17
21
30
P
VDD 3.3V for backup domain
Rev. 1.00
—
24 of 45
August 13, 2012
Overview
Pin Name
Type
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Pins
Pin Name
48
64
100
LQFP LQFP LQFP
Type
(Note1)
IO
Level
(Note2)
Description
Main
function
(AF0)
AF1
AF2
AF3
AF3
(HT32F1755)
(HT32F2755)
(HT32F1765)
18
22
31
AI/O
(BK)
—
XTAL32KIN
PB4
—
—
—
XTAL32KOUT
19
23
32
AI/O
(BK)
—
XTAL32KOUT PB5
—
—
—
RTCOUT
20
24
33
I/O
5V-T
(BK)
RTCOUT
PB6_
WAKEUP
—
—
—
25
34
I/O
5V-T
PB7
GT0_ETI
I2C1_
SDA
PB7
—
PB8
—
—
35
I/O
5V-T
PB8
UR0_RTS
/TXE
—
—
—
PB9
—
—
36
I/O
5V-T
PB9
UR0_CTS
/SCK
—
—
—
—
5V-T
PB10
UR0_DTR
37
I/O
PB10
UR0_TX
—
—
—
21
26
38
AI/O
—
XTALIN
PB11
—
—
—
XTALOUT 22
27
39
AI/O
—
XTALOUT
PB12
—
—
—
VDD33_2
23
28
40
P
—
3.3V voltage for digital I/O
VSS33_2
24
29
41
P
—
Ground reference for digital I/O
42
I/O
XTALIN
PB13
—
UR0_DTR
—
—
5V-T
PB13
UR0_RX
—
—
—
GT1_ETI
—
—
—
—
PB14
—
—
43
I/O
5V-T
PB14
UR1_CTS
/SCK
PB15
—
—
44
I/O
5V-T
PB15
UR1_RTS
/TXE
—
PC0
—
30
45
I/O
5V-T
PC0
SPI1_SEL
GT1_
CH0
I2C1_SCL
I2C1_SCL
PC1
—
31
46
I/O
5V-T
PC1
SPI1_SCK
GT1_
CH1
I2C1_SDA
I2C1_SDA
PC2
—
32
47
I/O
5V-T
PC2
SPI1_
MOSI
GT1_
CH2
UR0_RI
UR0_RI
PC3
—
33
48
I/O
5V-T
PC3
SPI1_
MISO
GT1_
CH3
UR0_DCD
UR0_DCD
PC4
—
—
49
I/O
5V-T
PC4
UR1_TX
I2C0_
SCL
—
—
PC5
—
—
50
I/O
5V-T
PC5
UR1_RX
I2C0_
SDA
—
—
PC6
—
—
51
I/O
5V-T
PC6
I2C1_SCL
SCI_
CLK
—
—
PC7
—
—
52
I/O
5V-T
PC7
I2C1_SDA SCI_DIO
—
—
PC8
25
34
53
I/O
5V-T_
PU
PC8_BOOT0 CKOUT
—
PC9
26
35
54
I/O
5V-T_
PU
PC9_BOOT1
—
PC10
27
36
55
I/O
5V-T
PC10
PE11
28
37
56
I/O
5V-T
JTDO_
PE11
TRACESWO
Rev. 1.00
25 of 45
—
SCI­_DET
MT_ETI
—
UR0_TX
—
UR0_RX
—
UR0_TX
—
UR0_RX
—
August 13, 2012
Overview
XTAL32KIN
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Pins
Type
IO
Level
Description
Main
function
(AF0)
AF3
AF3
(HT32F1755)
(HT32F2755)
(HT32F1765)
48
64
100
LQFP LQFP LQFP
PE12
29
38
57
I/O
5VT_PU
JTCK_
SWCLK
PE12
—
—
—
PE13
30
39
58
I/O
5VT_PU
JTMS/
SWDIO
PE13
—
—
—
PE14
31
40
59
I/O
5VT_PU
JTDI
PE14
MT_CH0 UR1_TX
CSIF_
HSYNC
PE15
32
41
60
I/O
5VT_PU
JTRST
PE15
MT_
CH0N
UR1_RX
CSIF_
VSYNC
(Note1)
(Note2)
AF1
AF2
VDD33_3
—
42
61
P
—
3.3V voltage for digital I/O
VSS33_3
—
43
62
P
—
Ground reference for digital I/O
PC11
33
44
63
I/O
5V-T
PC11
I2C0_SCL
MT_CH1
UR0_RTS
/TXE
CSIF_PCK
PC12
34
45
64
I/O
5V-T
PC12
I2C0_SDA
MT_
CH1N
UR0_CTS
/SCK
CSIF_MCK
PC13
—
46
65
I/O
5V-T
PC13
SCI_CLK
MT_CH0
UR1_RTS
/TXE
UR1_RTS
/TXE
PC14
—
47
66
I/O
5V-T
PC14
SCI_DIO
MT_
CH0N
UR1_CTS
/SCK
UR1_CTS
/SCK
PC15
—
48
67
I/O
5V-T
PC15
SCI_DET
GT0_ETI UR0_DSR
UR0_DSR
PD0
—
—
68
I/O
5V-T
PD0
GT0_CH0
SPI0_
SEL
UR0_DTR
UR0_DTR
PD1
—
—
69
I/O
5V-T
PD1
GT0_CH1
SPI0_
SCK
UR0_RI
UR0_RI
PD2
—
—
70
I/O
5V-T
PD2
GT0_CH2
SPI0_
MOSI
UR0_DCD
UR0_DCD
PD3
—
—
71
I/O
5V-T
PD3
GT0_CH3
SPI0_
MISO
—
—
PD4
—
—
72
I/O
5V-T
PD4
SPI1_SEL
—
—
—
PD5
—
—
73
I/O
5V-T
PD5
SPI1_SCK
—
—
—
PD6
—
—
74
I/O
5V-T
PD6
SPI1_
MOSI
—
—
—
PD7
—
—
75
I/O
5V-T
PD7
SPI1_
MISO
—
—
—
VDD33_3
35
VSS33_3
36
PD8
37
49
76
I/O
5V-T
PD8
SPI0_SEL
MT_CH2 GT1_CH0
CSIF_D0
PD9
38
50
77
I/O
5V-T
PD9
SPI0_SCK
MT_
CH2N
GT1_CH1
CSIF_D1
PD10
39
51
78
I/O
5V-T
PD10
SPI0_
MOSI
MT_CH3 GT1_CH2
CSIF_D2
PD11
40
52
79
I/O
5V-T
PD11
SPI0_
MISO
MT_BRK GT1_CH3
CSIF_D3
53
80
I/O
5V-T
PD12
MT_CH0
I2C0_
SCL
GT1_ETI
PD12
Rev. 1.00
—
—
—
—
P
—
P
—
3.3V voltage for digital I/O
—
Ground reference for digital I/O
26 of 45
GT1_ETI
August 13, 2012
Overview
Pin Name
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Pins
Pin Name
48
64
100
LQFP LQFP LQFP
Type
(Note1)
IO
Level
(Note2)
Description
Main
function
(AF0)
AF1
AF2
I/O
5V-T
PD13
MT_CH0N
I2C0_
SDA
—
82
I/O
5V-T
PD14
MT_CH1
SCI_
CLK
—
83
I/O
5V-T
PD15
—
84
I/O
5V-T
PE0
85
P
86
P
87
I/O
5V-T
PE1
—
88
I/O
5V-T
—
89
I/O
5V-T
—
90
I/O
5V-T
—
54
PD14
—
PD15
—
PE0
—
VDD33_4
—
55
VSS33_4
—
56
PE1
—
—
PE2
—
PE3
—
PE4
—
GT0_ETI
GT0_ETI
—
—
MT_CH1N SCI_DIO
—
—
MT_CH2
—
—
—
MT_CH2N
—
—
—
PE2
MT_CH3
—
—
—
PE3
MT_BRK
—
—
—
PE4
MT_ETI
—
—
—
—
3.3V voltage for digital I/O
—
Ground reference for digital I/O
PE5
41
57
91
AI/O
—
PE5
CN0
GT0_
CH0
PE6
42
58
92
AI/O
—
PE6
CP0
GT0_
CH1
SPI1_SCK CSIF_D5
PE7
43
59
93
AI/O
—
PE7
AOUT0
GT0_
CH2
SPI1_
MOSI
CSIF_D6
PE8
44
60
94
AI/O
—
PE8
CN1
GT0_
CH3
SPI1_
MISO
CSIF_D7
PE9
45
61
95
AI/O
—
PE9
CP1
GT0_ETI I2C1_SCL
I2C1_SCL
PE10
46
62
96
AI/O
—
PE10
AOUT1
GT1_ETI I2C1_SDA
I2C1_SDA
VDDA
47
63
97
P
—
3.3V analog voltage for ADC and OPA/Comparator
SPI1_SEL
CSIF_D4
VREF+
—
—
98
P
—
ADC positive reference voltage has to be lower or equal to
VDDA
VREF-
—
—
99
P
—
ADC negative reference voltage has to be directly connected to
VSSA
100
P
—
Ground reference for the ADC and OPA/Comparator
VSSA
48
64
NOTES: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, BK = Back-up domain.
2. 5V-T = 5V tolerant.
3. The GPIOs are in an AF0 state after a VDD18 power on reset (POR) except for the RTCOUT pin of in
the Backup Domain I/O. The RTCOUT pin is reset by the Backup Domain power-on-reset (PORB) or
by a Backup Domain software reset (BAK_RST bit in BAK_CR register).
4. The backup domain of I/O pins has drive current capability limitation of < 1mA @ VBAT = 3.3V.
Rev. 1.00
27 of 45
August 13, 2012
Overview
81
PD13
AF3
AF3
(HT32F1755)
(HT32F2755)
(HT32F1765)
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
4
Electrical Characteristics
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD33
External main supply voltage
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VLDOIN
External LDO supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V-tolerant I/O
VSS - 0.3
VSS + 5.5
V
Input voltage on other I/O
VSS - 0.3
VDD33 + 0.3
V
VIN
TA
Ambient operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
PD
Total power dissipation
—
500
mW
VESD
Electrostatic discharge voltage (human body mode)
-4000
+4000
V
Recommended DC Characteristics
Table 4. Recommended DC Operating Conditions
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
VDD33
I/O Operating voltage
—
2.7
3.3
3.6
V
VDDA
Analog operating voltage
—
2.7
3.3
3.6
V
VBAT
Battery supply operating voltage
—
2.7
3.3
3.6
V
VLDOIN
LDO operating voltage
—
2.7
3.3
3.6
V
On-Chip LDO Voltage Regulator Characteristics
Table 5. LDO Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min Typ Max Unit
VLDOOUT
Internal regulator output voltage
VLDOIN = 3.3V Regulator input
1.71
1.8
1.89
V
ILDOOUT
Output current
VLDOIN = 2.7V Regulator input
—
—
200
mA
CLDO
External filter capacitor value for
internal core power supply
The capacitor value is dependent on
the core power current consumption
2.2
—
10
μF
Rev. 1.00
28 of 45
August 13, 2012
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Power Consumption
Table 6. Power Consumption Characteristics
Symbol
Parameter
Min
Typ
VDD33 = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz,
fHCLK = 72MHz, fPCLK = 72MHz, All peripherals enabled
—
60
72
mA
VDD33 = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz,
fHCLK = 72MHz, fPCLK = 72MHz, All peripherals disabled
—
27
34
mA
VDD = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz, fHCLK
= 0MHz, fPCLK = 72MHz, All peripherals enabled
—
42
50
mA
VDD33 = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz,
fHCLK = 0MHz, fPCLK = 72MHz, All peripherals disabled
—
9
12
mA
Supply current
(Deep-Sleep1
mode)
VDD33 = VBAT = 3.3V, All clock off (HSE/PLL/fHCLK), LDO
in low power mode, LSI on, RTC on
—
58
90
μA
Supply current
(Deep-Sleep2
mode)
VDD33 = VBAT = 3.3V, All clock off (HSE/PLL/fHCLK), LDO
off (DMOS on), LSI on, RTC on
—
18
25
μA
VDD33 = VBAT = 3.3V, LDO off, LSE on, LSI off, RTC on
—
—
—
μA
VDD33 = VBAT = 3.3V, LDO off, LSE on, LSI off, RTC off
—
—
—
μA
VDD33 = VBAT = 3.3V, LDO off, LSE off, LSI on, RTC on
—
—
—
μA
VDD33 = VBAT = 3.3V, LDO off, LSE off, LSI on, RTC off
—
5
6
μA
VDD33 not present, VBAT = 3.3V, LDO off, LSE off, LSI
on, RTC on
—
4
—
μA
—
3.9
—
μA
Supply current
(Sleep mode)
Supply current
(Power-Down
mode)
Battery supply
current (PowerVDD33 not present, VBAT = 3.3V, LDO off, LSE off, LSI
Down mode)
on, RTC off
IBAT
Max Unit
NOTES: 1. HSE is the high speed external oscillator. HSI means 8MHz high speed internal oscillator.
2. LSE means low speed external oscillator. LSI means 32.768KHz low speed internal oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.
Reset and Supply Monitor Characteristics
Table 7. LVD/BOD Characteristics
Symbol
VBOD
VLVD
VPOR
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
—
—
2.6
—
V
LVDS
(Note1)
= ‘00’
—
2.7
—
V
LVDS
(Note1)
Brown Out Detector Voltage
Voltage of Low Voltage Detector
= ‘01’
—
2.8
—
V
LVDS (Note1) = ‘10’
—
2.9
—
V
LVDS
= ‘11’
—
3.0
—
V
—
—
1.36
—
V
Power On Reset Voltage
(Note1)
NOTE: LVDS field is in PWRCU LVDCSR register.
Rev. 1.00
29 of 45
August 13, 2012
Electrical Characteristics
Conditions
Supply current
(Run mode)
IDD
TA = 25°C, unless otherwise specified.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
External Clock Characteristics
Table 8. High Speed External Clock (HSE) Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
High Speed External oscillator frequency (HSE)
CHSE
Recommended load capacitance on XTAL32IN
and XTAL32OUT pins
RFHSE
VDD33 = 3.3V
4
—
16
MHz
—
—
TBD
—
pF
Recommended external feedback resistor
between XTAL32IN and XTAL32OUT pins
—
—
1.0
—
MΩ
DHSE
HSE Oscillator Duty cycle
—
40
—
60
%
IDDHSE
HSE Oscillator Operating Current
VDD33 = 3.3V, TA = 25°C
—
0.96
—
mA
ISTBHSE
HSE Oscillator Standby current
VDD33 = 3.3V, TA = 25°C
—
—
0.1
μA
tSUHSE
HSE Oscillator Startup time
VDD33 = 3.3V, TA = 25°C
—
—
4
ms
Table 9. Low Speed External Clock (LSE) Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max Unit
VDD33 = VBAT = 3.3V
—
32.768
—
kHz
fLSE
Low Speed External oscillator
frequency (LSE)
CLSE
Recommended load capacitance on
XTAL32KIN and XTAL32KOUT pins
—
—
TBD
—
pF
RFLSE
Recommended external feedback
resistor between XTAL32KIN and
XTAL32KOUT pins
—
—
10
—
MΩ
DLSE
LSE Oscillator Duty cycle
—
40
—
60
%
IDDLSE
LSE Oscillator Operating Current
VDD33 = VBAT = 3.3V,
LSESM = 0 (Normal startup mode)
—
1.7
—
μA
ISTBLSE
LSE Oscillator Standby current
VDD33 = VBAT = 3.3V, LSESM = 1
(Fast startup mode)
—
3
8
μA
tSULSE
LSE Oscillator Startup time
VDD33 = VBAT = 3.3V, LSESM = 1
(Fast startup mode)
—
200
—
ms
Rev. 1.00
30 of 45
August 13, 2012
Electrical Characteristics
fHSE
Min Typ Max Unit
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Internal Clock Characteristics
Table 10. High Speed Internal Clock (HSI) Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min Typ Max Unit
High Speed Internal Oscillator
Frequency (HSI )
VDD33 = 3.3V,
TA = -40°C ~ +85°C
—
8
—
MHz
ACCHSI
HSI Oscillator Frequency
accuracy
Factory-trimmed,
VDD33 = 3.3V, TA = -40°C ~ +85°C
-5
—
+5
%
DHSI
HSI Oscillator Duty cycle
VDD33 = 3.3V, fHSI = 8MHz
35
—
65
%
IDDHSI
HSI Oscillator Operating Current
VDD33 = 3.3V, fHSI = 8MHz
—
0.92
—
mA
tSUHSI
HSI Oscillator Startup time
VDD33 = 3.3V, fHSI = 8MHz, HSIRCBL = 0
(HSI Ready Counter Bits Length 7 Bits )
—
17
—
μs
NOTE: HSIRCBL field is in PWRCU HSIRCR register.
Table 11. Low Speed Internal Clock (LSI) Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min Typ Max Unit
fLSI
Low Speed Internal Oscillator
Frequency(LSI)
VDD33 = VBAT = 3.3V,
TA = -40°C ~ +85°C
25
32
43
kHz
IDDLSI
LSI Oscillator Operating Current
VDD33 = VBAT = 3.3V,
TA = 25°C
—
1.0
2
μA
tSULSI
LSI Oscillator Startup time
VDD33 = VBAT = 3.3V,
TA = 25°C
—
35
—
ms
PLL Characteristics
Table 12. PLL Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
fPLLIN
PLL input clock
—
4
—
16
MHz
fPLL
PLL output clock
—
8
—
144
MHz
tLOCK
PLL lock time
—
—
TBD
—
ms
Memory Characteristics
Table 13. Flash Memory Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
NENDU
Number of guaranteed program /erase
cycles before failure. (Endurance)
TA= -40°C ~ +85°C
20
—
—
kcycles
TRET
Data retention time
TA = 25°C
100
—
—
Years
tPROG
Word programming time
TA = -40°C ~ +85°C
40
—
—
μs
tERASE
Page erase time
TA = -40°C ~ +85°C
20
—
40
ms
tMERASE
Mass erase time
TA = -40°C ~ +85°C
20
—
40
ms
Rev. 1.00
31 of 45
August 13, 2012
Electrical Characteristics
fHSI
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
I/O Port Characteristics
Table 14. I/O Port Characteristics
Symbol
Parameter
Conditions
3.3V IO
IIL
Low level input current
5V-tolerant IO
3.3V IO
High level input current
5V-tolerant IO
Reset pin
VIL
VIH
VHYS
IOL
IOH
VOL
Low level input voltage
High level input voltage
Schmitt Trigger Input
Voltage Hysteresis
Low level output current
(GPO Sink current)
High level output current
(GPO Source current)
Low level output voltage
VI = 0V, On-chip pull-up
resister disabled.
VI = VDD33, On-chip pulldown resister disabled.
Rev. 1.00
High level output voltage
Typ Max Unit
—
—
3
μA
—
—
3
μA
—
—
3
μA
—
—
3
μA
—
—
3
μA
—
—
3
μA
3.3V IO
-0.3
—
0.8
V
5V-tolerant IO
-0.3
—
0.8
V
Reset pin
-0.3
—
0.8
V
3.3V IO
2
—
3.6
V
5V-tolerant IO
2
—
5.5
V
Reset pin
2
—
5.5
V
3.3V IO
—
400
—
mV
5V-tolerant IO
—
400
—
mV
Reset pin
—
400
—
mV
3.3V IO 4mA drive, VOL = 0.4V
4
—
—
mA
3.3V IO 8mA drive, VOL = 0.4V
8
—
—
mA
5V-tolerant 8mA drive IO, VOL=0.4V
8
—
—
mA
5V-tolerant 12mA drive IO, VOL=0.4V
12
—
—
mA
Backup Domain IO drive @ VBAT =3.3V,
VOL = 0.4V, PB4, PB5, PB6
—
—
1
mA
3.3V I/O 4mA drive, VOH=VDD33 - 0.4V
4
—
—
mA
3.3V I/O 8mA drive, VOH=VDD33 - 0.4V
8
—
—
mA
5V-tolerant I/O 8mA drive,
VOH = VDD33 - 0.4V
8
—
—
mA
5V-tolerant I/O 12mA drive,
VOH = VDD33 - 0.4V
12
—
—
mA
Backup Domain IO [email protected]=3.3V,
VOH = VDD33 - 0.4V, PB4, PB5, PB6
—
—
1
mA
3.3V 4mA drive IO, IOL = 4mA
—
—
0.4
V
3.3V 8mA drive IO, IOL = 8mA
—
—
0.4
V
5V-tolerant 8mA drive IO, IOL=8mA
—
—
0.4
V
5V-tolerant 12mA drive IO, IOL=12mA
VOH
Min
—
—
0.4
V
3.3V 4mA drive IO, IOH = 4mA
VDD33 - 0.4V
—
—
V
3.3V 8mA drive IO, IOH = 8mA
VDD33 - 0.4V
—
—
V
5V-tolerant 8mA drive IO, IOH=8mA
VDD33 - 0.4V
—
—
V
5V-tolerant 12mA drive IO,
IOH=12mA
VDD33 - 0.4V
—
—
V
32 of 45
August 13, 2012
Electrical Characteristics
Reset pin
IIH
TA = 25°C, unless otherwise specified.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Symbol
RPU
Parameter
Internal pull-up resistor
RPD
Internal pull-down resistor
Conditions
Min
Typ Max Unit
3.3V I/O
34
—
74
kΩ
5V-tolerant I/O
38
—
89
kΩ
3.3V I/O
29
—
86
kΩ
5V-tolerant I/O
35
—
107
kΩ
Table 15. ADC Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min Typ Max
Unit
VDDA
Operating voltage
—
2.7
3.3
3.6
V
VADCIN
A/D Converter input voltage range
—
0
—
VREF+
V
VREF+
A/D Converter Reference voltage
—
—
VDDA
VDDA
V
IADC
Current consumption
VDDA = 3.3V
—
1
TBD
mA
IADC_DN
Power down current consumption
VDDA = 3.3V
—
1
10
μA
fADC
A/D Converter clock
—
0.7
—
14
MHz
fS
Sampling rate
—
0.05
—
1
MHz
fADCCONV
A/D Converter conversion time
—
—
14
—
1/fADC
Cycles
RI
Input sampling switch resistance
—
—
—
1
kΩ
CI
Input sampling capacitance
No pin/pad capacitance included
—
—
5
pF
tSU
Start up time
—
—
—
1
μs
N
Resolution
—
—
12
—
bits
INL
Integral Non-linearity error
fS = 1MHz, VDDA = 3.3V
-—
±2
±5
LSB
DNL
Differential Non-linearity error
fS = 1MHz, VDDA = 3.3V
—
—
±1
LSB
EO
Offset error
—
—
—
±10
LSB
EG
Gain error
—
—
—
±10
LSB
NOTES: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input stage
where CI is the storage capacitor, RI is the resistance of the sampling switch and RS is the output
impedance of the signal source VS. Normally the sampling phase duration is approximately, 1.5/fADC.
The capacitance, CI, must be charged within this time frame and it must be ensured that the voltage
at its terminals becomes sufficiently close to VS for accuracy. To guarantee this, RS may not have an
arbitrarily large value.
Rev. 1.00
33 of 45
August 13, 2012
Electrical Characteristics
ADC Characteristics
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
SAR ADC
sample
RS
RI
Figure 7. ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and V REF ) are sampled
consecutively. In this situation a sampling error below 1/4 LSB is ensured by using the following
equation:
RS <
1.5
− RI
f ADC C I ln(2 N + 2 )
where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where this A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, Rs may be larger than the value indicated by the equation
above.
Rev. 1.00
34 of 45
August 13, 2012
Electrical Characteristics
CI
VS
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Operation Amplifier/Comparator Characteristics
Table 16. OPA/CMP Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
Operating voltage
Parameter
—
2.7
3.3
3.6
V
IOPA/CMP
Typical operating current
—
—
230
—
μA
Assign registers OPAEN = 0
and EN_OPAOP = 0
—
—
0.1
μA
VDDA = 3.3V,
AnOF[5:0] = ‘100000’
-15
—
15
mV
VDDA = 3.3V, After calibration
-1
—
1
mV
TA = -40°C ~ +85°C
—
—
0.04
mV/°C
IOPA/CMP_DN Power down supply current
VIOS
Input offset voltage
VIOS_DRIFT
Input offset voltage drift
RINPUT
Input resistance
—
—
10
—
MΩ
GV
Voltage Gain
—
60
100
—
dB
Ut
Unit-Gain Bandwidth
RL = 100kΩ
—
1.3
—
RL = 100kΩ, CL = 100pF
—
1.24
—
VCM
Common mode voltage range VDDA = 3.3V
VSSA
—
VDDA – 1.2
V
VOV
OPA output voltage swing
VDDA = 3.3V
VSSA + 0.3
—
VDDA – 0.5
V
tRT
Comparator response time
VDDA = 3.3V;
Input Overdrive = ±10mV
—
1
—
μs
SR
Slew Rate
VDDA = 3.3V;
Output capacitor load
CL=100pF
—
1.6
—
V/μs
MHz
NOTE: Guaranteed by design, not tested in production.
GPTM/MCTM Characteristics
Table 17. GPTM/MCTM Characteristics
Conditions
Min
Typ
Max
Unit
fTM
Symbol
Timer clock source for GPTM and MCTM
—
—
—
72
MHz
tRES
Timer resolution time
—
1
—
—
fTM
fEXT
External signal frequency on channel 1 ~ 4
—
—
—
1/2
fTM
RES
Timer resolution
—
—
—
16
bits
Rev. 1.00
Parameter
35 of 45
August 13, 2012
Electrical Characteristics
Conditions
VDDA
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
I2C Characteristics
Table 18. I2C Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SCL clock frequency
—
—
—
400
kHz
tSCL(H)
SCL clock high time
—
600
—
—
ns
tSCL(L)
SCL clock low time
—
1300
—
—
ns
tFALL
SCL and SDA fall time
—
—
—
300
ns
tRISE
SCL and SDA rise time
—
—
—
300
ns
tSU(STA)
START condition setup time
—
600
—
—
ns
tH(STA)
START condition hold time
—
600
—
—
ns
tSU(SDA)
SDA data setup time
—
100
—
—
ns
tH(SDA)
SDA data hold time
—
0
—
—
ns
tSU(STO)
STOP condition setup time
—
600
—
—
ns
tRISE
tFALL
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 8. I2C Timing Diagrams
Rev. 1.00
36 of 45
August 13, 2012
Electrical Characteristics
fSCL
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
SPI Characteristics
Table 19. SPI Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
fPCLK/4
MHz
tSCK(H)
SCK clock high time
—
fPCLK/8
—
—
ns
tSCK(L)
SCK clock low time
—
fPCLK/8
—
—
ns
tV(MO)
Data output valid time
—
—
—
5
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
SPI Slave mode
tSU(SEL)
SEL enable setup time
—
4 tPCLK
—
—
ns
tH(SEL)
SEL enable hold time
—
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
tV(MO)
MOSI
DATA VALID
tSU(MI)
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI)
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
tSU(MI)
tH(MO)
DATA VALID
DATA VALID
DATA VALID
tH(MI)
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 9. SPI Timing Diagrams – SPI Master Mode
Rev. 1.00
37 of 45
August 13, 2012
Electrical Characteristics
SPI Master mode
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
SEL
tSU(SEL)
tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(L)
Electrical Characteristics
tSCK(H)
SCK
(CPOL=1)
tSU(SI)
MOSI
tH(SI)
LSB/MSB IN
MSB/LSB IN
tA(SO)
tV(SO)
tDIS(SO)
tH(SO)
LSB/MSB OUT
MSB/LSB OUT
MISO
Figure 10. SPI Timing Diagrams – SPI Slave Mode and CPHA=1
CSIF Characteristics
Table 20. CSIF Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fMCK
CSIF_MCK clock frequency output
—
—
—
36
MHz
fPCK
CSIF_PCK clock frequency input
—
—
—
24
MHz
rF
APB clock and CSIF_PCK clock
input frequency ratio
—
—
3
—
Rev. 1.00
fPCLK/fPCK
38 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
USB Characteristics
The USB interface is USB-IF certified – Full Speed.
Table 21. USB DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
3.0
—
3.6
V
USB Operating voltage
VDI
Differential input sensitivity
0.2
—
—
V
VCM
Common mode voltage range
—
0.8
—
2.5
V
VSE
Single-ended receiver threshold
—
0.8
—
2.0
V
VOL
Pad output low voltage
VOH
Pad output high voltage
VCRS
Differential output signal cross-point voltage
ZDRV
CIN
|USBDP-USBDM|
0
—
0.3
V
2.8
—
3.6
V
—
1.3
—
2.0
V
Driver output resistance
—
—
10
—
Ω
Transceiver pad capacitance
—
—
—
20
pF
RL of 1.5kΩ to VDD
NOTES: 1. Guaranteed by design, not tested in production.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP pin should be pulled
up with a 1.5kΩ external resistor to a 3.0 to 3.6V voltage supply.
3. The USB functionality is ensured down to 2.7V but not the full USB electrical characteristics which will
experience degradation in the 2.7 to 3.0V VDD voltage range.
4. RL is the load connected to the USB driver USBDP.
Rev. 1.00
39 of 45
August 13, 2012
Electrical Characteristics
VDD
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Rise Time
Fall Time
Tr
Tf
90%
90%
10%
Electrical Characteristics
VCRS
10%
Figure 11. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition
Table 22. USB AC Electrical Characteristics
Min
Typ
Max
Unit
Tr
Symbol
Rise time
CL = 50pF
4
—
20
ns
Tf
Fall time
CL = 50pF
4
—
20
ns
Tr/f
Rise time / fall time matching
Tr/f = Tr / Tf
90
—
110
%
Rev. 1.00
Parameter
Conditions
40 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
5
Package Information
Note that the package information provided here is for consultation purposes only. As this information
may be updated at regular intervals users are reminded to consult the Holtek website (http://www.
holtek.com.tw/english/literature/package.pdf) for the latest version of the package information.
Package Information
48-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Rev. 1.00
Dimensions in inch
Min.
Nom.
Max.
A
0.350
―
0.358
B
0.272
―
0.280
C
0.350
―
0.358
D
0.272
―
0.280
E
―
0.020
―
F
―
0.008
―
G
0.053
―
0.057
H
―
―
0.063
I
―
0.004
—
J
0.018
―
0.030
K
0.004
―
0.008
α
0°
―
7°
41 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Symbol
Min.
Nom.
Max.
A
8.90
―
9.10
B
6.90
―
7.10
C
8.90
―
9.10
D
6.90
―
7.10
E
―
0.50
―
F
―
0.20
―
G
1.35
―
1.45
H
―
―
1.60
I
—
0.10
—
J
0.45
―
0.75
K
0.10
―
0.20
α
0°
―
7°
42 of 45
August 13, 2012
Package Information
Rev. 1.00
Dimensions in mm
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
64-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Min.
Nom.
Max.
A
0.350
―
0.358
B
0.272
―
0.280
C
0.350
―
0.358
D
0.272
―
0.280
E
―
0.016
―
F
0.005
―
0.009
G
0.053
―
0.057
H
―
―
0.063
I
0.002
―
0.006
J
0.018
―
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
8.90
―
9.10
B
6.90
―
7.10
C
8.90
―
9.10
D
6.90
―
7.10
E
―
0.40
―
F
0.13
―
0.23
G
1.35
―
1.45
H
―
―
1.60
I
0.05
―
0.15
J
0.45
―
0.75
K
0.09
―
0.20
α
0°
―
7°
43 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
100-pin LQFP (14mm×14mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.626
―
0.634
B
0.547
―
0.555
C
0.626
―
0.634
D
0.547
―
0.555
E
―
0.020
―
F
―
0.008
―
G
0.053
―
0.057
H
―
―
0.063
I
―
0.004
—
J
0.018
―
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
15.90
―
16.10
B
13.90
―
14.10
C
15.90
―
16.10
D
13.90
―
14.10
E
―
0.50
―
F
―
0.20
―
G
1.35
―
1.45
H
―
―
1.60
I
―
0.10
—
J
0.45
―
0.75
K
0.10
―
0.20
α
0°
―
7°
44 of 45
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Package Information
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned
herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such
applications will be suitable without further modification, nor recommends the use of its products for application
that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its products without
prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
45 of 45
August 13, 2012