Data Sheet

74ALVC164245-Q100
16-bit dual supply translating transceiver; 3-state
Rev. 1 — 14 May 2013
Product data sheet
1. General description
The 74ALVC164245-Q100 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245-Q100 is a 16-bit (dual octal) dual supply translating transceiver
featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there is no current flow from
the non-zero supply towards the zero supply. The nAn outputs must be set 3-state and the
voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B)  VCC(A) (except in
suspend mode).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 5 V tolerant inputs/outputs for interfacing with 5 V logic
 Wide supply voltage range:
 3 V port (VCC(A)): 1.5 V to 3.6 V
 5 V port (VCC(B)): 1.5 V to 5.5 V
 CMOS low power consumption
 Direct interface with TTL levels
 Control inputs voltage range from 2.7 V to 5.5 V
 Inputs accept voltages up to 5.5 V
 High-impedance outputs when VCC(A) or VCC(B) = 0 V
 Complies with JEDEC standard JESD8-B/JESD36
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Ordering information
Table 1.
Ordering information
Type number
Temperature
range
74ALVC164245DGG-Q100 40 C to +125 C
Package
Name
Description
Version
TSSOP48
plastic thin shrink small outline package; 48
leads; body width 6.1 mm
SOT362-1
4. Functional diagram
2DIR
1DIR
2OE
1OE
2A0
1A0
1B0
1A1
2B0
2A1
2B1
1B1
1A2
2A2
1B2
1A3
2B2
2A3
1B3
1A4
2B3
2A4
2B4
1B4
1A5
2A5
1B5
1A6
2B5
2A6
1B6
2B6
2A7
1A7
1B7
2B7
001aaa789
Fig 1.
Logic symbol
74ALVC164245_Q100
Product data sheet
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Rev. 1 — 14 May 2013
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74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
1OE
1DIR
2OE
2DIR
1A0
G3
3EN1[BA]
3EN2[AB]
G6
6EN1[BA]
6EN2[AB]
1B0
1
2
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2A0
2B0
4
5
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2B7
2A7
001aaa790
Fig 2.
IEC logic symbol
74ALVC164245_Q100
Product data sheet
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
$/9&4
',5
2(
%
$
%
$
*1'
*1'
%
$
%
$
9&&%
9&&$
%
$
%
$
*1' *1'
% $
% $
% $
% $
*1' *1'
% $
% $
9&&% 9&&$
% $
% $
*1' *1'
% $
% $
',5 2(
DDD
Fig 3.
Pin configuration SOT362-1 (TSSOP48)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
1DIR, 2DIR
1, 24
direction control input
1B0 to 1B7
2, 3, 5, 6, 8, 9, 11, 12
data input/output
2B0 to 2B7
13, 14, 16, 17, 19, 20, 22, 23
data input/output
GND
4, 10, 15, 21, 28, 34, 39, 45
ground (0 V)
VCC(B)
7, 18
supply voltage B (5 V bus)
1OE, 2OE
48, 25
output enable input (active LOW)
1A0 to 1A7
47, 46, 44, 43, 41, 40, 38, 37
data input/output
2A0 to 2A7
36, 35, 33, 32, 30, 29, 27, 26
data input/output
VCC(A)
31, 42
supply voltage A (3 V bus)
74ALVC164245_Q100
Product data sheet
Description
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
4 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3.
Function table[1]
Inputs
Outputs
nOE
nDIR
nAn
nBn
L
L
nAn = nBn
inputs
L
H
inputs
nBn = nAn
H
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1].
Symbol
Parameter
Conditions
Min
Max
Unit
VCC(B)
supply voltage B
VCC(B)  VCC(A)
0.5
+6.0
V
VCC(A)
supply voltage A
VCC(B)  VCC(A)
0.5
+4.6
V
IIK
input clamping current
VI < 0 V
50
-
mA
0.5
+6.0
V
VI
input voltage
VI/O
input/output voltage
IOK
output clamping current
output voltage
VO
[2]
0.5
VCC + 0.5
V
-
50
mA
output HIGH or LOW
[2]
0.5
VCC + 0.5
V
output 3-state
[2]
0.5
+6.0
V
-
50
mA
VO > VCC or VO < 0 V
IO(sink/source)
output sink or source
current
VO = 0 V to VCC
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
Ptot
total power dissipation
Tamb = 40 C to +125 C
[3]
65
+150
C
-
500
mW
[1]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3]
Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
74ALVC164245_Q100
Product data sheet
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC(B)
supply voltage B
VCC(B)  VCC(A)
supply voltage A
VCC(A)
Min
Typ
Max
Unit
maximum speed performance
2.7
-
5.5
V
low-voltage applications
1.5
-
5.5
V
maximum speed performance
2.7
-
3.6
V
low-voltage applications
1.5
-
3.6
V
VCC(B)  VCC(A)
VI
input voltage
control inputs: nOE and nDIR
0
-
5.5
V
VI/O
input/output voltage
nAn port
0
-
VCC(A)
V
nBn port
0
-
VCC(B)
V
nAn port
0
-
VCC(A)
V
nBn port
0
-
VCC(B)
V
40
-
+125
C
VCC(A) = 2.7 V to 3.0 V
0
-
20
ns/V
VCC(A) = 3.0 V to 3.6 V
0
-
10
ns/V
VCC(B) = 3.0 V to 4.5 V
0
-
20
ns/V
VCC(B) = 4.5 V to 5.5 V
0
-
10
ns/V
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise
and fall rate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
HIGH-level
input voltage
Tamb = 40 C to +85 C
Conditions
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Typ[1]
Max
2.0
-
-
2.0
-
-
V
nBn port
VCC(B) = 3.0 V to 5.5 V
[2]
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V
2.0
-
-
2.0
-
-
V
[2]
1.7
-
-
1.7
-
-
V
VCC(B) = 4.5 V to 5.5 V
[2]
-
-
0.8
-
-
0.8
V
VCC(B) = 3.0 V to 3.6 V
[2]
-
-
0.7
-
-
0.7
V
-
-
0.8
-
-
0.8
V
-
-
0.7
-
-
0.7
V
VCC(A) = 2.3 V to 2.7 V
VIL
LOW-level
input voltage
nBn port
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V
74ALVC164245_Q100
Product data sheet
[2]
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
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74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
Tamb = 40 C to +85 C
Conditions
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Typ[1]
Max
HIGH-level
nBn port; VI = VIH or VIL
output voltage
IO = 24 mA; VCC(B) = 4.5 V
VCC(B)  0.8
-
-
VCC(B)  1.2
-
-
V
IO = 12 mA; VCC(B) = 4.5 V
VCC(B)  0.5
-
-
VCC(B)  0.8
-
-
V
IO = 18 mA; VCC(B) = 3.0 V
VCC(B)  0.8
-
-
VCC(B)  1.0
-
-
V
IO = 100 A; VCC(B) = 3.0 V
VCC(B)  0.2 VCC(B)
-
VCC(B)  0.3 VCC(B)
-
V
IO = 24 mA; VCC(A) = 3.0 V
VCC(A)  0.7
-
-
VCC(A)  1.0
-
-
V
IO = 100 A; VCC(A) = 3.0 V
VCC(A)  0.2
-
-
VCC(A)  0.3
-
-
V
IO = 12 mA; VCC(A) = 2.7 V
VCC(A)  0.5
-
-
VCC(A)  0.8
-
-
V
IO = 8 mA; VCC(A) = 2.3 V
VCC(A)  0.6
-
-
VCC(A)  0.6
-
IO = 100 A; VCC(A) = 2.3 V
VCC(A)  0.2 VCC(A)
-
VCC(A)  0.3 VCC(A)
nAn port; VI = VIH or VIL
VOL
-
V
-
V
LOW-level
nBn port; VI = VIH or VIL
output voltage
IO = 24 mA; VCC(B) = 4.5 V
-
-
0.55
-
-
0.60 V
IO = 12 mA; VCC(B) = 4.5 V
-
-
0.40
-
-
0.80 V
IO = 100 A; VCC(B) = 4.5 V
-
-
0.20
-
-
0.30 V
IO = 18 mA; VCC(B) = 3.0 V
-
-
0.55
-
-
0.80 V
IO = 100 A; VCC(B) = 3.0 V
-
-
0.20
-
-
0.30 V
IO = 24 mA; VCC(A) = 3.0 V
-
-
0.55
-
-
0.80 V
IO = 100 A; VCC(A) = 3.0 V
-
-
0.20
-
-
0.30 V
IO = 12 mA; VCC(A) = 2.7 V
-
-
0.40
-
-
0.60 V
IO = 12 mA; VCC(A) = 2.3 V
-
-
0.60
-
-
0.60 V
IO = 100 A; VCC(A) = 2.3 V
-
-
0.20
-
-
0.20 V
-
0.1
5
-
0.1
10
A
-
0.1
10
-
0.1
20
A
-
0.1
40
-
0.1
80
A
-
5
500
-
5
-
4.0
-
-
-
-
pF
-
5.0
-
-
-
-
pF
nAn port; VI = VIH or VIL
II
input leakage
current
VI = 5.5 V or GND
IOZ
OFF-state
VI = VIH or VIL;
output current VO = VCC or GND
ICC
supply current VI = VCC or GND; IO = 0 A
ICC
additional
per control pin;
supply current VI = VCC  0.6 V; IO = 0 A
CI
input
capacitance
CI/O
input/output
capacitance
[3]
[4]
nAn and nBn port
[1]
All typical values are measured at VCC(B) = 5.0 V, VCC(A) = 3.3 V and Tamb = 25 C.
[2]
If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible.
[3]
For transceivers, the parameter IOZ includes the input leakage current.
[4]
VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND.
74ALVC164245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 May 2013
5000 A
© NXP B.V. 2013. All rights reserved.
7 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; for test circuit see Figure 6.
Symbol Parameter
tpd
propagation
delay
Tamb = 40 C to +85 C
Conditions
enable time
Max
Min
Max
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5
3.3
7.6
1.5
9.5
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
1.0
3.0
5.9
1.0
7.5
ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.0
2.9
5.8
1.0
7.5
ns
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.0
3.0
7.6
1.0
9.5
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
1.0
4.3
6.7
1.0
8.5
ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.2
2.5
5.8
1.2
7.5
ns
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5
4.1
11.5
1.5
14.5
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
1.5
3.6
9.2
1.5
11.5
ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.0
3.2
8.9
1.0
12.0
ns
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5
4.6
12.3
1.5
15.5
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
1.5
4.3
9.3
1.5
12.0
ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.0
3.2
8.9
1.0
11.5
ns
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
2.0
2.7
10.5
2.0
13.5
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
2.5
4.6
9.0
2.5
11.5
ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
2.1
4.9
8.6
2.1
11.0
ns
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.0
2.7
9.3
1.0
12.0
ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V
1.5
3.5
9.0
1.5
11.5
ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
2.0
3.2
8.6
2.0
11.0
ns
nAn to nBn; see Figure 4
nOE to nBn; see Figure 5
nOE to nAn; see Figure 5
tdis
disable time
nOE to nBn; see Figure 5
nOE to nAn; see Figure 5
74ALVC164245_Q100
Product data sheet
Unit
Min
nBn to nAn; see Figure 4
ten
Tamb = 40 C to +125 C
Typ[1]
[2]
[2]
[2]
[2]
[2]
[2]
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
8 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; for test circuit see Figure 6.
Symbol Parameter
CPD
power
dissipation
capacitance
Tamb = 40 C to +85 C
Conditions
Min
Max
Min
Max
-
30
-
-
-
pF
-
15
-
-
-
pF
outputs enabled
-
40
-
-
-
pF
outputs disabled
-
5
-
-
-
pF
5 V port: nAn to nBn;
VCC(B) = 5 V; VCC(A) = 3.3 V
outputs enabled
3 V port: nBn to nAn;
VCC(B) = 5 V; VCC(A) = 3.3 V
[2]
Unit
[3][4]
outputs disabled
[1]
Tamb = 40 C to +125 C
Typ[1]
[3][4]
All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb = 25 C.
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
[4]
The condition is VI = GND to VCC.
11. AC waveforms
VI
nAn, nBn
input
VM
GND
tPHL
tPLH
VOH
nBn, nAn
output
VM
VOL
001aaa792
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
Input (nAn, nBn) to output (nBn, nAn) propagation delays
74ALVC164245_Q100
Product data sheet
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
9 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
VI
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with output load.
Fig 5.
Table 8.
3-state enable and disable times
Measurement points
Direction
Supply voltage
Input
VCC(A)
VI
VM
VCC(B)
Output
VM
VX
VY
VOL(B) + 0.3 V
VOH(B)  0.3 V
nAn port to nBn
port
2.3 V to 2.7 V 2.7 V to 3.6 V
VCC(A)
0.5  VCC(A) 1.5 V
nBn port to nAn
port
2.3 V to 2.7 V 2.7 V to 3.6 V
2.7 V
1.5 V
0.5  VCC(A) VOL(A) + 0.15 V VOH(A)  0.15 V
nAn port to nBn
port
2.7 V to 3.6 V 4.5 V to 5.5 V
2.7 V
1.5 V
0.5  VCC(B) 0.2  VCC(B)
0.8  VCC(B)
nBn port to nAn
port
2.7 V to 3.6 V 4.5 V to 5.5 V
3.0 V
1.5 V
1.5 V
VOH(A)  0.3 V
74ALVC164245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 May 2013
VOL(A) + 0.3 V
© NXP B.V. 2013. All rights reserved.
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74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 6.
Table 9.
Test circuit for measuring switching times
Test data
Direction
Supply voltage
Load
VEXT
VCC(A)
VCC(B)
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
nAn port to nBn
port
2.3 V to 2.7 V
2.7 V to 3.6 V
50 pF
500 
open
GND
2  VCC
nBn port to nAn
port
2.3 V to 2.7 V
2.7 V to 3.6 V
50 pF
500 
open
GND
6.0 V
nAn port to nBn
port
2.7 V to 3.6 V
4.5 V to 5.5 V
50 pF
500 
open
GND
2  VCC
nBn port to nAn
port
2.7 V to 3.6 V
4.5 V to 5.5 V
50 pF
500 
open
GND
6.0 V
74ALVC164245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
11 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
12. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
Fig 7.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Package outline SOT362-1 (TSSOP48)
74ALVC164245_Q100
Product data sheet
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Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
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74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
74ALVC164245_Q100 v.1 20130514
74ALVC164245_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
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Rev. 1 — 14 May 2013
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NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74ALVC164245_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
14 of 16
74ALVC164245-Q100
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ALVC164245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
15 of 16
NXP Semiconductors
74ALVC164245-Q100
16-bit dual supply translating transceiver; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 May 2013
Document identifier: 74ALVC164245_Q100