Data Sheet

PCA2117
Automotive LCD driver for character displays
Rev. 4 — 8 April 2015
Product data sheet
1. General description
The PCA2117 is a low-power Liquid Crystal Display (LCD)1 controller and driver. It is
specifically designed to drive LCD dot-matrix displays of 2-lines by 20 characters or 1-line
by 40 characters with 5  8 dot format. In addition 200 icons can be displayed. The chip
contains a character generator and displays alphanumeric characters. The PCA2117
features an internal charge pump with internal capacitors for on-chip generation of the
LCD driving voltage. To ensure an optimal and stable contrast over the full temperature
range, the PCA2117 offers a programmable temperature compensation of the LCD supply
voltage. The PCA2117 can be easily connected to a microcontroller by either the two-line
I2C-bus or a four-line bidirectional SPI-bus.
Various character sets can be manufactured on request. In addition up to 48 user-defined
symbols (5  8 dot format) can be stored in three selectable RAM columns with 16
characters each.
For a selection of NXP LCD character drivers, see Table 58 on page 97.
2. Features and benefits











1.
AEC Q100 grade 2 compliant for automotive applications
Single-chip LCD controller and driver
Extended operating temperature range from 40 C to +105 C
2-line display of up to 20 characters plus 200 icons or 1-line display of up to 40
characters plus 200 icons
5  7 character format plus cursor and user-defined symbols
Icon blink function
On-chip:
 Programmable 4, 3, or 2 times voltage multiplier generating LCD supply voltage
(external supply also possible)
 Integrated temperature sensor with temperature readout
 Selectable linear temperature compensation of on-chip generated VLCD
 Generation of intermediate LCD bias voltages
 Oscillator requires no external components (external clock also possible)
Readout of RAM, CGROM, and all registers possible
Diagnostic features:
 Checksum on I2C and SPI bus
Frame frequency: programmable from 45 Hz to 360 Hz
Display Data RAM (DDRAM): 80 characters
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
 Character Generator ROM (CGROM): 240, 224, or 208 characters (5  8) depending
on the selected RAM size
 Character Generator RAM (CGRAM): 16, 32, or 48 characters (5  8); ICON-RAM:
400 bit
 Two-line I2C-bus interface or four-line SPI bus selectable through input pin
 Inversion modes
 n-line (n = 1 to 7) inversion
 Frame inversion
 Large supply voltage range: VDD1: 2.5 V to 5.5 V (chip can be driven with battery cells)
 Analog supply voltage VDD2: 2.5 V to 5.5 V
 LCD supply voltage VLCD: 4 V to 16 V
 Direct mode to save current consumption for icon mode and multiplex drive mode 1:9
(depending on VDD2 value and LCD properties)
 Power-down mode pin
 Very low current consumption (20 A to 200 A):
 Power-down mode: < 2 A
 Icon mode: < 25 A
 Icon mode is used to save current. When only icons are displayed, a much lower LCD
operating voltage can be used and the switching frequency of the LCD driver outputs
is reduced. In this case, for most applications it is possible to use VDD as LCD supply
voltage
3. Applications
 Automotive
 Instrument clusters
 Climate control display
 Car entertainment
 Car radio
 Industrial
 Medical and health care
 Measuring equipment
 Machine control systems
 Information boards
 General-purpose display modules
 Consumer
 White goods
 Home entertainment
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
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PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
PCA2117DUGR bare die
Description
Version
244 bumps
PCA2117DUG
PCA2117DUGS
4.1 Ordering options
Table 2.
Ordering options
Product type number Sales item
(12NC)
Orderable part
number
IC
revision
Delivery form
PCA2117DUGR/DA
935301518033 PCA2117DUGR/DAZ 1
character set R; chips with gold bumps in tray
PCA2117DUGS/DA
935303241033 PCA2117DUGS/DAZ 1
character set S; chips with gold bumps in tray
5. Marking
Each die has a laser marking on the rear side. The format is LLLLLLLWWXXXXXX
having the following meaning:
LLLLLLL - wafer lot number
WW - wafer number
XXXXXX - die identification number
PCA2117
Product data sheet
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3 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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Block diagram of PCA2117
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 107
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NXP Semiconductors
PCA2117
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Pinning diagram of PCA2117DUGx
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PCA2117
5 of 107
© NXP Semiconductors N.V. 2015. All rights reserved.
Viewed from active side. For mechanical details, see Figure 61 on page 89.
3&$
Automotive LCD driver for character displays
Rev. 4 — 8 April 2015
All information provided in this document is subject to legal disclaimers.
5
7.1 Pinning
5
Product data sheet
7. Pinning information
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
7.2 Pin description
Table 3.
Pin description of PCA2117DUGx
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
output
LCD row driver output
Row output pins
R13
1 to 3
R14
4, 5
R15
6, 7
R16
8, 9, 232, 233 output
R17
110, 111, 130,
131
R7
112, 113
R6
114, 115
R5
116 to 118
R4
119 to 121
R3
122, 123
R2
124, 125
R1
126, 127
R0
128, 129
R8
234, 235
R9
236, 237
R10
238, 239
R11
240, 241
R12
242 to 244
LCD row driver output for driving the icons
output
LCD row driver output
132 to 231
output
LCD column driver output
10 to 13
Column output pins
C99 to C0
VLCD pins
supply
VLCD input
VLCDSENSE 14 to 16
input
VLCD regulation input
VLCDOUT
17 to 20
output
VLCD output
VSS2[1]
21 to 30
supply
ground supply
VSS3[1]
31 to 34
VSS1[1]
35 to 47
VDD1
61 to 65
supply
supply voltage 1
VDD2
66 to 73
supply
supply voltage 2
PWROUT
81, 82
output
regulated voltage output; must be connected to PWRIN
PWRIN
83 to 89
input
regulated voltage input; must be connected to PWROUT
T1
48, 49
input
not accessible; must be connected to VSS1
T2
50, 51
T4
52 to 54
output
not accessible; must be left open
VLCDIN
Supply pins
Test pins
PCA2117
Product data sheet
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Automotive LCD driver for character displays
Table 3.
Pin description of PCA2117DUGx …continued
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
T3
76 to 80
input
not accessible; must be connected to PWROUT
Oscillator, synchronization, and reset pins
OSC[2]
55, 56
input
clock (internal/external) selector
PD
74, 75
input
power-down mode select
•
•
for normal operation, pin PD must be LOW
for power-down mode, pin PD must be HIGH
CLK
92 to 94
input/output
internal oscillator output, external oscillator input
RST
95, 96
input
active LOW reset input
Bus-related pins
SA0
57, 58
input
SPI-bus
I2C-bus
unused;
slave address selector;
•
connect to VSS1
•
•
connect to VSS1 for logic 0
connect to VDD1 for logic 1
interface selector input
IFS
59, 60
input
interface selector input
CE
90, 91
input
chip enable input (active LOW)
unused
•
connect to VSS1
•
•
connect to VDD1
connect to VDD1
SDI/SDAIN
97 to 99
input
SPI-bus data input
I2C-bus
SDO
100, 101
output
SPI serial data output
unused
•
serial data input
must be left open
SCL
102 to 104
input
serial clock input
serial clock input
SDAOUT
105 to 109
output
unused
serial data output
•
must be connected to VSS1
[1]
The substrate (rear side of the die) is at VSS1 potential and must not be connected.
[2]
If pin OSC is tied to VSS1, CLK is the output pin of the internal oscillator. If pin OSC is tied to VDD1, CLK is the input pin for the external
oscillator.
PCA2117
Product data sheet
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NXP Semiconductors
Automotive LCD driver for character displays
8. Functional description
8.1 Commands of PCA2117
The commands defined in Table 5 control the PCA2117.
The sequence to execute a command is like shown in Table 4:
Table 4.
Bus
Command execution sequence
Byte 1
Byte 2
I2C
address[1]
slave
SPI
R/W[2] + subaddress[4]
+
R/W[2]
Byte 3
RS[1:0][3]
command
CO + RS[1:0][3]
command
CO +
[1]
More about the slave address, see Section 9.2.7.
[2]
See Section 9.2.7 and Section 9.3.1.
[3]
See Section 9.1.
[4]
More about the subaddress, see Section 9.3.1.
Remark: Any other combinations of operation code bits that are not mentioned in this
document can lead to undesired operation modes of PCA2117.
Table 5.
Commands of PCA2117
Command name
R/W Register
select
RS[1:0]
Bits
Reference
7
6
5
4
3
2
1
0
General control commands
Register_update
0
0
0
0
0
0
0
0
Section 8.1.1.1
Initialize
0
0
0
0
0
0
0
0
0
0
1
Section 8.1.1.2
Clear_reset_flag
0
0
0
1
1
1
1
1
Section 8.1.1.3
OTP_refresh
0
0
0
0
0
0
1
0
Section 8.1.1.4
Clock_out_ctrl
0
0
1
0
0
0
0
COE
Section 8.1.1.5
Read_reg_select
0
0
0
0
0
1
XC
SO
Section 8.1.1.6
Read_status_reg
1
TD[7:0]
Section 8.1.1.7
CS[7:0]
Status_Register_1 to Status_Register_9
RAM_ROM_config
0
1
0
1
0
0
Sel_mem_bank
0
0
0
1
0
SMB[2:0]
Set_mem_addr
1
ADD[6:0]
Read_data
0
1
0
1
Write_data
0
PCA2117
Product data sheet
Section 8.1.1.9
Section 8.1.1.11
0
0
RD[4:0]
WD[7:0]
0
Section 8.1.1.8
Section 8.1.1.10
RD[7:0]
0
RR[1:0]
0
Section 8.1.1.12
0
WD[4:0]
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Automotive LCD driver for character displays
Table 5.
Commands of PCA2117 …continued
Command name
R/W Register
select
Bits
Reference
RS[1:0]
7
6
5
4
3
2
1
0
1
Display control commands
Clear_display
0
0
0
0
0
0
0
0
Section 8.1.2.1
Return_home
0
0
0
0
0
0
0
0
1
Section 8.1.2.2
Entry_mode_set
0
0
1
0
1
0
I_D
S
Section 8.1.2.3
Function_set
0
0
1
1
0
0
M
SL
Section 8.1.2.4
0
INV[2:0]
Inversion_mode
0
0
0
1
0
0
Frame_frequency
1
0
1
0
0
FF[4:0]
Section 8.1.2.5
Display_control
0
0
1
0
0
D
C
B
Section 8.1.2.7
Cursor_display_shift
0
0
0
1
0
0
SC
RL
Section 8.1.2.8
Screen_config
0
0
0
0
0
0
1
L
Section 8.1.2.9
Display_config
0
0
0
0
0
1
P
Q
Section 8.1.2.10
Icon_config
0
0
0
0
1
0
IM
IB
Section 8.1.2.11
0
CPE
CPC[1:0]
Section 8.1.2.6
Charge pump and LCD bias control commands
Charge_pump_ctrl
0
1
1
Set_VLCD_A
Set_VLCD_B
1
0
0
0
1
0
1
VLCDA[8:4]
1
0
0
1
1
1
0
VLCDB[8:4]
1
1
1
0
VLCDB[3:0]
Section 8.1.3.1
Section 8.1.3.2
VLCDA[3:0]
Section 8.1.3.2
Temperature compensation control commands
Temperature_ctrl
0
1
1
TC_slope
0
0
0
0
0
TCE
TMF
0
0
0
0
1
TSA[2:0]
0
0
0
1
0
TSB[2:0]
0
0
0
1
1
TSC[2:0]
0
0
1
0
0
TSD[2:0]
TME
Section 8.1.4.1
Section 8.1.4.2
8.1.1 General control commands
8.1.1.1
Command: Register_update
This command updates registers of the PCA2117. It must be sent after the Return_home
command or Cursor_display_shift command if no other command follows.
Table 6.
Bit
8.1.1.2
Register_update - Register update command bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
00000000
update register
Command: Initialize
This command generates a chip-wide reset by setting all command registers to their
default values. It must be sent to the PCA2117 after power-on. For further information, see
Section 8.2.1 on page 27.
PCA2117
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Automotive LCD driver for character displays
Table 7.
8.1.1.3
Initialize - Initialize command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
00000001
initialize
Command: Clear_reset_flag
The Clear_reset_flag command clears the reset flag CRF, see Table 12 on page 11.
Table 8.
8.1.1.4
Clear_reset_flag - Clear_reset_flag command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
00011111
clear reset status flag
Command: OTP_refresh
In order to achieve the specified accuracy of the VLCD, the frame frequency, and the
temperature measurement, each IC is calibrated during production. These calibration
values are stored in One Time Programmable (OTP) cells. Their content is loaded into the
associated registers every time when the Initialize command or the OTP_refresh
command is sent. This command takes approximately 10 ms to finish.
Table 9.
8.1.1.5
OTP_refresh - OTP_refresh command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
00000010
refresh register settings from OTP
Command: Clock_out_ctrl
When pin CLK is configured as an output pin, the Clock_out_ctrl command enables or
disables the clock output on pin CLK.
Table 10.
Bit
Clock_out_ctrl - CLK pin input/output switch command bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 1
-
0010000
fixed value
0
COE
[1]
CLK pin setting
0[1]
clock signal not available on pin CLK;
pin CLK is in 3-state
1
clock signal available on pin CLK
Default value.
For lower power consumption, the clock is only active when display (see Table 25),
charge pump (see Table 30), or temperature measurement (see Table 32) is enabled.
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Automotive LCD driver for character displays
8.1.1.6
Command: Read_reg_select
The Read_reg_select command allows choosing to read out the temperature or the status
registers (Checksum to Status_Register_9) of the device (see Table 12).
Table 11.
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 2
-
000001
1
XC
0
8.1.1.7
Read_reg_select - select registers for readout command bit description
Bit
fixed value
checksum mode setting
0[1]
XOR checksum
1
CRC-8 checksum
SO
readout select
0[1]
temperature
1
status registers
[1]
Default value.
[2]
Only valid for RAM. See .Section 8.5.2 “Checksum”
Command: Read_status_reg
With the Read_status_reg command the temperature, checksum, and the status registers
can be read out. The behavior of the Read_status_reg command is controlled by the SO
bit of the Read_reg_select command (see Table 11).
Table 12.
Bit
Read_status_reg - readout register command bit description
Symbol
Value
Description
-
R/W
1
fixed value
-
RS[1:0]
00
fixed value
Temperature readout if SO = 0 (see Table 11)
7 to 0
TD[7:0]
00000000 to
11111111[1]
temperature readout
Status readout if SO = 1 (see Table 11)
Checksum
7 to 0
00000000[1] to checksum result from RAM writing with
11111111
checksum mode set by bit XC (see Table 11)
CS[7:0]
Status_Register_1
7, 6
-
00
fixed value
5, 4
RR[1:0]
see Table 13
CGRAM and CGROM select status
3
I_D
see Table 20
address stepping select status
2
S
1
M
0
SL
display shift select status
see Table 21
display lines setting status
multiplex drive mode setting status
Status_Register_2
PCA2117
Product data sheet
7 to 5
INV[2:0]
see Table 22
inversion mode setting status
4 to 0
FF[4:0]
see Table 24
frame frequency setting status
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Automotive LCD driver for character displays
Table 12.
Bit
Read_status_reg - readout register command bit description …continued
Symbol
Value
Description
see Table 25
display setting status
Status_Register_3
7
D
6
C
5
B
4
SC
3
RL
2
L
see Table 27
screen configuration setting status
1
P
see Table 28
display column setting status
0
Q
cursor setting status
character blink setting status
see Table 26
shift or move setting status
shift or move direction setting status
display row setting status
Status_Register_4
7
-
0
fixed value
6
IM
see Table 29
icon mode setting status
5
IB
4
CPE
see Table 30
charge pump setting status
3
-
0
fixed value
2, 1
CPC[1:0]
see Table 30
charge pump voltage multiplier setting
status
0
VLCDA8
see Table 31
value of VLCDA
see Table 31
value of VLCDA
see Table 32
temperature compensation setting status
icon blink select status
Status_Register_5
7 to 0
VLCDA[7:0]
Status_Register_6
7
TCE
6
TMF
5 to 3
TSA[2:0]
2 to 0
TSB[2:0]
temperature measurement filter setting
status
see Table 33
temperature compensation slope A setting
status
temperature compensation slope B setting
status
Status_Register_7
7
TME
see Table 32
temperature measurement setting status
6 to 4
TSC[2:0]
see Table 33
temperature compensation slope C setting
status
3 to 1
TSD[2:0]
0
VLCDB8
temperature compensation slope D setting
status
see Table 31
value of VLCDB
see Table 31
value of VLCDB
Status_Register_8
7 to 0
PCA2117
Product data sheet
VLCDB[7:0]
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Automotive LCD driver for character displays
Table 12.
Bit
Read_status_reg - readout register command bit description …continued
Symbol
Value
Description
00000
fixed value
Status_Register_9
7 to 3
-
2
QPR
1
8.1.1.8
0
charge pump has not reached programmed
value
1
charge pump has reached programmed value
CRF
0
[1]
charge pump charge status
reset flag status
the reset flag is set whenever a reset occurs; it
should be cleared for reset monitoring (see
Table 8)
COE
0
no reset has occurred since the reset flag
register was cleared last time
1[1]
reset has occurred since the reset flag
register was cleared last time
see Table 10
CLK pin setting status
Start-up value.
Command: RAM_ROM_config
The RAM_ROM_config command allows configuring the display memory.
Table 13.
RAM_ROM_config - display memory configuration command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 2
-
010100
fixed value
1, 0
RR[1:0]
CGRAM and CGROM select (see Section 8.5)
00[1]
column 1 (address 0001) = CGROM
column 2 (address 0010) = CGROM
01
column 1 (address 0001) = CGROM
column 2 (address 0010) = CGRAM
10
column 1 (address 0001) = CGRAM
column 2 (address 0010) = CGROM
11
column 1 (address 0001) = CGRAM
column 2 (address 0010) = CGRAM
[1]
PCA2117
Product data sheet
Default value.
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8.1.1.9
Command: Sel_mem_bank
The Sel_mem_bank command determines which memory to access.
Table 14.
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 3
-
00010
fixed value
2 to 0
SMB[2:0]
[1]
8.1.1.10
Sel_mem_bank - RAM access configuration command
RAM access select
000[1]
DDRAM is selected
001
column 0 (0000) of CGRAM is selected
010
column 1 (0001) of CGRAM is selected
011
column 2 (0010) of CGRAM is selected
100
ICON-RAM is selected
101
CGROM
110 to 111
not implemented
Default value.
Command: Set_mem_addr
The Set_mem_addr command allows setting the RAM address in the address counter to
access. The Sel_mem_bank command (see Section 8.1.1.9) determines whether to
access the CGRAM, DDRAM, or ICON-RAM.
Table 15.
Bit
Set_mem_addr - memory address command bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7
-
1
fixed value
ADD[6:0]
0000000[1]
6 to 0
to
RAM address
1111111
[1]
PCA2117
Product data sheet
Default value.
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8.1.1.11
Command: Read_data
The Read_data command reads binary 8-bit data from the CGRAM, CGROM, DDRAM or
ICON-RAM.
Table 16.
Read_data - data read bit description
Bit
Symbol
Value
Description
-
R/W
1
fixed value
-
RS[1:0]
01
fixed value
00000000 to
11111111
read data from DDRAM and CGROM
DDRAM and CGROM
7 to 0
RD[7:0]
CGRAM and ICON-RAM
7 to 5
-
000
fixed value
4 to 0
RD[4:0]
00000 to
11111
read data from CGRAM and ICON-RAM
The Sel_mem_bank command (see Section 8.1.1.9) determines whether to read from the
CGRAM, CGROM, DDRAM, or ICON-RAM. After reading, the address counter
automatically increments or decrements by 1 in accordance with the setting of bit I_D of
the Entry_mode_set command (see Section 8.1.2.3).
Only bit 4 to bit 0 of the CGRAM or ICON-RAM data are valid. Bit 7 to bit 5 are set logic 0.
8.1.1.12
Command: Write_data
The Write_data command writes binary 8-bit data to the CGRAM, DDRAM or ICON-RAM.
Table 17.
Write_data - data write bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
01
fixed value
WD[7:0]
00000000 to
11111111
write data to DDRAM
DDRAM
7 to 0
CGRAM and ICON-RAM
7 to 5
-
000
not implemented
4 to 0
WD[4:0]
00000 to
11111
write data to CGRAM and ICON-RAM
The Sel_mem_bank command determines whether to write data into the CGRAM,
DDRAM or ICON-RAM. After writing, the address counter automatically increments or
decrements by 1 in accordance with the setting of bit I_D of the Entry_mode_set
command (see Section 8.1.2.3).
Only bit 4 to bit 0 of the CGRAM or ICON-RAM data are valid. Bit 7 to bit 5 are not
implemented and should always be logic 0. The cursor and the character blink have to be
turned off when writing to the CGRAM (see Table 25 on page 20).
• The ICON-RAM to display mapping is given in Section 8.5.5 “ICON-RAM”.
• The DDRAM to display mapping is given in Section 8.5.6 “DDRAM”.
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8.1.2 Display control commands
8.1.2.1
Command: Clear_display
The Clear_display command clears the entire display.
Table 18.
Bit
Clear_display - clear display bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 0
-
00000000
clear display
Clear_display: Writes the character code 20h (blank pattern) into all DDRAM addresses
except for the character set ‘R’ where the character code 20h is not a blank pattern.
When using character set ‘R’, use the following alternative instruction:
1. Switch off display (Display_control, bit D = 0).
2. Write a blank pattern into all DDRAM addresses (Write_data).
3. Switch on display (Display_control, bit D = 1).
The address counter remains on the previously accessed pointer, bit I_D keeps the
previously programmed value.
8.1.2.2
Command: Return_home
The Return_home command sets the cursor to the left top corner of the display.
Table 19.
Return_home - return home bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 0
-
00000001
return home
Return_home: Sets the address counter to logic 0 and switches a shifted display back to
an unshifted state. The DDRAM content remains unchanged. The cursor or blink position
goes to the left of the first display line. Bit I_D and bit S of the Entry_mode_set instruction
remain unchanged. If no other command follows, this command must be terminated with
the Register_update command.
PCA2117
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8.1.2.3
Command: Entry_mode_set
The Entry_mode_set command sets the address stepping and the shift of the display.
Table 20.
Entry_mode_set - entry mode bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 2
-
001010
fixed value
1
I_D
0
[1]
address stepping select
0
DDRAM, CGRAM or ICON-RAM address
decrements by 1, cursor moves to the left
1[1]
DDRAM, CGRAM or ICON-RAM address
increments by 1, cursor moves to the right
S
display shift select
0[1]
display does not shift
1
display shifts
Default value.
Bit I_D: When bit I_D = 1 the DDRAM, CGRAM, or ICON-RAM address increments by 1
when data is written into or read from the DDRAM, CGRAM or ICON-RAM. The cursor or
blink position moves to the right.
When bit I_D = 0 the DDRAM, CGRAM, or ICON-RAM address decrements by 1 when
data is written into or read from the DDRAM, CGRAM or ICON-RAM. The cursor or blink
position moves to the left.
Bit S: When bit S = 0, the display does not shift.
During DDRAM write, when bit S = 1 and bit I_D = 0, the entire display shifts to the right.
When bit S = 1 and bit I_D = 1, the entire display shifts to the left.
Thus it appears as if the cursor remains and the display moves. The display does not shift
when reading from the DDRAM, CGRAM or ICON-RAM or when writing to or from the
DDRAM, CGRAM or ICON-RAM.
GLVSOD\DUHD
7KLVLVDQH[DPSOHRIDGLVSOD\VKLIW
%RWKOLQHVVKLIWULJKWOHIWVLPXOWDQHRXVO\
DDD
Command: Entry_mode_set, S = 1, display line setting: 2 line  20 characters.
Fig 3.
PCA2117
Product data sheet
Example of the display shift
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8.1.2.4
Command: Function_set
The Function_set command allows setting the display lines and the multiplex drive mode.
Table 21.
Function_set - function set bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 2
-
001100
fixed value
1
M
display lines setting
0[1]
1
0
[1]
8.1.2.5
SL
1 line  40 characters
2 line  20 characters
multiplex drive mode setting
0[1]
1:18 multiplex drive mode, 1  40 character or
2  20 character display
1
1:9 multiplex drive mode, 1  20 character
display
Default value.
Command: Inversion_mode
The Inversion_mode command allows changing the drive scheme inversion mode.
The waveforms used to drive an LCD (see Figure 27 to Figure 29) inherently produce a
DC voltage across the display cell. The PCA2117 compensates for the DC voltage by
inverting the waveforms on alternate frames or alternate lines. The choice of the
compensation method is determined with INV[2:0] in Table 22.
Table 22.
Inversion_mode - inversion mode command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
01000
fixed value
2 to 0
INV[2:0]
[1]
inversion mode setting
000[1]
frame inversion mode
001
1-line inversion mode
010
2-line inversion mode
011
3-line inversion mode
100
4-line inversion mode
101
5-line inversion mode
110
6-line inversion mode
111
7-line inversion mode
Default value.
Line inversion mode (driving scheme A): In line inversion mode, the DC value is
compensated every nth line. Changing the inversion mode to line inversion mode reduces
the possibility for flickering but increases the power consumption.
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Frame inversion mode (driving scheme B): In frame inversion mode, the DC value is
compensated across two frames and not within one frame. Changing the inversion mode
to frame inversion reduces the power consumption, therefore it is useful when power
consumption is a key point in the application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined, however since the switching frequency is reduced there is the
possibility for flicker to occur.
8.1.2.6
Command: Frame_frequency
With this command, the clock and frame frequency can be programmed when using the
internal clock. The default frame frequency of 80 Hz is factory calibrated.
Table 23.
Bit
Frame-frequency - frame frequency select command bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 5
-
100
fixed value
4 to 0
FF[4:0]
see Table 24
frame frequency setting
The duty cycle depends on the frequency chosen (see Table 24).
Table 24. Clock and frame frequency values
Duty cycle definition: % HIGH-level time : % LOW-level time.
PCA2117
Product data sheet
FF[4:0]
Frame frequency (Hz)
Clock frequency (Hz)
Typical duty cycle (%)
00000
45
36000
50 : 50
00001
50
39724
44 : 56
00010
55
44308
38 : 62
00011
60
48000
33 : 67
00100
65
52364
27 : 73
00101
70
54857
23 : 77
00110
75
60632
15 : 85
00111[1]
80
64000
11 : 89
01000
85
67765
5 : 95
01001
90
72000
50 : 50
01010
95
76800
46 : 54
01011
100
82286
42 : 58
01100
110
88615
38 : 62
01101
120
96000
33 : 67
01110
130
104727
27 : 73
01111
145
115200
20 : 80
10000
160
128000
11 : 89
10001
180
144000
50 : 50
10010
210
164571
42 : 58
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Table 24. Clock and frame frequency values …continued
Duty cycle definition: % HIGH-level time : % LOW-level time.
FF[4:0]
Frame frequency (Hz)
Clock frequency (Hz)
Typical duty cycle (%)
10011
240
192000
33 : 67
10100
290
230400
20 : 80
10101 to 360
288000
50 : 50
11111
[1]
8.1.2.7
Default value.
Command: Display_control
With the Display_control command the entire display, the cursor, and the cursor blinking
can be switched on or off.
Table 25.
Bit
Display_control - Display control bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00100
fixed value
2
D
1
display setting
0[1]
display is off
1
display is on
C
cursor setting
0[1]
1
0
[1]
B
cursor is off
cursor is on
character blink setting
0[1]
character blink is off
1
character blink is on
Default value
Bit D: The display is on when bit D = 1 and off when bit D = 0. Display data in the DDRAM
is not affected and can be displayed immediately by setting bit D = 1.
Bit C: The cursor is displayed when bit C = 1 and inhibited when bit C = 0. The cursor is
displayed using 5 dots in the eighth line.
Bit B: The character, indicated by the cursor, blinks when bit B = 1. The character blink is
displayed by switching between display characters and all dots on with a period of
1 second.
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8.1.2.8
Command: Cursor_display_shift
The Cursor_display_shift command configures whether the cursor or the display moves or
shifts to right or left.
Table 26.
Cursor_display_shift - cursor display shift bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 2
-
000100
1
SC
0
[1]
fixed value
shift or move cursor setting
0[1]
move cursor
1
cursor shift
RL
shift or move direction setting
0[1]
left shift or move
1
right shift or move
Default value.
Bits SC and RL: Cursor_display_shift moves the cursor position or the display to the right
or left without writing or reading display data. This function is used to correct a character
or move the cursor through the display.
In 2-line displays, the cursor moves to the next line when it passes the last position (40) of
the line. When the displayed data is shifted repeatedly, all lines shift at the same time;
displayed characters do not shift into the next line.
If shift display (SC = 1) is the only action performed, the address counter content does not
change. But increments or decrements with shift cursor (SC = 0).
If no other command follows, this command must be terminated with the Register_update
command.
GLVSOD\DUHD
7KLVLVDQH[DPSOHWRVKRZWKHIXQFWLRQRIVKLIWLQJWKHGLVSOD\OLQHV
WRJHWDOLQHIHHG
DDD
Display line setting: 1 line  40 characters; possible setups:
(1) Command Entry_mode_set: S = 1, command Cursor_display_shift: RL = 1.
(2) Command Entry_mode_set: S = 1, command Cursor_display_shift: SC = 1, RL = 1.
Fig 4.
PCA2117
Product data sheet
Example of a linefeed
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8.1.2.9
Command: Screen_config
Table 27.
Bit
Screen_config - screen configuration bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 1
-
0000001
fixed value
0
L
[1]
screen configuration setting
0[1]
split screen standard connection
1
split screen mirrored connection
Default value.
Screen_config:
• If bit L = 0, then the two halves of a split screen are connected in a standard way, that
is column 0/100, 1/101 to 99/199.
• If bit L = 1, then the two halves of a split screen are connected in a mirrored way, that
is column 0/199, 1/198 to 99/100. This feature allows a single layer PCB or glass
layout.
8.1.2.10
Command: Display_config
The Display_config command allows setting how the data is displayed.
Table 28.
Bit
Display_config - display configuration bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 2
-
000001
fixed value
1
P
display column setting
0[1]
column data: left to right;
column data is displayed from column 0 to
column 99
1
column data: right to left;
column data is displayed from column 99 to
column 0
0
Q
display row setting
0[1]
row data: top to bottom;
row data is displayed from row 0 to row 15
and icon row data in row 16 and row 17
in single-line mode (SL = 1) row data is
displayed from row 0 to row 7 and icon row
data in row 16
1
row data: bottom to top;
row data is displayed from row 15 to row 0
and icon row data in row 17 and row 16
in single-line mode (SL = 1) row data is
displayed from row 15 to row 8 and icon row
data in row 17
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[1]
Default value.
Bit P: The P bit flips the display left to right by mirroring the column data.
Bit Q: The Q bit flips the display top to bottom by mirroring the row data.
Combination of bit P and bit Q: A combination of bit P and bit Q allows the display to be
rotated horizontally and vertically by 180 degrees.
%LW3 ELW4 %LW3 ELW4 %LW3 ELW4 %LW3 ELW4 DDD
Fig 5.
8.1.2.11
Illustration of the display configuration bits
Command: Icon_config
The PCA2117 can drive up to 200 icons. With the Icon_config command the displaying of
the icons can be configured.
Table 29. Icon_config - icon display configuration bit description
See Table 38 for the ICON-RAM to ICON mapping.
PCA2117
Product data sheet
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 2
-
000010
fixed value
1
IM
icon mode setting
0[1]
character mode, full display; VLCD
programming with the Set_VLCD_A
command
1
icon mode, only icons displayed; VLCD
programming with the Set_VLCD_B
command
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Table 29. Icon_config - icon display configuration bit description …continued
See Table 38 for the ICON-RAM to ICON mapping.
Bit
Symbol
0
IB
[1]
Value
Description
icon blink setting
0[1]
icon blink disabled
1
icon blink enabled
Default value.
Bit IM: When bit IM = 0, the chip is in character mode. In the character mode, both,
characters and icons are driven (multiplex drive mode 1:18 or 1:9). The VLCD generator, if
used, produces the LCD supply voltage (pin VLCDOUT) programmed with the
Set_VLCD_A command.
When bit IM = 1, the chip is in icon mode. In the icon mode only the icons are driven
(multiplex drive mode 1:2). The VLCD generator, if used, produces the LCD supply voltage
(pin VLCDOUT) programmed with the Set_VLCD_B command.
Bit IB: The icon blink control is independent of the cursor/character blink function.
When bit IB = 0, the icon blink is disabled. In this case, the even phase of icon data is
used which is stored in the ICON-RAM 00h to 27h.
When bit IB = 1, the icon blink is enabled. In this case, each icon is controlled by 2 bits.
The blinking consists of two half phases (corresponding to the cursor on and off phases,
called even and odd phases in the following). The Icon states for the even phase are
stored in the ICON-RAM 00h to 27h. These bits also define the icon state when icon
blinking is not used. The Icon states for the odd phase are stored in the ICON-RAM 28h to
4Fh.
8.1.3 Charge pump and LCD bias control commands
8.1.3.1
Command: Charge_pump_ctrl
The Charge_pump_ctrl command enables or disables the internal VLCD generation and
controls the charge pump voltage multiplier setting.
Table 30.
Charge_pump_ctrl - charge pump control command bit description
Bit
Symbol
Binary value
Description
-
R/W
0
fixed value
-
RS[1:0]
11
fixed value
7 to 3
-
10000
fixed value
2
CPE
charge pump setting
0[1]
1
1 to 0
PCA2117
Product data sheet
CPC[1:0]
charge pump disabled;
no internal VLCD generation;
external supply of VLCD
charge pump enabled
charge pump voltage multiplier setting
00[1]
VLCD = 2  VDD2
01
VLCD = 3  VDD2
10
VLCD = 4  VDD2
11
VLCD = VDD2 (direct mode)
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[1]
8.1.3.2
Default value.
Command: Set_VLCD_A and Set_VLCD_B
The Set_VLCD_A and Set_VLCD_B commands allow programming the VLCD value of the
character and icon mode, respectively. The generated VLCD is independent of the power
supply, allowing battery operation of the PCA2117.
Table 31. Set_VLCD_A and Set_VLCD_B - set VLCD command bit description
See Section 8.4.3.1.
Bit
Symbol
Value
Description
Set_VLCD_A command bit description
The 5 MSB of VLCDA
-
R/W
0
fixed value
-
RS[1:0]
11
fixed value
7 to 5
-
101
fixed value
VLCDA[8:4]
00000[1]
4 to 0
to
VLCD value of VLCDA
11111
The 4 LSB of VLCDA
-
R/W
0
fixed value
-
RS[1:0]
11
fixed value
7 to 4
-
1001
fixed value
3 to 0
VLCDA[3:0]
0000[1] to 1111 VLCD value of VLCDA
Set_VLCD_B command bit description
The 5 MSB of VLCDB
0
fixed value
-
R/W
-
RS[1:0]
11
fixed value
7 to 5
-
110
fixed value
4 to 0
VLCDB[8:4]
00000[1] to
11111
VLCD value of VLCDB
The 4 LSB of VLCDB
-
R/W
0
fixed value
-
RS[1:0]
11
fixed value
7 to 4
-
1110
VLCDB[3:0]
0000[1]
3 to 0
[1]
fixed value
to 1111 VLCD value of VLCDB
Default value.
8.1.4 Temperature compensation control commands
8.1.4.1
Command: Temperature_ctrl
The Temperature_ctrl command enables or disables the temperature measurement block
and the temperature compensation of VLCD (see Section 8.4.5).
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Automotive LCD driver for character displays
Table 32.
Temperature_ctrl - temperature measurement control command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
11
fixed value
7 to 3
-
00000
fixed value
2
TCE
temperature compensation setting
0[1]
temperature compensation of VLCD disabled
temperature compensation of VLCD enabled
1
1
TMF
0
temperature measurement filter setting
0[1]
digital temperature filter disabled[2]
1
digital temperature filter enabled
TME
temperature measurement setting
0[1]
temperature measurement disabled;
no temperature readout possible
1
temperature measurement enabled;
temperature readout possible
8.1.4.2
[1]
Default value.
[2]
The unfiltered digital value of TD[7:0] is immediately available for the readout and VLCD compensation.
Command: TC_slope
The TC_slope command allows setting the temperature coefficients of VLCD
corresponding to 4 temperature intervals.
Table 33.
TC_slope - VLCD temperature compensation slope command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
11
fixed value
-
00001
fixed value
TSA[2:0]
000[1]
temperature factor A setting[2]
TC-slope-A
7 to 3
2 to 0
to 111
TC-slope-B
7 to 3
2 to 0
-
00010
fixed value
TSB[2:0]
000[1]
temperature factor B setting[2]
to 111
TC-slope-C
7 to 3
2 to 0
-
00011
fixed value
TSC[2:0]
000[1]
temperature factor C setting[2]
to 111
TC-slope-D
PCA2117
Product data sheet
7 to 3
-
00100
fixed value
2 to 0
TSD[2:0]
000[1] to 111
temperature factor D setting[2]
[1]
Default value.
[2]
See Table 35 on page 43.
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PCA2117
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Automotive LCD driver for character displays
8.2 Start-up and shut-down
8.2.1 Initialization
The first command sent to the device after power-on or a reset by using the RST pin must
be the Initialize command (see Section 8.1.1.2).
The Initialize command resets the PCA2117 to the following starting conditions:
1. All row and column driver outputs are set to VSS1.
2. Selected drive mode is the 1  40 character mode.
3. The address counter is cleared (set logic 0).
4. Temperature measurement is disabled.
5. Temperature filter is disabled.
6. The internal VLCD voltage generation is disabled. The charge pump is switched off.
7. The VLCD temperature compensation is disabled.
8. The display is disabled.
The reset state is as shown in Table 34.
PCA2117
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PCA2117
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Automotive LCD driver for character displays
Table 34.
Reset state of PCA2117
Command name
Bits
7
6
5
4
3
2
1
0
Clock_out_ctrl
0
0
1
0
0
0
0
0
Read_reg_select
0
0
0
0
0
1
0
0
RAM_ROM_config
0
0
0
0
1
0
0
0
Sel_mem_bank
0
0
0
1
0
0
0
0
Set_mem_addr
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
General control commands
Display control commands
Entry_mode_set
Function_set
0
0
1
1
0
0
0
0
Inversion_mode
0
1
0
0
0
0
0
0
Frame_frequency
1
0
0
0
0
1
1
1
Display_control
0
0
1
0
0
0
0
0
Cursor_display_shift
0
0
0
1
0
0
0
0
Screen_config
0
0
0
0
0
0
1
0
Display_config
0
0
0
0
0
1
0
0
Icon_config
0
0
0
0
1
0
0
0
Charge pump and LCD bias control commands
Charge_pump_ctrl
1
0
0
0
0
0
0
0
Set_VLCD_A
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
Set_VLCD_B
Temperature compensation control commands
Temperature_ctrl
0
0
0
0
0
0
0
0
TC_slope
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
Remarks:
1. Do not transfer data for at least 1 ms after a power-on.
2. After power-on and before enabling the display, the DDRAM content must be brought
to a defined status
– by sending the Clear_display command
– or by writing meaningful display content by loading a character code
otherwise unwanted display artifacts can appear on the display.
PCA2117
Product data sheet
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PCA2117
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Automotive LCD driver for character displays
8.2.2 Reset pin function
The reset pin (RST) of the PCA2117 resets all the registers to their default state. The reset
state is given in Table 34. The RAM contents remain unchanged. After the reset signal is
released, the Initialize command must be sent to complete the initialization of the chip.
8.2.3 Power-down pin function
When connected to VDD1, the internal circuits are switched off, leaving only 2 A (typical)
as an overall current consumption. When connected to VSS1, the PCA2117 runs or starts
up to normal mode again. For the start-up and power-down sequences, see Section 8.2.4
and Section 8.2.5.
8.2.4 Recommended start-up sequences
This section describes how to proceed with the initialization of the chip in different
application modes.
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(1) The QPR flag (see Table 12) indicates if the programmed LCD voltage value was reached. The
latency time depends on the external capacitor on the VLCD pins. For a capacitor of 100 nF a delay
of 50 ms to 60 ms is expected.
Fig 6.
Recommended start-up sequence when using the internal charge pump and the
internal clock signal
When using the internal VLCD generation, the display must not be enabled before the
generation of VLCD with the internal charge pump is completed. Otherwise unwanted
display artifacts may appear on the display.
PCA2117
Product data sheet
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29 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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Fig 7.
Recommended start-up sequence when using an externally supplied VLCD and
the internal clock signal
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(1) Alternatively, the external clock signal can be applied after the generation of the VLCD voltage.
(2) The QPR flag (see Table 12) indicates if the programmed LCD voltage value was reached. The
latency time depends on the external capacitor on the VLCD pins. For a capacitor of 100 nF a delay
of 50 ms to 60 ms is expected.
Fig 8.
PCA2117
Product data sheet
Recommended start-up sequence when using the internal charge pump and an
external clock signal
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PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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Fig 9.
PCA2117
Product data sheet
Recommended start-up sequence when using an externally supplied VLCD and an
external clock signal
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PCA2117
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Automotive LCD driver for character displays
8.2.5 Recommended power-down sequences
With the following sequences, the PCA2117 can be set to a state of minimum power
consumption, called power-down mode.
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(1) If previously enabled.
Remark: When bits D (Table 25 on page 20), CPE (Table 30 on page 24), and TME (Table 32 on
page 26) are logic 0, the internal clock signal is switched off.
Fig 10. Recommended power-down sequence for minimum power-down current when
using the internal charge pump and the internal clock signal
PCA2117
Product data sheet
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PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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(1) If previously enabled.
Remark: When bits D (Table 25 on page 20), CPE (Table 30 on page 24), and TME (Table 32 on
page 26) are logic 0, the internal clock signal is switched off.
Fig 11. Recommended power-down sequence when using an externally supplied VLCD
and the internal clock signal
The chip can be put into power-down mode by applying a HIGH-level to pin PD. In
power-down mode, all static currents are switched off (no internal oscillator, no bias level
generation and all LCD outputs are internally connected to VSS).
During power-down, information in the RAM and the chip state are not preserved.
Instruction execution during power-down is not possible.
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
33 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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Fig 12. Recommended power-down sequence when using the internal charge pump and
an external clock signal
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Fig 13. Recommended power-down sequence when using an externally supplied VLCD
and an external clock signal
Remarks:
1. It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, care must be taken that no other signals are present at
the chip input or output pins when removing the supplies (refer to Section 10 on
page 76). Otherwise it may cause unwanted display artifacts. Uncontrolled removal of
supply voltages does not damage the PCA2117.
PCA2117
Product data sheet
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PCA2117
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Automotive LCD driver for character displays
2. Static voltages across the liquid crystal display can build up when the external LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD1 and VDD2) is off, or the
other way round. This may cause unwanted display artifacts. To avoid such artifacts,
external VLCD, VDD1, and VDD2 must be applied or removed together.
3. A clock signal must always be supplied to the device when the device is active.
Removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. Disable the display first and then remove the clock signal afterwards.
8.3 Possible display configurations
The PCA2117 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of character displays (see Figure 14 and Figure 15).
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Fig 15. Connecting PCA2117 with a 1  40 character LCD
The host microcontroller maintains the communication channel with the PCA2117. The
only other connections required to complete the system are the power supplies (VDD1,
VDD2, and VSS1 to VSS3), the VLCD pins (VLCDOUT, VLCDSENSE, VLCDIN), the
external capacitors, and the LCD panel selected for the application. The appropriate
biasing voltages for the multiplexed LCD waveforms are generated internally.
External capacitors of 100 nF minimum are required on each of the pins VDD1 and VDD2.
If they are connected to the same power supply (not recommended if VLCD is generated
internally), a capacitor of 300 nF minimum is required.
VSS1 to VSS3 have to be connected to the same ground supply.
PCA2117
Product data sheet
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PCA2117
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Automotive LCD driver for character displays
The VLCD pins (VLCDOUT, VLCDSENSE, VLCDIN) can be connected, whether VLCD is
generated internally or supplied from external. An external capacitor of 300 nF minimum is
recommended for VLCD. For high display loads, 1 F is suggested.
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VDD1 and VDD2 can be connected to the same power supply.
VSS1 to VSS3 can be connected to the same ground supply.
Fig 16. Typical system configuration if using the internal VLCD generation and I2C-bus
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Fig 17. Typical system configuration if using the external VLCD and SPI-bus
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
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PCA2117
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Automotive LCD driver for character displays
8.4 LCD voltage
8.4.1 VLCD pins
The PCA2117 has 3 VLCD pins:
VLCDIN — VLCD supply input
VLCDOUT — VLCD voltage output
VLCDSENSE — VLCD regulation circuitry input
The VLCD voltage can be generated on-chip or externally supplied.
8.4.2 External VLCD supply
When the external VLCD supply is selected, the VLCD voltage must be supplied to the pin
VLCDIN. The pins VLCDOUT and VLCDSENSE can be left unconnected or alternatively
connected to VLCDIN. The VLCD voltage is available at the row and column drives of the
device through the chosen bias system.
The internal charge pump must not be enabled, otherwise high internal currents may flow
as well as high currents via pin VDD2 and pin VLCDOUT. No internal temperature
compensation occurs on the externally supplied VLCD even if bit TCE is set logic 1 (see
Section 8.1.4.1). Also programming VLCDA[8:0] and VLCDB[8:0] has no effect on the
externally supplied VLCD.
8.4.3 Internal VLCD generation
When the internal VLCD generation is selected, the VLCD voltage is available on pin
VLCDOUT. The pins VLCDIN and VLCDSENSE must be connected to the pin VLCDOUT.
The Charge_pump_ctrl command (see Table 30 on page 24) controls the charge pump. It
can be enabled with the CPE bit. The multiplier setting can be configured with the
CPC[1:0] bits. The charge pump can generate a VLCD up to 4  VDD2.
8.4.3.1
VLCD programming
VLCD can be programmed by two bit-fields: VLCDA[8:0] and VLCDB[8:0]. VLCDA[8:0] is
programmed with the voltage for the character mode and VLCDB[8:0] with the voltage for
the icon mode.
The final value of VLCD is a combination of the programmed VLCDA[8:0] respectively
VLCDB[8:0] value and in addition the output of the temperature compensation block. The
system is exemplified in Figure 18.
PCA2117
Product data sheet
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PCA2117
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Automotive LCD driver for character displays
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Fig 18. VLCD generation including temperature compensation
Equation 1 to Equation 3 exemplify the VLCD generation with temperature compensation.
V prog  LCD  = VLCDx  0.03 V + 4 V
(1)
V offset  LCD  = VT  0.03 V
(2)
V LCD = V prog  LCD  + V offset  LCD  = VLCDx  0.03 V + 4 V + VT  0.03 V
(3)
1. VLCDx is the decimal value of the programmed VLCD factor (VLCDA[8:0] or
VLCDB[8:0]).
2. VT is the binary value of the calculated temperature compensating factor (VT[8:0]) of
the temperature compensation block (see Table 36). The temperature compensation
block provides the value which is a two’s complement with the value of 0h at 20 C.
Figure 19 shows how the VLCD changes with the programmed value of VLCDx[8:0].
PCA2117
Product data sheet
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PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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(1) VLCDx[8:0] must be set such that VLCD > VDD2.
(2) Automatic limitation for VLCD > 16 V.
Fig 19. VLCD programming of PCA2117 (assuming VT[8:0] = 0h)
Remarks:
1. VLCDx[8:0] has to be set to such a value that the resultant VLCD, including the
temperature compensation, is higher than VDD2.
2. The programmable range of VLCDx[8:0] is from 0h to 1FFh. It would allow achieving a
VLCD of higher voltages but the PCA2117 has a built-in automatic limitation set to
16 V.
8.4.4 VLCD drive capability
Figure 20 to Figure 22 illustrate the drive capability of the internal charge pump for various
conditions. VLCD is internally limited to 16 V.
PCA2117
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PCA2117
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Automotive LCD driver for character displays
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Conditions: VDD2 = 2.5 V; VLCD = 8 V; Tamb = 25 C; RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
(1) VLCD = 2  VDD2.
(2) VLCD = 3  VDD2.
(3) VLCD = 4  VDD2.
Iload is the overall current sink of the column and row outputs depending on the display, plus the
on-chip VLCD current consumption.
Fig 20. VLCD with respect to Iload at VDD2 = 2.5 V
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(1) VLCD = 2  VDD2.
(2) VLCD = 3  VDD2.
(3) VLCD = 4  VDD2.
Iload is the overall current sink of the column and row outputs depending on the display, plus the
on-chip VLCD current consumption.
Fig 21. VLCD with respect to Iload at VDD2 = 5 V
PCA2117
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PCA2117
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Automotive LCD driver for character displays
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Conditions: VDD2 = 5 V; VLCD = 16 V; Tamb = 25 C; RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
(1) VLCD = 2  VDD2.
(2) VLCD = 3  VDD2.
(3) VLCD = 4  VDD2.
Iload is the overall current sink of the column and row outputs depending on the display, plus the
on-chip VLCD current consumption.
Fig 22. VLCD with respect to Iload at VDD2 = 5 V
8.4.5 Temperature measurement and temperature compensation of VLCD
8.4.5.1
Temperature readout
The PCA2117 has a built-in temperature sensor which provides an 8-bit digital value
(TD[7:0]) of the ambient temperature. This value can be read by command (see
Section 8.1.1.6 on page 11). The actual temperature is determined from TD[7:0] using
Equation 4.
T  C  = 0.6275  TD – 40
(4)
TD[7:0] = FFh means that no temperature readout is available or was performed. FFh is
the default value after initialization. The measurement needs about 8 ms to complete. It is
repeated periodically every second as long as bit TME is set logic 1 (see Table 32 on
page 26).
Due to the nature of a temperature sensor, oscillations may occur. To avoid it, a filter has
been implemented in PCA2117. A control bit, TMF, is implemented to enable or disable
the digital temperature filter (see Table 32 on page 26). The system is exemplified in
Figure 23.
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
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41 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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The digital temperature filter introduces a certain delay in the measurement of the
temperature. This behavior is illustrated in Figure 24.
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(1) Environment temperature, T1 (C).
(2) Measured temperature, T2 (C).
(3) Measurement temperature variation, Tmeas = T2  T1.
Fig 24. Temperature measurement delay
8.4.5.2
Temperature adjustment of the VLCD
Due to the temperature dependency of the liquid crystal viscosity, the LCD supply voltage
may have to be adjusted at different temperatures to maintain optimal contrast. The
temperature characteristics of the liquid are provided by the LCD manufacturer. The slope
has to be set to compensate for the liquid behavior. Internal temperature compensation
can be enabled via bit TCE (see Table 32 on page 26).
The ambient temperature range is split up into 4 regions (see Figure 25) and to each a
different temperature coefficient can be applied.
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
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42 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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Fig 25. Example of segmented temperature coefficients
The temperature coefficients can be selected from a choice of eight different slopes. Each
one of theses coefficients is independently selected via the TC_slope command (see
Section 8.1.4.2 on page 26).
Table 35.
Temperature coefficients
TSA[2:0] to TSD[2:0] value
Slope factor (mV/C)
Temperature factor
TSA to TSD[1]
000[2]
0
0.000
001
6
0.125
010
12
0.250
011
24
0.500
100
60
1.250
101
+6
+0.125
110
+12
+0.250
111
+24
+0.500
[1]
The relationship between the temperature coefficients TSA to TSD and the slope factor is derived from
Equation 5. where LSB of VLCDx[8:0]  30 mV.
[2]
Default value.
0.6275  C 
TSn = ----------------------------  slope factor (mV/C 
30 (mV)
(5)
The value of the temperature compensated factor VT[8:0] is calculated according to
Table 36.
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Table 36.
Calculation of the temperature compensating factor VT
Temperature range (C) Decimal value of TD[7:0] Equations of factor VT
T  –40 C
0
VT = – 48  TSB – 48  TSA
– 40C  T  – 10 C
0 to 48
VT = – 48  TSB –  48 – TD[7:0]   TSA
– 10 C  T  20 C
49 to 96
VT = –  96 – TD[7:0]   TSB
20 C  T  50 C
97 to 143
VT =  TD[7:0] – 96   TSC
50 C  T  105 C
144 to 230
VT = 47  TSC +  TD[7:0] – 143   TSD
105 C  T
231
VT = 47  TSC + 88  TSD
[1]
8.4.5.3
[1]
No temperature compensation is possible above 105 C. Above this value, the system maintains the
compensation value from 105 C.
Example calculation of Voffset(LCD)
Assumed that Tamb = 8 C
1. Choose a temperature factor from Table 35, for example TSB[2:0] = 001, which gives
a slope factor of 0.125.
2. Calculate the decimal value of TD[7:0] with Equation 4:
– 8 + 40
TD = -------------------  51 .
0.6275
3. Calculate the temperature compensating factor VT with the appropriate equation from
Table 36:
VT = –  96 – 51   – 0.125 = 5.625 .
4. Calculate Voffset(LCD) with Equation 2:
V offset  LCD  = 5.625  0.03 V = 0.169 V .
8.4.6 LCD bias voltage generator
The intermediate bias voltages for the LCD are generated on-chip. It removes the need for
an external resistive bias chain and significantly reduces the system current consumption.
The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth)
and the number of bias levels.
The intermediate bias levels for the different multiplex rates are shown in Table 37. These
bias levels are automatically set to the given values when switching to the corresponding
multiplex rate.
Table 37.
PCA2117
Product data sheet
Bias levels as a function of multiplex rate
Multiplex
rate
LCD bias
configuration
Bias voltages
V1
V2
V3
V4
V5
V6
1:18
1⁄
4
VLCD
3
--- V LCD
4
1
--- V LCD
2
1
--- V LCD
2
1
--- V LCD
4
VSS
1:9
1⁄
4
VLCD
3
--- V LCD
4
1
--- V LCD
2
1
--- V LCD
2
1
--- V LCD
4
VSS
1:2
1⁄
3
VLCD
2
--- V LCD
3
2
--- V LCD
3
1
--- V LCD
3
1
--- V LCD
3
VSS
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The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 6 and the
RMS off-state voltage (Voff(RMS)) with Equation 7:
V on  RMS  =
V LCD
a 2 + 2a + n
-----------------------------2
n  1 + a
(6)
V off  RMS  =
V LCD
a 2 – 2a + n
-----------------------------2
n  1 + a
(7)
where the values of a are
a = 2 for 1⁄3 bias
a = 3 for 1⁄4 bias
and the values for n are
n = 2 for 1:2 multiplex rate
n = 9 for 1:9 multiplex rate
n = 18 for 1:18 multiplex rate.
Discrimination (D) is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 8.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
V on  RMS 
D = ---------------------- =
V off  RMS 
2
a + 1 + n – 1
-------------------------------------------2
a – 1 + n – 1
(8)
Remark:
• Row and column outputs comprise a series resistance RO (see Table 50).
• VLCD is sometimes referred as the LCD operating voltage.
8.4.6.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determines the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 26. For a good contrast performance, the following rules should be followed:
V on  RMS   V th  on 
(9)
V off  RMS   V th  off 
(10)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a (see Equation 6), n (see Equation 8), and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
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It is important to match the module properties to those of the driver in order to achieve
optimum performance.
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Fig 26. Electro-optical characteristic: relative transmission curve of the liquid
8.4.7 LCD drive mode waveforms
The PCA2117 contains 18 row and 100 column drivers, which drive the appropriate LCD
bias voltages in sequence to the display and in accordance with the data to be displayed.
R16 and R17 drive the icon rows. Unused outputs should be left open.
The bias voltages and the timing are automatically selected when the number of lines in
the display is selected. Figure 27 to Figure 29 show typical waveforms.
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Automotive LCD driver for character displays
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State(n) marks intersection(row(x),col(n)) of LCD element(x,n).
Vstate(n)(t) = VC(n)(t)  VR(x)(t).
Vstate1(t) = VC0(t)  VR0(t).
Vstate2(t) = VC1(t)  VR0(t).
Fig 27. Waveforms for the 1:18 multiplex drive mode. 5 bias levels, character mode, frame inversion mode
PCA2117
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Rev. 4 — 8 April 2015
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47 of 107
PCA2117
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Automotive LCD driver for character displays
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State(n) marks intersection(row(x),col(n)) of LCD element(x,n).
Vstate(n)(t) = VC(n)(t)  VR(x)(t).
Vstate1(t) = VC0(t)  VR0(t).
Vstate2(t) = VC1(t)  VR0(t).
Fig 28. Waveforms for the 1:9 multiplex drive mode, 5 bias levels, character mode, R8 to R15 and R17 open,
frame inversion mode
PCA2117
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Rev. 4 — 8 April 2015
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48 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
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State(n) marks intersection(row(x),col(n)) of LCD element(x,n).
Vstate(n)(t) = VC(n)(t)  VR(x)(t).
Vstate1(t) = VC0(t)  VR16(t).
Vstate2(t) = VC1(t)  VR16(t).
Vstate3(t) = VC2(t)  VR1 to 15(t).
Fig 29. Waveforms for the 1:2 multiplex drive mode, 4 bias levels, icon mode, frame inversion mode
PCA2117
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Automotive LCD driver for character displays
8.5 Display data RAM and ROM
The PCA2117 has a CGROM containing the character set, a CGRAM for user-defined
characters, an ICON-RAM for user-defined icons and a DDRAM which contains the
display data from the CGROM and CGRAM. There is a one-to-one correspondence
between the bits in the DDRAM and the LCD elements. The whole dataflow is exemplified
in Figure 30.
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Fig 30. Dataflow from CGROM, CGRAM and ICON-RAM to the display
PCA2117
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Automotive LCD driver for character displays
8.5.1 RAM/ROM access
The RAM and ROM access of the PCA2117 is exemplified in Figure 31
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Fig 31. RAM/ROM access flowchart
8.5.2 Checksum
In order to detect transmission failures for RAM content transfers, the PCA2117 has a
checksum calculator providing an XOR or CRC-8 checksum. The checksum calculator
can be configured with bit XC of the Read_reg_select command (see Section 8.1.1.6).
The checksum result can be read out with the Read_status_reg command (see
Section 8.1.1.7).
The checksum results are:
• when XC = 0 (XOR checksum)
– The checksum is the result of the XOR operation on the values loaded with the
Write_data command and the previous register content.
– The checksum result is reset when the bits of the command select RS[1:0] or R/W
are changed.
• when XC = 1 (CRC-8 checksum)
PCA2117
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Automotive LCD driver for character displays
– The checksum is the result of the CRC-8 operation on the values loaded with the
Write_data command and the previous register content. The polynomial used is
8
5
4
x +x +x +1.
– The checksum result is reset when the bits of the command select RS[1:0] or R/W
are changed.
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Fig 32. Logic diagram of the CRC8 generator
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Fig 33. Checksum generation
8.5.3 CGROM
The Character Generator ROM (CGROM) contains 240 character patterns in a 5  8 dot
format from 8-bit character codes. The PCA2117 has the character set shown in
Figure 34. It can be provided with other character sets on request.
PCA2117
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Automotive LCD driver for character displays
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Fig 34. Character set ‘R’ in CGROM
PCA2117
Product data sheet
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Automotive LCD driver for character displays
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Fig 35. Character set ‘S’ in CGROM
PCA2117
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Automotive LCD driver for character displays
8.5.3.1
CGROM addressing
To display a character from the CGROM, it has to be written to the DDRAM with WD[7:0}
of the Write_data command. The addressing sequence is “4 MSB 4 LSB” (see Figure 31).
Addressing examples:
• 1101 0000 points to character P
• 1110 0010 points to character b
8.5.4 CGRAM
Up to 48 user-defined characters may be stored in the Character Generator RAM
(CGRAM), depending on the configuration of CGRAM and CGROM (RR[1:0]) with the
RAM_ROM_config command (see Section 8.1.1.8).
With the RAM_ROM_config command, the CGROM column 1 and column 2 can be
overlaid with the corresponding CGRAM columns.
RR[1:0] = 00 — 16 CGRAM characters in CGRAM column 0
RR[1:0] = 01 — 32 CGRAM characters in CGRAM column 0 and CGRAM column 2
RR[1:0] = 10 — 32 CGRAM characters in CGRAM column 0 and CGRAM column 1
RR[1:0] = 11 — 48 CGRAM characters in CGRAM column 0, CGRAM column 1 and
CGRAM column 2
Figure 36 exemplifies the overlay of the CGROM with the CGRAM columns.
PCA2117
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Automotive LCD driver for character displays
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Fig 36. Configuration of CGROM and CGRAM with RR[1:0]
PCA2117
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Automotive LCD driver for character displays
8.5.4.1
CGRAM addressing
For addressing, the CGRAM the following steps have to be taken (see Figure 31):
• Select the column of the CGRAM (SMB[2:0]) with the Sel_mem_bank command (see
Section 8.1.1.9)
• Set the requested address counter (ADD[6:0]) with the Set_mem_addr command
(see Section 8.1.1.10)
• Write data to the CGRAM with the Write_data command (WD[4:0]) (see
Section 8.1.1.12)
• Read the data from the CGRAM with the Read_data command (RD[4:0]) (see
Section 8.1.1.11)
8.5.4.2
User-defined characters and symbols
User-defined characters can be stored in the CGRAM. The content of the CGRAM is lost
during power-down, therefore the CGRAM has to be rewritten after every power-on.
DDD
Fig 37. User-defined euro currency sign
Below some source code is printed, which shows how a user-defined character can be
coded - in this case the euro currency sign. The display used is a 2 lines by 20 characters
display and the interface is the I2C-bus:
// Write a user-defined character into the CGRAM
startI2C();
// PCA2117 slave address for write, SA0 is connected to VDD
SendI2CAddress(0x76);
// MSB (Continuation bit CO) = 0, no more control bytes will follow, RS[1:0]= 10
// next byte is command byte on register page "10"
i2c_write(0x40);
// 2 lines x 20 chars, 1/18 duty. Next byte will be another command.
i2c_write(0x32);
// Repeated Start condition
startI2C();
SendI2CAddress(0x76);
// MSB (Continuation bit CO) = 0, no more control bytes will follow, RS[1:0]= 00
// next bytes are command bytes on register page "00"
i2c_write(0x00);
// Select Memory Bank 1: Column 0 of CGRAM
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i2c_write(0x11);
// Select Memory Address 0: Point to first row in the CGRAM
i2c_write(0x80);
// Repeated Start condition
startI2C();
SendI2CAddress(0x76);
// MSB (Continuation bit CO) = 0, no more control bytes will follow, RS[1:0]= 01
// next bytes are RAM data bytes written in the CGRAM column 0
i2c_write(0x20);
// Here the data bytes to define the character
// Behind the write commands the 5x8 dot matrix is shown, the 1 represents a on pixel.
// The Euro currency character can be recognized by the 0/1 pattern (see Figure 37)
// 00110
i2c_write(0x06); // 00110
i2c_write(0x09); // 01001
i2c_write(0x08); // 01000
i2c_write(0x1E); // 11110
i2c_write(0x1E); // 11110
i2c_write(0x08); // 01000
i2c_write(0x09); // 01001
i2c_write(0x06); // 00110
i2c_stop();
// Until here the definition of the character and writing it into the CGRAM. Now it
// still has to be displayed. See below.
// PCA2117, setting of proper display modes
startI2C();
// PCA2117 slave address for write, SA0 is connected to VDD
SendI2CAddress(0x76);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 10
// next byte is a command byte on register page "10"
i2c_write(0xC0);
// Set display configuration to right to left, column 80 to 1. Row data displ. top to
// bottom 1 to 16. P-bit='1' Q-bit = '1
i2c_write(0x06);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 10
// next byte is a command byte on register page "10"
i2c_write(0xC0);
// Set to character mode, full display, icon blink disabled
i2c_write(0x08);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 11
// next byte is a command byte on register page "11"
i2c_write(0xE0);
// Set voltage multiplier to 2 and enable chargepump
i2c_write(0x84);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 11
// next byte is a command byte on register page "11"
i2c_write(0xE0);
// Set Vlcda MSB
i2c_write(0xA2);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 11
// next byte is a command byte on register page "11"
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i2c_write(0xE0);
// Set Vlcda LSB
i2c_write(0x90);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 10
// next byte is a command byte on register page "10"
i2c_write(0xC0);
// Display control: set display on, cursor off, no blink
i2c_write(0x24);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 00
// next byte is a command byte on register page "00"
i2c_write(0x80);
// Select Memory Bank 0: DDRAM
i2c_write(0x10);
// MSB (Continuation bit CO) = 1, more control bytes will follow, RS[1:0]= 00
// next byte is a command byte on register page "00"
i2c_write(0x80);
// Set Memory Address to be 0
i2c_write(0x80);
// MSB (Continuation bit CO) = 0, last control bytes, RS[1:0]= 10
// next bytes are command bytes on register page "10"
i2c_write(0x40);
// Entry mode set, increase DDRAM after access, no shift
i2c_write(0x2A);
// Clear entire display
i2c_write(0x00);
// Return home, set DDRAM address 0 in address counter
i2c_write(0x01);
// Repeated Start condition because RS bits need to point to RAM data registers
startI2C();
// PCA2117 slave address for write, SA0 is connected to VDD
SendI2CAddress(0x76);
// MSB (Continuation bit CO) = 0, last control bytes, RS[1:0]= 01
// next bytes are RAM data bytes written in DDRAM at address 0
i2c_write(0x20);
// Write the character at address 0, which is the previously defined Euro currency
// character
i2c_write(0x00):
i2c_stop();
8.5.5 ICON-RAM
To display an icon, see Figure 31:
1. Select the ICON-RAM with SMB[2:0] = 100 of the Sel_mem_bank command.
2. Set the address with the Set_mem_addr command.
3. Write the data with WD[4:0] of the Write_data command.
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Automotive LCD driver for character displays
GLVSOD\
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52:
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Fig 38. Icon to row/column mapping
Table 38.
Icon to ICON-RAM mapping table
ICON-RAM
address
blink
phase
ICON-RAM bits
7
6
5
4
3
2
1
0
00h
even
-
-
-
icon 0
icon 1
icon 2
icon 3
icon 4
01h
even
-
-
-
icon 5
icon 6
icon 7
icon 8
icon 9
02h
even
-
-
-
icon 10
icon 11
icon 12
icon 13
icon 14
03h
even
-
-
-
icon 15
icon 16
icon 17
icon 18
icon 19
:
:
:
:
:
:
:
:
:
:
26h
even
-
-
-
icon 190
icon 191
icon 192
icon 193
icon 194
27h
even
-
-
-
icon 195
icon 196
icon 197
icon 198
icon 199
28h
odd
-
-
-
icon 0
icon 1
icon 2
icon 3
icon 4
29h
odd
-
-
-
icon 5
icon 6
icon 7
icon 8
icon 9
:
:
:
:
:
:
:
:
:
:
4Ch
odd
-
-
-
icon 180
icon 181
icon 182
icon 183
icon 184
4Dh
odd
-
-
-
icon 185
icon 186
icon 187
icon 188
icon 189
4Eh
odd
-
-
-
icon 190
icon 191
icon 192
icon 193
icon 194
4Fh
odd
-
-
-
icon 195
icon 196
icon 197
icon 198
icon 199
8.5.6 DDRAM
The Display Data RAM (DDRAM) stores up to 80 characters of display data represented
by 8-bit character codes. RAM locations which are not used for storing display data can
be used as general-purpose RAM.
The basic RAM to display addressing scheme is shown in Figure 39 to Figure 41. With no
display shift, the characters represented by the codes in the first 40 RAM locations
starting at address 00h are displayed in line 1.
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Automotive LCD driver for character displays
GLVSOD\
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All addresses are shown in hex.
Fig 39. DDRAM to display mapping: no shift
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All addresses are shown in hex.
Fig 40. DDRAM to display mapping: right shift
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All addresses are shown in hex.
Fig 41. DDRAM to display mapping: left shift
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When data is written to or read from the DDRAM, wrap-around occurs from the end of one
line to the start of the next line. When the display is shifted each line wraps around within
itself, independently of the others. Thus all lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the various modes are shown in
Table 39.
Table 39.
PCA2117
Product data sheet
Address space and wrap-around operation
Mode
1  40
2  20
1  20
Address space
00h to 4Fh
00h to 27h;
40h to 67h
00h to 27h
Read/write wrap-around (moves
to next line)
4Fh to 00h
27h to 40h;
67h to 00h
27h to 00h
Display shift wrap-around (stays
within line)
4Fh to 00h
27h to 00h;
67h to 40h
27h to 00h
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8.5.7 Cursor control circuit
The cursor control circuit generates the cursor underline and/or cursor blink as shown in
Figure 42 at the DDRAM address contained in the address counter.
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Fig 42. Cursor and blink display examples
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Fig 43. Display example with icons
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9. Bus interfaces
9.1 Control byte and register selection
After initiating the communication over the bus and sending the slave address (I2C-bus,
see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The
purpose of this byte is to indicate both, the content for the following data bytes (RAM or
command) and to indicate that more control bytes will follow.
Typical sequences could be:
• Slave address/subaddress - control byte - command byte - control byte - command
byte - control byte - command byte - end
• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end
• Slave address/subaddress - control byte - command byte - control byte - RAM byte end
This allows sending a mixture of RAM and command data in one access or alternatively,
to send just one type of data in one access. In this way, it is possible to configure the
device and then fill the display RAM with little overhead. The display bytes are stored in
the display RAM at the address specified by the data pointer.
Table 40.
Control byte description
Bit
Symbol
7
CO
6 to 5
4 to 0
Value
Description
continue bit
0
last control byte
1
control bytes continue
RS[1:0]
register selection
-
00, 10, 11
command register
01
RAM data
-
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Fig 44. Control byte format
9.2 I2C interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
In Chip-On-Glass (COG) applications, where the track resistance between the SDA
output pin to the system SDA input line can be significant, the bus pull-up resistor and the
Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a
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Automotive LCD driver for character displays
consequence it may be possible that the acknowledge cycle, generated by the LCD driver,
cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG
applications to have the acknowledge output separated from the data line. For that
reason, the SDA line of the PCA2117 is split into SDAIN and SDAOUT.
In COG applications where the acknowledge cycle is required, it is necessary to minimize
the track resistance from the SDAOUT pin to the system SDAIN line to guarantee a valid
LOW level.
By splitting the SDA line into SDAIN and SDAOUT (having the SDAOUT open circuit), the
device could be used in a mode that ignores the acknowledge cycle. Separating the
acknowledge output from the serial data line can avoid design efforts to generate a valid
acknowledge level. However, in that case the I2C-bus master has to be set up in such a
way that it ignores the acknowledge cycle.2
By connecting pin SDAOUT to pin SDAIN the SDAIN line becomes fully I2C-bus
compatible (see Figure 45). The following definition assumes that SDAIN and SDAOUT
are connected and refers to the pair as SDA.
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Fig 45. SDAOUT and SDAIN configuration
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 46).
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Fig 46. Bit transfer
9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
2.
For further information, consider the NXP application note: Ref. 1 “AN10170”.
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A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 47.
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Fig 47. Definition of START and STOP conditions
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 48.
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Fig 48. System configuration
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 49.
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Automotive LCD driver for character displays
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Fig 49. Acknowledgement on the I2C-bus
9.2.5 I2C-bus controller
The PCA2117 acts as an I2C-bus slave. It does not initiate I2C-bus transfers.
9.2.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
9.2.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address.
Two different I2C-bus slave addresses can be used to address the PCA2117 (see
Table 41).
Table 41.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
slave address
0
0
LSB
1
1
1
0
1
SA0
R/W
The least significant bit of the slave address byte is bit R/W (see Table 42).
Table 42.
R/W-bit description
R/W
Description
0
write data
1
read data
Bit 1 of the slave address is defined by connecting the input SA0 to either VSS1 (logic 0) or
VDD1 (logic 1). Therefore, two instances of PCA2117 can be distinguished on the same
I2C-bus.
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9.2.8 I2C-bus protocol
Table 43. Example: Writing to RAM by I2C-bus
Bits labeled as - are ignored.
Commands and signals
Values
1. Select RAM bank and set address pointer
I2C-START
S
Slave address
0
1
1
1
0
1
SA0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
Acknowledge from PCA2117
Command: Sel_mem_bank
0
0
-
-
-
0
0
1
0
SMB[2:0]
-
A
0
DDRAM
Acknowledge from PCA2117
A
Command: Set_mem_addr
1
address 0h
Acknowledge from PCA2117
-
0
0
0
0
ADD[6:0]
0
0
0
0
0
0
1
1
1
0
1
SA0
A
2. Select write RAM data
I2C-RESTART
Sr
Slave address
0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
0
Acknowledge from PCA2117
Command: Write_data
1
-
-
-
-
-
A
writing 0 to n byte
Acknowledge from master after
each byte
A
I2C-STOP
P
The I2C-bus protocol is shown in Table 43. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the two slave addresses
available. All PCA2117 with the corresponding SA0 level acknowledge in parallel to the
slave address, but all PCA2117 with the alternative SA0 level ignore the whole I2C-bus
transfer.
After acknowledgement, a control byte (see Section 9.1) follows which defines if the next
byte is RAM or command information. The control byte also defines if the next byte is a
control byte or further RAM or command data.
In this way, it is possible to configure the device and then fill the display RAM with little
overhead.
The display bytes are stored in the display RAM at the address specified by the data
pointer.
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The acknowledgement after each byte is made only by the addressed PCA2117. After the
last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a
repeated START may be issued to RESTART an I2C-bus access.
If a register readout is made, the R/W bit must be logic 1 and then the next data byte
following is provided by the PCA2117 as shown in Table 44.
Table 44. Example: Reading from RAM by I2C-bus
Bits labeled as - are ignored.
Commands and signals
Values
1. Straight forward example
1.1 Select RAM bank and set address pointer
I2C-START
S
Slave address
0
1
1
1
0
1
SA0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
Acknowledge from PCA2117
Command: Sel_mem_bank
0
0
-
-
-
0
0
0
1
0
SMB[2:0]
DDRAM
Acknowledge from PCA2117
A
Command: Set_mem_addr
1
address 0h
Acknowledge from PCA2117
-
-
A
0
0
0
0
ADD[6:0]
0
0
0
0
0
0
1
1
1
0
1
SA0
A
1.2 Select read RAM data
I2C-RESTART
Sr
Slave address
0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
Acknowledge from PCA2117
A
I2C-RESTART
Sr
Slave address
0
0
1
-
-
-
-
1
1
1
0
1
SA0
1
R/W
Acknowledge from PCA2117
Command: Read_data
PCA2117
Product data sheet
-
A
reading 0 to n byte
Acknowledge from master after
each byte
A
I2C-STOP
P
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Table 44. Example: Reading from RAM by I2C-bus …continued
Bits labeled as - are ignored.
Commands and signals
Values
2. Extended example: select new mem address
2.1 Setting the address pointer[1]
I2C-START
S
Slave address
0
1
1
1
0
1
SA0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
0
Acknowledge from PCA2117
A
Command: Set_mem_addr
1
address 40h
-
-
-
-
-
0
0
0
0
0
0
1
1
0
1
SA0
ADD[6:0]
1
Acknowledge from PCA2117
0
A
2.2 Select read RAM data from new mem address
I2C-RESTART
Sr
Slave address
0
1
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
Acknowledge from PCA2117
A
I2C-RESTART
Sr
Slave address
0
0
1
-
-
-
-
1
1
1
0
1
SA0
-
1
R/W
Acknowledge from PCA2117
Command: Read_data
A
reading 0 to n byte
Acknowledge from master after
each byte
A
I2C-STOP
P
3. Extended example: decrementing address pointer
3.1 Setting the address pointer[1]
I2C-START
S
Slave address
0
1
1
1
0
1
SA0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
0
Acknowledge from PCA2117
A
Command: Set_mem_addr
1
address 4Fh
PCA2117
Product data sheet
-
-
-
-
-
0
1
1
1
1
ADD[6:0]
1
Acknowledge from PCA2117
0
0
A
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Table 44. Example: Reading from RAM by I2C-bus …continued
Bits labeled as - are ignored.
Commands and signals
Values
3.2 Select decrement address pointer
I2C-RESTART
Sr
Slave address
0
1
1
1
0
1
SA0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
Acknowledge from PCA2117
Command: Entry_mode_set
Acknowledge from PCA2117
1
0
-
-
-
-
-
0
1
0
1
0
0
0
1
1
1
0
1
SA0
A
0
A
3.3 Select read RAM data
I2C-RESTART
Sr
Slave address
0
0
R/W
Acknowledge from PCA2117
CO
A
0
RS[1:0]
Acknowledge from PCA2117
A
I2C-RESTART
Sr
Slave address
0
0
1
-
-
-
-
1
1
1
0
1
SA0
1
R/W
Acknowledge from PCA2117
Command: Read_data
A
reading 0 to n byte
Acknowledge from master after
each byte
A
I2C-STOP
P
[1]
-
Assuming that general-purpose RAM was already selected.
9.3 SPI interface
Data transfer to the device is made via a four-line SPI-bus (see Table 45). The SPI-bus is
initialized whenever the chip enable line pin CE is inactive.
Table 45.
Serial interface
Symbol
Function
Description
CE
chip enable input;
active LOW[1]
when HIGH, the interface is reset
SCL
serial clock input
input may be higher than VDD1
SDI/SDAIN serial data input
input may be higher than VDD1;
input data is sampled on the rising edge of SCL
SDO
[1]
PCA2117
Product data sheet
serial data output
-
The chip enable must not be wired permanently LOW.
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9.3.1 SPI-bus data transfer
The chip enable signal is used to identify the transmitted data. Each data transfer is a
byte, with the MSB sent first.
The transmission is controlled by the active LOW chip enable signal CE. The first byte
transmitted is the subaddress byte.
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Fig 50. SPI data transfer overview
The subaddress byte opens the communication with a read/write bit and a subaddress.
The subaddress is used to identify multiple devices on one SPI bus.
Table 46.
Subaddress byte definition
Bit
Symbol
7
R/W
6 to 5
SA
4 to 0
-
Value
Description
data read or write selection
0
write data
1
read data
01
Subaddress; other codes cause the device to
ignore data transfer
unused
After the subaddress byte, a control byte follows (see Section 9.1). The purpose of this
byte is to indicate the content for the following data bytes (RAM, command or control
byte).
In this way, it is possible to send a mixture of RAM and command data in one access or
alternatively, to send just one type of data in one access.
PCA2117
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Automotive LCD driver for character displays
Table 47. Example: Writing to RAM by SPI-bus
Bits labeled as - are ignored.
Commands and signals
Values
1.1 Select RAM bank and set address pointer
CE LOW
0
R/W
Subaddress
CO
0
1
-
-
-
-
-
0
0
-
-
-
-
-
0
0
1
0
SMB[2:0]
0
RS[1:0]
Command: Sel_mem_bank
0
DDRAM
Command: Set_mem_addr
1
address 0h
0
0
0
ADD[6:0]
0
0
0
0
0
0
0
0
1
-
-
-
-
-
0
1
-
-
-
-
-
CE HIGH
1.2 Select write RAM data
CE LOW
0
R/W
Subaddress
CO
0
RS[1:0]
Command: Write_data
writing 0 to n byte
CE HIGH
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Automotive LCD driver for character displays
Table 48. Example: Reading from RAM by SPI-bus
Bits labeled as - are ignored.
Commands and signals
Values
1. Straight forward example
1.1 Select RAM bank and set address pointer
CE LOW
0
R/W
Subaddress
CO
0
1
-
-
-
-
-
0
0
-
-
-
-
-
0
0
0
1
0
SMB[2:0]
1
ADD[6:0]
0
RS[1:0]
Command: Sel_mem_bank
DDRAM
Command: Set_mem_addr
address 0h
0
0
0
0
0
0
0
0
0
0
0
1
-
-
-
-
-
0
1
-
-
-
-
-
0
1
-
-
-
-
-
CE HIGH
1.2 Select read RAM data
CE LOW
0
R/W
Subaddress
CO
0
RS[1:0]
CE HIGH
CE LOW
1
R/W
Subaddress
Command: Read_data
reading 0 to n byte
CE HIGH
2. Extended example: select new mem address
2.1 Setting the address pointer[1]
CE LOW
0
R/W
Subaddress
CO
0
1
-
-
-
-
-
0
0
-
-
-
-
-
0
0
0
0
0
0
0
1
-
-
-
-
-
0
1
-
-
-
-
-
0
RS[1:0]
Command: Set_mem_addr
1
address 40h
ADD[6:0]
1
CE HIGH
2.2 Select read RAM data from new mem address
CE LOW
R/W
0
Subaddress
CO
RS[1:0]
PCA2117
Product data sheet
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Automotive LCD driver for character displays
Table 48. Example: Reading from RAM by SPI-bus …continued
Bits labeled as - are ignored.
Commands and signals
Values
CE HIGH
CE LOW
1
R/W
Subaddress
0
Command: Read_data
1
-
-
-
-
-
reading 0 to n byte
CE HIGH
3. Extended example: decrementing address pointer
3.1 Setting the address pointer[1]
CE LOW
0
R/W
Subaddress
CO
0
1
-
-
-
-
-
0
0
-
-
-
-
-
0
RS[1:0]
Command: Set_mem_addr
1
address 4Fh
ADD[6:0]
1
0
0
1
1
1
1
0
1
-
-
-
-
-
1
0
-
-
-
-
-
0
1
0
1
0
0
0
0
1
-
-
-
-
-
0
1
-
-
-
-
-
0
1
-
-
-
-
-
CE HIGH
3.2 Select decrement address pointer
CE LOW
0
R/W
Subaddress
CO
0
RS[1:0]
Command: Entry_mode_set
0
CE HIGH
3.3 Select read RAM data
CE LOW
0
R/W
Subaddress
CO
0
RS[1:0]
CE HIGH
CE LOW
1
R/W
Subaddress
Command: Read_data
reading 0 to n byte
CE HIGH
[1]
PCA2117
Product data sheet
Assuming that general-purpose RAM was already selected.
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Automotive LCD driver for character displays
10. Internal circuitry
9/&',1
9''9/&',19/&'6(16(
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Fig 51. Device protection diagram
11. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
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Product data sheet
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Automotive LCD driver for character displays
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
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Automotive LCD driver for character displays
12. Limiting values
Table 49. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD1
supply voltage 1
analog and digital
0.5
+6.5
V
VDD2
supply voltage 2
charge pump
0.5
+6.5
V
IDD1
supply current 1
analog and digital
50
+50
mA
IDD2
supply current 2
charge pump
50
+50
mA
VLCD
LCD supply voltage
external supply, input on pin
VLCDIN
0.5
+20
V
IDD(LCD)
LCD supply current
50
+50
mA
Vi
input voltage
on pins CLK, OSC, RST, PD, IFS,
SCL, SDI/SDAIN, SA0, CE
0.5
+6.5
V
on pin VLCDSENSE
0.5
+20
V
II
input current
10
+10
mA
VO
output voltage
on pins C0 to C99, R0 to R17,
VLCDOUT
0.5
+20
V
on pins SDO, SDAOUT, CLK
0.5
+6.5
V
IO
output current
10
+10
mA
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per
output
-
100
mW
VESD
electrostatic
discharge voltage
[1]
-
3000
V
Ilu
latch-up current
[2]
-
100
mA
Tstg
storage temperature
[3]
65
+150
C
Tamb
ambient temperature
40
+105
C
[1]
HBM
operating device
Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.
[2]
Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)).
[3]
According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
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Automotive LCD driver for character displays
13. Static characteristics
Table 50. Static characteristics
VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD1
supply voltage 1
2.5
-
5.5
V
VDD2
supply voltage 2
2.5
-
5.5
V
VLCD
LCD supply voltage
external supply, input on pin
VLCDIN
4.0
-
16.0
V
internal supply, output on pin
VLCDOUT
4.0
-
16.0
V
default condition after
power-on and Initialize
command
-
40[1]
59[2]
A
display enabled;
internal clock
-
95[1]
-
A
default condition after
power-on and Initialize
command;
charge pump off
-
0
-
A
VDD2 = 5 V;
charge pump at
VLCD = 2  VDD2;
VLCD = 8 V;
CVLCD = 100 nF;
display disabled;
see Figure 53
-
25
-
A
display disabled
-
7
12
A
MUX 1:18;
1⁄ bias;
4
ffr = 80 Hz;
all display elements on;
frame inversion mode;
display enabled;
no display attached;
see Figure 54
-
70
-
A
-
2
-
A
IDD1
IDD2
IDD(LCD)
IDD(pd)
supply current 1
supply current 2
LCD supply current
power-down mode
supply current
PCA2117
Product data sheet
VLCD  VDD2
on pin VDD1;
see Figure 52
on pin VDD2
on pin VLCDIN;
external VLCD = 8 V
on pin VDD1;
pin PD is HIGH;
VDD1 = 5 V;
Tamb = 25 C
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Automotive LCD driver for character displays
Table 50. Static characteristics …continued
VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VLCD
LCD voltage variation
on pin VLCDOUT;
internal VLCD;
VLCD = 8 V;
Tamb = 25 C;
see Figure 55
7.9
8
8.1
V
ffr
frame frequency
variation
internal clock;
ffr = 80 Hz;
Tamb = 25 C;
see Figure 56
77
80
83
Hz
Tmeas
measurement
temperature variation
Tamb = 25 C
22
25
28
C
on pin R0 to R17;
external VLCD = 8 V
-
1
-
k
on pin C0 to C99;
external VLCD = 8 V
-
2.5
-
k
V
Accuracy
Output resistance
RO
output resistance
Logic
On pins CLK, OSC, PD, RST, IFS, SA0
VIL
LOW-level input
voltage
0.3
-
0.3VDD1
VIH
HIGH-level input
voltage
0.7VDD1
-
VDD1 + 0.3 V
ILI
input leakage current
-
0
-
VI = VDD1 or VSS1
A
On pin CLK
VOH
HIGH-level output
voltage
0.8VDD1
-
VDD1 + 0.3 V
VOL
LOW-level output
voltage
0.3
-
0.2VDD1
V
IOH
HIGH-level output
current
output source current;
VOH = 4.6 V;
VDD1 = 5 V
1
-
-
mA
IOL
LOW-level output
current
output sink current;
VOL = 0.4 V;
VDD1 = 5 V
1
-
-
mA
ILO
output leakage current VO = VDD1 or VSS1
-
0
-
A
I2C-bus
On pins SCL, SDI/SDAIN
VIL
LOW-level input
voltage
0.3
-
0.3VDD1
V
VIH
HIGH-level input
voltage
0.7VDD1
-
5.5
V
ILI
input leakage current
-
0
-
A
PCA2117
Product data sheet
VI = VDD1 or VSS1
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Automotive LCD driver for character displays
Table 50. Static characteristics …continued
VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.5
-
+5.5
V
On pin SDAOUT
VO
output voltage
IOL
LOW-level output
current
output sink current;
VOL = 0.4 V
6
-
-
mA
ILI
input leakage current
VI = VDD1 or VSS1
-
0
-
A
ILO
output leakage current VO = VSS1
-
0
-
A
V
SPI-bus
On pins SCL, SDI/SDAIN, CE
VIL
LOW-level input
voltage
0.3
-
0.3VDD1
VIH
HIGH-level input
voltage
0.7VDD1
-
VDD1 + 0.3 V
ILI
input leakage current
-
0
-
VI = VDD1 or VSS1
A
On pin SDO
VOH
HIGH-level output
voltage
0.8VDD1
-
VDD1 + 0.3 V
VOL
LOW-level output
voltage
0.3
-
0.2VDD1
V
IOH
HIGH-level output
current
output source current;
VOH = 4.6 V;
VDD1 = 5 V
1
-
-
mA
IOL
LOW-level output
current
output sink current;
VOL = 0.4 V;
VDD1 = 5 V
1
-
-
mA
ILO
output leakage current VO = VDD1 or VSS1
-
0
-
A
[1]
VDD1 = 5 V; Tamb = 25 C.
[2]
VDD1 = 5.5 V; Tamb = 105 C.
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Automotive LCD driver for character displays
DDD
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7DPEž&
VDD1 = 5 V.
(1) Display enabled, oscillator enabled.
(2) Default conditions after power-on and initialization.
Fig 52. Typical IDD1 with respect to temperature
DDD
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(1) VDD2 = 3 V; charge pump at VLCD = 3  VDD2; VLCD = 8 V; CVLCD = 100 nF; display disabled.
(2) VDD2 = 5 V; charge pump at VLCD = 2  VDD2; VLCD = 8 V; CVLCD = 100 nF; display disabled.
(3) Default conditions after power-on and initialization; charge pump off.
Fig 53. Typical IDD2 with respect to temperature
PCA2117
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Automotive LCD driver for character displays
DDD
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—$
7DPEž&
External VLCD = 8 V.
(1) Driving mode 1:18, ffr = 80 Hz; frame inversion; no-load; display enabled.
(2) Driving mode 1:18, ffr = 80 Hz; frame inversion; no-load; display disabled.
Fig 54. Typical IDD(LCD) with respect to temperature
DDD
9/&'
9
7DPEž&
Conditions: VDD2 = 5 V; charge pump at VLCD = 2  VDD2; VLCD = 8 V; VLCDx[8:0] = 134h;
temperature compensation disabled.
Fig 55. Typical VLCD variation with respect to temperature
PCA2117
Product data sheet
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NXP Semiconductors
Automotive LCD driver for character displays
DDD
IIU
+]
7DPEž&
Conditions: frame frequency prescaler = 00111; 80 Hz typical.
Fig 56. Typical frame frequency variation with respect to temperature
DDD
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7PHDVPD[
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7DPEž&
Fig 57. Measurement temperature variation with respect to temperature
PCA2117
Product data sheet
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NXP Semiconductors
Automotive LCD driver for character displays
14. Dynamic characteristics
14.1 General timing characteristics
Table 51. General dynamic characteristics
VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk(int)
internal clock
frequency
on pin CLK; Tamb = 25 C;
FF[4:0] = 00111
61600
64000
66400
Hz
fclk(ext)
external clock
frequency
on pin CLK
36000
-
288000
Hz
tclk(H)
HIGH-level clock time external clock source used
5
-
-
s
tclk(L)
LOW-level clock time
5
-
-
s
14.2 I2C-bus timing characteristics
Table 52. I2C-bus timing characteristics
VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.[1]
Symbol
Parameter
fSCL
Conditions
Min
Typ
Max
Unit
SCL frequency
-
-
400
kHz
tBUF
bus free time between
a STOP and START
condition
1.3
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a
repeated START
condition
0.6
-
-
s
tVD;DAT
data valid time
[2]
-
-
0.9
s
tVD;ACK
data valid
acknowledge time
[3]
-
-
0.9
s
tLOW
LOW period of the
SCL clock
1.3
-
-
s
tHIGH
HIGH period of the
SCL clock
0.6
-
-
s
tf
fall time
of both SDA and SCL signals
-
-
0.3
s
of both SDA and SCL signals
tr
rise time
-
-
0.3
s
Cb
capacitive load for
each bus line
-
-
400
pF
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tw(spike)
spike pulse width
-
-
50
ns
[1]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS1 to VDD1.
[2]
tVD;DAT = minimum time for valid SDA output following SCL LOW.
[3]
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
PCA2117
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Automotive LCD driver for character displays
IFON
WFON+
WFON/
9''
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9''
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Fig 58. Driver timing waveforms
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Fig 59. I2C-bus timing diagram
PCA2117
Product data sheet
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Automotive LCD driver for character displays
14.3 SPI-bus timing characteristics
Table 53. SPI-bus characteristics
VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified. All
timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input
voltage swing of VSS1 to VDD1 (see Figure 60).
Symbol
Parameter
Conditions
Min
Max
Unit
Pin SCL
fclk(SCL)
SCL clock frequency
-
3.0
MHz
tSCL
SCL time
333
-
ns
tclk(H)
clock HIGH time
100
-
ns
tclk(L)
clock LOW time
150
-
ns
tr
rise time
for SCL signal
-
100
ns
tf
fall time
for SCL signal
-
100
ns
Pin CE
tsu(CE_N)
CE_N set-up time
30
-
ns
th(CE_N)
CE_N hold time
30
-
ns
trec(CE_N)
CE_N recovery time
30
-
ns
Pin SDI
tsu
set-up time
set-up time for SDI data
30
-
ns
th
hold time
hold time for SDI data
30
-
ns
td(R)SDO
SDO read delay time
CL = 100 pF
-
150
ns
tdis(SDO)
SDO disable time
[1]
-
50
ns
tt(SDI-SDO)
transition time from
SDI to SDO
to avoid bus conflict
0
-
ns
Pin SDO
[1]
No load value; bus is held up by bus capacitance; use RC time constant with application values.
PCA2117
Product data sheet
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NXP Semiconductors
Automotive LCD driver for character displays
&(
WVX&(B1
WUHF&(B1
WU
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WFON6&/
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6&/
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5:
6',6'$,1
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5$
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E
E
E
E
KLJK=
6'2
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WW6',6'2
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E
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Fig 60. SPI-bus timing
15. Test information
15.1 Quality information
This product has been qualified to the appropriate Automotive Electronics Council (AEC)
standard Q100 or Q101 and is suitable for use in automotive applications.
PCA2117
Product data sheet
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NXP Semiconductors
Automotive LCD driver for character displays
16. Bare die outline
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Fig 61. Bare die outline of PCA2117DUGx
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
89 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
Table 54. Dimensions of PCA2117DUGx
Original dimensions are in mm.
Unit (mm)
A
A1
A2
b
D
E
e
e1
L
max
-
0.018
-
-
-
-
-
-
-
nom
0.395
0.015
0.38
0.025
5.64
1.24
0.040
0.114
0.1
min
-
0.012
-
-
-
-
-
-
-
Table 55. Bump locations of PCA2117DUGx
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 61
Symbol
Pin Coordinates
X (µm)
X (µm)
Pin Coordinates
X (µm)
Pitch
Y (µm)
X (µm)
1
2711.3 509.0
-
119 2681.5
509.0
-
2666.3 509.0
45.0
120 2636.5
509.0
45.0
3
2621.3 509.0
45.0
121 2591.5
509.0
45.0
R14
4
2576.3 509.0
45.0
R3
122 2546.5
509.0
45.0
5
2531.3 509.0
45.0
123 2501.5
509.0
45.0
R15
6
2486.3 509.0
45.0
R2
124 2456.5
509.0
45.0
7
2441.3 509.0
45.0
125 2411.5
509.0
45.0
R16
8
2396.3 509.0
45.0
126 2366.5
509.0
45.0
9
2351.3 509.0
45.0
127 2321.5
509.0
45.0
VLCDIN
10
2242.7 509.0
108.6 R0
128 2276.5
509.0
45.0
11
2197.7 509.0
45.0
129 2231.5
509.0
45.0
12
2152.7 509.0
45.0
R17
130 2186.5
509.0
45.0
R4
R1
13
2107.7 509.0
45.0
131 2141.5
509.0
45.0
VLCDSENSE 14
2062.7 509.0
45.0
C99
132 2027.9
509.0
113.6
15
2017.7 509.0
45.0
C98
133 1987.9
509.0
40.0
16
1972.7 509.0
45.0
C97
134 1947.9
509.0
40.0
VLCDOUT
VSS2
Product data sheet
Symbol
2
R13
PCA2117
Y (µm)
Pitch
17
1927.7 509.0
45.0
C96
135 1907.9
509.0
40.0
18
1882.7 509.0
45.0
C95
136 1867.9
509.0
40.0
19
1837.7 509.0
45.0
C94
137 1827.9
509.0
40.0
20
1792.7 509.0
45.0
C93
138 1787.9
509.0
40.0
21
1747.7 509.0
45.0
C92
139 1747.9
509.0
40.0
22
1702.7 509.0
45.0
C91
140 1707.9
509.0
40.0
23
1657.7 509.0
45.0
C90
141 1667.9
509.0
40.0
24
1612.7 509.0
45.0
C89
142 1627.9
509.0
40.0
25
1567.7 509.0
45.0
C88
143 1587.9
509.0
40.0
26
1522.7 509.0
45.0
C87
144 1547.9
509.0
40.0
27
1477.7 509.0
45.0
C86
145 1507.9
509.0
40.0
28
1432.7 509.0
45.0
C85
146 1467.9
509.0
40.0
29
1387.7 509.0
45.0
C84
147 1427.9
509.0
40.0
30
1342.7 509.0
45.0
C83
148 1387.9
509.0
40.0
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
90 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
Table 55. Bump locations of PCA2117DUGx …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 61
Symbol
Pin Coordinates
X (µm)
VSS3
VSS1
X (µm)
Pin Coordinates
X (µm)
Y (µm)
Pitch
X (µm)
31
1297.7 509.0
45.0
C82
149 1347.9
509.0
40.0
32
1252.7 509.0
45.0
C81
150 1307.9
509.0
40.0
33
1207.7 509.0
45.0
C80
151 1267.9
509.0
40.0
34
1162.7 509.0
45.0
C79
152 1227.9
509.0
40.0
35
1117.7 509.0
45.0
C78
153 1187.9
509.0
40.0
36
1072.7 509.0
45.0
C77
154 1147.9
509.0
40.0
37
1027.7 509.0
45.0
C76
155 1107.9
509.0
40.0
38
982.7
45.0
C75
156 1067.9
509.0
40.0
509.0
39
937.7
509.0
45.0
C74
157 1027.9
509.0
40.0
40
892.7
509.0
45.0
C73
158 987.9
509.0
40.0
41
847.7
509.0
45.0
C72
159 947.9
509.0
40.0
42
802.7
509.0
45.0
C71
160 907.9
509.0
40.0
43
757.7
509.0
45.0
C70
161 867.9
509.0
40.0
44
712.7
509.0
45.0
C69
162 827.9
509.0
40.0
45
667.7
509.0
45.0
C68
163 787.9
509.0
40.0
46
622.7
509.0
45.0
C67
164 747.9
509.0
40.0
47
577.7
509.0
45.0
C66
165 707.9
509.0
40.0
532.7
509.0
45.0
C65
166 606.9
509.0
101.0
49
487.7
509.0
45.0
C64
167 566.9
509.0
40.0
T2
50
442.7
509.0
45.0
C63
168 526.9
509.0
40.0
51
397.7
509.0
45.0
C62
169 486.9
509.0
40.0
T4
52
352.7
509.0
45.0
C61
170 446.9
509.0
40.0
53
307.7
509.0
45.0
C60
171 406.9
509.0
40.0
54
262.7
509.0
45.0
C59
172 366.9
509.0
40.0
OSC
SA0
IFS
VDD1
Product data sheet
Symbol
48
T1
PCA2117
Y (µm)
Pitch
55
217.7
509.0
45.0
C58
173 326.9
509.0
40.0
56
172.7
509.0
45.0
C57
174 286.9
509.0
40.0
57
127.7
509.0
45.0
C56
175 246.9
509.0
40.0
58
82.7
509.0
45.0
C55
176 206.9
509.0
40.0
59
37.7
509.0
45.0
C54
177 166.9
509.0
40.0
60
7.3
509.0
45.0
C53
178 126.9
509.0
40.0
61
52.3
509.0
45.0
C52
179 86.9
509.0
40.0
62
97.3
509.0
45.0
C51
180 46.9
509.0
40.0
63
142.3
509.0
45.0
C50
181 6.9
509.0
40.0
64
187.3
509.0
45.0
C49
182 33.1
509.0
40.0
65
232.3
509.0
45.0
C48
183 73.1
509.0
40.0
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
91 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
Table 55. Bump locations of PCA2117DUGx …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 61
Symbol
Symbol
509.0
40.0
185 153.1
509.0
40.0
C45
186 193.1
509.0
40.0
45.0
C44
187 233.1
509.0
40.0
509.0
45.0
C43
188 273.1
509.0
40.0
509.0
45.0
C42
189 313.1
509.0
40.0
547.3
509.0
45.0
C41
190 353.1
509.0
40.0
73
592.3
509.0
45.0
C40
191 393.1
509.0
40.0
74
637.3
509.0
45.0
C39
192 433.1
509.0
40.0
75
682.3
509.0
45.0
C38
193 473.1
509.0
40.0
76
727.3
509.0
45.0
C37
194 513.1
509.0
40.0
77
772.3
509.0
45.0
C36
195 553.1
509.0
40.0
78
817.3
509.0
45.0
C35
196 593.1
509.0
40.0
79
862.3
509.0
45.0
C34
197 633.1
509.0
40.0
80
907.3
509.0
45.0
C33
198 673.1
509.0
40.0
PWROUT
81
952.3
509.0
45.0
C32
199 713.1
509.0
40.0
82
997.3
509.0
45.0
C31
200 753.1
509.0
40.0
PWRIN
83
1042.3
509.0
45.0
C30
201 793.1
509.0
40.0
84
1087.3
509.0
45.0
C29
202 894.1
509.0
101.0
85
1132.3
509.0
45.0
C28
203 934.1
509.0
40.0
86
1177.3
509.0
45.0
C27
204 974.1
509.0
40.0
87
1222.3
509.0
45.0
C26
205 1014.1 509.0
40.0
88
1267.3
509.0
45.0
C25
206 1054.1 509.0
40.0
89
1312.3
509.0
45.0
C24
207 1094.1 509.0
40.0
90
1357.3
509.0
45.0
C23
208 1134.1 509.0
40.0
91
1402.3
509.0
45.0
C22
209 1174.1 509.0
40.0
92
1447.3
509.0
45.0
C21
210 1214.1 509.0
40.0
93
1492.3
509.0
45.0
C20
211 1254.1 509.0
40.0
CE
CLK
RST
SDI/SDAIN
SDO
Y (µm)
X (µm)
X (µm)
66
277.3
509.0
45.0
C47
67
322.3
509.0
45.0
C46
68
367.3
509.0
45.0
69
412.3
509.0
70
457.3
71
502.3
72
Pitch
184 113.1
T3
X (µm)
Pin Coordinates
X (µm)
PD
Product data sheet
Pitch
Y (µm)
VDD2
PCA2117
Pin Coordinates
94
1537.3
509.0
45.0
C19
212 1294.1 509.0
40.0
95
1582.3
509.0
45.0
C18
213 1334.1 509.0
40.0
96
1627.3
509.0
45.0
C17
214 1374.1 509.0
40.0
97
1672.3
509.0
45.0
C16
215 1414.1 509.0
40.0
98
1717.3
509.0
45.0
C15
216 1454.1 509.0
40.0
99
1762.3
509.0
45.0
C14
217 1494.1 509.0
40.0
100 1807.3
509.0
45.0
C13
218 1534.1 509.0
40.0
101 1852.3
509.0
45.0
C12
219 1574.1 509.0
40.0
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
92 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
Table 55. Bump locations of PCA2117DUGx …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 61
Symbol
SCL
SDAOUT
R17
R7
R6
R5
Pin Coordinates
Pitch
Symbol
Pin Coordinates
X (µm)
Y (µm)
Pitch
X (µm)
Y (µm)
X (µm)
X (µm)
102 1897.3
509.0
45.0
C11
220 1614.1 509.0
40.0
103 1942.3
509.0
45.0
C10
221 1654.1 509.0
40.0
104 1987.3
509.0
45.0
C9
222 1694.1 509.0
40.0
105 2032.3
509.0
45.0
C8
223 1734.1 509.0
40.0
106 2077.3
509.0
45.0
C7
224 1774.1 509.0
40.0
107 2122.3
509.0
45.0
C6
225 1814.1 509.0
40.0
108 2167.3
509.0
45.0
C5
226 1854.1 509.0
40.0
109 2212.3
509.0
45.0
C4
227 1894.1 509.0
40.0
110 2320.9
509.0
108.6 C3
228 1934.1 509.0
40.0
111 2365.9
509.0
45.0
C2
229 1974.1 509.0
40.0
112 2410.9
509.0
45.0
C1
230 2014.1 509.0
40.0
113 2455.9
509.0
45.0
C0
231 2054.1 509.0
40.0
114 2500.9
509.0
45.0
R16
232 2160.2 509.0
106.1
115 2545.9
509.0
45.0
233 2205.2 509.0
45.0
116 2590.9
509.0
45.0
234 2250.2 509.0
45.0
117 2635.9
509.0
45.0
235 2295.2 509.0
45.0
236 2340.2 509.0
45.0
237 2385.2 509.0
45.0
238 2430.2 509.0
45.0
239 2475.2 509.0
45.0
240 2520.2 509.0
45.0
241 2565.2 509.0
45.0
242 2610.2 509.0
45.0
R8
118 2680.9
509.0
45.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
243 2655.2 509.0
45.0
-
-
-
-
-
244 2700.2 509.0
45.0
5()
R9
R10
R11
R12
6
5()
&
DDD
Fig 62. Alignment marks
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
93 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
Table 56. Alignment marking
All x/y coordinates represent the position of the REF point (see Figure 62) with respect to the center
(x/y = 0) of the chip; see Figure 61.
Symbol
Size (m)
X (m)
Y (m)
S1
90  90
2585.0
36.0
C1
90  90
2522.0
36
17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
94 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
18. Packing information
18.1 Packing information on the tray
-
$
+
%
$
$
[
;
.
)
GLH
(
GHWDLO;
'
\
\
[
*
)
(
&
2
1
/
0
6(&7,21$$
<
'LPHQVLRQVLQPP
GHWDLO<
DDD
Schematic drawing, not drawn to scale. Top side view. For dimensions, see Table 57. Tray has pockets on both, top side and
bottom side. The IC is stored with the active side up. To get the active side down, turn the tray.
Fig 63. Tray details of PCA2117DUGx
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
95 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
Table 57. Specification of 3 inch tray details
Tray details are shown in Figure 63. Nominal values without production tolerances.
Tray details
Dimensions
A
B
C
D
E
F
G
H
J
K
L
M
N
O
Unit
7.0
2.5
5.74
1.34
76.0
68.0
56.0
6.75
10.0
62.5
4.2
2.6
3.2
0.48
mm
Number of pockets
x direction
y direction
9
26
SLQ
DDD
The orientation of the IC in a pocket with active side up is indicated by the position of pin 1 with
respect to the chamfer on the upper left corner of the tray.
Fig 64. Die alignment in the tray
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
96 of 107
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCA2117
Product data sheet
19. Appendix
19.1 LCD character driver selection
Table 58.
Selection of LCD character drivers
Type name
Number of
1  24 2  12 -
120
A
1.8 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2113DU
1  24 2  12 -
120
D
1.8 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2113EU
1  24 2  12 -
120
E
1.8 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2113WU
1  24 2  12 -
120
W
1.8 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2116AU
1  24 2  24 4  12 -
A
2.5 to 6
2.5 to 6
3.5 to 9
65
Y
N
40 to 85
I2C /
Parallel
N
PCF2116CU
1  24 2  24 4  12 -
C
2.5 to 6
2.5 to 6
3.5 to 9
65
Y
N
40 to 85
I2C /
Parallel
N
PCF2119AU
1  32 2  16 -
160
A
1.5 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2119DU
1  32 2  16 -
160
D
1.5 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2119FU
1  32 2  16 -
160
F
1.5 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2119IU
1  32 2  16 -
160
I
1.5 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2119RU
1  32 2  16 -
160
R
1.5 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF2119SU
1  32 2  16 -
160
S
1.5 to 5.5 2.2 to 4
2.2 to 6.5 95
Y
Y
40 to 85
I2C /
Parallel
N
PCF21219DUGR 1  32 2  16 -
160
R
1.5 to 5.5 2.2 to 4
2.2 to 6.5 220
Y
Y
40 to 85
I2C /
Parallel
N
PCA2117DUGR
1  40 2  20 -
200
R
2.5 to 5.5 2.5 to 5.5 4 to 16
45 to 360[1] Y
Y
40 to 105 I2C / SPI
Y
PCA2117DUGS
1  40 2  20 -
Y
40 to 105
Y
S
VLCD (V)
2.5 to 5.5 2.5 to 5.5 4 to 16
ffr (Hz)
45 to
360[1]
VLCD (V) VLCD (V) Tamb (C)
charge
temp.
pump
comp
Y
Interface AECQ100
I2C
/ SPI
PCA2117
97 of 107
© NXP Semiconductors N.V. 2015. All rights reserved.
PCF2113AU
200
VDD2 (V)
Automotive LCD driver for character displays
Rev. 4 — 8 April 2015
All information provided in this document is subject to legal disclaimers.
Lines  Characters
Character VDD1 (V)
Icons set
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Software programmable.
NXP Semiconductors
PCA2117
Product data sheet
[1]
PCA2117
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Automotive LCD driver for character displays
Rev. 4 — 8 April 2015
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PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
20. Abbreviations
Table 59.
PCA2117
Product data sheet
Abbreviations
Acronym
Description
AEC
Automotive Electronics Council
CGRAM
Character Generator RAM
CGROM
Character Generator ROM
CRC
Cyclical Redundancy Check
DDRAM
Double Data Random Access Memory
COG
Chip-On-Glass
DC
Direct Current
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit bus
IC
Integrated Circuit
ITO
Indium Tin Oxide
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MSB
Most Significant Bit
MUX
Multiplexer
NC
Numeric Code
OTP
One Time Programmable
PCB
Printed-Circuit Board
RC
Resistance-Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
ROM
Read-Only Memory
SCL
Serial CLock line
SDA
Serial DAta line
SPI
Serial Peripheral Interface
XOR
EXclusive OR operator
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Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
99 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
21. References
[1]
AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2]
AN10439 — Wafer Level Chip Size Package
[3]
AN10706 — Handling bare die
[4]
AN10853 — ESD and EMC sensitivity of IC
[5]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[6]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[7]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[8]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[9]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] UM10204 — I2C-bus specification and user manual
[13] UM10569 — Store and transport requirements
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
100 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
22. Revision history
Table 60.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA2117 v.4
20150408
Product data sheet
-
PCA2117 v.3
Modifications:
•
Fixed typos
PCA2117 v.3
20140919
Product data sheet
-
PCA2117 v.2
PCA2117 v.2
20131113
Product data sheet
-
PCA2117 v.1
PCA2117 v.1
20130930
Product data sheet
-
-
PCA2117
Product data sheet
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Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
101 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
23. Legal information
23.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA2117
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
102 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
103 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
25. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin description of PCA2117DUGx . . . . . . . . . . .6
Command execution sequence . . . . . . . . . . . . .8
Commands of PCA2117 . . . . . . . . . . . . . . . . . .8
Register_update - Register update command
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .9
Initialize - Initialize command bit description . .10
Clear_reset_flag - Clear_reset_flag command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
OTP_refresh - OTP_refresh command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock_out_ctrl - CLK pin input/output switch
command bit description . . . . . . . . . . . . . . . . .10
Read_reg_select - select registers for readout
command bit description . . . . . . . . . . . . . . . . . 11
Read_status_reg - readout register command
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 11
RAM_ROM_config - display memory
configuration command bit description . . . . . . .13
Sel_mem_bank - RAM access configuration
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Set_mem_addr - memory address command
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read_data - data read bit description . . . . . . .15
Write_data - data write bit description . . . . . . .15
Clear_display - clear display bit description . . .16
Return_home - return home bit description . . .16
Entry_mode_set - entry mode bit description .17
Function_set - function set bit description . . . .18
Inversion_mode - inversion mode command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .18
Frame-frequency - frame frequency select
command bit description . . . . . . . . . . . . . . . . .19
Clock and frame frequency values . . . . . . . . .19
Display_control - Display control bit description .
20
Cursor_display_shift - cursor display shift bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Screen_config - screen configuration bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Display_config - display configuration bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Icon_config - icon display configuration bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Charge_pump_ctrl - charge pump control
command bit description . . . . . . . . . . . . . . . . .24
Set_VLCD_A and Set_VLCD_B - set VLCD
command bit description. . . . . . . . . . . . . . . . . .25
Temperature_ctrl - temperature measurement
control command bit description . . . . . . . . . . .26
TC_slope - VLCD temperature compensation
slope command bit description . . . . . . . . . . . .26
Reset state of PCA2117 . . . . . . . . . . . . . . . . .28
Temperature coefficients. . . . . . . . . . . . . . . . . .43
Calculation of the temperature compensating
PCA2117
Product data sheet
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
factor VT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bias levels as a function of multiplex rate . . . . 44
Icon to ICON-RAM mapping table . . . . . . . . . 60
Address space and wrap-around operation . . 62
Control byte description . . . . . . . . . . . . . . . . . 64
I2C slave address byte . . . . . . . . . . . . . . . . . . . 67
R/W-bit description. . . . . . . . . . . . . . . . . . . . . . 67
Example: Writing to RAM by I2C-bus . . . . . . . 68
Example: Reading from RAM by I2C-bus . . . . 69
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 71
Subaddress byte definition. . . . . . . . . . . . . . . . 72
Example: Writing to RAM by SPI-bus . . . . . . . 73
Example: Reading from RAM by SPI-bus . . . . 74
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 78
Static characteristics . . . . . . . . . . . . . . . . . . . . 79
General dynamic characteristics . . . . . . . . . . . 85
I2C-bus timing characteristics . . . . . . . . . . . . . 85
SPI-bus characteristics . . . . . . . . . . . . . . . . . . 87
Dimensions of PCA2117DUGx . . . . . . . . . . . 90
Bump locations of PCA2117DUGx . . . . . . . . . 90
Alignment marking . . . . . . . . . . . . . . . . . . . . . . 94
Specification of 3 inch tray details . . . . . . . . . . 96
Selection of LCD character drivers . . . . . . . . . 97
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 99
Revision history . . . . . . . . . . . . . . . . . . . . . . . 101
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
104 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
26. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Block diagram of PCA2117 . . . . . . . . . . . . . . . . . .4
Pinning diagram of PCA2117DUGx . . . . . . . . . . . .5
Example of the display shift . . . . . . . . . . . . . . . . .17
Example of a linefeed . . . . . . . . . . . . . . . . . . . . .21
Illustration of the display configuration bits . . . . .23
Recommended start-up sequence when using
the internal charge pump and the internal clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Recommended start-up sequence when using an
externally supplied VLCD and the internal clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Recommended start-up sequence when using
the internal charge pump and an external clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Recommended start-up sequence when using an
externally supplied VLCD and an external clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Recommended power-down sequence for
minimum power-down current when using the
internal charge pump and the internal clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Recommended power-down sequence when
using an externally supplied VLCD and the
internal clock signal . . . . . . . . . . . . . . . . . . . . . . .33
Recommended power-down sequence when
using the internal charge pump and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Recommended power-down sequence when
using an externally supplied VLCD and an
external clock signal . . . . . . . . . . . . . . . . . . . . . .34
Connecting PCA2117 with a 2 ´ 20 character
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Connecting PCA2117 with a 1 ´ 40 character
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Typical system configuration if using the
internal VLCD generation and I2C-bus . . . . . . . . .36
Typical system configuration if using the
external VLCD and SPI-bus . . . . . . . . . . . . . . . . .36
VLCD generation including temperature
compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .38
VLCD programming of PCA2117 (assuming
VT[8:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
VLCD with respect to Iload at VDD2 = 2.5 V . . . . . .40
VLCD with respect to Iload at VDD2 = 5 V . . . . . . . .40
VLCD with respect to Iload at VDD2 = 5 V . . . . . . . .41
Temperature measurement block with digital
temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .42
Temperature measurement delay . . . . . . . . . . . .42
Example of segmented temperature
coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .46
Waveforms for the 1:18 multiplex drive mode.
5 bias levels, character mode, frame inversion
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Waveforms for the 1:9 multiplex drive mode,
PCA2117
Product data sheet
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Fig 36.
Fig 37.
Fig 38.
Fig 39.
Fig 40.
Fig 41.
Fig 42.
Fig 43.
Fig 44.
Fig 45.
Fig 46.
Fig 47.
Fig 48.
Fig 49.
Fig 50.
Fig 51.
Fig 52.
Fig 53.
Fig 54.
Fig 55.
Fig 56.
Fig 57.
Fig 58.
Fig 59.
Fig 60.
Fig 61.
Fig 62.
Fig 63.
Fig 64.
5 bias levels, character mode, R8 to R15
and R17 open, frame inversion mode . . . . . . . . . 48
Waveforms for the 1:2 multiplex drive mode,
4 bias levels, icon mode, frame inversion mode . 49
Dataflow from CGROM, CGRAM and ICON-RAM
to the display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RAM/ROM access flowchart . . . . . . . . . . . . . . . . 51
Logic diagram of the CRC8 generator . . . . . . . . 52
Checksum generation . . . . . . . . . . . . . . . . . . . . . 52
Character set ‘R’ in CGROM. . . . . . . . . . . . . . . . 53
Character set ‘S’ in CGROM . . . . . . . . . . . . . . . . 54
Configuration of CGROM and CGRAM with
RR[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
User-defined euro currency sign . . . . . . . . . . . . . 57
Icon to row/column mapping . . . . . . . . . . . . . . . . 60
DDRAM to display mapping: no shift . . . . . . . . . 61
DDRAM to display mapping: right shift . . . . . . . . 61
DDRAM to display mapping: left shift . . . . . . . . . 61
Cursor and blink display examples . . . . . . . . . . . 63
Display example with icons . . . . . . . . . . . . . . . . . 63
Control byte format . . . . . . . . . . . . . . . . . . . . . . . 64
SDAOUT and SDAIN configuration. . . . . . . . . . . 65
Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Definition of START and STOP conditions . . . . . 66
System configuration. . . . . . . . . . . . . . . . . . . . . . 66
Acknowledgement on the I2C-bus. . . . . . . . . . . . 67
SPI data transfer overview . . . . . . . . . . . . . . . . . 72
Device protection diagram . . . . . . . . . . . . . . . . . 76
Typical IDD1 with respect to temperature . . . . . . . 82
Typical IDD2 with respect to temperature . . . . . . . 82
Typical IDD(LCD) with respect to temperature . . . . 83
Typical VLCD variation with respect to
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Typical frame frequency variation with respect
to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Measurement temperature variation with respect
to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Driver timing waveforms . . . . . . . . . . . . . . . . . . . 86
I2C-bus timing diagram . . . . . . . . . . . . . . . . . . . . 86
SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Bare die outline of PCA2117DUGx . . . . . . . . . . . 89
Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . . 93
Tray details of PCA2117DUGx . . . . . . . . . . . . . . 95
Die alignment in the tray . . . . . . . . . . . . . . . . . . . 96
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
105 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
27. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
7.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
8
Functional description . . . . . . . . . . . . . . . . . . . 8
8.1
Commands of PCA2117 . . . . . . . . . . . . . . . . . . 8
8.1.1
General control commands . . . . . . . . . . . . . . . 9
8.1.1.1
Command: Register_update. . . . . . . . . . . . . . . 9
8.1.1.2
Command: Initialize . . . . . . . . . . . . . . . . . . . . . 9
8.1.1.3
Command: Clear_reset_flag. . . . . . . . . . . . . . 10
8.1.1.4
Command: OTP_refresh . . . . . . . . . . . . . . . . 10
8.1.1.5
Command: Clock_out_ctrl . . . . . . . . . . . . . . . 10
8.1.1.6
Command: Read_reg_select . . . . . . . . . . . . . 11
8.1.1.7
Command: Read_status_reg . . . . . . . . . . . . . 11
8.1.1.8
Command: RAM_ROM_config . . . . . . . . . . . . 13
8.1.1.9
Command: Sel_mem_bank . . . . . . . . . . . . . . 14
8.1.1.10 Command: Set_mem_addr . . . . . . . . . . . . . . 14
8.1.1.11 Command: Read_data . . . . . . . . . . . . . . . . . . 15
8.1.1.12 Command: Write_data . . . . . . . . . . . . . . . . . . 15
8.1.2
Display control commands . . . . . . . . . . . . . . . 16
8.1.2.1
Command: Clear_display . . . . . . . . . . . . . . . . 16
8.1.2.2
Command: Return_home . . . . . . . . . . . . . . . . 16
8.1.2.3
Command: Entry_mode_set . . . . . . . . . . . . . . 17
8.1.2.4
Command: Function_set . . . . . . . . . . . . . . . . 18
8.1.2.5
Command: Inversion_mode . . . . . . . . . . . . . . 18
8.1.2.6
Command: Frame_frequency . . . . . . . . . . . . . 19
8.1.2.7
Command: Display_control. . . . . . . . . . . . . . . 20
8.1.2.8
Command: Cursor_display_shift. . . . . . . . . . . 21
8.1.2.9
Command: Screen_config . . . . . . . . . . . . . . . 22
8.1.2.10 Command: Display_config . . . . . . . . . . . . . . . 22
8.1.2.11 Command: Icon_config. . . . . . . . . . . . . . . . . . 23
8.1.3
Charge pump and LCD bias control
commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1.3.1
Command: Charge_pump_ctrl . . . . . . . . . . . . 24
8.1.3.2
Command: Set_VLCD_A and Set_VLCD_B . 25
8.1.4
Temperature compensation control
commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1.4.1
Command: Temperature_ctrl . . . . . . . . . . . . . 25
8.1.4.2
Command: TC_slope . . . . . . . . . . . . . . . . . . . 26
8.2
Start-up and shut-down. . . . . . . . . . . . . . . . . . 27
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.3.1
8.4.4
8.4.5
8.4.5.1
8.4.5.2
8.4.5.3
8.4.6
8.4.6.1
8.4.7
8.5
8.5.1
8.5.2
8.5.3
8.5.3.1
8.5.4
8.5.4.1
8.5.4.2
8.5.5
8.5.6
8.5.7
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.3
9.3.1
10
11
12
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset pin function . . . . . . . . . . . . . . . . . . . . .
Power-down pin function . . . . . . . . . . . . . . . .
Recommended start-up sequences . . . . . . . .
Recommended power-down sequences . . . .
Possible display configurations . . . . . . . . . . .
LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . .
VLCD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External VLCD supply . . . . . . . . . . . . . . . . . . .
Internal VLCD generation . . . . . . . . . . . . . . . .
VLCD programming . . . . . . . . . . . . . . . . . . . . .
VLCD drive capability . . . . . . . . . . . . . . . . . . .
Temperature measurement and temperature
compensation of VLCD . . . . . . . . . . . . . . . . . .
Temperature readout . . . . . . . . . . . . . . . . . . .
Temperature adjustment of the VLCD . . . . . . .
Example calculation of Voffset(LCD) . . . . . . . . .
LCD bias voltage generator . . . . . . . . . . . . . .
Electro-optical performance . . . . . . . . . . . . . .
LCD drive mode waveforms. . . . . . . . . . . . . .
Display data RAM and ROM . . . . . . . . . . . . .
RAM/ROM access . . . . . . . . . . . . . . . . . . . . .
Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGROM addressing. . . . . . . . . . . . . . . . . . . .
CGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGRAM addressing . . . . . . . . . . . . . . . . . . . .
User-defined characters and symbols . . . . . .
ICON-RAM. . . . . . . . . . . . . . . . . . . . . . . . . . .
DDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cursor control circuit . . . . . . . . . . . . . . . . . . .
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . .
Control byte and register selection . . . . . . . .
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
START and STOP conditions. . . . . . . . . . . . .
System configuration . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . .
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus slave address . . . . . . . . . . . . . . . . . .
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . .
SPI-bus data transfer . . . . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
27
29
29
29
32
35
37
37
37
37
37
39
41
41
42
44
44
45
46
49
51
51
52
55
55
57
57
59
60
63
64
64
64
65
65
66
66
67
67
67
68
71
72
76
76
78
continued >>
PCA2117
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
106 of 107
PCA2117
NXP Semiconductors
Automotive LCD driver for character displays
13
14
14.1
14.2
14.3
15
15.1
16
17
18
18.1
19
19.1
20
21
22
23
23.1
23.2
23.3
23.4
24
25
26
27
Static characteristics. . . . . . . . . . . . . . . . . . . . 79
Dynamic characteristics . . . . . . . . . . . . . . . . . 85
General timing characteristics . . . . . . . . . . . . 85
I2C-bus timing characteristics . . . . . . . . . . . . . 85
SPI-bus timing characteristics . . . . . . . . . . . . 87
Test information . . . . . . . . . . . . . . . . . . . . . . . . 88
Quality information . . . . . . . . . . . . . . . . . . . . . 88
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 89
Handling information. . . . . . . . . . . . . . . . . . . . 94
Packing information . . . . . . . . . . . . . . . . . . . . 95
Packing information on the tray . . . . . . . . . . . 95
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LCD character driver selection . . . . . . . . . . . . 97
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 99
References . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . . 101
Legal information. . . . . . . . . . . . . . . . . . . . . . 102
Data sheet status . . . . . . . . . . . . . . . . . . . . . 102
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 103
Contact information. . . . . . . . . . . . . . . . . . . . 103
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 April 2015
Document identifier: PCA2117
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