Data Sheet

TJA1145
High-speed CAN transceiver for partial networking
Rev. 2 — 18 April 2014
Product data sheet
1. General description
The TJA1145 is a high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is designed for high-speed CAN applications in the automotive industry,
providing differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller.
The TJA1145 features very low power consumption in Standby and Sleep modes and
supports ISO 11898-6 compliant CAN Partial Networking by means of a selective wake-up
function.
A dedicated implementation of the partial networking function has been embedded into
the TJA1145/FD variants TJA1145T/FD and TJA1145TK/FD (see Section 6.3.1 for further
details on CAN FD). This function is called ‘FD-passive’ and is the ability to ignore CAN
FD frames while waiting for a valid wake-up frame in Sleep/Standby mode. This additional
feature of partial networking is the perfect fit for networks that support both CAN FD and
standard CAN 2.0 communications. It allows normal CAN controllers that do not need to
communicate CAN FD messages to remain in partial networking Sleep/Standby mode
during CAN FD communication without generating bus errors.
Advanced power management regulates the supply throughout the node and supports
local and remote wake-up functionality. I/O levels are automatically adjusted to the I/O
levels of the controller, allowing the TJA1145 to interface directly with 3.3 V to 5 V
microcontrollers. An SPI interface is provided for transceiver control and for retrieving
status information. Bus connections are truly floating when power is off.
The TJA1145 implements the CAN physical layer as defined in the current ISO11898
standard (-2, -5 and -6). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
These features make the TJA1145 the ideal choice for high-speed CAN networks
containing nodes that are always connected to the battery supply line but, in order to
minimize current consumption, are only active when required by the application.
2. Features and benefits
2.1 General
 Fully compliant with the ISO 11898-2, ISO 11898-5 and ISO 11898-6 standards
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
 Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
 Autonomous bus biasing according to ISO 11898-6
 Optimized for in-vehicle high-speed CAN communication
 No ‘false’ wake-ups due to CAN FD frame detection in TJA1145/FD variants
2.2 Designed for automotive applications
 8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
 6 kV ESD protection, according to IEC 61000-4-2 on pins BAT and WAKE and on the
CAN bus pins
 CAN bus pins short-circuit proof to 58 V
 Battery and CAN bus pins protected against transients according to ISO 7637-3, test
pulses 1, 2a, 3a and 3b.
 Suitable for use in 12 V and 24 V systems
 Available in SO14 and leadless HVSON14 package (3 mm  4.5 mm) with improved
Automated Optical Inspection (AOI) capability
 Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.3 Advanced ECU power management system
 Very low-current Standby and Sleep modes, with full wake-up capability
 Entire node can be powered down via the inhibit output
 Remote wake-up capability via standard CAN wake-up pattern or via ISO 11898-6
compliant selective wake-up frame detection
 Local wake-up via the WAKE pin
 Wake-up source recognition
 Local and/or remote wake-up can be disabled to reduce current consumption
 Transceiver disengages from the bus when the battery supply is removed
 VIO input allows for direct interfacing with 3.3 V to 5 V microcontrollers
2.4 Protection and diagnosis






TJA1145
Product data sheet
16-, 24- or 32-bit SPI for configuration, control and diagnosis
Transmit Data (TXD) dominant time-out function with diagnosis
Overtemperature warning and shut-down
Undervoltage detection and recovery on pins VCC, VIO and BAT
Cold start diagnosis (via bits PO and NMS)
Advanced system and transceiver interrupt handling
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Rev. 2 — 18 April 2014
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TJA1145
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High-speed CAN transceiver for partial networking
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
TJA1145T
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
TJA1145T/FD
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
TJA1145TK
HVSON14
plastic thermal enhanced very thin small outline package; no leads;
14 terminals; body 3  4.5  0.85 mm
SOT1086-2
TJA1145TK/FD
HVSON14
plastic thermal enhanced very thin small outline package; no leads;
14 terminals; body 3  4.5  0.85 mm
SOT1086-2
4. Block diagram
BAT
RXD
TXD
VCC
VIO
3
5
10
INH
TJA1145
7
13
4
HS-CAN
1
12
INH
CANH
CANL
PARTIAL NETWORKING
CAN FD-passive(1)
WAKE
SCK
SDI
SDO
SCSN
9
WAKE-UP
8
11
SPI
6
14
2
GND
015aaa259
(1) TJA1145T/FD and TJA1145TK/FD only.
Fig 1.
TJA1145
Product data sheet
Block diagram
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Rev. 2 — 18 April 2014
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TJA1145
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High-speed CAN transceiver for partial networking
5. Pinning information
5.1 Pinning
TJA1145T/
TJA1145T/FD
TJA1145TK/
TJA1145TK/FD
terminal 1
index area
TXD
1
14 SCSN
TXD
1
14 SCSN
GND
2
13 CANH
GND
2
13 CANH
VCC
3
12 CANL
VCC
3
12 CANL
RXD
4
11 SDI
RXD
4
11 SDI
VIO
5
10 BAT
VIO
5
10 BAT
SDO
6
9
WAKE
SDO
6
9
WAKE
INH
7
8
SCK
INH
7
8
SCK
015aaa260
Fig 2.
015aaa261
Pin configuration diagram: SO14
Fig 3.
Pin configuration diagram: HVSON14
Transparent top view
5.2 Pin description
Table 2.
Symbol
Pin
Description
TXD
1
transmit data input
GND
2[1]
ground
VCC
3
5 V CAN transceiver supply voltage
RXD
4
receive data output; reads out data from the bus lines
VIO
5
supply voltage for I/O level adaptor
SDO
6
SPI data output
INH
7
inhibit output for switching external voltage regulators
SCK
8
SPI clock input
WAKE
9
local wake-up input
BAT
10
battery supply voltage
SDI
11
SPI data input
CANL
12
LOW-level CAN bus line
CANH
13
HIGH-level CAN bus line
SCSN
14
SPI chip select input
[1]
TJA1145
Product data sheet
Pin description
The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
device via the printed circuit board. For enhanced thermal and electrical performance, it is recommended to
solder the exposed die pad to GND.
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Rev. 2 — 18 April 2014
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TJA1145
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High-speed CAN transceiver for partial networking
6. Functional description
The TJA1145 is a stand-alone high-speed CAN transceiver containing a variety of fail-safe
and diagnostic features that offer enhanced system reliability and advanced power
management. The transceiver combines the functionality of the TJA1043 with
ISO 11898-6 compliant CAN partial networking and autonomous bus biasing.
6.1 System controller
The system controller manages register configuration and controls the internal functions
of the TJA1145. Detailed device status information is collected and made available to the
microcontroller.
6.1.1 Operating modes
The system controller contains a state machine that supports five operating modes:
Normal, Standby, Sleep, Overtemp and Off. The state transitions are illustrated in
Figure 4.
6.1.1.1
Normal mode
Normal mode is the active operating mode. In this mode, the TJA1145 is fully operational.
All device hardware is available and can be activated (see Table 3).
Normal mode can be selected from Standby or Sleep mode via an SPI command
(MC = 111).
6.1.1.2
Standby mode
Standby mode is the first-level power-saving mode of the TJA1145, featuring low current
consumption. The transceiver is unable to transmit or receive data in Standby mode, but
the INH pin remains active so voltage regulators controlled by this pin will be active.
If remote CAN wake-up is enabled (CWE = 1; see Table 27), the receiver monitors bus
activity for a wake-up request. The bus pins are biased to GND (via Ri(cm)) when the bus is
inactive and at approximately 2.5 V when there is activity on the bus (autonomous
biasing). CAN wake-up can occur via a standard wake-up pattern or via a selective
wake-up frame (selective wake-up is enabled when CPNC = PNCOK = 1; otherwise
standard wake-up is enabled).
Pin RXD is forced LOW when any enabled wake-up or interrupt event is detected (see
Section 6.6).
The TJA1145 switches to Standby mode:
• from Off mode if the battery voltage rises above the power-on detection threshold,
Vth(det)pon.
• from Overtemp mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp.
• from Sleep mode on the occurrence of a wake-up or interrupt event (see Section 6.6)
• from Normal or Sleep mode via an SPI command (MC = 100)
• from Normal mode if Sleep mode is selected via an SPI command (MC = 001) while a
wake-up event is pending or all wake-up sources are disabled
TJA1145
Product data sheet
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TJA1145
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High-speed CAN transceiver for partial networking
overtemperature event
NORMAL
OVERTEMP
MC = Sleep &
no wake-up pending &
wake-up enabled
MC = Normal
MC = Standby
MC = Normal
no overtemperature
event
MC = Standby OR
wake-up event
SLEEP
STANDBY
MC = Sleep &
no wake-up pending &
wake-up enabled
MC=Sleep &
(wake-up pending or
wake-up disabled)
from Normal
VCC or VIO undervoltage event
power-on
from Standby or Normal
VBAT undervoltage event
OFF
from any mode
015aaa262
Fig 4.
TJA1145 system controller state diagram
6.1.1.3
Sleep mode
Sleep mode is the second-level power saving mode of the TJA1145. In Sleep mode, the
transceiver behaves as in Standby Mode with the exception that pin INH is set to a
high-ohmic state. Voltage regulators controlled by this pin will be switched off, and the
current into pin BAT will be reduced to a minimum.
Any enabled wake-up or interrupt event, or an SPI command (provided a valid VIO voltage
is connected), will wake up the transceiver from Sleep mode.
Sleep mode can be selected from Normal or Standby mode via an SPI command
(MC = 001). The TJA1145 will switch to Sleep mode on receipt of this command, provided
there are no pending wake-up events and at least one regular wake-up source (CAN bus
or WAKE pin; see Section 6.6) is enabled. Any attempt to enter Sleep mode while one of
these conditions has not been met will cause the TJA1145 to switch to Standby mode; if
SPI failure detection is enabled (SPIFE = 1), pin RXD will be forced LOW to signal a
wake-up event.
TJA1145
Product data sheet
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TJA1145
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High-speed CAN transceiver for partial networking
The TJA1145 will also be forced to switch to Sleep mode if a VCC of VIO undervoltage
event is detected (VCC/VIO < VUVD(VCC)/VUVD(VIO) for longer than tdet(uv)(VCC)/tdet(uv)(VIO)). In
this event, all pending wake-up events will be cleared. CAN wake-up (CWE = 1) and local
wake-up via the WAKE pin (WPFE = WPRE = 1) are enabled in order to avoid a system
deadlock (see Section 6.11) and selective wake-up is disabled (CPNC = 0).
Status bit FSMS in the Main status register (Table 5) indicates whether a transition to
Sleep mode was selected via an SPI command (FSMS = 0) or was forced by an
undervoltage event on VCC or VIO (FSMS = 1). This bit can be read after the TJA1145
wakes up from Sleep mode to allow the settings of CWE, WPFE, WPRE and CPNC to be
re-adjusted if an undervoltage event forced the transition to Sleep mode (FSMS = 1).
6.1.1.4
Off mode
The TJA1145 will be in Off mode when the battery voltage is too low to supply the IC. This
is the default mode when the battery is first connected. The TJA1145 will switch to Off
mode from any mode if the battery voltage drops below the power-off threshold
(Vth(det)poff). In Off mode, the CAN pins and pin INH are in a high-ohmic state.
When the battery supply voltage rises above the power-on threshold (Vth(det)pon), the
TJA1145 starts to boot up, triggering an initialization procedure. The TJA1145 will switch
to Standby mode after tstartup.
6.1.1.5
Overtemp mode
Overtemp mode is provided to prevent TJA1145 being damaged by excessive
temperatures. The TJA1145 switches immediately to Overtemp mode from Normal mode
when the global chip temperature rises above the overtemperature protection activation
threshold, Tth(act)otp.
To help prevent the loss of data due to overheating, the TJA1145 issues a warning when
the IC temperature rises above the overtemperature warning threshold (Tth(warn)otp). When
this happens, status bit OTWS is set and an overtemperature interrupt is generated
(OTW = 1), if enabled (OTWE = 1).
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD.
The TJA1145 exits Overtemp mode:
• and switches to Standby mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
• if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
TJA1145
Product data sheet
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Rev. 2 — 18 April 2014
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TJA1145
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High-speed CAN transceiver for partial networking
6.1.1.6
Table 3.
Hardware characterization for the TJA1145 operating modes
Hardware characterization by functional block
Block
Operating mode
Off
Standby
Normal
Sleep
Overtemp
SPI
disabled
active
active
active if VIO supplied[1]
disabled
INH
high-ohmic
VBAT level
VBAT level
high-ohmic
VBAT level
CAN
off
Offline
Active/ Offline/ Listen-only
(determined by bits CMC;
see Table 6)
Offline
off
RXD
VIO level
VIO level/LOW if
wake-up event detected
CAN bit stream if
VIO level/LOW if
VIO level/LOW if
CMC = 01/10/11; otherwise wake-up event detected wake-up pending
same as Standby/Sleep
[1]
SPI speed is limited in Sleep mode (see Table 40).
6.1.2 System control registers
The operating mode is selected via bits MC in the Mode control register. The Mode control
register is accessed via SPI address 0x01 (see Section 6.12).
Table 4.
Bit
Mode control register (address 01h)
Symbol
Access Value
7:3
reserved
R
2:0
MC
R/W
Description
mode control:
001
Sleep mode
100
Standby mode
111
Normal mode
The Main status register can be accessed to monitor the status of the overtemperature
warning flag and to determine whether the TJA1145 has entered Normal mode after initial
power-up. Bit FSMS indicates whether the most recent transition to Sleep mode was
triggered by an undervoltage event or by an SPI command.
Table 5.
Bit
Symbol
Access Value
Description
7
FSMS
R
Sleep mode transition status:
6
5
4:0
TJA1145
Product data sheet
Main status register (address 03h)
OTWS
NMS
reserved
0
transition to Sleep mode triggered by an SPI command
1
an undervoltage on VCC and/or VIO forced a transition to
Sleep mode
R
overtemperature warning status:
0
IC temperature below overtemperature warning threshold
1
IC temperature above overtemperature warning threshold
R
R
Normal mode status:
0
TJA1145 has entered Normal mode (after power-up)
1
TJA1145 has powered up but has not yet switched to
Normal mode
-
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TJA1145
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High-speed CAN transceiver for partial networking
6.2 High-speed CAN transceiver
The integrated high-speed CAN transceiver is designed for active communication at bit
rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol
controller. The transceiver is ISO 11898-2, ISO 11898-5 and ISO 11898-6 compliant
(defining high-speed CAN with selective wake-up functionality and autonomous bus
biasing). The CAN transmitter is supplied via pin VCC while the CAN receiver is supplied
via pin BAT. The TJA1145 includes additional timing parameters on loop delay symmetry
to ensure reliable communication in fast phase at data rates up to 2 Mbit/s, as used in
CAN FD networks.
The CAN transceiver supports autonomous CAN biasing as defined in ISO 11898-6,
which helps to minimize RF emissions. CANH and CANL are always biased to 2.5 V when
the transceiver is in Active or Listen-only modes (CMC = 01/10/11).
Autonomous biasing is active in CAN Offline mode - to 2.5 V if there is activity on the bus
(CAN Offline Bias mode) and to GND if there is no activity on the bus for t > tto(silence)
(CAN Offline mode).
This is useful when the node is disabled due to a malfunction in the microcontroller or
when CAN partial networking is enabled. The TJA1145 ensures that the CAN bus is
correctly biased to avoid disturbances to communications. The autonomous CAN bias
voltage is derived directly from VBAT.
6.2.1 CAN operating modes
The integrated CAN transceiver supports four operating modes: Active, Listen-only,
Offline and Offline Bias (see Figure 5). The CAN transceiver operating mode depends on
the TJA1145 operating mode and on the setting of bits CMC in the CAN control register
(Table 6).
When the TJA1145 is in Normal mode, the CAN transceiver operating mode (Offline,
Active or Listen-only) can be selected via bits CMC in the CAN control register (Table 6).
When the TJA1145 is in Standby or Sleep modes, the transceiver is forced to Offline or
Offline Bias mode (depending on bus activity).
6.2.1.1
CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
CAN Active mode is selected when CMC = 01 or 10. When CMC = 01, VCC undervoltage
detection is enabled and the transceiver will switch to CAN Offline or CAN Offline Bias
mode when the voltage on VCC drops below the 90 % threshold. When CMC = 10, VCC
undervoltage detection is disabled. The transmitter will remain active until the TJA1145 is
forced into Sleep mode by the VCC undervoltage event; the transceiver will then switch to
CAN Offline or CAN Offline Bias mode.
The CAN transceiver is in Active mode when:
• the TJA1145 is in Normal mode (MC = 111) and the CAN transceiver has been
enabled by setting bits CMC in the CAN control register to 01 or 10 (see Table 6) and:
TJA1145
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TJA1145
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High-speed CAN transceiver for partial networking
– if CMC = 01, the voltage on pin VCC is above the VCC undervoltage detection
threshold (Vuvd(VCC))
If pin TXD is held LOW (e.g. by a short-circuit to GND) when CAN Active mode is selected
via bits CMC, the transceiver will not enter CAN Active mode but will switch to or remain in
CAN Listen-only mode. It will remain in Listen-only mode until pin TXD goes HIGH in
order to prevent a hardware and/or software application failure from driving the bus lines
to an unwanted dominant state.
In CAN Active mode, the CAN bias voltage is derived from VCC.
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(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode if pin
TXD is held LOW (e.g. by a short-circuit to GND)
Fig 5.
CAN transceiver state machine
TJA1145
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TJA1145
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High-speed CAN transceiver for partial networking
The application can determine whether the CAN transceiver is ready to transmit/receive
data or is disabled by reading the CAN Transceiver Status (CTS) bit in the Transceiver
Status Register (Table 7).
6.2.1.2
CAN Listen-only mode
CAN Listen-only mode allows the TJA1145 to monitor bus activity while the transceiver is
inactive, without influencing bus levels. This facility could be used by development tools
that need to listen to the bus but do not need to transmit or receive data or for
software-driven selective wake-up. Dedicated microcontrollers could be used for selective
wake-up, providing an embedded low-power CAN engine designed to monitor the bus for
potential wake-up events.
In Listen-only mode the CAN transmitter is disabled, reducing current consumption. The
CAN receiver and CAN biasing remain active.
The CAN transceiver is in Listen-only mode when:
• the TJA1145 is in Normal mode and CMC = 11
The CAN transceiver will not leave Listen-only mode while TXD is LOW or CAN Active
mode is selected with CMC = 01 while the voltage on V1 is below the 90 % undervoltage
threshold.
6.2.1.3
CAN Offline and Offline Bias modes
In CAN Offline mode, the transceiver monitors the CAN bus for a wake-up event, provided
CAN wake-up detection is enabled (CWE = 1). CANH and CANL are biased to GND.
CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the CAN
bus is biased to 2.5 V. This mode is activated automatically when activity is detected on
the CAN bus while the transceiver is in CAN Offline mode. The transceiver will return to
CAN Offline mode if the CAN bus is silent (no CAN bus edges) for longer than tto(silence).
The CAN transceiver switches to CAN Offline mode from CAN Active mode or CAN
Listen-only mode if:
• the TJA1145 switches to Standby or Sleep mode OR
• the TJA1145 is in Normal mode and CMC = 00
provided the CAN-bus has been inactive for at least tto(silence). If the CAN-bus has been
inactive for less than tto(silence), the CAN transceiver switches first to CAN Offline Bias
mode and then to CAN Offline mode once the bus has been silent for tto(silence).
The CAN transceiver switches to CAN Offline/Offline Bias mode from CAN Active mode if
CMC = 01 and the voltage on VCC drops below the 90 % undervoltage threshold or if
CMC = 10 and the TJA1145 switches to Sleep mode in response to a VCC undervoltage
event.
The CAN transceiver switches to CAN Offline mode:
• from CAN Offline Bias mode if no activity is detected on the bus (no CAN edges) for
t > tto(silence) OR
• when the TJA1145 switches from Off or Overtemp mode to Standby mode
The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:
TJA1145
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TJA1145
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High-speed CAN transceiver for partial networking
• a standard wake-up pattern (according to ISO11898-5/-6) is detected on the CAN bus
OR
• the CAN transceiver is in Normal mode, CMC = 01 and VCC < 90 %
6.2.1.4
CAN Off mode
The CAN transceiver is switched off completely with the bus lines floating when:
• the TJA1145 switches to Off or Overtemp mode OR
• VBAT falls below the CAN receiver undervoltage detection threshold, Vuvd(CAN)
It will be switched on again on entering CAN Offline mode when VBAT rises above the
undervoltage recovery threshold (Vuvr(CAN)) and the CAN transceiver is no longer in
Off/Overtemp mode. CAN Off mode prevents reverse currents flowing from the bus when
the battery supply to the CAN transceiver is lost.
6.2.2 CAN standard wake-up (partial networking not enabled)
If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), but
CAN selective wake-up is disabled (CPNC = 0 or PNCOK = 0), the TJA1145 will monitor
the bus for a standard wake-up pattern.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN bus within the wake-up time-out time (tto(wake)) to pass the
wake-up filter and trigger a wake-up event (see Figure 6; note that additional pulses may
occur between the recessive/dominant phases). The recessive and dominant phases
must last at least twake(busrec) and twake(busdom), respectively.
When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the
Transceiver event status register is set (see Table 24) and pin RXD is driven LOW. If the
TJA1145 was in Sleep mode when the wake-up event was detected, it will switch pin INH
to VBAT to activate external voltage regulators (e.g. for supplying VCC and VIO) and enter
Standby mode.
dominant
tdom ≥ twake(busdom)
recessive
dominant
trec ≥ twake(busrec)
tdom ≥ twake(busdom)
twake < tto(wake)
CAN wake-up
015aaa267
Fig 6.
CAN wake-up timing
TJA1145
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6.2.3 CAN control and Transceiver status registers
Table 6.
Bit
Symbol
Access
Value
7
reserved
R
-
6
CFDC
R/W
5
4
CPNC
0
CAN FD tolerance disabled
1
CAN FD tolerance enabled
CAN partial networking configuration registers:
0
partial networking register configuration invalid
(wake-up via standard wake-up pattern only)
1
partial networking registers configured successfully
R/W
reserved
R
CMC
R/W
Description
CAN FD tolerance (TJA1145T/FD and
TJA1145TK/FD only; otherwise ignored)
R/W
1:0
CAN selective wake-up; when enabled, node is part
of a partial network:
0
disable CAN selective wake-up
1
enable CAN selective wake-up
CAN transceiver operating mode selection (available
when TJA1145 is in Normal mode; MC = 111):
00
Offline mode
01
Active mode (when the TJA1145 is in Normal
mode); VCC 90 % undervoltage detection active
10
Active mode (when the TJA1145 is in Normal
mode); VCC undervoltage detection inactive;
TJA1145 switches from Normal to Off mode when
VBAT < Vuvd(CAN)
11
Listen-only mode
Transceiver status register (address 22h)
Bit
Symbol
Access
Value
Description
7
CTS
R
0
CAN transceiver not in Active mode
1
CAN transceiver in Active mode
0
no CAN partial networking error detected
(PNFDE = 0 AND PNCOK = 1)
1
CAN partial networking error detected (PNFDE = 1
OR PNCOK = 0)
0
CAN partial networking configuration error detected
(PNCOK = 0)
1
CAN partial networking configuration OK
(PNCOK = 1)
0
CAN partial networking oscillator not running at target
frequency
1
CAN partial networking oscillator running at target
frequency
0
CAN bus active (communication detected on bus)
1
CAN bus inactive (for longer than tto(silence))
6
5
4
3
Product data sheet
PNCOK
3:2
Table 7.
TJA1145
CAN control register (address 20h)
CPNERR
CPNS
COSCS
CBSS
R
R
R
R
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Table 7.
Bit
Symbol
Access
Value
2
reserved
R
-
1
VCS
R
0
VCC is above the undervoltage detection threshold
(Vuvd(VCC))
1
VCC is below the undervoltage detection threshold
(Vuvd(VCC))
0
no TXD dominant time-out event detected
1
CAN transmitter disabled due to a TXD dominant
time-out event
0
TJA1145
Product data sheet
Transceiver status register (address 22h) …continued
CFS
R
Description
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6.3 CAN partial networking
Partial networking allows nodes in a CAN network to be selectively activated in response
to dedicated wake-up frames (WUF). Only nodes that are functionally required are active
on the bus while the other nodes remain in a low-power mode until needed.
If both CAN wake-up (CWE = 1) and CAN selective wake-up (CPNC = 1) are enabled,
and the partial networking registers are configured correctly (PNCOK = 1), the transceiver
monitors the bus for dedicated CAN wake-up frames.
A wake-up frame is a CAN frame according to ISO11898-1, consisting of an identifier field
(ID), a Data Length Code (DLC), a data field and a Cyclic Redundancy Check (CRC) code
including the CRC delimiter.
The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via
bit IDE in the Frame control register (Table 17).
A valid WUF identifier is defined and stored in the ID registers (Table 9 to Table 12). An ID
mask can be defined to allow a group of identifiers to be recognized as valid by an
individual node. The identifier mask is defined in the mask registers (Table 13 to
Table 16), where a 1 means ‘don’t care’.
In the example illustrated in Figure 7, based on the standard frame format, the 11-bit
identifier is defined as 0x1A0. The identifier is stored in ID registers 2 and 3 (Table 11 and
Table 12). The three least significant bits of the ID mask (bits 2 to 4 of Mask register 2;
Table 15) are ‘don’t care’. This means that any of eight different identifiers will be
recognized as valid in the received WUF (from 0x1A0 to 0x1A7).
TJA1145 SPI Settings
11-bit Identifier field:
0x1A0 stored in ID
registers 2 and 3
ID mask:
0x007 stored in Mask
registers 2 and 3
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
x
x
x
Valid Wake-Up Identifiers: 0x1A0 to 0x1A7
0
0
1
015aaa364
Fig 7.
Evaluating the ID field in a selective wake-up frame
The data field indicates which nodes are to be woken up. Groups of nodes can be
pre-defined and associated with bits in a data mask. By comparing the incoming data field
with the data mask, multiple groups of nodes can be woken up by a single wake-up
message.
The data length code (bits DLC in the Frame control register; Table 17) determines the
number of data bytes (between 0 and 8) expected in the data field of a CAN wake-up
frame. If one or more data bytes are expected (DLC  0000), at least one bit in the data
field of the received wake-up frame must be set to 1 and at least one equivalent bit in the
associated data mask register in the transceiver (see Table 18) must also be set to 1 for a
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successful wake-up. Each matching pair of 1s indicates a group of nodes to be activated
(since the data field is up to 8 byes long, up to 64 groups of nodes can be defined).
If DLC = 0000, a node will wake up if the WUF contains a valid identifier and the received
data length code is 0000, regardless of the values stored in the data mask. If DLC  0000
and all data mask bits are set to 0, the device cannot be woken up via the CAN bus (note
that all data mask bits are set to 1 by default; see Table 36). If a WUF contains a valid ID
but the DLCs (in the Frame control register and in the WUF) don’t match, the data field is
ignored and no nodes are woken up.
In the example illustrated in Figure 8, the data field consists of a single byte (DLC = 1).
This means that the data field in the incoming wake-up frame is evaluated against data
mask 7 (stored at address 6Fh; see Table 18 and Figure 9). Data mask 7 is defined as
10101000 in the example. This means that up to three groups of nodes could be woken
up (group1, 3 and 5) if the respective bits in the data frame are also set to 1.
The received message shown in Figure 8 could, potentially, wake up four groups of
nodes: groups 2, 3, 4 and 5. Two matches are found (groups 3 and 5) when the message
data bits are compared with the configured data mask (DM7).
DLC
stored
values
received
message
0
0
0
Data mask 7
0
0
0
1
1
0
1
0
1
0
0
0
Groups:
1
2
3
4
5
6
7
8
1
0
1
1
1
1
0
0
0
015aaa365
Fig 8.
Evaluating the Data field in a selective wake-up frame
Optionally, the data length code and the data field can be excluded from the evaluation of
the wake-up frame. If bit PNDM = 0, only the identifier field is evaluated to determine if the
frame contains a valid wake-up message. If PNDM = 1 (the default value), the data field is
included as part of the wake-up filtering.
When PNDM = 0, a valid wake-up message is detected and a wake-up event is captured
(and CW is set to 1) when:
• the identifier field in the received wake-up frame matches the pattern in the ID
registers after filtering AND
• the CRC field in the received frame (including a recessive CRC delimiter) was
received without error
When PNDM = 1, a valid wake-up message is detected when:
• the identifier field in the received wake-up frame matches the pattern in the ID
registers after filtering AND
• the frame is not a Remote frame AND
• the data length code in the received message matches the configured data length
code (bits DLC) AND
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• if the data length code is greater than 0, at least one bit in the data field of the
received frame is set and the corresponding bit in the associated data mask register is
also set AND
• the CRC field in the received frame (including a recessive CRC delimiter) was
received without error
If the TJA1145 receives a CAN message containing errors (e.g. a ‘stuffing’ error) that are
received in advance of the ACK field, an internal error counter is incremented. If a CAN
message is received without any errors appearing in front of the ACK field, the counter is
decremented. Data received after the CRC delimiter and before the next SOF is ignored
by the partial networking module. If the counter overflows (counter > 31), a frame detect
error is captured (PNFDE = 1) and the device wakes up; the counter is reset to zero when
the bias is switched off and partial networking is re-enabled.
Partial networking is assumed to be configured correctly when PNCOK is set to 1 by the
application software. The TJA1145 clears PNCOK after a write access to any of the CAN
partial networking configuration registers (see Section 6.3.2).
If selective wake-up is disabled (CPNC = 0) or partial networking is not configured
correctly (PNCOK = 0), and the CAN transceiver is in Offline mode with wake-up enabled
(CWE = 1), then any valid wake-up pattern (according to ISO 11898-5/-6) will trigger a
wake-up event.
If the CAN transceiver is not in Offline mode (CMC  00) or CAN wake-up is disabled
(CWE = 0), all wake-up patterns on the bus will be ignored.
6.3.1 CAN FD frames
CAN FD stands for ‘CAN with Flexible Data-Rate’. It is based on the CAN protocol as
specified in ISO 11898-1. It still uses the CAN bus arbitration method. However, it
increases the bit-rate by switching to a shorter bit time at the end of the arbitration process
and returns to the longer bit time at the CRC Delimiter, before the receivers transmit their
acknowledge bits. The effective data-rate is increased by allowing longer data fields. CAN
uses four bits for the data length code, allowing for 16 different codes. However, only the
first nine values are used to define the data field length (between 0 and 8 bytes; DLC
values from of 9 to 15 all indicate an 8-byte data field). In CAN FD, DLC codes 9 to 15 are
used to signify longer data fields.
CAN FD is being gradually introduced into automotive market. In time, all CAN controllers
will be required to comply with the new standard (enabling ‘FD-active’ nodes) or at least to
tolerate CAN FD communication (enabling ‘FD-passive’ nodes). The TJA1145T/FD and
TJA1145TK/FD enable FD-passive nodes by means of a dedicated implementation of the
partial networking protocol.
The TJA1145/FD variants can be configured to recognize CAN FD frames as valid frames.
When CFDC = 1, the error counter is decremented every time the control field of a CAN
FD frame is received. The TJA1145/FD remains in Sleep mode (CAN FD-passive) with
partial networking enabled. CAN FD frames are never recognized as valid wake-up
frames, even if PNDM = 0 and the frame contains a valid ID. After receiving the control
field of a CAN FD frame, the TJA1145/FD ignores further bus signals until idle is again
detected.
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CAN FD frames are interpreted as frames with errors by the partial networking module in
the TJA1145T and TJA1145TK and in the TJA1145/FD variants when CFDC = 0. So the
error counter is incremented when a CAN FD frame is received. Bit PNFDE is set to 1 and
the device wakes up if the ratio of CAN FD frames to valid CAN frames exceeds the
threshold that triggers error counter overflow.
6.3.2 CAN partial networking configuration registers
Dedicated registers are provided for configuring CAN partial networking.
Table 8.
Bit
Data rate register (address 26h)
Symbol
-
reserved
R
2:0
CDR
R/W
Description
CAN data rate selection:
000
50 kbit/s
001
100 kbit/s
010
125 kbit/s
011
250 kbit/s
100
reserved (intended for future use; currently
selects 500 kbit/s)
101
500 kbit/s
110
reserved (intended for future use; currently
selects 500 kbit/s)
111
1000 kbit/s
ID register 0 (address 27h)
Bit
Symbol
Access
Value
Description
7:0
ID07:ID00
R/W
-
bits ID07 to ID00 of the extended frame format
Table 10.
ID register 1 (address 28h)
Bit
Symbol
Access
Value
Description
7:0
ID15:ID08
R/W
-
bits ID15 to ID08 of the extended frame format
Table 11.
ID register 2 (address 29h)
Bit
Symbol
Access
Value
Description
7:2
ID23:ID18
R/W
-
bits ID23 to ID18 of the extended frame format
bits ID05 to ID00 of the standard frame format
1:0
ID17:ID16
R/W
-
bits ID17 to ID16 of the extended frame format
Table 12.
Product data sheet
Value
7:3
Table 9.
TJA1145
Access
ID register 3 (address 2Ah)
Bit
Symbol
Access
Value
7:5
reserved
R
-
4:0
ID28:ID24
R/W
-
Description
bits ID28 to ID24 of the extended frame format
bits ID10 to ID06 of the standard frame format
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Table 13.
Bit
Symbol
Access
Value
Description
7:0
M07:M00
R/W
-
mask bits ID07 to ID00 of the extended frame format
Table 14.
Symbol
Access
Value
Description
7:0
M15:M08
R/W
-
mask bits ID15 to ID08 of the extended frame format
Mask register 2 (address 2Dh)
Bit
Symbol
Access
Value
Description
7:2
M23:M18
R/W
-
mask bits ID23 to ID18 of the extended frame format
mask bits ID05 to ID00 of the standard frame format
1:0
M17:M16
R/W
-
mask bits ID17 to ID16 of the extended frame format
Table 16.
Mask register 3 (address 2Eh)
Bit
Symbol
Access
7:5
reserved
R
4:0
M28:M24
R/W
Table 17.
Value
Description
-
mask bits ID28 to ID24 of the extended frame format
mask. bits ID10 to ID06 of the standard frame format
Frame control register (address 2Fh)
Bit
Symbol
Access
Value
Description
7
IDE
R/W
-
identifier format:
6
Product data sheet
Mask register 1 (address 2Ch)
Bit
Table 15.
TJA1145
Mask register 0 (address 2Bh)
PNDM
R/W
5:4
reserved
R
3:0
DLC
R/W
0
standard frame format (11-bit)
1
extended frame format (29-bit)
-
partial networking data mask:
0
data length code and data field are ‘don’t care’ for
wake-up
1
data length code and data field are evaluated at
wake-up
number of data bytes expected in a CAN frame:
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001 to
1111
tolerated, 8 bytes expected; DM0 ignored
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Table 18.
Data mask registers (addresses 68h to 6Fh)
Addr.
Bit
Symbol
Access
Value
Description
68h
7:0
DM0
R/W
-
data mask 0 configuration
69h
7:0
DM1
R/W
-
data mask 1 configuration
6Ah
7:0
DM2
R/W
-
data mask 2 configuration
6Bh
7:0
DM3
R/W
-
data mask 3 configuration
6Ch
7:0
DM4
R/W
-
data mask 4 configuration
6Dh
7:0
DM5
R/W
-
data mask 5 configuration
6Eh
7:0
DM6
R/W
-
data mask 6 configuration
6Fh
7:0
DM7
R/W
-
data mask 7 configuration
DLC > 8
00h
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DLC = 8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM2
DM3
DM4
DM5
DM6
DM7
DM3
DM4
DM5
DM6
DM7
DM4
DM5
DM6
DM7
DM5
DM6
DM7
DM6
DM7
DLC = 7
DLC = 6
DLC = 5
DLC = 4
DLC = 3
DLC = 2
DLC = 1
DM7
015aaa280
Fig 9.
Data mask register usage for different values of DLC
6.4 Fail-safe features
6.4.1 TXD dominant time-out
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in Active Mode. If the LOW state on pin TXD persists for longer than the
TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
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When the TXD dominant time-out time is exceeded, a CAN failure interrupt is generated
(CF = 1; see Table 24), if enabled (CFE = 1; see Table 27). In addition, the status of the
TXD dominant time-out can be read via the CFS bit in the Transceiver status register
(Table 7) and bit CTS is set to 0.
6.4.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards VIO to ensure a safe defined recessive driver
state in case the pin is left floating.
6.4.3 VCC undervoltage event
An enabled CAN failure interrupt is generated (CF = 1) when the CAN transceiver supply
voltage on VCC falls below the undervoltage detection threshold (VUVD(VCC)), provided
CMC = 01. In addition, status bit VCS is set to 1.
6.4.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
6.5 Local wake-up via WAKE pin
Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture
enable register (see Table 28). A wake-up event is triggered by a LOW-to-HIGH (if
WPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This
arrangement allows for maximum flexibility when designing a local wake-up circuit. In
applications that don’t make use of the local wake-up facility, local wake-up should be
disabled and the WAKE pin connected to GND to ensure optimal EMI performance.
Table 19.
WAKE status register (address 4Bh)
Bit
Symbol
Access
Value
7:2
reserved
R
-
1
WPVS
R
0
reserved
R
Description
WAKE pin status:
0
voltage on WAKE pin below switching threshold (Vth(sw))
1
voltage on WAKE pin above switching threshold (Vth(sw))
-
While the TJA1145 is in Normal mode, the status of the voltage on pin WAKE can always
be read via bit WPVS. Otherwise, WPVS is only valid if local wake-up is enabled
(WPRE = 1 and/or WPFE = 1).
6.6 Wake-up and interrupt event diagnosis via pin RXD
Wake-up and interrupt event diagnosis in the TJA1145 is intended to provide the
microcontroller with information on the status of a range of features and functions. This
information is stored in the event status registers (Table 23 to Table 25) and is signaled on
pin RXD pin, if enabled.
A distinction is made between regular wake-up events and interrupt events (at least one
regular wake-up source must be enabled to allow the TJA1145 to switch to Sleep mode;
see Section 6.1.1.3).
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Table 20.
Regular wake-up events
Symbol
Event
Power-on Description
CW
CAN wake-up
disabled
a CAN wake-up event was detected while the
transceiver was in CAN Offline mode.
WPR
rising edge on WAKE
pin
disabled
a rising-edge wake-up was detected on pin WAKE
WPF
falling edge on WAKE disabled
pin
a falling-edge wake-up was detected on pin WAKE
Table 21.
Interrupt events
Symbol
Event
Power-on Description
PO
power-on
always
enabled
the TJA1145 has exited Off mode (after battery
power has been restored/connected)
OTW
overtemperature
warning
disabled
the IC temperature has exceeded the
overtemperature warning threshold (only detected
in Normal mode)
SPIF
SPI failure
disabled
SPI clock count error (only 16-, 24- and 32-bit
commands are valid), illegal MC code or
attempted write access to locked register (not in
Sleep mode)
PNFDE
PN frame detection
error
always
enabled
partial networking frame detection error
CBS
CAN bus silence
disabled
no activity on CAN bus for tto(silence)
CF
CAN failure
disabled
one of the following CAN failure events detected
(not is Sleep mode):
- CAN transceiver deactivated due to a
dominant clamped TXD
- CAN transceiver deactivated due to a VCC
undervoltage event (if CMC = 01)
PO and PNFDE interrupts are always captured. Wake-up and interrupt detection can be
enabled/disabled for the remaining events individually via the event capture enable
registers (Table 26 to Table 28).
If an event occurs while the associated event capture function is enabled, the relevant
event status bit is set. If the transceiver is in CAN Offline mode, pin RXD is forced LOW to
indicate that a wake-up or interrupt event has been detected. If the TJA1145 is in Sleep
mode when the event occurs, pin INH is forced HIGH and the TJA1145 switches to
Standby mode. If the TJA1145 is in Standby mode when the event occurs, pin RXD is
forced LOW to flag an interrupt/wake-up event. The detection of any enabled wake-up or
interrupt event will trigger a wake-up in Standby or Sleep mode.
The microcontroller can monitor events via the event status registers. An extra status
register, the Global event status register (Table 22), is provided to help speed up software
polling routines. By polling the Global event status register, the microcontroller can quickly
determine the type of event captured (system, transceiver or WAKE) and then query the
relevant table (Table 23, Table 24 or Table 25 respectively).
After the event source has been identified, the status flag should be cleared (set to 0) by
writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be
cleared in a single write operation by writing 1 to all relevant bits.
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It is strongly recommended to clear only the status bits that were set to 1 when the status
registers were last read. This precaution ensures that events triggered just before the
write access are not lost.
6.6.1 Interrupt/wake-up delay
If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline
mode, they can have a significant impact on the software processing time (because pin
RXD is repeatedly driven LOW, requiring a response from the microcontroller each time
an interrupt/wake-up is generated). The TJA1145 incorporates an interrupt/wake-up delay
timer to limit the disturbance to the software.
When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a
timer is started. If further events occur while the timer is running, the relevant status bits
are set. If one or more events are pending when the timer expires after td(event), pin RXD
goes LOW again to alert the microcontroller.
In this way, the microcontroller is interrupted once to process a number of events rather
than several times to process individual events. If all active event capture bits have been
cleared (by the microcontroller) when the timer expires after td(event), pin RXD remains
HIGH (since there are no pending events). The event capture registers can be read at any
time.
6.6.2 Sleep mode protection
It is very important that event detection is configured correctly when the TJA1145 switches
to Sleep mode to ensure it will respond to a wake-up event. For this reason, and to avoid
potential system deadlocks, at least one regular wake-up event must be enabled and all
event status bits must be cleared before the TJA1145 switches to Sleep mode. Otherwise
the TJA1145 will switch to Standby mode in response to a go-to-sleep command
(MC = 001).
6.6.3 Event status and event capture registers
After an event source has been identified, the status flag should be cleared (set to
0) by writing 1 to the relevant status bit (writing 0 will have no effect).
Table 22.
TJA1145
Product data sheet
Global event status register (address 60h)
Bit
Symbol
Access
Value
Description
7:4
reserved
R
-
3
WPE
R
0
1
WAKE pin event pending at address 0x64
2
TRXE
R
0
no pending transceiver event
1
transceiver event pending at address 0x63
no pending WAKE pin event
1
reserved
R
-
0
SYSE
R
0
no pending system event
1
system event pending at address 0x61
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Table 23.
System event status register (address 61h)
Bit
Symbol
Access
Value
Description
7:5
reserved
R
-
4
PO[1]
R/W
0
no recent power-on
1
the TJA1145 has left Off mode after power-on
3
reserved
R
-
2
OTW
R/W
0
overtemperature not detected
1
the global chip temperature has exceeded the
overtemperature warning threshold (Tth(warn)otp)
0
no SPI failure detected
1
SPI failure detected
1
0
[1]
SPIF
reserved
R/W
R
-
PO is cleared when the TJA1145 is forced to Sleep mode due to an undervoltage event. The information
stored in PO could be lost if the transition to Sleep mode was forced by an undervoltage event. Bit NMS,
which is set to 0 when the TJA1145 switches to Normal mode after power-on, compensates for this.
Table 24.
Transceiver event status register (address 63h)
Bit
Symbol
Access
Value
7:6
reserved
R
-
5
PNFDE
R/W
0
no partial networking frame detection error detected
1
partial networking frame detection error detected
0
CAN bus is active
1
no activity on CAN bus for tto(silence)
4
CBS
R/W
Description
3:2
reserved
R
-
1
CF
R/W
0
no CAN failure event detected
1
CAN failure event detected
CF is only enabled in Normal mode while the
transceiver is in CAN Active mode and is triggered if:
- TXD is clamped dominant OR
- a VCC undervoltage is detected (when CMC = 01)
0
CW
Table 25.
Product data sheet
0
no CAN wake-up event detected
1
CAN wake-up event detected
WAKE pin event status register (address 64h)
Bit
Symbol
Access
Value
7:2
reserved
R
-
1
WPR
R/W
0
no rising edge detected on WAKE pin
1
rising edge detected on WAKE pin
0
TJA1145
R/W
WPF
R/W
Description
0
no falling edge detected on WAKE pin
1
falling edge detected on WAKE pin
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Table 26.
System event capture enable register (address 04h)
Bit
Symbol
Access
Value
7:3
reserved
R
-
2
OTWE
R/W
1
0
SPIFE
reserved
Table 27.
R/W
R
Description
0
overtemperature warning disabled
1
overtemperature warning enabled
0
SPI failure detection disabled
1
SPI failure detection enabled
-
Transceiver event capture enable register (address 23h)
Bit
Symbol
Access
Value
Description
7:5
reserved
R
-
4
CBSE
R/W
0
CAN bus silence detection disabled
1
CAN bus silence detection enabled
3:2
reserved
R
-
1
CFE
R/W
0
1
CAN failure detection enabled
0
CWE
R/W
0
CAN wake-up detection disabled
1
CAN wake-up detection enabled
Table 28.
CAN failure detection disabled
WAKE pin event capture enable register (address 4Ch)
Bit
Symbol
Access
Value
7:2
reserved
R
-
1
WPRE
R/W
0
rising-edge detection on WAKE pin disabled
1
rising-edge detection on WAKE pin enabled
0
falling-edge detection on WAKE pin disabled
1
falling-edge detection on WAKE pin enabled
0
WPFE
R/W
Description
6.7 Device ID
A byte is reserved at address 0x7E for a TJA1145 identification code.
Table 29.
Identification register (address 7Eh)
Bit
Symbol
Access
7:0
IDS[7:0]
R
Value
Description
device identification code
70h
TJA1145T, TJA1145TK
74h
TJA1145T/FD, TJA1145TK/FD
6.8 Lock control register
Sections of the register address area can be write-protected to protect against unintended
modifications. Note that this facility only protects locked bits from being modified via the
SPI and will not prevent the TJA1145 updating status registers etc.
TJA1145
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Table 30.
Lock control register (address 0Ah)
Bit
Symbol
Access
Value
Description
7
reserved
R
-
cleared for future use
6
LK6C
R/W
5
4
3
2
1
LK5C
lock control 6: address area 0x68 to 0x6F - partial
networking data byte registers
0
SPI write-access enabled
1
SPI write-access disabled
R/W
LK4C
lock control 5: address area 0x50 to 0x5F
0
SPI write-access enabled
1
SPI write-access disabled
R/W
LK3C
lock control 4: address area 0x40 to 0x4F - WAKE pin
configuration
0
SPI write-access enabled
1
SPI write-access disabled
R/W
LK2C
lock control 3: address area 0x30 to 0x3F
0
SPI write-access enabled
1
SPI write-access disabled
R/W
LK1C
lock control 2: address area 0x20 to 0x2F transceiver control and partial networking
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 1: address area 0x10 to 0x1F
0
SPI write-access enabled
1
0
LK0C
R/W
SPI write-access disabled
lock control 0: address area 0x06 to 0x09 - general
purpose memory
0
SPI write-access enabled
1
SPI write-access disabled
6.9 General-purpose memory
TJA1145 allocates 4 bytes of RAM as general-purpose registers for storing user
information. The general purpose registers can be accessed via the SPI at address 0x06
to 0x09 (see Table 31).
6.10 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage. This will cause the
signal levels of the TXD, RXD and the SPI interface pins to be adjusted to the I/O levels of
the microcontroller, enabling direct interfacing without the need for glue logic.
6.11 VCC/VIO undervoltage protection
If an undervoltage is detected on pins VCC or VIO, and it remains valid for longer than the
undervoltage detection delay time, td(uvd), the TJA1145 is forced to Sleep mode (see
Figure 4). A number of preventative measures are taken when the TJA1145 is forced to
Sleep mode to avoid deadlock and unpredictable states:
TJA1145
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• All previously captured events (address range 0x61 to 0x64) are cleared before the
TJA1145 switches to Sleep Mode to avoid repeated attempts to wake up while an
undervoltage is present.
• Both CAN wake-up (CWE = 1) and local wake-up via the WAKE pin (WPFE =
WPRE = 1) are enabled in order to avoid a deadlock situation where the TJA1145
cannot be woken up after entering Sleep mode.
• Partial Networking is disabled (CPNC = 0) to ensure immediate wake-up in response
to bus traffic after the TJA1145 has recovered from an undervoltage event.
• The Partial Networking Configuration bit is cleared (CPNOK = 0) to indicate that
partial networking might not have been configured correctly when the TJA1145
switched to Sleep mode.
Status bit FSMS is set to 1 when a transition to Sleep mode is forced by an undervoltage
event (see Table 5). This bit can be sampled after the TJA1145 wakes up from Sleep
mode to allow the settings of CWE, WPFE, WPRE and CPNC to be re-adjusted if an
undervoltage event forced the transition to Sleep mode (FSMS = 1).
TJA1145
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6.12 SPI
6.12.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
•
•
•
•
SCSN: SPI chip select; active LOW
SCK: SPI clock; default level is LOW due to internal pull-down
SDI: SPI data input
SDO: SPI data output; floating when pin SCSN is HIGH
Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the
rising edge, as illustrated in Figure 10.
SCSN
SCK
01
02
03
04
N–1
N
sampled
SDI
SDO
X
floating
X
MSB
MSB–1
MSB–2
MSB–3
01
LSB
MSB
MSB–1
MSB–2
MSB–3
01
LSB
X
floating
015aaa255
Fig 10. SPI timing protocol
The SPI data in the TJA1145 is stored in a number of dedicated 8-bit registers. Each
register is assigned a unique 7-bit address. Two bytes must be transmitted to the TJA1145
for a single register write operation. The first byte contains the 7-bit address along with a
‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a write operation (if this bit
is 1, a read operation is assumed and any data on the SDI pin is ignored). The second
byte contains the data to be written to the register.
24- and 32-bit read and write operations are also supported. The register address is
automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as
illustrated in Figure 11.
TJA1145
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TJA1145 Register Address Range
0x00
0x01
0x02
0x03
0x04
0x05
ID=0x05
addr 0000101
A6
A5
A4
A3
A2
A1
Address Bits
A0
0x06
data
0x07
data
data byte 1
0x7D
0x7E
0x7F
data
data byte 2
data byte 3
RO
x
x
x
Read-only Bit
x
x
x
x
x
x
x
Data Bits
x
x
x
x
x
x
x
x
Data Bits
x
x
x
x
x
x
Data Bits
015aaa281
Fig 11. SPI data structure for a write operation (16-, 24- or 32-bit)
During an SPI data read or write operation, the contents of the addressed register(s) is
returned via pin SDO.
The TJA1145 tolerates attempts to write to registers that don't exist. If the available
address space is exceeded during a write operation, the data above the valid address
range is ignored (without generating an SPI failure event).
During a write operation, the TJA1145 monitors the number of SPI bits transmitted. If the
number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure
event is captured (SPIF = 1).
If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on
SDI is reflected on SDO from bit 33 onwards.
6.12.2 Register map
The addressable register space contains 128 registers with addresses from 0x00 to 0x7F.
An overview of the register mapping is provided in Table 31 to Table 35. The functionality
of the individual bits is discussed in more detail in relevant sections of the data sheet.
Table 31.
Address
Overview of primary control registers
Register Name
Bit:
7
6
0x01
Mode control
0x03
Main status
FSMS
0x04
System event enable
reserved
0x06
Memory 0
GPM[7:0]
0x07
Memory 1
GPM[15:8]
TJA1145
Product data sheet
5
4
3
reserved
2
1
0
SPIFE
reserved
MC
OTWS
NMS
reserved
OTWE
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Table 31.
Address
Overview of primary control registers
Register Name
Bit:
7
6
0x08
Memory 2
GPM[23:16]
0x09
Memory 3
GPM[31:24]
0x0A
Lock control
reserved LK6C
Table 32.
Address
5
4
3
2
1
0
LK5C
LK4C
LK3C
LK2C
LK1C
LK0C
2
1
0
Overview of transceiver control and partial networking registers
Register Name
Bit:
7
6
5
4
3
0x20
CAN control
reserved
CFDC
PNCOK
CPNC
reserved
0x22
Transceiver status
CTS
CPNERR
CPNS
COSCS
CBSS
0x23
Transceiver event
enable
reserved
CBSE
reserved
0x26
Data rate
reserved
0x27
Identifier 0
ID[7:0]
0x28
Identifier 1
ID[15:8]
0x29
Identifier 2
ID[23:16]
0x2A
Identifier 3
reserved
0x2B
Mask 0
M[7:0]
0x2C
Mask 1
M[15:8]
0x2D
Mask 2
M[23:16]
0x2E
Mask 3
reserved
0x2F
Frame control
IDE
0x68
Data mask 0
DM0[7:0]
0x69
Data mask 1
DM1[7:0]
0x6A
Data mask 2
DM2[7:0]
0x6B
Data mask 3
DM3[7:0]
0x6C
Data mask 4
DM4[7:0]
0x6D
Data mask 5
DM5[7:0]
0x6E
Data mask 6
DM6[7:0]
0x6F
Data mask 7
DM7[7:0]
Table 33.
CMC
reserved VCS
CFE
CFS
CWE
CDR
ID[28:24]
M[28:24]
PNDM
reserved
DLC
Overview of WAKE pin control and status registers
Address
Register Name
Bit:
1
0
0x4B
WAKE pin status
reserved
WPVS
reserved
0x4C
WAKE pin enable
reserved
WPRE
WPFE
7
TJA1145
Product data sheet
6
5
4
3
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Table 34.
Overview of Event Capture registers
Address
Register Name
Bit:
7
6
0x60
Event capture status
reserved
0x61
System event status
reserved
0x63
Transceiver event status
reserved
0x64
WAKE pin event status
reserved
Table 35.
Overview of Identification register
Address
Register Name
Identification
TJA1145
Product data sheet
PNFDE
4
3
2
1
0
WPE
TRXE
reserved SYSE
PO
reserved OTW
SPIF
reserved
CBS
reserved
CF
CW
WPR
WPF
1
0
Bit:
7
0x7E
5
6
5
4
3
2
IDS[7:0]
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6.12.3 Register configuration in TJA1145 operating modes
A number of register bits may change state automatically when the TJA1145 switches
from one operating mode to another. This is particularly evident when the TJA1145
switches to Off mode or when an undervoltage event forces a transition to Sleep mode.
These changes are summarized in Table 36. If an SPI transmission is in progress when
the TJA1145 changes state, the transmission is ignored (automatic state changes have
priority).
Table 36.
Register bit settings in TJA1145 operating modes
Symbol
Off (reset
values)
Standby
Normal
Sleep
Overtemp
Forced Sleep (uv)
CBS
0
no change
no change
no change
no change
0
CBSE
0
no change
no change
no change
no change
no change
CBSS
1
actual state
actual state
actual state
actual state
actual state
CDR
101
no change
no change
no change
no change
no change
CF
0
no change
no change
no change
no change
0
CFDC
0
no change
no change
no change
no change
no change
CFE
0
no change
no change
no change
no change
no change
CFS
0
actual state
actual state
actual state
actual state
actual state
CMC
00
no change
no change
no change
no change
no change
COSCS
0
actual state
actual state
actual state
actual state
actual state
CPNC
0
no change
no change
no change
no change
0
CPNERR
1
actual state
actual state
actual state
actual state
actual state
CPNS
0
actual state
actual state
actual state
actual state
actual state
CTS
0
0
actual state
0
0
0
CW
0
no change
no change
no change
no change
0
CWE
0
no change
no change
no change
no change
1
DMn
11111111
no change
no change
no change
no change
no change
DLC
0000
no change
no change
no change
no change
no change
FSMS
0
no change
no change
0
no change
1
GPMn
00000000
no change
no change
no change
no change
no change
IDn
00000000
no change
no change
no change
no change
no change
IDE
0
no change
no change
no change
no change
no change
IDS
01110000
01110000
01110000
01110000
01110000
01110000
LKnC
0
no change
no change
no change
no change
no change
Mn
00000000
no change
no change
no change
no change
no change
MC
100
100
111
001
don’t care
001
NMS
1
no change
0
no change
no change
no change
OTW
0
no change
no change
no change
no change
0
OTWE
0
no change
no change
no change
no change
no change
OTWS
0
actual state
actual state
actual state
actual state
actual state
PNCOK
0
no change
no change
no change
no change
0
PNDM
1
no change
no change
no change
no change
no change
PNFDE
0
no change
no change
no change
no change
0
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Table 36.
Register bit settings in TJA1145 operating modes …continued
Symbol
Off (reset
values)
Standby
Normal
Sleep
Overtemp
Forced Sleep (uv)
PO
1
no change
no change
no change
no change
0
SPIF
0
no change
no change
no change
no change
0
SPIFE
0
no change
no change
no change
no change
no change
SYSE
1
no change
no change
no change
no change
0
TRXE
0
no change
no change
no change
no change
0
VCS
0
actual state
actual state
actual state
actual state
actual state
WPE
0
no change
no change
no change
no change
0
WPF
0
no change
no change
no change
no change
0
WPFE
0
no change
no change
no change
no change
1
WPR
0
no change
no change
no change
no change
0
WPRE
0
no change
no change
no change
no change
1
WPVS
0
no change
no change
no change
no change
no change
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7. Limiting values
Table 37. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Vx
voltage on pin x
DC value
voltage between pin CANH
and pin CANL
Vtrt
transient voltage
Max
Unit
0.2
+6
V
pins TXD, RXD, SDI, SDO, SCK, SCSN
0.2
VIO + 0.2
V
pins WAKE, INH
18
+40
V
pin BAT
0.2
+40
V
pins CANH and CANL with respect to any
other pin
58
+58
V
40
+40
V
150
+100
V
6
+6
kV
8
+8
kV
on pins BAT, WAKE
4
+4
kV
on any other pin
2
+2
kV
100
+100
V
750
+750
V
500
+500
V
40
+150
C
55
+150
C
pins VCC, VIO
V(CANH-CANL)
Min
on pins
[1]
[2]
BAT via reverse polarity diode and
capacitor to ground
CANL, CANH, WAKE
VESD
electrostatic discharge
voltage
IEC 61000-4-2
[3]
on pins CANH and CANL; pin BAT with
capacitor; pin WAKE with 10 nF capacitor
and 10 k resistor
[4]
HBM
on pins CANH, CANL
[5]
[6]
MM
on any pin
[7]
CDM
on corner pins
on any other pin
Tvj
virtual junction temperature
Tstg
storage temperature
[8]
[1]
When the device is not powered up, IVCC(max) = 25 mA.
[2]
Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.
[3]
ESD performance according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house; the result was equal to or
better than 6 kV.
[4]
Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).
[5]
VCC, VIO and BAT connected to GND, emulating the application circuit.
[6]
Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).
[7]
Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF).
[8]
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P  Rth(j-a), where Rth(j-a) is a
fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
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8. Thermal characteristics
Table 38.
Symbol
Rth(vj-a)
Thermal characteristics
Parameter
Conditions
[1]
thermal resistance from virtual junction to ambient SO14
HVSON14
[1]
Typ
Unit
106
K/W
60
K/W
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 µm) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).
9. Static characteristics
Table 39. Static characteristics
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin BAT
Vth(det)pon
power-on detection threshold
voltage
VBAT rising
4.2
-
4.55
V
Vth(det)poff
power-off detection threshold
voltage
VBAT falling
2.8
-
3
V
Vuvr(CAN)
CAN undervoltage recovery
voltage
VBAT rising
4.5
-
5
V
Vuvd(CAN)
CAN undervoltage detection
voltage
VBAT falling
4.2
-
4.55
V
IBAT
battery supply current
Sleep mode; MC = 001;
CWE = 1; CAN Offline mode;
40 C < Tvj < 85 C;
VBAT = 7 V to 18 V
-
40
59
A
Standby mode; MC = 100;
CWE = 1; CAN Offline mode;
40 C < Tvj < 85 C;
VBAT = 7 V to 18 V
-
44
68
A
additional current in CAN Offline
Bias mode; 40 C < Tvj < 85 C
-
46
63
A
additional current when partial
networking enabled; bus active;
CPNC = 1; PNCOK = 1
-
300
400
A
2
3
A
-
1
1.5
mA
4.5
-
4.75
V
additional current from WAKE
input; WPRE = WPFE = 1;
40 C < Tvj < 85 C
Normal mode; MC = 111
Supply; pin VCC
Vuvd(VCC)
undervoltage detection voltage on
pin VCC
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
35 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 39. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC
supply current
CAN Active mode; CAN
recessive; VTXD = VIO
-
3
6
mA
CAN Active mode; CAN
dominant; VTXD = 0 V
-
45
65
mA
Standby/Normal mode; CAN
inactive; 40 C < Tvj < 85 C
-
4.7
8.5
A
Sleep mode; CAN inactive;
40 C < Tvj < 85 C
-
3.8
7
A
Supply; pin VIO
Vuvd(VIO)
undervoltage detection voltage on VBAT > 4.5 V
pin VIO
2.7
-
2.85
V
II(VIO)
input current on pin VIO
Standby/Normal mode;
40 C < Tvj < 85 C
-
7.1
11
A
Sleep mode;
40 C < Tvj < 85 C
-
5
8
A
Serial peripheral interface inputs; pins SDI, SCK and SCSN
Vth(sw)
switching threshold voltage
0.25VIO
-
0.75VIO
V
Rpd(SCK)
pull-down resistance on pin SCK
40
60
80
k
Rpu(SCSN)
pull-up resistance on pin SCSN
40
60
80
k
ILI(SDI)
input leakage current on pin SDI
5
-
+5
A
VIO = 2.97 V to 5.5 V
Serial peripheral interface data output; pin SDO
VOH
HIGH-level output voltage
IOH = 4 mA
VIO  0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
ILO(off)
off-state output leakage current
VSCSN = VIO; VO = 0 V to VIO
5
-
+5
A
Inhibit output: pin INH
VO
output voltage
IINH = 180 A
VBAT  0.8 -
VBAT
V
Rpd
pull-down resistance
Sleep mode
3
5
M
4
CAN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
Rpu
pull-up resistance
VIO = 2.97 V to 5.5 V
0.25VIO
-
0.75VIO
V
40
60
80
k
VIO  0.4
-
-
V
CAN receive data output; pin RXD
VOH
HIGH-level output voltage
IOH = 4 mA
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
Rpu
pull-up resistance
CAN Offline mode
40
60
80
k
Local wake input; pin WAKE
Vth(sw)r
rising switching threshold voltage
2.8
-
4.1
V
Vth(sw)f
falling switching threshold voltage
2.4
-
3.75
V
Vhys(i)
input hysteresis voltage
250
-
800
mV
Ii
input current
-
-
1.5
A
TJA1145
Product data sheet
Tvj = 40 C to +85 C
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
36 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 39. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pin CANH
2.75
3.5
4.5
V
pin CANL
0.5
1.5
2.25
V
400
-
+400
mV
0.9VCC
-
1.1VCC
V
CAN Active mode (dominant);
VTXD = 0 V;
VCC = 4.75 V to 5.5 V;
R(CANH-CANL) = 45  to 65 
1.5
-
3.0
V
CAN Active mode (recessive);
CAN Listen-only mode;
CAN Offline mode; VTXD = VIO;
R(CANH-CANL) = no load
50
-
+50
mV
CAN Active mode; VTXD = VIO;
R(CANH-CANL) = no load
2
0.5VCC 3
V
CAN Offline mode;
R(CANH-CANL) = no load
0.1
-
+0.1
V
CAN Offline Bias/Listen-only
modes; R(CANH-CANL) = no load;
VCC = 0 V
2
2.5
3
V
pin CANH; VCANH = 0 V
50
-
-
mA
pin CANL; VCANL = 5 V
-
-
52
mA
High-speed CAN bus lines; pins CANH and CANL
VO(dom)
dominant output voltage
CAN Active mode; VTXD = 0 V
Vdom(TX)sym
transmitter dominant voltage
symmetry
Vdom(TX)sym =
VCC  VCANH  VCANL; VCC = 5 V
VTXsym
transmitter voltage symmetry
VTXsym = VCANH + VCANL;
fTXD = 250 kHz; CSPLIT = 4.7 nF
VO(dif)bus
VO(rec)
IO(dom)
bus differential output voltage
recessive output voltage
dominant output current
[1]
[2]
CAN Active mode;
VTXD = 0 V; VCC = 5 V
IO(rec)
recessive output current
VCANL = VCANH = 27 V to
+32 V; VTXD = VIO
3
-
+3
mA
Vth(RX)dif
differential receiver threshold
voltage
CAN Active/Listen-only modes;
VCANL = VCANH = 12 V to +12 V
0.5
0.7
0.9
V
CAN Offline mode;
VCANL = VCANH = 12 V to +12 V
0.4
0.7
1.15
V
CAN Active/Listen-only modes;
VCANL = VCANH = 12 V to +12 V
50
200
400
mV
9
15
28
k
Vhys(RX)dif
differential receiver hysteresis
voltage
Ri(cm)
common-mode input resistance
Ri
input resistance deviation
Ri(dif)
differential input resistance
Ci(cm)
common-mode input capacitance
Ci(dif)
differential input capacitance
ILI
input leakage current
TJA1145
Product data sheet
1
-
+1
%
19
30
52
k
[1]
-
-
20
pF
[1]
-
-
10
pF
5
-
+5
A
VCANL = VCANH = 12 V to +12 V
VBAT = VCC = 0 V or VBAT = VCC
= shorted to ground via 47 k;
VCANH = VCANL = 5 V
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
37 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 39. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Temperature protection
Tth(act)otp
overtemperature protection
activation threshold temperature
167
177
187
C
Tth(rel)otp
overtemperature protection
release threshold temperature
127
137
147
C
Tth(warn)otp
overtemperature protection
warning threshold temperature
127
137
147
C
[1]
Not tested in production; guaranteed by design.
[2]
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 16.
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
38 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
10. Dynamic characteristics
Table 40. Dynamic characteristics
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
from VBAT exceeding the
power-on detection threshold
until INH active
-
2.8
4.7
ms
6
-
54
s
200
-
400
ms
Voltage sources; pins BAT, VCC and VIO
tstartup
start-up time
td(uvd)
undervoltage detection delay time
td(uvd-sleep)
delay time from undervoltage
detection to sleep mode
from undervoltage detection on
VCC and/or VIO until TJA1145
forced to Sleep mode
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO in Normal and Standby modes
tcy(clk)
tSPILEAD
tSPILAG
tclk(H)
tclk(L)
tsu(D)
th(D)
tv(Q)
tWH(S)
clock cycle time
SPI enable lead time
SPI enable lag time
clock HIGH time
clock LOW time
data input set-up time
data input hold time
data output valid time
chip select pulse width HIGH
Normal/Standby modes
250
-
-
ns
Sleep mode
1
-
-
s
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
Normal/Standby modes
125
-
-
ns
Sleep mode
500
-
-
ns
Normal/Standby modes
125
-
-
ns
Sleep mode
500
-
-
ns
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
pin SDO; CL = 20 pF;
Normal/Standby modes
-
-
50
ns
pin SDO; CL = 20 pF; Sleep mode
-
-
200
ns
pin SCSN; Normal/Standby
modes
250
-
-
ns
pin SCSN; Sleep mode
1
-
-
s
-
-
255
ns
-
-
350
ns
-
80
-
ns
CAN transceiver timing; pins CANH, CANL, TXD and RXD
td(TXD-RXD)
RL = 60 ; CL = 100 pF;
delay time from TXD to RXD
50 % VTXD to 50 % VRXD;
CRXD = 15 pF;
fTXD = 250 kHz
RL = 120 ; CL = 200 pF;
50 % VTXD to 50 % VRXD;
CRXD = 15 pF;
fTXD = 250 kHz
td(TXD-busdom)
delay time from TXD to bus dominant
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
[1]
© NXP Semiconductors N.V. 2014. All rights reserved.
39 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 40. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.
Symbol
Parameter
Min
Typ
Max
Unit
td(TXD-busrec)
delay time from TXD to bus
recessive
-
80
-
ns
td(busdom-RXD)
delay time from bus dominant to
RXD
CRXD = 15 pF
-
105
-
ns
td(busrec-RXD)
delay time from bus recessive to
RXD
CRXD = 15 pF
-
120
-
ns
tbit(RXD)
bit time on pin RXD
tbit(TXD) = 500 ns
400
-
550
ns
twake(busdom)
bus dominant wake-up time
first pulse (after first recessive) for
wake-up on pins CANH and
CANL;
CAN Offline mode
0.5
-
3.0
s
second pulse for wake-up on pins
CANH and CANL
0.5
-
3.0
s
first pulse for wake-up on pins
CANH and CANL;
CAN Offline mode
0.5
-
3.0
s
second pulse (after first
dominant) for wake-up on pins
CANH and CANL
0.5
-
3.0
s
twake(busrec)
Conditions
bus recessive wake-up time
[2]
tto(wake)
wake-up time-out time
between first and second
dominant pulses; CAN Offline
mode
570
-
1200
s
tto(dom)TXD
TXD dominant time-out time
CAN Active mode; VTXD = 0 V
2.7
-
3.3
ms
tto(silence)
bus silence time-out time
recessive time measurement
started in all CAN modes; RL =
120 
0.95
-
1.17
s
td(busact-bias)
delay time from bus active to bias
-
-
200
s
tstartup(CAN)
CAN start-up time
-
-
220
s
when switching to Active mode
(CTS = 1)
Pin RXD: interrupt/wake-up event timing (valid in CAN Offline mode only) change to interrupt response time
td(event)
event capture delay time
CAN Offline mode
0.9
-
1.1
ms
tblank
blanking time
when switching from Offline to
Active/Listen-only mode
-
-
25
s
50
-
-
s
-
-
100
s
Pin WAKE
twake
wake-up time
Pin INH
td(buswake-INHH) delay time from bus wake-up to INH
HIGH
[1]
Guaranteed by design.
[2]
See Figure 13.
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
40 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
+,*+
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WG7;'EXVUHF
WGEXVGRP5;'
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Fig 12. CAN transceiver timing diagram
7;'
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WELW7;'
5;'
WELW5;'
DDD
Fig 13. Loop delay symmetry timing diagram
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
41 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
11. Application information
11.1 Application diagram
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termination of e.g. RT = 1.3 k can be used, if required by the OEM.
Fig 14. Typical application using the TJA1145
11.2 Application hints
Further information on the application of the TJA1145 can be found in the NXP application
hints document TR1309 Application Hints - High speed CAN transceiver for partial
networking TJA1145.
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
42 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
12. Test information
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Fig 16. Test circuit for measuring transceiver driver symmetry
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
43 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
13. Package outline
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TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
44 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
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TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
45 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
46 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 41 and 42
Table 41.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 42.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
TJA1145
Product data sheet
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Rev. 2 — 18 April 2014
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47 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Soldering of HVSON packages
Section 15 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
48 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
17. Revision history
Table 43.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1145 v.2
20140418
Product data sheet
-
TJA1145 v.1
Modifications:
TJA1145 v.1
TJA1145
Product data sheet
•
•
•
•
•
•
•
•
•
•
Section 1: text revised (5th paragraph added)
•
•
•
Figure 13: added
Section 2.1: feature added (loop delay symmetry)
Table 2: table note amended
Table 3: row CAN revised
Section 6.2: text and state diagram revised
Table 6: description for bits CMC revised
Table 7: description for bit CTS revised
Section 6.6.3: note added at beginning of section
Section 6.12.1: text revised (3rd last paragraph)
Table 40: conditions revised for symbol tstartup; parameter values changed: td(uvd), twake for pin WAKE;
parameter tbit(RXD) added; additional measurement for parameter td(TXD-RXD)
Section 11.2: added
Section 12.1: text updated
20130927
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
-
© NXP Semiconductors N.V. 2014. All rights reserved.
49 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1145
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
50 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
51 of 52
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
20. Contents
1
2
2.1
2.2
2.3
2.4
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
6.1.2
6.2
6.2.1
6.2.1.1
6.2.1.2
6.2.1.3
6.2.1.4
6.2.2
6.2.3
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.6
6.6.1
6.6.2
6.6.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Designed for automotive applications. . . . . . . . 2
Advanced ECU power management system . . 2
Protection and diagnosis . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
System controller . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 7
Hardware characterization for the TJA1145
operating modes . . . . . . . . . . . . . . . . . . . . . . . . 8
System control registers . . . . . . . . . . . . . . . . . . 8
High-speed CAN transceiver . . . . . . . . . . . . . . 9
CAN operating modes . . . . . . . . . . . . . . . . . . . 9
CAN Active mode . . . . . . . . . . . . . . . . . . . . . . . 9
CAN Listen-only mode . . . . . . . . . . . . . . . . . . 11
CAN Offline and Offline Bias modes. . . . . . . . 11
CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 12
CAN standard wake-up (partial networking
not enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CAN control and Transceiver status
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CAN partial networking . . . . . . . . . . . . . . . . . . 15
CAN FD frames . . . . . . . . . . . . . . . . . . . . . . . 17
CAN partial networking configuration
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 20
TXD dominant time-out. . . . . . . . . . . . . . . . . . 20
Pull-up on TXD pin . . . . . . . . . . . . . . . . . . . . . 21
VCC undervoltage event . . . . . . . . . . . . . . . . . 21
Loss of power at pin BAT . . . . . . . . . . . . . . . . 21
Local wake-up via WAKE pin . . . . . . . . . . . . . 21
Wake-up and interrupt event diagnosis
via pin RXD. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt/wake-up delay . . . . . . . . . . . . . . . . . 23
Sleep mode protection . . . . . . . . . . . . . . . . . . 23
Event status and event capture registers . . . . 23
6.7
6.8
6.9
6.10
6.11
6.12
6.12.1
6.12.2
6.12.3
7
8
9
10
11
11.1
11.2
12
12.1
13
14
15
15.1
15.2
15.3
15.4
16
17
18
18.1
18.2
18.3
18.4
19
20
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock control register. . . . . . . . . . . . . . . . . . . .
General-purpose memory . . . . . . . . . . . . . . .
VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . .
VCC/VIO undervoltage protection . . . . . . . . . .
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Register map . . . . . . . . . . . . . . . . . . . . . . . . .
Register configuration in TJA1145
operating modes . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . .
Application hints . . . . . . . . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering of HVSON packages . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
26
26
28
28
29
32
34
35
35
39
42
42
42
43
43
44
46
46
46
46
46
47
48
49
50
50
50
50
51
51
52
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 18 April 2014
Document identifier: TJA1145
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