Data Sheet

TDA8026
Multiple smart card slot interface IC
Rev. 1 — 9 March 2010
Product data sheet
1. General description
The TDA8026 is a cost-effective, analog interface for addressing multiple smart card slots
in a Point Of Sales (POS) terminal. It can address up to two main cards (synchronous or
asynchronous smart cards supported) and up to four Security Access Modules (SAMs).
Its packaging supports the latest payment terminal security requirements.
2. Features and benefits
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
I2C-bus controlled IC card interface in a TFBGA64 package
Supply voltage between 2.7 V and 5.5 V
Dedicated microcontroller interface supply voltage (VDD(INTF))
Shutdown mode ensures very low power consumption when the TDA8026 is inactive
Programmable power reduction modes triggered when the card slots are inactive
VCC(n) generation via DC-to-DC converter: two card slots can be fully loaded, the three
others in reduced consumption mode
Two clock input pins: CLKIN1 for card slot 1 and CLKIN2 for card slots 2 to 5
Two transparent I/O lines on microcontroller side, one for card slot 1 and the other for
card slots 2 to 5
Five protected, half-duplex, bidirectional, buffered I/O lines with current limitation at
± 15 mA and a maximum frequency 1 MHz
Two I2C-bus controlled auxiliary I/O lines
VCC(n) regulation on all card slots at ICC ≤ 55 mA:
u 5 V, 3 V or 1.8 V ± 5 %
u Current spikes of 40 nAs up to 20 MHz for 5 V cards with controlled rise and fall
times
u Current limitation of approximately 100 mA
Thermal protection and short-circuit protection on all card contacts
Automatic activation and deactivation sequences initiated by the software or hardware
in the event of a short-circuit, card take-off or voltage drop-out for VDD(INTF), VDD or VUP
Enhanced ElectroStatic Discharge (ESD) protection on the card-side up to 6 kV
20 MHz clock input
Card clock generation up to 20 MHz and dividable by 1, 2, 4 or 5 with synchronous
frequency changes:
u Stop, HIGH or LOW
u Clock frequency between 1 MHz and 2.2 MHz in card low-power mode
u Current limitation on pin CLK(n)
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
n RST(n) signal lines with current limitation at 20 mA, controlled by an embedded
programmable clock pulse counter on asynchronous cards or by a register on
synchronous cards
n ISO 7816-3 and EMV 4.2 payment systems compatibility
n VDD(INTF) supply voltage supervisor ensures correct communication between
microcontroller and circuit; threshold internally fixed or set using an external resistor
bridge
n VDD supply voltage supervisor for spike suppression during power-on and emergency
deactivation at power-off; threshold internally fixed
n Card presence input with a 17.8 ms (typical) built-in debouncing system on card slots
1 and 2
n One interrupt signal (IRQN)
3. Applications
n Point Of Sale terminals
n Multiple SAM contact readers
4. Quick reference data
Table 1.
Quick reference data
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
on pin VDD; DC-to-DC converter on
[1]
2.7
-
5.5
V
[1]
on pin VDD; DC-to-DC converter off and
VCC(n) pin = 5 V
5.25
-
5.5
V
shutdown mode
-
25
40
µA
Standby mode
-
300
450
µA
clock-stop mode; all card slots in this mode;
fclk(ext) stopped on pins CLK(n); pins CLKIN1
and CLKIN2 either stopped, HIGH-level or
LOW-level
-
3.7
-
mA
-
210
260
mA
1.6
-
3.6
V
Supply
VDD
IDD
supply current
active mode; all VCC(n) pins = 5 V; fclk(ext) on
pins CLK(n) = 5 MHz; ICC(1) = ICC(2) = 55 mA;
ICC(3) = ICC(4) = ICC(5) = 2 mA
VDD(INTF)
interface supply voltage on pin VDD(INTF)
IDD(INTF)
interface supply current shutdown mode
active mode; all VCC(n) pins = 5 V; fclk(ext) on
pins CLK(n) = 5 MHz
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
[2]
[3]
-
10
15
µA
-
35
-
µA
© NXP B.V. 2010. All rights reserved.
2 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 1.
Quick reference data …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
5 V card; DC ICC(n) ≤ 55 mA
4.75
5
5.25
V
3 V card; DC ICC(n) ≤ 55 mA
2.85
3
3.15
V
1.71
1.8
1.89
V
5 V card; current spikes of 40 nAs
4.65
-
5.35
V
3 V card; current spikes of 17.5 nAs
2.76
-
3.24
V
Card supply voltage pins: VCC(1) to VCC(5)
VCC
supply voltage
[4]
active mode; 2.7 V < VDD < 5.5 V
[5]
1.8 V card; DC ICC(n) ≤ 35 mA
active mode; AC current pulses with
I < 200 mA, t < 400 ns and f < 20 MHz
[5]
1.62
-
1.98
V
Vripple(p-p)
peak-to-peak ripple
voltage
20 kHz to 200 MHz with default Register6
(Slew Rate register) settings
1.8 V card; current spikes of 11.1 nAs
-
-
350
mV
ICC
supply current
VCC(n) = 5 V
-
-
55
mA
VCC(n) = 3 V
-
-
55
mA
VCC(n) = 1.8 V
-
-
35
mA
sum of all card supply currents on pins
VCC(n); active mode; All VCC pins = 5 V;
fclk(ext) on pins CLK(n) = 5 MHz;
ICC(1) = ICC(2) = 55 mA;
ICC(3) = ICC(4) = ICC(5) = 2 mA
[3]
-
total sequence
[6]
60
80
100
µs
-
17.8
23.8
ms
-
455
665
mW
−25
+25
+85
°C
116 125
mA
General
tdeact
deactivation time
tdeb
debounce time
Ptot
total power dissipation
Tamb
ambient temperature
Tamb = −25 °C to +85 °C
[1]
Refer to Section 8.6 for further information about the DC-to-DC converter operation.
[2]
Typical value measurement based on a 85 % DC-to-DC converter and inductance efficiency; depends on PCB layout and external
component quality (inductor, capacitor).
[3]
Maximum value measurement based on a 125 mA (sum of all card supply currents on pins VCC(n)) current load and a 75 % DC-to-DC
converter and inductance efficiency; depends on PCB layout and external component quality (inductor, capacitor).
[4]
Two ceramic multilayer 100 nF (minimum) capacitors with a low Equivalent Series Resistance (ESR) should be used to meet these
specifications.
[5]
Output voltage to the card including ripple.
[6]
Refer to Section 8.8.3 for further information.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8026ET/C2
TFBGA64
plastic thin fine-pitch ball grid array package; 64 balls
SOT1073-1
TDA8026_1
Product data sheet
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
6. Block diagram
VDD
VDD(INTREGD)
GNDP
GND2 to GND10
LX
H4
VDD(INTF)
B4
A7
A6
G4
VUP
H5
D3 to D5,E4,E5,
F3 to F5, H8
A4
PORADJ
DCDC_OFF
SDWNN
VDD(INTF)
A8
B8
A5
SEQUENCER
POWER
MANAGEMENT
UNIT
VCC
GENERATOR
STEP UP
CONVERTER
RST BUFFER
A4
CLK BUFFER
I/O BUFFER
I/O BUFFER
I/O BUFFER
SCL
SDA
IRQN
A0
INTAUXN
I/OUC1
I/OUC2
CLKIN1
CLKIN2
SPRES
TESTMODE
INHIB
G2
F2
E3
G1
F1
B2
PRES
DETECTION
C2
H2
H3
VCC(1)
RST(1)
CLK(1)
I/O(1)
C4(1)
C8(1)
PRES(1)
GNDC(1)
E2
SEQUENCER
E1
VCC
GENERATOR
TDA8026
D2
INTERFACE
AND
CONTROL
UNIT
C4
C5
RST BUFFER
CLK BUFFER
C3
I/O BUFFER
B3
PRES
DETECTION
G5
G6
G7
F7
F8
G8
H1
A3
SEQUENCER
SEQUENCER
SEQUENCER
H7
VCC
GENERATOR
VCC
GENERATOR
VCC
GENERATOR
RST BUFFER
RST BUFFER
RST BUFFER
CLK BUFFER
CLK BUFFER
CLK BUFFER
I/O BUFFER
I/O BUFFER
I/O BUFFER
D1
C1
B1
A1
A2
STAP5
STAP3
TST1
STAP4
TST2
C7
B7
B6
B5
I/O(5)
RST(5)
CLK(5)
D7
C6
D6
E7
D8
I/O(4)
RST(4)
CLK(4)
VCC(5)
Fig 1.
G3
E6
F6
C8
VCC(2)
RST(2)
CLK(2)
I/O(2)
PRES(2)
GNDC(2)
GNDS
E8
I/O(3)
RST(3)
CLK(3)
VCC(4)
VCC(3)
001aal083
TDA8026 Block diagram
TDA8026_1
Product data sheet
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
7. Pinning information
7.1 Pinning
TDA8026
ball A1
index area
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
001aal084
Transparent top view
Fig 2.
TDA8026 pin configuration for the TFBGA64 package
Table 3.
TDA8026 ball map
Ball position[1][2]
1
2
3
A
TST2
TST1
TESTMODE VDD(INTF) SDWNN VDD(INTREGD) VDD
B
STAP3
SCL
CLKIN2
GND1
VCC(5)
RST(5)
CLK(5)
DCDC_OFF
C STAP4
SDA
CLKIN1
I/OUC1
I/OUC2
CLK(4)
I/O(5)
GNDS
Product data sheet
5
6
7
8
PORADJ
D STAP5
INTAUXN
GND2
GND3
GND4
RST(4)
I/O(4)
VCC(4)
E
A0
IRQN
I/O(1)
GND5
GND6
CLK(3)
I/O(3)
VCC(3)
F
C8(1)
CLK(1)
GND7
GND8
GND9
RST(3)
I/O(2)
PRES(2)
G C4(1)
RST(1)
VCC(1)
GNDP
VCC(2)
RST(2)
CLK(2)
GNDC(2)
GNDC(1)
LX
VUP
n.c.
INHIB
GND10
H SPRES PRES(1)
TDA8026_1
4
[1]
The numbers in subscript and between brackets “(n)” indicate the relevant card slot.
[2]
The ball positions are those when the TDA8026 is viewed from the top.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
7.2 Pin description
Table 4.
Pin description
Symbol
Pin
Type[1] Supply
power
Description
IRQN
E2
O
VDD(INTF)
microcontroller interrupt; active LOW; open-drain
INTAUXN
D2
I
VDD(INTF) auxiliary interrupt line input:
auxiliary contact reader front end not connected:
connect INTAUXN pad to supply voltage VDD(INTF)
auxiliary contact reader front end connected:
connect INTAUXN pad to an external 10 kΩ pull-up
resistor; active LOW
SDWNN
A5
I[3]
VDD(INTF) shutdown and reset input; active LOW
VDD(INTF)
A4
P
VDD(INTF)
SDA
C2
I/O
VDD(INTF) serial data line to and from the I2C-bus master;
open-drain
SCL
B2
I
VDD(INTF) serial clock line from the I2C-bus master
A0
E1
C
VDD(INTF) I2C-bus address configuration and selection
SPRES
H1
C
VDD(INTF) PRES mode[2] configuration and selection
CLKIN1
C3
I
VDD(INTF) card slot 1 external clock input; connect external clock
(fclk(ext)) to generate the CLK(1) frequency
CLKIN2
B3
I
VDD(INTF) card slots 2 to 5 external clock input; connect external
clock (fclk(ext)) to generate the CLK(2) to CLK(5)
frequency
GND1
B4
G
-
I/OUC1
C4
I/O[3]
VDD(INTF) card slot 1 microcontroller data input and output
I/OUC2
C5
I/O[3]
VDD(INTF) card slots 2 to 5 microcontroller data input and output
VCC(1)
G3
P
VCC(1)
card slot 1 card supply; position C1
RST(1)
G2
O
VCC(1)
card slot 1 card reset output; position C2
CLK(1)
F2
O
VCC(1)
card slot 1 card clock output; provides fCLK; position C3
G1
I/O[4]
VCC(1)
card slot 1 auxiliary input and output; position C4
F1
I/O[4]
VCC(1)
card slot 1 auxiliary input and output; position C8
I/O(1)
E3
I/O[4]
VCC(1)
card slot 1 card input and output; position C7
GNDC(1)
H3
G
-
card slot 1 card ground signal; position C5
PRES(1)
H2
I
VDD(INTF) card slot 1 card presence input
VCC(2)
G5
P
VCC(2)
card slot 2 card supply; position C1
RST(2)
G6
O
VCC(2)
card slot 2 card reset; position C2
CLK(2)
G7
O
VCC(2)
card slot 2 card clock output; provides fCLK; position C3
I/O(2)
F7
I/O[4]
VCC(2)
card slot 2 card input and output; position C7
GNDC(2)
G8
G
-
card slot 2 card signal ground; position C5
C4(1)
C8(1)
TDA8026_1
Product data sheet
microcontroller interface supply voltage
ground connection
PRES(2)
F8
I
VDD(INTF) card slot 2 card presence input
GNDS
C8
G
-
card slots 3 to 5 card signal ground; position C5
VCC(3)
E8
P
VCC(3)
card slot 3 card supply; position C1
RST(3)
F6
O
VCC(3)
card slot 3 card reset output; position C2
CLK(3)
E6
O
VCC(3)
card slot 3 card clock output; provides fCLK; position C3
I/O(3)
E7
I/O[4]
VCC(3)
card slot 3 card input and output; position C7
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 4.
Pin description …continued
Symbol
Pin
Type[1] Supply
power
Description
VCC(4)
D8
P
VCC(4)
card slot 4 card supply; position C1
RST(4)
D6
O
VCC(4)
card slot 4 card reset output; position C2
CLK(4)
C6
O
VCC(4)
card slot 4 card clock output; provides fCLK; position C3
I/O(4)
D7
I/O[4]
VCC(4)
card slot 4 card input and output; position C7
VCC(5)
B5
P
VCC(5)
card slot 5 card supply; position C1
RST(5)
B6
O
VCC(5)
card slot 5 card reset output; position C2
CLK(5)
B7
O
VCC(5)
card slot 5 card clock output; provides fCLK; position C3
I/O(5)
C7
I/O[4]
VCC(5)
card slot 5 card input and output; position C7
TST1
A2
C
VDD(INTF) test pin; connect to ground
TST2
A1
C
VDD(INTF) test pin; connect to ground
STAP3
B1
I
VDD(INTF) card slot 3 presence status input[5]
STAP4
C1
I
VDD(INTF) card slot 4 presence status input[5]
STAP5
D1
I
VDD(INTF) card slot 5 status presence input[5]
n.c.
H6
-
-
PORADJ
A8
I
VDD(INTF) power-on reset threshold input for VDD(INTF):
not connected
threshold used: connect pin PORADJ using an
external resistor bridge
threshold not used: connect to VDD(INTF)
TDA8026_1
Product data sheet
VDD
A7
P
VDD
main supply voltage
VUP
H5
O
VUP
DC-to-DC converter output
LX
H4
I
LX
DC-to-DC converter power supply input
GNDP
G4
G
-
DC-to-DC converter ground
VDD(INTREGD)
A6
O
VDD
internal voltage regulator output
DCDC_OFF
B8
C
VDD(INTF) DC-to-DC converter on/off control; active HIGH
INHIB
H7
C
VDD(INTF) connect to ground
TESTMODE
A3
C
VDD(INTF) connect to ground
GND2
D3
G
-
ground
GND3
D4
G
-
ground
GND4
D5
G
-
ground
GND5
E4
G
-
ground
GND6
E5
G
-
ground
GND7
F3
G
-
ground
GND8
F4
G
-
ground
GND9
F5
G
-
ground
GND10
H8
G
-
ground
[1]
I = Input, O = Output, P = Power, G = Ground, C = Configuration.
[2]
Refer to the Application note AN10724 for further information.
[3]
Integrated pull-up to VDD(INTF) value.
[4]
Integrated pull-up to the related VCC(n) value.
[5]
In Shutdown mode, set to LOW.
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
7 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
8. Functional description
Remark: Throughout this document ISO 7816-3 and EMV standard terminology
conventions have been adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The TDA8026 supply pins are VDD, VDD(INTF) and GND1 to GND10.
• VDD must be between 2.7 V and 5.5 V
• VDD(INTF) must be between 1.6 V and 3.6 V
The VDD, VDD(INTF) supply voltages can be applied to the device at any time, in any
sequence. All interface signals to the system controller are referenced to the VDD(INTF)
supply voltage which can be lower or higher than VDD. The integrated DC-to-DC converter
generates the card supply voltage (VCC(n)) of either 5 V , 3 V or 1.8 V (± 5 %). In addition,
the internal voltage regulator delivers VDD(INTREGD) 3.3 V supply voltage.
POWER ON
RESET
supply failure
(VDD(INTF), VDD)
SHDWN = 1
supply failure
(VDD(INTF), VDD)
activation
command
SHUTDOWN
MODE
STANDBY
MODE
deactivation
command for all
card slots
SDWNN = 0
VCC(n) overcurrent
on a
card slot
DEACTIVATION
ACTIVE
OF FAULTY
MODE(1)
CARD SLOT(2)
temperature
failure or DC-to-DC
converter overload
SDWNN = 0
001aal085
(1) Active mode; DC-to-DC converter is ON.
(2) VCC(n) overcurrent on a card slot causes deactivation of a faulty card slot. All others remain active.
Fig 3.
TDA8026 Power diagram
8.2 Power modes
Three power modes are available for the TDA8026. These are:
• Standby mode
• Active mode with a clock-stop sub-mode
• Shutdown mode
TDA8026_1
Product data sheet
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
8 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
8.2.1 Standby mode
In Standby mode, both the supply voltages VDD and VDD(INTF) are applied within the
specification limits as described in Table 40 on page 39. In addition, the DC-to-DC
converter is not running and the card slots are not activated.
8.2.2 Active mode
In active mode, both the VDD and VDD(INTF) supply voltages are applied to the device
within the specification limits as described in Table 40 on page 39. A minimum of one card
slot is activated. All card slots can be activated at once and communication performed
with up to two cards slots.
The DC-to-DC converter has been developed to handle a 116 mA (typical) DC load. This
allows two active card slots to communicate with a load of 55 mA while the three
remaining card slots are in clock-stop mode (see Section 8.2.3 for information about this
mode) with a 2 mA load.
The DC-to-DC converter overload protection is triggered when a higher current load than
specified in Table 40 on page 39 is supplied to the DC-to-DC converter (see Section 8.11
for further information).
8.2.3 Clock-stop mode
Clock-stop mode is a low-power mode which is triggered when a card is activated without
any communication. In this mode, a supply voltage with a low frequency clock is applied to
cards that do not support the clock-stop feature.
8.2.4 Shutdown mode
Shutdown mode is the very low power consumption mode, typically 25 µA. The TDA8026
enters this mode when the SDWNN pin is driven LOW. Only presence monitoring on card
slot 1 remains enabled. When card insertion or removal is detected on card slot 1, an
interrupt signal (IRQN) is sent to the microcontroller.
In shutdown mode, it is assumed that the VDD(INTF) and VDD supply voltages are stable
and the SDWNN pin is active LOW.
8.2.4.1
Entering shutdown mode
Shutdown mode is activated when the SDWNN pin is driven LOW. On entering this mode:
1. All card slots are automatically deactivated
2. The power consumption is reduced on completion of the deactivation sequence.
This causes the following:
• Digital module moves in to reset mode. However, card presence monitoring on slot 1
continues to operate normally
• All card slots are disabled and all card pins are forced to 0 V. Again, card presence
monitoring on slot 1 continues to operate normally
• Thermal protection is disabled
• The DC-to-DC converter is bypassed
• All interface signal pull-up resistors are disconnected from their supply rail (except the
pull-up resistor on the SDWNN pin)
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
9 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
• I/OUC1 and I/OUC2 are set to high-impedance.
SDWNN
(1)
DEACTIVATION
card slot
(2)
internal digital
reset
Fig 4.
8.2.4.2
shutdown state
001aal086
The enter shutdown sequence
Exiting shutdown mode
The TDA8026 performs the following steps when exiting shutdown mode:
1. Card insertion on card slot 1 is signalled by the IRQN pin signal being driven LOW.
2. Using the IRQN pin signal, the microcontroller detects the card insertion and drives
the SDWNN pin HIGH to wake-up the TDA8026
3. When the SDWNN pin is HIGH, the IRQN pin is set to HIGH and the analog module is
powered-up. A full power-up sequence is executed by the TDA8026
4. When the TDA8026 is ready, the IRQN pin is set to LOW
5. The microcontroller detects the device interrupt using the IRQN pin and services it
which resets pin IRQN to HIGH
PRES(1)
1
5
IRQN
2
3
SDWNN
4
internal digital
reset
shutdown state
Fig 5.
TDA8026_1
Product data sheet
2tw
ready for activation
001aal087
The exit shutdown sequence
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
10 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
8.3 Voltage supervisors
8.3.1 Block diagram
VDD(INTF)
R1
PORADJ
VDD(INTREGD)
R2
REFERENCE
VOLTAGE
VDD(INTREGD)
001aai961
Fig 6.
The voltage supervisor circuit
8.3.2 Description
The voltage supervisor can be used to perform Power-On Resets (POR) and supply drop
detection during a card session. The supervisors control the internal regulated supply
voltage (VDD(INTREGD)) and the microcontroller interface supply voltage (VDD(INTF)) to
ensure problem-free operation of the TDA8026. This block controls:
• VDD using the internal voltage regulator’s output (VDD(INTREGD))
• the microcontroller interface supply voltage (VDD(INTF)) using the voltage on the
PORADJ pin (VPORADJ)
When an alarm occurs, the internal digital controller resets the TDA8026.
VDD
VDD(INTREGD)
Vth + Vhys
Vth
supply
drop
power-up
VDD(INTREGD)
device
ready for
activation
ALARMN
(internal signal)
Fig 7.
TDA8026_1
Product data sheet
twake
device
ready for
activation
twake
001aal088
VDD voltage supervisor
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Multiple smart card slot interface IC
VDD(INTF)
supply
drop
Vth + Vhys
Vth
power-up
VDD(INTREGD)
device
ready for
activation
ALARMN
(internal signal)
Fig 8.
twake
device
ready for
activation
twake
001aal089
VDD(INTF) voltage supervisor
Remark: Refer to the Application note AN10724 for further information.
8.3.3 VDD(INTREGD) voltage supervisor without external divider on PORADJ pin
An alarm signal is triggered and the analog controller resets the TDA8026 when:
• VDD(INTREGD) is less than Vth on pin VDD(INTREGD)
• Pin PORADJ monitoring VDD(INTF) is less than Vth
The alarm is reset and the TDA8026 leaves reset mode 8 ms after VDD and VPORADJ are
above their respective Vth + Vhys.
Vth on VDD(INTF) is set as shown in Equation 1:
R2
V th = V bg  1 + -------

R1
(1)
Thus Vbg = 1.21 V (see Figure 6).
In reset mode, the TDA8026 is inactive and does not respond to any external command
lines.
TDA8026_1
Product data sheet
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TDA8026
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Multiple smart card slot interface IC
8.4 I2C-bus description
Remark: Refer to the I2C-bus specification for more information.
The I2C-bus interface in the TDA8026 is an I2C-bus slave operating either Standard mode
(100 kHz) or Fast mode (400 kHz). In addition, it integrates shift register functions, shift
timing generation and slave address recognition.
8.4.1 I2C-bus protocol
The I2C-bus protocol is based on bidirectional, 2-line communication between ICs or
modules. The serial bus consists of two bidirectional lines: one for data signals (SDA) and
one for clock signals (SCL). Both the SDA and SCL lines must be connected to the
VDD(INTF) supply voltage using a pull-up resistor (refer to the I2C-bus specification for more
details).
The I2C-bus protocol is defined as follows:
• Data transfer can only be initialized when the I2C-bus is not busy.
• During data transfer, the data line must remain stable when the clock line is HIGH.
Changes in the data line while the clock line is HIGH are interpreted as control
signals.
8.4.2 Bus conditions
The following bus conditions are defined.
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — The START condition is generated when the state of the data line
changes from HIGH to LOW while the clock line is HIGH.
Stop data transfer — The STOP condition is generated when the state of the data line
changes from LOW to HIGH while the clock line is HIGH.
Data valid — The data line state represents valid data, after a START condition with the
data line stable for the duration of the clock signal HIGH period. There is one clock pulse
per bit of data.
8.4.3 Data transfer
Each data transfer is triggered by a START condition and finished by a STOP condition
(see Figure 13 for timing information).
Data transfers can be performed in Standard mode at 100 kHz or Fast mode at 400 kHz.
Data transfer is performed on a byte for byte basis in both read or write modes. The
information is transmitted in bytes and each receiver acknowledges with a 9th bit
(acknowledge).
Each byte is followed by an acknowledge bit and the transmitter must release the SDA line
during the acknowledge bit. The master generates an extra acknowledge related clock
pulse. The addressed slave receiver must generate an acknowledge bit after receiving
each byte. The master-receiver must generate an acknowledge bit after receiving each
byte clocked out of the slave transmitter.
The acknowledging device must pull-down the SDA line during the acknowledge clock
pulse to ensure the SDA line is stable LOW during the acknowledge related clock pulse
HIGH period.
TDA8026_1
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TDA8026
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Multiple smart card slot interface IC
In addition, the set-up and hold times must be taken into account. The master-receiver
must signal the end of the last data byte to the slave transmitter by not sending an
acknowledge bit on the last byte that has been clocked out of the slave. The transmitter
must ensure the data line is HIGH to enable the master to generate the STOP condition.
8.4.4 Device addressing
Three device addresses are needed to control the TDA8026.
• One high address: The high address enables selection of a bank page (Bank 0 or
Bank 1) based on a configuration byte. A bank page relates to a card slot or general
registers. See Table 7 for detailed information.
• Two low addresses: The microcontroller uses two low addresses to read and write into
the selected bank page (see Table 6 on page 14 to Table 39 on page 37 for detailed
information).
The addresses for the device are shown in Table 5 and Table 6.
Table 5.
Base addressing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
1
A0
0
R/W
Bit 1 is the address bit which selects Register0 or Register1. Bit 0 defines either Read or
Write mode.
• When bit 0 is set to logic 1, read mode is selected
• When bit 0 is set to logic 0, write mode is selected
Table 6.
Write mode addresses
A0 Pin
Bank 0 base register
address (Hex)
Bank 1 Register0 address Bank 1 Register1
(Hex)
address (Hex)
0
48h
40h
42h
1
4Ch
44h
46h
Bank 1 page selection is performed when the configuration byte (CSb[7:0]) is written to
the high address representing bank 0 based on the A0 pin value.
Using pin A0, two TDA8026s can be used in parallel based on the selection made to the
address selection pin A0. Pin A0 is externally hardwired to the pins VDD(INTF) or GND. The
voltage on the A0 pin sets the bit 2 address bit
TDA8026_1
Product data sheet
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Multiple smart card slot interface IC
8.5 Banks and registers
The device registers enable the microcontroller to control the TDA8026. These registers
are defined as banks:
• Bank 0 register is a read/write register which enables selection of the required card
slot number and access to the corresponding registers Bank 1 registers. In addition,
Bank 0 is used to write information about the interrupt status and the product version.
The registers in bank 0 (CSb[7:0] = 1h to 5h) are similar to the registers of the
TDA8023.
• Bank 1 provides access to the corresponding card slot registers. Bank 1 is composed
of several pages which in turn contain registers related to each individual card slot or
general registers. Typically, pages can contain two general registers or five card slot
related registers.
Remark: The registers are organized in bank pages in order to keep compatibility with the
TDA8023.
Bank 1 page selection is performed when the configuration byte (CSb[7:0]) is written to
the high I2C-bus address representing bank 0 based on the A0 pin.
TDA8026_1
Product data sheet
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Rev. 1 — 9 March 2010
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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Table 7.
NXP Semiconductors
TDA8026_1
Product data sheet
8.5.1 Register overview
Register overview
Page number/
register
Subaddress
(Hex)[1]
Register
name
R/W
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset value
(Binary)
Bank 0: Card slot selection, product version and interrupt registers (see Table 8 and Table 9)
-/48h
CSb
R/W
CSb[7:0]
0000 0001
Bank 1: Card slot registers (see Table 11 through Table 33)
Slot 1
Rev. 1 — 9 March 2010
Register0
R
ACTIVE
EARLY
MUTE
PROT
01h/40h
Register0
W
VCC1V8
I/OEN
01h/42h
Register1[3]
R/W
-[2]
RSTIN
01h/42h
Register1[4]
R/W
D[7:0]
1010 1010
01h/42h
Register1[5]
R/W
C[15:8]
1010 0100
01h/42h
Register1[6]
R/W
C[7:0]
0111 0100
02h/40h
Register0
R
ACTIVE
EARLY
02h/40h
Register0
W
VCC1V8
I/OEN
REG[1:0]
02h/42h
Register1[3]
R/W
RSTIN
-[2]
02h/42h
Register1[4]
R/W
D[7:0]
1010 1010
02h/42h
Register1[5]
R/W
C[15:8]
1010 0100
02h/42h
Register1[6]
R/W
C[7:0]
0111 0100
03h/40h
Register0
R
ACTIVE
EARLY
03h/40h
Register0
W
VCC1V8
I/OEN
REG[1:0]
03h/42h
Register1[3]
R/W
RSTIN
-[2]
03h/42h
Register1[4]
R/W
D[7:0]
1010 1010
03h/42h
Register1[5]
R/W
C[15:8]
1010 0100
03h/42h
Register1[6]
R/W
C[7:0]
0111 0100
REG[1:0]
C81
C41
SUPL
CLKSW
PRESL
PRES
0000 1000
PDWN
5V/3VN
WARM
START
0000 0000
CLKPD[1:0]
CLKDIV[1:0]
0111 1111
Slot 2
CFGP2
MUTE
PROT
SUPL
CLKSW
PRESL
PRES
0000 1000
PDWN
5V/3VN
WARM
START
0000 0000
CLKPD[1:0]
CLKDIV[1:0]
0100 1111
Slot 3
-[2]
MUTE
PROT
SUPL
CLKSW
-[2]
STAP3
0000 1000
PDWN
5V/3VN
WARM
START
0000 0000
CLKPD[1:0]
CLKDIV[1:0]
0100 1111
TDA8026
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01h/40h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Register overview …continued
Page number/
register
Subaddress
(Hex)[1]
R/W
Bit definition
04h/40h
Register0
R
ACTIVE
EARLY
04h/40h
Register0
W
VCC1V8
I/OEN
REG[1:0]
04h/42h
Register1[3]
R/W
RSTIN
-[2]
04h/42h
Register1[4]
R/W
D[7:0]
1010 1010
04h/42h
Register1[5]
R/W
C[15:8]
1010 0100
04h/42h
Register1[6]
R/W
C[7:0]
0111 0100
05h/40h
Register0
R
ACTIVE
EARLY
05h/40h
Register0
W
VCC1V8
I/OEN
REG[1:0]
05h/42h
Register1[3]
R/W
RSTIN
-[2]
05h/42h
Register1[4]
R/W
D[7:0]
1010 1010
05h/42h
Register1[5]
R/W
C[15:8]
1010 0100
05h/42h
Register1[6]
R/W
C[7:0]
0111 0100
PV[7:0]
1100 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset value
(Binary)
Slot 4
-[2]
MUTE
PROT
SUPL
CLKSW
-[2]
STAP4
0000 1000
PDWN
5V/3VN
WARM
START
0000 0000
CLKPD[1:0]
CLKDIV[1:0]
0100 1111
Slot 5
-[2]
MUTE
PROT
SUPL
CLKSW
-[2]
STAP5
0000 1000
PDWN
5V/3VN
WARM
START
0000 0000
CLKPD[1:0]
CLKDIV[1:0]
0100 1111
Bank 1: General registers (see Table 34 through Table 39)
00h/42h
Product
version
R
00h/42h
Interrupt
status
R
06h/40h
Slew rate
R/W
-[2]
INTAUX
CLK_SR[3:2]
See Table 8, Table 9 and Table 11 through Table 39 for detailed information.
Reserved bit position.
[3]
REG[1:0] = 00 depending on the setting for Bank1 CSb[7:0].
[4]
REG[1:0] = 01 depending on the setting for Bank1 CSb[7:0].
[5]
REG[1:0] = 10 depending on the setting for Bank1 CSb[7:0].
[6]
REG[1:0] = 11 depending on the setting for Bank1 CSb[7:0].
CLK_SR[1:0]
0001 1111
IO_SR[1:0]
0100 0100
TDA8026
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[1]
[2]
IO_SR[3:2]
INT[4:0]
Multiple smart card slot interface IC
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Rev. 1 — 9 March 2010
Register
name
NXP Semiconductors
TDA8026_1
Product data sheet
Table 7.
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
8.5.2 Bank 0 register description
The device registers enable the microcontroller to control the TDA8026. The registers are
organized in bank pages to ensure compatibility with the TDA8023.
Bank 0 write register enables selection of the card slot number and access to the
corresponding registers in bank 1. The card slot registers in bank 1 are accessed using
the configuration byte (CSb[7:0]). The range 01h to 05h is used to select the specific card
slot starting at card slot 1 (01h) and ending with card slot 5 (05h) in a similar way to the
TDA8023 registers.
8.5.2.1
Bank 0 register (address: 48h) bit allocation
Table 8.
Bit
8.5.2.2
Bank 0 register (address: 48h) bit allocation
7
6
5
4
3
Symbol
CSb[7:0]
Access
R/W
2
1
0
Bank 0 bit description
Table 9.
Bit
Bank 0 bit description
Symbol
Value
7 to 0 CSb[7:0]
Description
Bank 1 page selection:
00h
selects product version and interrupts status register page
01h
selects card slot 1 page
02h
selects card slot 2 page
03h
selects card slot 3 page
04h
selects card slot 4 page
05h
selects card slot 5 page
06h
selects the clock frequency and I/O lines slew rate settings page
8.5.3 Bank 1 card slots 1 and 2 register descriptions
8.5.3.1
Bank 1 CSb[7:0] Register0 (address 40h) card slot 1 and card slot 2 bit allocation
Table 10.
Bit
Bank 1 CSb[7:0] Register0 (address 40h) card slot 1 and card slot 2 bit
allocation
7
6
5
4
3
2
1
0
Card slot 1 (address 01h) and Card slot 2 (address 02h)
Symbol
ACTIVE
EARLY
MUTE
PROT
SUPL
Access
[1]R
R
R
R
R
R
R
R
Symbol
VCC1V8
I/OEN
PDWN
5V/3VN
WARM
START
Access
[1]W
W
W
W
W
W
[1]
REG[1:0]
W
W
CLKSW PRESL
PRES
See Table 11 for the read mode bits and Table 12 for the write mode bits.
When at least one of the PRESL, SUPL, PROT, MUTE and EARLY bits is set to logic 1,
IRQN pin is driven LOW until the status byte has been read. After power-on, the SUPL bit
is set to logic 1 until the status byte has been read and the IRQN pin is LOW until the
voltage supervisor is deactivated.
TDA8026_1
Product data sheet
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8.5.3.2
Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) read mode
bit descriptions
Table 11.
Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) read
mode bit descriptions
Bit
Symbol
Value
Description
7
ACTIVE
1
set to logic 1: the card is active
0
set to logic 0: the card is inactive
1
set to logic 1: during ATR, when the card answers too early
0
set to logic 0: after reading the byte
1
set to logic 1: during ATR, when the card does not answer
according to the ISO 7816 time period
0
set to logic 0: after reading the byte
1
set to logic 1: during a card session when an overload or
overheating occurs
0
set to logic 0: after reading the byte
1
set to logic 1: when the supervisor signals a fault
0
set to logic 0: after reading the byte
1
set to logic 1: when the card slot is in Power-down mode and the
clock has switched to f osc ( int ) ⁄ 2
6
EARLY
5
MUTE
4
PROT
3
SUPL
2
CLKSW
Remark: (fosc(int) is the internal oscillator frequency)
1
PRESL
0
PRES
[1]
TDA8026_1
Product data sheet
0
set to logic 0: when exiting Power-down mode and when the clock
is switched back to the fclk(ext) frequency[1]
1
set to logic 1: the card has been inserted or extracted
0
set to logic 0: after reading the byte
1
set to logic 1: the card is present
0
set to logic 0: the card is not present or has been removed
fclk(ext) is the external clock frequency applied to pins CLKIN1 and CLKIN2.
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8.5.3.3
Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) write mode
bit descriptions
Table 12.
Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) write
mode bit descriptions
Bit
Symbol
7
VCC1V8[1]
I/OEN[2]
6
Value
Description
used together with the 5V/3VN bit
1
set to logic 1: VCC(n) = 1.8 V; ignores the 5V/3VN bit logic state
0
set to logic 0: VCC(n) is set using the 5V/3VN bit
1
set to logic 1: pins I/OUCn are switched to pins I/O(n)
0
set to logic 0: pins I/OUCn and I/O(n) are high-impedance with
internal pull-up resistor
5 to 4
REG[1:0]
-
See Table 13 “Bank 1 CSb[7:0] Register0 (address 42h) card
slots 1 and card slots 2 bit allocation” on page 21 for detailed
information
3
PWDN[3]
1
set to logic 1 to apply the CLKPD[1:0] bit clock settings to pin
CLK(n) for the selected card slot
0
set to logic 0 to apply the CLKDIV[1:0] bits clock options to pin
CLK(n) for the selected card slot
1
used together with VCC1V8 bit.
2
5V/3VN[1]
set to logic 1 and the VCC1V8 bit is logic 0: VCC(n) = 5 V
0
1
0
TDA8026_1
Product data sheet
WARM
START
set to logic 0 and the VCC1V8 bit is logic 0: VCC(n) = 3 V
1
set to logic 1: a warm reset procedure is started
0
set to logic 0: by hardware when a START bit is detected or when
MUTE bit is set to logic 1
1
set to logic 1: starts the activation sequence and cold reset
procedure (only if the SUPL and PROT bits are logic 0 and the
PRES bit is logic 1)
0
set to logic 0: starts the deactivation sequence
[1]
This bit cannot be written when the START bit is logic 1.
[2]
It is a mandatory condition for card slots 2 to 5 that only one card slot I/O line is enabled at a time. When
switching from one slot to another, the enabled I/O must be disabled before the I/O line for the required card
slot is enabled.
Remark: If both pins I/OUC1 and I/OUC2 are connected at the same time, this mandatory condition also
applies to card slot 1.
[3]
In synchronous mode, this bit cannot be written when START bit is logic 1.
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TDA8026
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8.5.3.4
Bank 1 CSb[7:0] Register0 (address 42h) card slots 1 and card slot 2 bit allocation
Table 13.
Bank 1 CSb[7:0] Register0 (address 42h) card slots 1 and card slots 2 bit
allocation
Bit
7
6
5
4
3
2
1
0
Card slot 1 (address 01h) and Card slot 2 (address 02h)
Card Slot 1 Reg[1:0] = 00; see Table 14 on page 21
Symbol
-[1]
RSTIN
C8(1)
C4(1)
CLKPD[1:0][2]
CLKDIV[1:0][3]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Card Slot 2 Reg[1:0] = 00; see Table 14 on page 21
Symbol
CFGP2
RSTIN
Access
R/W
R/W
-[1]
R/W
R/W
CLKPD[1:0][2]
CLKDIV[1:0[3]]
R/W
R/W
R/W
R/W
Card Slot 1 and card slot 2 Reg[1:0] = 01; see Table 16 on page 23
Symbol
D[7:0]
Access
R/W
Card Slot 1 and card slot 2 Reg[1:0] = 10; see Table 18 on page 23
Symbol
C[15:8]
Access
R/W
Card Slot 1 and card slot 2 Reg[1:0] = 11; see Table 20 on page 23
8.5.3.5
Symbol
C[7:0]
Access
R/W
[1]
Reserved bit position.
[2]
CLKPD[2] = bit 3 and CLKPD[1] = bit 2.
[3]
CLKDIV[2] = bit 2 and CLKDIV[1] = bit 1.
Bank 1 Register1 (REG[1:0] = 00) card slot 1 (address 01h) and card slot 2
(address 02h) read/write mode bit descriptions
Table 14.
Bank 1 Register1 (REG[1:0] = 00) card slot 1 (address 01h) and card slot 2
(address 02h) Read/Write mode bit descriptions
Bit
Symbol
7
CFGP2[1]
6
RSTIN
Value
Description
enables another type of card detection switch to be used on card
socket 1 and card socket 2
1
if CFGP2 is logic 1, an interrupt is generated during each
power-up because the reset value of CFGP2 is logic level 0.
Refer to the Application note AN10724 for further information
0
the reset value of CFGP2 is logic 0. Refer to the Application
note AN10724 for further information
1
synchronous mode: when set to logic 1, pin RST(n) is set to HIGH
asynchronous mode: RSTIN is controlled by hardware (ATR
management)
TDA8026_1
Product data sheet
5
C8(1)[2]
4
C4(1)[2]
0
set to logic 0: pin RST(n) is LOW
-
writing C8(1) bit writes the corresponding value on C8(1) pin
-
reading C8(1) bit reads the state of C8(1) pin
-
writing C41 bit writes the corresponding value on C4(1) pin
-
reading C41 bit reads the state of C4(1) pin
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Multiple smart card slot interface IC
Table 14.
Bank 1 Register1 (REG[1:0] = 00) card slot 1 (address 01h) and card slot 2
(address 02h) Read/Write mode bit descriptions …continued
Bit
Symbol
Value
Description
3 to 2
CLKPD[1:0]
-
asynchronous mode: when PWDN bit is set to logic 1, the
CLKPD[1] and CLKPD[2] bits define the card clock
-
synchronous mode: when the PWDN bit and the START bit are
set to logic 1, the CLKPD[2] bit remains logic 0 and the clock
frequency is controlled by the CLKPD[1] bit
00
asynchronous mode: the card clock is stopped and set to
logic 0
-
synchronous mode: the card clock is set to logic 0
01
asynchronous mode: the card clock is stopped and set to
logic 1
-
synchronous mode: the card clock is set to logic 1
10
asynchronous mode: the card clock = f osc ( int ) ⁄ 2
Remark: (fosc(int) is the internal oscillator frequency)
11
1 to 0
CLKDIV[1:0]
asynchronous mode: the card clock frequency (f(clk)) is set using
the CLKDIV[1:0] bits.
asynchronous mode: when the PWDN bit is set to logic 0 the
CLKDIV[1:0] bits define the card clock frequency.
synchronous mode: the CLKDIV[1:0] bits are logic 0
00
[3]card
slot 1 card clock frequency = fclk(ext) on pin CLK(1)
card slot 2 card clock frequency = fclk(ext) on pin CLK(2)
01
card slot 1 card clock frequency = fclk(ext) / 2 on pin CLK(1)
card slots 2 card clock frequency = fclk(ext) / 2 on pin CLK(2)
10
card slot 1 card clock frequency = fclk(ext) / 4 on pin CLK(1)
card slot 2 card clock frequency = fclk(ext) / 4 on pin CLK(2)
11
card slot 1 card clock frequency = fclk(ext) / 5 on pin CLK(1)
card slot 2 card clock frequency = fclk(ext) / 5 on pin CLK(2)
8.5.3.6
[1]
Only for card slot 2 register.
[2]
Only for card slot 1 register.
[3]
fclk(ext) is the external clock frequency applied to pins CLKIN1 and CLKIN2.
Bank 1 Register1 (REG[1:0] = 01) card slot 1 (address 01h) and card slot 2
(address 02h) bit allocation
Table 15.
Bit
TDA8026_1
Product data sheet
Bank 1 Register1 (REG[1:0] = 01) card slot 1 (address 01h) and card slot 2
(address 02h) bit allocation
7
6
5
4
3
Symbol
D[7:0]
Access
R/W
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2
1
0
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Multiple smart card slot interface IC
8.5.3.7
Bank 1 Register1 (REG[1:0] = 01) card slot 1 (address 01h) and card slot 2
(address 02h) read/write mode bit descriptions
Table 16.
8.5.3.8
Bit
Symbol
Description
7 to 0
D[7:0]
programmable 8-bit clock counter. This value is applied to all slots. The
reset value is AAh. See Section 8.9 “Answer to reset counters” on page
35
Bank 1 Register1 (REG[1:0] = 10) card slot 1 (address 01h) and card slot 2 (address
02h) bit allocation
Table 17.
Bit
8.5.3.9
5
4
3
R/W
2
1
0
Bank 1 Register1 (REG[1:0] = 10) card slot 1 (address 01h) and card slot 2
(address 02h) read/write mode bit descriptions
Bank 1 Register1 (REG[1:0] = 10) card slot 1 (address 01h) and card slot 2
(address 02h) Read/Write mode bit descriptions
Bit
Symbol
Description
7 to 0
C[15:8]
most significant byte of a programmable 16-bit clock counter. This value
is applied to all slots. The reset value is A4h. See Section 8.9 “Answer
to reset counters” on page 35
Bank 1 Register1 (REG[1:0] = 11) card slot 1 (address 01h) and card slot 2
(address 02h) bit allocation
Bank 1 Register1 (REG[1:0] = 11) card slot 1 (address 01h) and card slot 2
(address 02h) bit allocation
7
6
5
4
3
Symbol
C[7:0]
Access
R/W
2
1
0
Bank 1 Register1 (REG[1:0] = 11) card slot 1 (address 01h) and card slot 2
(address 02h) read/write mode bit descriptions
Table 20.
Product data sheet
6
Access
Bit
TDA8026_1
7
C[15:8]
Table 19.
8.5.3.11
Bank 1 Register1 (REG[1:0] = 10) card slot 1 (address 01h) and card slot 2
(address 02h) bit allocation
Symbol
Table 18.
8.5.3.10
Bank 1 Register1 (REG[1:0] = 01) card slot 1 (address 01h) and card slot 2
(address 02h) Read/Write mode bit descriptions
Bank 1 Register1 (REG[1:0] = 11) card slot 1 (address 01h) and card slot 2
(address 02h) read/write mode bit descriptions
Bit
Symbol
Description
7 to 0
C[7:0]
least significant byte of a programmable 16-bit clock counter. This value
is applied to all slots. The reset value is 74h. See Section 8.9 “Answer
to reset counters” on page 35.
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Multiple smart card slot interface IC
8.5.4 Card slots 3 to 5 register descriptions
8.5.4.1
Bank 1 CSb[7:0] Register0 (address 40h) card slots 3 to 5 bit allocation
Table 21.
Bank 1 CSb[7:0] Register0 (address 40h) card slots 3 to 5 bit allocation
Bit
7
6
5
4
3
2
1
0
Card slot 3 (address 03h), Card slot 4 (address 04h) and Card slot 5 (address 05h)
8.5.4.2
Symbol
ACTIVE
EARLY
MUTE
PROT
SUPL
CLKSW
-[1]
STAP
Access
R[2]
R
R
R
R
R
R
R
Symbol
VCC1V8
I/OEN
PDWN
5V/3VN
WARM
START
Access
W[2]
W
W
W
W
W
REG[1:0]
W
W
[1]
Reserved bit position.
[2]
See table Table 22 for more detailed information on read mode bits and Table 23 for more detailed
information on write mode bits.
Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5
(address 05h) read mode bit descriptions
Table 22.
Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read mode bit descriptions
Bit
Symbol
7
ACTIVE
6
5
4
3
2
EARLY
MUTE
PROT
SUPL
CLKSW
Value
Description
1
set to logic 1: the card is active
0
set to logic 0: the card is inactive
1
set to logic 1: during ATR, when the card answers too early
0
set to logic 0: after reading the byte
1
set to logic 1: during ATR, when the card does not answer
according to the ISO 7816 time period
0
set to logic 0: after reading the byte
1
set to logic 1: during a card session when an overload or
overheating occurs
0
set to logic 0: after reading the byte
1
set to logic 1: the supervisor signaled a fault
0
set to logic 0: after reading the byte
1
set to logic 1: when the card slot is in Power-down mode and the
clock has switched to f osc ( int ) ⁄ 2
Remark: (fosc(int) is the internal oscillator frequency)
0
set to logic 0: when exiting Power-down mode and when the clock
is switched back to fclk(ext)
1
-
-
reserved
0
STAP
-
gives the value of the corresponding STAPn pin when read
When at least one of the SUPL, PROT, MUTE and EARLY bits are set to logic 1, the IRQN
pin is driven LOW until the status byte has been read. After power-on, the SUPL bit is set
to logic 1 until the status byte has been read and the IRQN pin is LOW until the voltage
supervisor is deactivated.
TDA8026_1
Product data sheet
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Multiple smart card slot interface IC
8.5.4.3
Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5
(address 05h) write mode bit descriptions
Table 23.
Bit
Symbol
7
VCC1V8[1]
I/OEN[2]
6
Description
used together with the 5V/3VN bit
1
set to logic 1: VCC(n) = 1.8 V; ignores the 5V/3VN bit logic state
0
if set to logic 0 VCC(n) is set using the 5V/3VN bit
1
set to logic 1: pins I/OUCn are switched to pins I/O(n)
0
set to logic 0: pins I/OUCn and I/O(n) are high-impedance with
internal pull-up resistor
REG[1:0]
-
see Table 24 “Bank 1 CSb[7:0] Register1 (address 42h) card
slots 3 and 5 bit allocation” on page 26 for detailed information
3
PWDN[3]
1
set to logic 1: to apply the CLKPD[1:0] bit clock settings to pin
CLK(n) for the selected card slot
0
set to logic 0: to apply the CLKDIV[1:0] bits clock options to pin
CLK(n) for the selected card slot
1
0
Product data sheet
Value
5 to 4
2
TDA8026_1
Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) write mode bit descriptions
5V/3VN[1]
WARM
START
used together with VCC1V8 bit
1
set to logic 1: and the VCC1V8 bit is logic 0: VCC(n) = 5 V
0
set to logic 0: and the VCC1V8 bit is logic 0: VCC(n) = 3 V
1
set to logic 1: a warm reset procedure is started
0
set to logic 0: by the hardware: a START bit is detected or the
MUTE bit is set to logic 1
1
set to logic 1: when the SUPL and PROT bits are logic 0 and the
PRES bit is logic 1, the activation sequence and cold reset
procedure are started
0
set to logic 0: deactivation sequence starts
[1]
This bit cannot be written when START bit is logic 1.
[2]
It is a mandatory condition for card slots 2 to 5 that only one card slot I/O line is enabled at a time. When
switching from one slot to another, the enabled I/O must be disabled before the I/O line for the required card
slot is enabled.
Remark: If both pins I/OUC1 and I/OUC2 are connected at the same time, this mandatory condition also
applies to card slot 1.
[3]
In synchronous mode, this bit cannot be written when START bit is logic 1.
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Multiple smart card slot interface IC
8.5.4.4
Bank 1 CSb[7:0] Register1 (address 42h) card slots 3 and 5 bit allocation
Table 24.
Bank 1 CSb[7:0] Register1 (address 42h) card slots 3 and 5 bit allocation
Bit
7
6
5
4
3
2
1
0
Card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h)
Reg[1:0] = 00
Symbol
-[1]
RSTIN
Access
R/W
R/W
-[1]
R/W
R/W
CLKPD[1:0][2]
CLKDIV[1:0[3]]
R/W
R/W
R/W
R/W
Reg[1:0] = 01
Symbol
D[7:0]
Access
R/W
Reg[1:0] = 10
Symbol
C[15:8]
Access
R/W
Reg[1:0] = 11
8.5.4.5
Symbol
C[7:0]
Access
R/W
[1]
Reserved bit position.
[2]
CLKPD[2] = bit 3 and CLKPD[1] = bit 2.
[3]
CLKDIV[2] = bit 2 and CLKDIV[1] = bit 1.
Bank 1 Register1 (REG[1:0] = 00) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode
Table 25.
Bank 1 Register1 (REG[1:0] = 00) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode
Bit
Symbol
Value
Description
7
-
-
reserved
6
RSTIN
1
synchronous mode: when set to logic 1, pin RST(n) is set to HIGH
asynchronous mode: RSTIN is controlled by the hardware (ATR
management)
5 to 4
TDA8026_1
Product data sheet
-
0
set to logic 0: RST(n) is set LOW
-
reserved
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Multiple smart card slot interface IC
Table 25.
Bank 1 Register1 (REG[1:0] = 00) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode …continued
Bit
Symbol
Value
Description
3 to 2
CLKPD[1:0]
-
asynchronous mode: when PWDN bit is set to logic 1, the
CLKPD[1] and CLKPD[2] bits define the card clock
-
synchronous mode: when the PWDN bit and the START bit are
set to logic 1, the CLKPD[2] bit remains logic 0 and the clock
frequency is controlled by the CLKPD[1] bit
00
asynchronous mode: the card clock is stopped and set to
logic 0
-
synchronous mode: the card clock is set to logic 0
01
asynchronous mode: the card clock is stopped and set to
logic 1
-
synchronous mode: the card clock is set to logic 1
10
asynchronous mode: the card clock = f osc ( int ) ⁄ 2
Remark: (fosc(int) is the internal oscillator frequency)
11
1 to 0
CLKDIV[1:0]
asynchronous mode: the card clock frequency (f(clk)) is set using
the CLKDIV[1:0] bits.
synchronous mode: the CLKDIV[1] and CLKDIV[2] bits are set to
logic 0 by the hardware
asynchronous mode: PWDN bit is logic 0, the CLKDIV[1] and
CLKDIV[2] bits define the card clock as follows:
8.5.4.6
Bit
Product data sheet
fclk(ext) / 2 on pin CLKIN2 for card slots 2 to 5
10
fclk(ext) / 4 on pin CLKIN2 for card slots 2 to 5
11
fclk(ext) / 5 on pin CLKIN2 for card slots 2 to 5
Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
7
6
5
4
3
Symbol
D[7:0]
Access
R/W
2
1
0
Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Table 27.
TDA8026_1
fclk(ext) on pin CLKIN2 for card slots 2 to 5
01
Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Table 26.
8.5.4.7
00
Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Bit
Symbol
Description
7 to 0
D[7:0]
programmable 8-bit clock counter. This value applies to all slots. The
reset value is AAh. See Section 8.9 “Answer to reset counters” on page
35
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NXP Semiconductors
Multiple smart card slot interface IC
8.5.4.8
Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Table 28.
Bit
8.5.4.9
6
5
4
3
C[15:8]
Access
R/W
2
1
0
Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Bit
Symbol
Description
7 to 0
C[15:8]
most significant byte of a programmable 16-bit clock counter. This value
applies to all slots. The reset value is A4h. See ATR Section 8.9
“Answer to reset counters” on page 35
Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Table 30.
Bit
8.5.4.11
7
Symbol
Table 29.
8.5.4.10
Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
7
6
5
4
3
Symbol
C[7:0]
Access
R/W
2
1
0
Bank 1: Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4
(address 04h) and card slot 5 (address 05h) read/write mode bit descriptions
Table 31.
Bank 1: Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4
(address 04h) and card slot 5 (address 05h) read/write mode bit descriptions
Bit
Symbol
Description
7 to 0
C[7:0]
least significant byte of a programmable 16-bit clock counter. This value
applies to all slots. The reset value is 74h. See Section 8.9 on page 35
8.5.5 Selection of asynchronous or synchronous mode
When the activation sequence starts, the selected card slot on the TDA8026 uses the
RSTIN bit value to configure itself for use with asynchronous or synchronous cards. If the
RSTIN bit is set to logic 1 at the activation sequence start (the START bit changes from
LOW to HIGH), the TDA8026 will manage asynchronous cards.
In asynchronous mode, the card slot RST(n) pin is controlled by the corresponding ATR
counter (see Section 8.9 on page 35).
In synchronous mode, the card slot RST(n) pin is controlled by the corresponding RSTIN
bit. The card clock configuration is set by the PWDN bit value at the activation sequence
start of the selected card slot (the START bit changed from LOW to HIGH).
TDA8026_1
Product data sheet
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© NXP B.V. 2010. All rights reserved.
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Multiple smart card slot interface IC
• If the PDWN bit is set to logic 0 at the start of the activation, the card clock value is the
CLKIN1 pin frequency for card slot 1 and the CLKIN2 pin frequency for card slots 2
to 5. If CLKDIV[1:0] = 00, the first four clock cycles are not transferred to CLK(n).
When CLKDIV[1:0] = 01, 10 or 11, the first five clock cycles are not transferred to
CLK(n).
• If the PDWN bit is set to logic 1 at the start of the activation, the clock uses the
CLKPD1 bit.
The card clock frequency and the stop state are configured using the CLKDIV[1:0] and
CLKPD[1:0] bits. Refer to Table 32 for the configuration in asynchronous mode and
Table 33 for synchronous mode.
Table 32.
Asynchronous mode card clock settings
PWDN bit
CLKDIV[1:0] bit
CLKPD[1:0] bit
Card clock (CLK)
0
00
-
fclk(ext)
0
01
-
fclk(ext) / 2
0
10
-
fclk(ext) / 4
0
11
-
fclk(ext) / 5
1
-
00
logic 0
1
-
01
logic 1
1
-
10
f osc ( int ) ⁄ 2
1
-
11
fclk(ext) / x (no change)
Table 33.
Synchronous mode card clock settings
PWDN bit
CLKDIV[1:0] bit
CLKPD[1:0] bit Card clock (CLK)
logic 1 at activation sequence start
-
x0
logic 0
logic 1 at activation sequence start
-
x1
logic 1
-
xx
fclk(ext)
logic 0 at activation sequence
[1]
start[1]
If CLKDIV[1:0] = 00, the first four clock cycles are not transferred to CLK(n). When CLKDIV[1:0] is not 00,
the first five clock cycles are not transferred to CLK(n).
fclk(ext) is the clock input frequency on either pin CLKIN1 or pin CLKIN2 depending on the
card slot number.
During transitions, no pulse is shorter than 45 % of the smallest period and both the
first/last clock pulse around the change have the correct width; making the frequency
change synchronous.
When changing the card clock frequency from one fclk(ext) frequency division to another,
the modification is only active after the next rising clock edge.
Any change after switching the card clock frequency from an external fclk(ext) frequency
division to the internal oscillator frequency (fosc(int)) is not immediate. The change is
indicated by the state of the CLKSW bit (see the register descriptions in Table 11 and
Table 22). In addition, it is assumed that the fclk(ext) / x frequency division is less than or
equal to 6.25 MHz.
TDA8026_1
Product data sheet
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Multiple smart card slot interface IC
8.5.6 General registers
8.5.6.1
Bank 1 General registers (address: 40h, 42h; CSb[7:0] = 00h, 06h) bit allocation
Table 34.
Bit
Bank 1 General registers (addresses: 40h, 42h; CSb[7:0] = 00h, 06h) bit
allocation
7
6
5
4
3
2
1
0
Address 40h; CSb[7:0] = 00h, see Table 35
Symbol
PV[7:0]
Access
R
Address 40h; CSb[7:0] = 06h
Symbol
CLK_SR[3:2]
IO_SR[3:2]
CLK_SR[1:0]
IO_SR[1:0]
Access
R/W
R/W
R/W
R/W
Address 42h; CSb[7:0] = 00h
8.5.6.2
Symbol
-[1]
INTAUX
INT[4:0][2]
Access
R
R
R
[1]
Reserved bit position.
[2]
The INT numbers do not match the bit positions and are as follows:
bit 4 = INT5, bit 3 = INT4, bit 2 = INT3, bit 1 = INT2 and bit 0 = INT1
Bank 1 Product version register (address 40h; CSb[7:0] = 00h) read mode bit
descriptions
Table 35.
TDA8026_1
Product data sheet
Bank 1 Product version register (address 40h; CSb[7:0] = 00h) read mode bit
descriptions
Bit
Symbol
Description
7 to 0
PV[7:0]
reading this register returns the product version. The MSB nibble is
C (commercial product) and the LSB nibble is 2 (release number)
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Multiple smart card slot interface IC
8.5.6.3
Bank 1 Interrupt register (address 42h; CSb[7:0] = 00h) read mode bit descriptions
Table 36.
Bank 1 Interrupt register (address 42h; CSb[7:0] = 00h) read mode bit
descriptions
Bit
Symbol
Value
Description
7 to 6
-
-
reserved
5
INTAUX
-
auxiliary interrupt line
4 to 0
INT[4:0][1]
These interrupt bits remain at logic 1 until the interrupt SUPL,
PROT, MUTE and EARLY bits have been read
INT5: card slot 5 interrupt:
1
set to logic 1: when any of the bits SUPL, PROT, MUTE and
EARLY are set to logic 1
0
set to logic 0: when any of the bits SUPL, PROT, MUTE and
EARLY are set to logic 0 when read
INT4: card slot 4 interrupt:
1
set to logic 1: when any of the bits SUPL, PROT, MUTE and
EARLY are set to logic 1
0
set to logic 0: when any of the bits SUPL, PROT, MUTE and
EARLY are set to logic 0 when read
INT3: card slot 3 interrupt:
1
set to logic 1: when any of the bits SUPL, PROT, MUTE and
EARLY are set to logic 1
0
set to logic 0: when any of the bits SUPL, PROT, MUTE and
EARLY are set to logic 0 when read
INT2: card slot 2 interrupt:
1
set to logic 1: when any of the bits PRESL, SUPL, PROT, MUTE
and EARLY are set to logic 1
0
set to logic 0: when any of the bits PRESL, SUPL, PROT, MUTE
and EARLY are set to logic 0 when read
INT1: card slot 1 interrupt:
[1]
8.5.6.4
1
set to logic 1: when any of the bits PRESL, SUPL, PROT, MUTE
and EARLY are set to logic 1
0
set to logic 0: when any of the bits PRESL, SUPL, PROT, MUTE
and EARLY are set to logic 0 when read
The INTx numbers do not match the bit positions and are as follows:
bit 4 = INT5, bit 3 = INT4, bit 2 = INT3, bit 1 = INT2 and bit 0 = INT1
Bank 1 Slew rate register (address 40h; CSb[7:0] = 06h) read/write mode bit
descriptions
Table 37.
Bank 1 Slew rate register (address 40h; CSb[7:0] = 06h) read/write mode bit
descriptions
Bit
Symbol
Description
7 to 6
CLK_SR[3:2]
card slot 2 to 5 clock slew rate selection
5 to 4
IO_SR[3:2]
card slot 2 to 5 I/O slew rate selection
3 to 2
CLK_SR[1:0]
card slot 1 clock slew rate selection
1 to 0
IO_SR[1:0]
card slot 1 I/O slew rate selection
Refer Section 8.10 on page 37 for more detailed information.
TDA8026_1
Product data sheet
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Rev. 1 — 9 March 2010
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Multiple smart card slot interface IC
8.6 DC-to-DC converter
The DC-to-DC converter has been designed to provide an average of 5.4 V to the
programmable voltage regulators (5 V, 3 V and 1.8 V) for the card slots. It is capable of
delivering a total DC current of 116 mA to the card slots.
If the total current from all card slots exceeds 170 mA, the overcurrent/overload protection
deactivates the DC-to-DC converter. The addition of a 10 µH external coil and Schottky
diode ensures the DC-to-DC converter operates at an input voltage range between 2.7 V
and 5.5 V.
When the DC-to-DC converter cannot act as a step-up converter, an overload alarm is
sent to the digital module and all card slot interfaces are deactivated. This causes the
IRQN line to be driven LOW and the Bank 1 Register 0 PROT bit is set to logic 1.
The DC-to-DC converter is deactivated when the TDA8026 is in shutdown mode.
The card slots can be directly supplied by the VDD supply voltage, if it is always above
5.25 V, thus removing the need to use the DC-to-DC converter. In this situation, the supply
voltage can be directly applied to the VUP and LX pins as shown in Figure 9.
VDD(INTF)
VDD(INTF)
VDD > 5.25 V
VDD(INTF)
VDD
LX
DC-to-DC CONVERTER
DCDC_OFF
VUP
10 µF
GNDP
001aal090
Fig 9.
The DC-to-DC converter
When DCDC_OFF is set to VDD(INTF), the DC-to-DC converter is shutdown:
• the output power transistors are switched OFF
• the DC-to-DC converter current consumption is 0 A.
8.7 VCC buffer
The current on the VCC buffer is internally limited to approximately 100 mA. When this limit
is reached, the automatic deactivation sequence is performed. Each card slot has its own
limitation and deactivation of one card slot does not affect the other card slots.
The VCC(n) voltage should be decoupled with two low ESR 100 nF (minimum) capacitors.
One capacitor should be placed close to the VCC pin of the device and the other close to
the C1 pin of the card connector. See Figure 14 for detailed information.
8.8 Sequencer and clock counter
Each card slot has a dedicated sequencer and clock counter.
The sequencer ensures that the activation and deactivation sequences meet the
ISO 7816 and EMV 4.2 standards, even during an emergency deactivation caused by
card removal during transaction, supply drop out or a hardware problem. The sequencer
is clocked with an internal oscillator (fosc(int)).
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Multiple smart card slot interface IC
Card slot 1 or card slot 2 can only be activated if a card is detected as present in the slot
and if an alarm is not triggered by the voltage supervisor. When both of these parameters
are met, the card slots can be activated by setting the Command register START bit. The
activation sequence is described in Section 8.8.2.
Card slots 3 to 5 do not have presence monitoring. The corresponding STAP pin is used
for card presence detection on these slots.
The deactivation is initiated by the system controller or automatically in the case of a
hardware problem or a supply drop out. The deactivation sequence is described in
Section 8.8.3.
Outside a session, the card contacts are forced to low-impedance with respect to the
GNDC pin.
8.8.1 Standby mode
Standby mode is the default state after a power-on reset. This mode ensures the power
consumption remains low until a card is inserted or the microcontroller starts a card
session. When there is not an ongoing card session, the internal oscillator runs at its low
frequency (t15).
A debouncing time of 17.8 ms is applied to card slot 1 and card slot 2 to allow for card
insertion (presence) detection.
8.8.2 Activation sequence
When the card is inactive, pins VCC(n), CLK(n), RST(n) and I/O(n) are LOW which is
low-impedance with respect to pin GNDC(n) or pin GNDS depending of the card slot.
The sequencer is clocked by an internal oscillator. When everything is satisfactory
(voltage supply, card presence, no hardware problem), the system controller can trigger
the card present activation sequence by setting card slot’s START bit to logic 1:
•
•
•
•
The internal oscillator switches to its high frequency (t0, see Figure 10).
The DC-to-DC converter starts (t1).
VCC(n) starts to rise from 0 V to 1.8 V, 3 V or 5 V during the controlled rise time (t2).
The voltage on the I/O(n) pin rises to VCC(n), due to integrated 10 kΩ pull-ups for
VCC(n) (t3).
CLK(n) clock signal is sent to the card (t4 = tact) and the RST(n) pin is enabled. The RST(n)
pin is managed by the ATR counter or the Register1 RSTIN bit depending on the card slot
mode (asynchronous or synchronous).
f osc ( int )
The sequencer is clocked by ------------------- which leads to a time interval T = 25 µs (typical).
64
3T
7T
Thus, t 1 = 0 , t 2 = t 1 + ------- , t 3 = t 1 + ------- and t 4 = t 1 + 4T .
2
2
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START
internal clock low frequency
oscillator
high frequency
internal DC-to-DC
converter enable
VCC(n)
I/O(n)
CLK(n)
RST(n)
0
t1
1
2
3
t2
4
5
6
7 8
t3 t4
T/2
9 10 11 12 13 14
001aal096
Fig 10. The card slot activation sequence
In Figure 10 only one card slot is activated. If another card slot is active, the DC-to-DC
converter remains active.
8.8.3 Deactivation sequence
When the session finishes, the microcontroller resets the START bit to logic 0 (Figure 11)
and the following deactivation sequence is performed:
•
•
•
•
•
•
Card reset: RST(n) pin falls to 0 V (t11).
Pin CLK(n) is stopped (t12).
Pin I/O(n) falls to 0 V (t13).
Pin VCC(n) falls to 0 V with a controlled slew rate (t14).
The DC-to-DC converter is stopped.
Pins CLK(n), RST(n), VCC(n) and I/O(n) are driven to 0 V with a low-impedance switch
attached to pin GNDS (t15).
• The internal oscillator switches to its low frequency (t15)
T
3T
7T
Thus, t 11 = 0 , t 12 = t 11 + --- , t 13 = t 11 + T , t 14 = t 11 + ------- and t 15 = t 11 + ------- .
2
2
2
The deactivation time tdeact is the time that VCC(n) needs to be driven below 0.4 V, counting
from the moment START bit is reset.
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Multiple smart card slot interface IC
START
RST(n)
CLK(n)
I/O(n)
VCC(n)
internal DC-to-DC
converter enable
internal clock
oscillator
high frequency
0 1 2 3 4
t11 t12 t13 t14
low frequency
5
6
7
t15
T/2
001aal091
Fig 11. Deactivation sequence
In Figure 11 only one card slot is active. If another card slot is active, the DC-to-DC
converter is still active.
8.9 Answer to reset counters
Each TDA8026 card slot has its own sequencer. The sequencer controls the activation
and deactivation sequences. In addition to these sequencers, there are two Answer To
Reset (ATR) counters:
• ATR dedicated to card slot 1
• ATR dedicated to the other slots
The operating mode (asynchronous or synchronous) has to be selected by the
microcontroller. The ATR counters are used in asynchronous mode to manage the RST(n)
pin and to check the card’s ATR. In synchronous mode, the RST pin is controlled by the
microcontroller using the RSTIN bit (see the bit description in Table 11 on page 19 and
Table 22 on page 24) and the card’s ATR is not checked.
The ATR counter module comprises two counters:
• EARLY answer counter: The early answer counter consists of a fixed part which
counts up to 200 clock cycles. The secondary part counts up to the D[7:0] bits value of
clock cycles (see the register descriptions in Table 16 on page 23 and Table 27 on
page 27). The default D[7:0] bits value is 170 which gives a total default count of
370 clock cycles
• MUTE counter: The mute counter counts up to C[15:8] and C[7:0] bits value for the
clock cycles (see the register descriptions in Table 22 on page 24 and Table 30 on
page 28). The default value of the C[15:0] bits is 42100 which gives a default count of
42100 clock cycles.
Both counters can be easily quickly reprogrammed, if for example, a card does not
fully meet the EMVCo/ISO7816 standards or to enable the implementation of new and
enhanced standards.
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When operating, the microcontroller starts to configure the selected card slot (card supply
voltage) and then triggers the activation sequence using the START bit. The sequencer
then performs the activation sequence. The DC-to-DC converter is started, pin VCC(n) is
set to the previously configured card supply voltage, pin I/O(n) is enabled and CLK(n) starts
(see Section 8.8.2 on page 33 and Section 8.8.3 on page 34). Pin RST(n) is set to LOW.
The ATR counter dedicated to the card slot makes the following checks and takes the
steps required:
• START bits from a card detected on pin I/O(n) during the first 200 clock cycles are
ignored and the count continues.
• START bits from a card detected while pin RST(n) is set to LOW, with the number of
clock cycles between 200 and the C[15:0] bits value (default 42100), cause the
EARLY and MUTE bits to be set to logic 1. Pin RST(n) remains LOW and the
microcontroller decides if it will accept the card.
• START bits detected after the number of clock cycles is equal to the C[15:0] bits value
cause pin RST(n) to be set to HIGH.
• START bits received from the card when the first number of clock cycles is equal to
the D[7:0] bits value (default 370) and pin RST(n) set to HIGH cause the EARLY bit to
be set to logic 1.
• Cards not answering before 42100 clock cycles (or the C[15:0] bits value) with RST(n)
set to HIGH cause the MUTE bit to be set to logic 1.
• Cards answering within the correct time frame, stops the clock cycles count and the
microcontroller can send commands to the card.
Figure 12 shows the timings checked by the ATR counters.
VCC(n)
I/O(n)
CLK(n)
RST(n)
200 CLK
cycles (I/O
ignored)
370 CLK
cycles (early
answer check)
42100 CLK cycles
answer check
(EARLY and MUTE bits)
200 CLK
cycles (I/O
ignored)
42100 CLK cycles
(mute check)
370 CLK
cycles (early
answer check)
42100 CLK cycles
42100 CLK cycles
(mute check)
answer check
(EARLY and MUTE bits)
WARM
cold reset
warm reset
001aal092
Fig 12. ATR counter timing check
When the EARLY and MUTE bits are set to logic 1, they signal an interrupt (see the bit
descriptions in Table 12 on page 20, Table 22 on page 24 and Table 36 on page 31).
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The sequence described in Section 8.9 relates to a cold reset. If the card is mute (has not
answered), the microcontroller can start a warm reset by setting WARM bit to logic 1 (see
the bit descriptions in Table 11 on page 19 and Table 22 on page 24). Then, the ATR
counter set pin RST(n) to LOW and performs the same timing checks (see Figure 12).
Remark: It is assumed that two card activations will not take place simultaneously on card
slots 2 to 5 because only one I/O(n) line is available for these four slots. There is no
protection on the second ATR counter against starting an activation while a count is
ongoing. The first ATR counter is dedicated to the slot 1. Consequently, it is mandatory to
enable only one slot I/O(n) line at the same time for card slots 2 to 5. When switching from
one slot to another one, it is mandatory to first disable the slot I/O(n) line in use before
enabling the slot I/O(n) line required. During this transition, no I/O(n) lines are enabled for
card slots 2 to 5. This allows the ATR counter to be reset between card slot switching
actions. If both pins I/OUC1 and I/OUC2 are connected at the same time, this mandatory
condition also applies to card slot 1.
8.10 Slew rate control
Slew rate control is embedded for the clock buffer and the I/O(n) line of each card slot. The
rising and falling edge of the card clock signal can be configured using 2 bits in Register6
of bank 1. The settings based on a 30 pF load capacitance and a VCC(n) = 5 V are shown
in Table 38.
Table 38.
Clock Slew rate
CLK_SR[1]
(high)
CLK_SR[2] (low)
Rise and fall time (ns)
L
L
10
L
H
7
H
L
6
H
H
5
[1]
The high slots are define by [1] (slot 1) and [3] (all other slots).
[2]
The low slots are define by [0] (slot 1) and [2] (all other slots).
The rise and fall time is calculated from 10 % to 90 % and 90 % to 10 % (respectively) of
the signal amplitude. The default setting for CLK_SR[1]/CLK_SR[3] (high) is LOW and
CLK_SR[0]/CLK_SR[2] (low) is HIGH.
Only the falling edge of the card I/O(n) signal can be configured with the two
programmable bits in Register6 of bank 1. The settings based on a 30 pF load
capacitance and a VCC(n) = 5 V are shown in Table 39 on page 37:
Table 39.
IO_SR[1]
TDA8026_1
Product data sheet
I/O slew rate
IO_SR[2] (low)
Fall time (ns)
L
L
67
L
H
54
H
L
35
H
H
17
(high)
[1]
The high slots are define by [1] (slot 1) and [3] (all other slots).
[2]
The low slots are define by [0] (slot 1) and [2] (all other slots).
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The fall time is calculated from 90 % to 10 % of the signal amplitude. The default setting
for IO_SR[0]/IO_SR[2] (low) and IO_SR[1]/IO_SR[3] (high) is LOW (see table Table 39 on
page 37).
8.11 Fault detection
The following fault conditions are monitored by the TDA8026.
• Overheating: All the card slots are automatically deactivated and the device is forced
in to Standby mode when the detected temperature range is between
125 °C to 209 °C. The card slot PROT bit is set to logic 1. Above 209 °C the device is
shutdown.
• Card removal during transaction: A deactivation sequence is performed in
accordance with the EMV 4.2 standard.
• DC-to-DC converter overload: All card slots are automatically deactivated and the
device is placed in Standby mode when the current supplied by the DC-to-DC
converter exceeds 170 mA (ICC parameter for VCC(n)). The card slot PROT bit is set to
logic 1
• Card slot current limitation and deactivation: A current level drawn by a card which
exceeds 120 mA (Isd parameter for VCC(n)) triggers the deactivation sequence on the
faulty card slot. During the deactivation, the current is limited to approximately
110 mA. The card slot PROT bit is set to logic 1
• VDD or VDD(INTF) dropping: A voltage drop occurring on VDD or VDD(iNTF) generates
card slot deactivation followed by a device reset. The completion of this phase is
validated when the SUPL bits are set to logic 1.
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9. Limiting values
Table 40. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
on pin VDD
−0.5
+6
V
VDD(INTF)
interface supply
voltage
on pin VDD(INTF)
−0.5
+4.6
V
VIH
HIGH-level input
voltage
on all card pins
−0.5
+6
V
output voltage
Vo
−0.5
+4.6
V
on pin LX
[1]
−0.5
+7.2
V
DC-to-DC converter output on pin
VUP
[1]
−0.5
+7.2
V
-
665
mW
−55
+150
°C
−7
+7
kV
−2
+2
kV
−200
+200
V
−500
+500
V
on all other pins
Tamb = −25 °C to +85 °C
Ptot
total power
dissipation
Tstg
storage
temperature
VESD
electrostatic
discharge voltage
[2]
HBM
on I/O(n), VCC(n), CLK(n), GNDC(n),
PRES, RST(n), C4(1), C8(1) card
pins
on all other pins
[3]
MM
on all pins
CDM
on all pins
[1]
The limiting values depend on the external inductor and VUP decoupling capacitor used.
[2]
Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the
remaining. Method 3015 (HBM; 1500 Ω; 100 pF) defines three pulses positive and three pulses negative on
each pin referenced to ground.
[3]
The 7 kV ESD test is performed in the typical application configuration as depicted in the Application note
AN10724 with two external capacitors connected to each VCC(n) line.
10. Thermal characteristics
Table 41.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
[1]
TDA8026_1
Product data sheet
Conditions
thermal resistance from junction to ambient
[1]
Typ
Unit
47.1
K/W
With a 4-layer board
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11. Characteristics
Table 42. Supply
VDD = VDD(INTF) = 3.3 V; fclk(ext)[1] = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on
pins VDD and VUP = 10 µF; Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
supply voltage
VDD
Vhys
hysteresis
voltage
VDD(INTF) interface supply
voltage
Min Typ Max Unit
on pin VDD; DC-to-DC converter on
[2]
2.7
-
5.5
V
on pin VDD; DC-to-DC converter off;
VCC(n) pins = 5 V
[2]
5.25 -
5.5
V
on pin VDD
[3]
50
100 150 mV
1.6
-
on pin VDD(INTF)
threshold voltage decreasing voltage on pin VDD
Vth
on pin VDD(INTF)
supply current
IDD
interface supply
current
[3]
2.35 2.45 2.55 V
[4]
1.19 1.26 1.32 V
25
Standby mode
-
300 450 µA
clock-stop mode; All card slots in this
mode; fclk(ext) = stopped on pins
CLKIN1 and CLKIN2
-
3.7
-
210 260 mA
shutdown mode
-
10
15
µA
active mode; All VCC(n) pins = 5 V;
fclk(ext) = 5 MHz;
-
35
-
µA
[5]
40
µA
-
increasing voltage on pin VDD
twake
V
shutdown mode
active mode; All VCC(n) pins = 5 V;
fclk(ext) = 5 MHz;
ICC(1) = ICC(2) = 55 mA;
ICC(3) = ICC(4) = ICC(5) = 2 mA
IDD(INTF)
3.6
-
mA
[6]
[3]
wake-up time
2.35 2.55 2.65 V
5.8
[1]
fclk(ext) is the external clock frequency applied to pins CLKIN1 and CLKIN2.
[2]
Refer to Section 8.6 for further information about DC-to-DC converter operation.
-
11
ms
[3]
See Figure 6 “The voltage supervisor circuit” on page 11.
[4]
See Section 8.3.2 “Description” for a description of the voltage supervisor.
[5]
Typical value measurement based on a 85 % DC-to-DC converter and inductance efficiency; depends on
PCB layout and external component quality (inductor, capacitor).
[6]
Maximum measurement value based on a 125 mA ICC current load and a 75 % DC-to-DC converter and
inductance efficiency; depends on PCB layout and external component quality (inductor, capacitor).
Table 43. Supply supervisor
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on
pins VDD and VUP = 10 µF; Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max
Unit
PORADJ Pin
TDA8026_1
Product data sheet
IL
leakage current
−1
-
+1
µA
IIL
LOW-level input current
−1
-
+1
µA
IIH
HIGH-level input
current
−1
-
+1
µA
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Table 44. DC-to-DC converter
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins V and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
fosc(int)
internal oscillator
frequency
Vo
output voltage
Vi
ton(DCDC)
Conditions
Min
Typ
Max
Unit
2.1
2.8
3.5
MHz
from DC-to-DC converter;
DC-to-DC converter on; not
bypassed
5.25
5.5
-
V
input voltage
pin LX input voltage; DC-to-DC
converter on; not bypassed
-
-
7.2
V
DC-to-DC converter
turn-on time
VDD < 4.2 V
-
1.4
-
µs
VDD > 4.2 V
-
0.35
-
µs
Table 45. Card drivers
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Card supply voltage: VCC(1) to VCC(5)
[1]
VCC
Standby mode
supply voltage
−0.1
-
+0.1
V
−0.1
-
+0.3
V
5 V card; DC ICC(n) ≤ 55 mA
4.75
5
5.25
V
3 V card; DC ICC(n) ≤ 55 mA
2.85
3
3.15
V
1.71
1.8
1.89
V
5 V card; 40 nAs current
spikes
4.65
-
5.35
V
3 V card; 17.5 nAs current
spikes
2.76
-
3.24
V
1.8 V card; 11.1 nAs current
spikes
1.62
-
1.98
V
-
-
350
mV
active mode; AC current pulses
with I < 200 mA, t < 400 ns and
f < 20 MHz
TDA8026_1
Product data sheet
Unit
Io = 1 mA
[2]
1.8 V card; DC ICC(n) ≤ 35 mA
peak-to-peak ripple
voltage
Max
no load
active mode;
2.7 V < VDD < 5.5 V
Vripple(p-p)
Typ
on pins VCC(n); 20 kHz < card
clock frequency < 200 MHz
[2]
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Table 45. Card drivers …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC
supply current
Standby mode and pin VCC(n)
grounded
-
-
−1
mA
5 V card
-
-
55
mA
3 V card
-
-
55
mA
1.8 V card
-
-
35
mA
active mode;
2.7 V < VDD < 5.5 V
sum of all card supply currents
on pins VCC(n); active mode; All
VCC pins = 5 V; fclk(ext) on pins
CLK(n) = 5 MHz;
ICC(1) = ICC(2) = 55 mA;
ICC(3) = ICC(4) = ICC(5) = 2 mA
[5]
-
116 125
mA
SR
slew rate
rising; maximum CL = 200 nF;
5 V, 3 V and 1.8 V cards
0.06
0.16
0.27
V/µs
Cdec
decoupling capacitance
connected to VCC(n); 100 nF and
100 nF at 20 %
160
200
240
nF
no load
0
-
0.1
V
Io = 1 mA
0
-
0.3
V
Card reset output pins: RST(1) to RST(5)
Vo
output voltage
Standby mode
Io
output current
Standby mode and pin RST(n)
grounded
0
-
−1
mA
VOL
LOW-level output
voltage
IOL ≤ 200 µA
0
-
0.3
V
IOL ≤ 20 mA
VCC(n) − 0.4
-
VCC(n)
V
VOH
HIGH-level output
voltage
−200 µA ≤ IOH ≤ 0
VCC(n) − 0.5
-
VCC(n)
V
−20 mA ≤ IOH ≤ 0
0
-
0.4
V
tr
rise time
CL = 100 pF; 10 % to 90 %
-
-
0.1
µs
tf
fall time
CL = 100 pF; 90 % to 10 %
-
-
0.1
µs
no load
0
-
0.1
V
Io = 1 mA
0
-
0.3
V
Clock to card output pins: CLK(1) to CLK(5); default register values
Vo
output voltage
Standby mode
Io
output current
Standby mode and CLK(n) pin
grounded
0
-
−1
mA
VOL
LOW-level output
voltage
IOL ≤ 200 µA
0
-
0.3
V
IOL ≤ 70 mA
VCC(n) − 0.4
-
VCC(n)
V
VOH
HIGH-level output
voltage
−200 µA ≤ IOH ≤ 0
VCC(n) − 0.5
-
VCC(n)
V
−70 mA ≤ IOH ≤ 0
0
-
0.4
V
tr
rise time
CL = 30 pF; 10 % to 90 %
-
-
7
ns
tf
fall time
CL = 30 pF; 90 % to 10 %
-
-
7
ns
fCLK
frequency on pin CLK
all CLK(n) pins; operating
0
-
20
MHz
TDA8026_1
Product data sheet
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
42 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 45. Card drivers …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
δclk
clock duty cycle
CL = 30 pF
45
-
55
%
SR
slew rate
rise and fall; CL = 30 pF;
90 % to 10 %
0.2
-
V/ns
Data line pins: I/O(1) to I/O(5), C4(1) and C8(1)
Vo
output voltage
Standby mode
no load
0
-
0.1
V
Io = 1 mA
-
-
0.3
V
-
−1
mA
Io
output current
Standby mode and I/O(n), C4(1)
or C8(1) pins grounded.
0
VOL
LOW-level output
voltage
IOL ≤ 1 mA
0
-
0.3
V
IOL ≤ 15 mA
VCC(n) − 0.4
-
VCC(n)
V
HIGH-level output
voltage
no DC load
0.9VCC(n)
-
VCC(n) + 0.1
V
−20 µA ≤ IOH ≤ 0
0.8VCC(n)
-
VCC(n) + 0.1
V
−40 µA ≤ IOH ≤ 0
0.7VCC(n)
-
VCC(n) + 0.1
V
−15 mA ≤ IOH ≤ 0
0
-
0.4
V
−0.3
-
+0.8
V
0.6VCC(n)
-
VCC(n)
V
VOH
VIL
LOW-level input voltage
All VCC(n)
VIH
HIGH-level input voltage VCC(n) = 5 V and 3 V
VCC(n) = 1.8 V
0.7VCC(n)
-
VCC(n)
V
Vhys
hysteresis voltage
on I/O(n)
-
50
-
mV
IIL
LOW-level input current
0 V applied to pin
[3]
-
-
650
µA
[3]
-
-
10
µA
[3]
1
-
-
mA
-
400
ns
ILIH
HIGH-level input
leakage current
VIH = VCC(n)
Ipu
pull-up current
VOH = 0.9VCC(n); CL = 30 pF
[3][4]
td
delay time
falling edge on pins I/O and
I/O(n) or vice versa
tr(i)
input rise time
VIL minimum to VIH maximum;
10 % to 90 %
-
-
1.2
µs
tf(i)
input fall time
VIL maximum to VIH minimum;
90 % to 10 %
-
-
1.2
µs
tr(o)
output rise time
VIL minimum to VIH maximum;
10 % to 90 %
-
-
0.1
µs
tf(o)
output fall time
VIL maximum to VIH minimum;
90 % to 10 %
-
-
0.1
µs
Ci
input capacitance
Rpu
pull-up resistance
fmax
maximum frequency
TDA8026_1
Product data sheet
[3]
-
-
10
pF
between pins I/O(n) or C4(1) or
C8(1) and VCC(n)
[3]
8
10
12
kΩ
input clock
[3]
-
-
500
kHz
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
43 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 45. Card drivers …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Card presence input: pin PRES; active HIGH when SPRES pin = LOW or active LOW when SPRES pin = HIGH
VIL
LOW-level input voltage
−0.3
-
+0.2 VDD(INTF)
VIH
HIGH-level input voltage
0.8 VDD(INTF)
-
VDD(INTF) + 0.3 V
ILIL
LOW-level input leakage Vi = 0.2VDD(INTF)
current
-
-
70
µA
ILIH
HIGH-level input
leakage current
-
-
5
µA
tdeb
debounce time
-
17.8
23.8
ms
Vi = 0.8VDD(INTF)
V
[1]
Two ceramic multilayer capacitors of minimum 100 nF with low Equivalent Series Resistance (ESR) should be used in order to meet
these specifications.
[2]
Output voltage towards the card, including ripple.
[3]
I/O(n) pin has an internal 10 kΩ pull-up resistor to VCC(n).
[4]
I/OUCn pin has an internal 11 kΩ pull-up resistor to VDD(INTF).
[5]
Maximum value measurement based on a 125 mA (sum of all card supply currents on pins VCC(n)) current load and a 75 % DC-to-DC
converter and inductance efficiency; depends on PCB layout and external component quality (inductor, capacitor).
Table 46. Sequencer and clock counter
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tact
activation time
total sequence
[1]
-
-
135
µs
[1]
60
80
100
µs
-
25
-
µs
tdeact
deactivation time
total sequence
Tclk
clock period
sequencer
[1]
Refer to Section 8.8.3 for further information.
Table 47. Interface signals to microcontroller
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
0
-
0.3
V
no DC load
0.9 VDD(INTF)
-
VDD(INTF) + 0.2
V
−10 µA ≤ IOH ≤ 0
0.75 VDD(INTF)
-
VDD(INTF) + 0.2
V
Data line pins: I/OUC1 and I/OUC2[1]
VOL
LOW-level output
voltage
VOH
HIGH-level output
voltage
IOL = 1 mA
VIL
LOW-level input
voltage
−0.3
-
+0.25 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
IIL
LOW-level input
current
VIL = 0 V
-
-
600
µA
Vhys
hysteresis voltage
on I/OUC(n)
-
0.19VDD(INTF) -
V
ILIH
HIGH-level input
leakage current
VIH = VDD(INTF)
-
-
µA
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
10
© NXP B.V. 2010. All rights reserved.
44 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 47. Interface signals to microcontroller …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tr(o)
output rise time
VIL minimum to VIH maximum;
10 % to 90 %
-
-
0.1
µs
tr(i)
input rise time
VIL minimum to VIH maximum;
10 % to 90 %
-
-
1.2
µs
tf(o)
output fall time
VIL maximum to VIH minimum;
90 % to 10 %
-
-
0.1
µs
tf(i)
input fall time
VIL maximum to VIH minimum;
90 % to 10 %
-
-
1.2
µs
Ci
input capacitance
[1]
-
-
10
pF
Rpu(int)
internal pull-up
resistance
between pins I/OUC(n) and
VDD(INTF)
[1]
9
11
13
kΩ
Ipu
pull-up current
VOH = 0.9 VDD, Ci = 30 pF
−1
-
-
mA
Clock input pins: CLKIN1 and CLKIN2
fclk(ext)
external clock
frequency
on pins CLKIN1 and CLKIN2
0
-
20
MHz
VIL
LOW-level input
voltage
VDD(INTF) > 2 V
0
-
0.3 VDD(INTF)
V
1.6 V ≤ VDD(INTF) ≤ 2 V
0
-
0.15VDD(INTF)
V
VIH
HIGH-level input
voltage
VDD(INTF) > 2 V
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
1.6 V ≤ VDD(INTF) ≤ 2 V
0.85 VDD(INTF)
-
VDD(INTF) + 0.3
V
tr
rise time
10 % to 90 %
-
-
0.1 / fclk(ext)
ns
tf
fall time
90 % to 10 %
-
-
0.1 / fclk(ext)
ns
Logic input pins: A0, SPRES, INHIB, DCDC_OFF and TESTMODE
VIL
LOW-level input
voltage
−0.3
-
+0.3 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
ILIL
LOW-level input
leakage current
−1
-
+1
µA
Vhys
hysteresis voltage
-
0.14VDD(INTF) -
ILIH
HIGH-level input
leakage current
−1
-
+1
µA
Ci
input capacitance
-
-
10
pF
on pin SPRES
V
Logic input pin: SDWNN
VIL
LOW-level input
voltage
−0.3
-
+0.3 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
ILIH
HIGH-level input
leakage current
−1
-
+1
µA
Ci
input capacitance
-
-
10
pF
Rpu(int)
internal pull-up
resistance
2
2.5
3
MΩ
TDA8026_1
Product data sheet
between pins SDWNN and
VDD(INTF)
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Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
45 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 47. Interface signals to microcontroller …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Logic input pin: INTAUXN
VIL
LOW-level input
voltage
−0.3
-
+0.3 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
ILIL
LOW-level input
leakage current
−425
−330
−260
µA
Ci
input capacitance
-
-
10
pF
Rpu(int)
internal pull-up
resistance
8
10
12
kΩ
-
-
0.3
V
-
-
10
µA
between pins INTAUXN and
VDD(INTF); SDWNN pin equal
to pin VDD(INTF)
Interrupt line: IRQN pin; open-drain, active LOW output
VOL
LOW-level output
voltage
ILH
HIGH-level leakage
current
IOL = 2 mA
Logic input/output pins: TST1, TST2, STAP3, STAP4, STAP5
VIL
LOW-level input
voltage
−0.3
-
+0.3 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
VOL
LOW-level output
voltage
VDD(INTF) = 3.3 V; IOL = 4 mA
0
-
0.4
V
VDD(INTF) = 1.8 V; IOL = 4 mA
0
-
0.4
V
HIGH-level output
voltage
VDD(INTF) = 3.3 V;
IOH = −4 mA
VDD(INTF) − 0.4 -
VDD(INTF)
V
VDD(INTF) = 1.8 V;
IOH = −4 mA
VDD(INTF) − 0.4 -
VDD(INTF)
V
VDD(INTF) = 3.3 V;
VOL = 0.3 VDD(INTF)
4
-
-
mA
VDD(INTF) = 1.8 V;
VOL = 0.3 VDD(INTF)
2
-
-
mA
VDD(INTF) = 3.3 V;
VOH = 0.7 VDD(INTF)
−4
-
-
mA
VDD(INTF) = 1.8 V;
VOH = 0.7 VDD(INTF)
−2
-
-
mA
VOH
IOL
IOH
LOW-level output
current
HIGH-level output
current
ILIL
LOW-level input
leakage current
−1
-
+1
µA
ILIH
HIGH-level input
leakage current
−1
-
+1
µA
Ci
input capacitance
-
-
10
pF
Co
output capacitance
-
30
-
pF
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
46 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 47. Interface signals to microcontroller …continued
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pins VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Serial data input/output pin: SDA; open-drain
VIL
LOW-level input
voltage
−0.3
-
+0.3 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
VOL
LOW-level output
voltage
IOL = 3 mA
-
-
0.3
V
ILH
HIGH-level leakage
current
I/O
-
-
1
µA
ILL
LOW-level leakage
current
depending on the pull-up
resistance; input or output
-
-
1
µA
Serial clock input pin: SCL
VIL
LOW-level input
voltage
−0.3
-
+0.3 VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
ILIH
HIGH-level input
leakage current
-
-
1
µA
IIL
LOW-level input
current
-
-
1
µA
depends on the pull-up
resistance
I2C-bus timing; see Figure 13
fSCL
SCL clock frequency
0
-
400
kHz
tBUF
bus free time between
a STOP and START
condition
1.3
-
-
µs
tHD;STA
hold time (repeated)
START condition
0.6
-
-
µs
tLOW
LOW period of the
SCL clock
1.3
-
-
µs
tHIGH
HIGH period of the
SCL clock
0.6
-
-
µs
tSU;STA
set-up time for a
repeated START
condition
0.6
-
-
µs
tHD;DAT
data hold time
0
-
-
ns
tSU;DAT
data set-up time
100
-
-
ns
tr
rise time
both SDA and SCL signals;
10 % to 90 %
-
-
300
ns
tf
fall time
both SDA and SCL signals;
90 % to 10 %
-
-
300
ns
tSU;STO
set-up time for STOP
condition
0.6
-
-
µs
hold time after which first
clock pulse is generated
[2]
[1]
I/OUCn pin has an internal 11 kΩ pull-up resistor to VDD(INTF).
[2]
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
47 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
Table 48. Protections
VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 µH; decoupling capacitors on pin VDD and VUP = 10 µF;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Tsd
shutdown temperature
Conditions
Isd
shutdown current
IOlim
output current limit
Min
Typ
Max
Unit
125
167
209
°C
all VCC(n) pins
80
120
150
mA
pins I/O(n)
−15
-
+15
mA
pins CLK(n)
−70
-
+70
mA
pins RST(n)
−20
-
+20
mA
pins VCC(n)
80
-
150
mA
Tamb
ambient temperature
−25
+25
+85
°C
Tj
junction temperature
-
-
+125
°C
ICC
supply current
-
170
-
mA
sum of all VCC(n) signals on all card slots;
active mode; DC-to-DC converter on
SDA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
msc610
P = STOP condition; S = START condition.
Fig 13. Timing requirements for the I2C-bus
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
48 of 59
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
B4
PORADJ
A8
C11
SDWNN
VDD(INTF)
100 nF
MICROCONTROLLER
Rpu
3.3 kΩ
Rpu
3.3 kΩ
R1
SCL
SDA
100 kΩ
IRQN
I/OUC1
I/OUC2
CLKIN1
CLKIN2
SPRES
H5 GNDC
(1)
H3
VCC(1)
G3
RST(1)
G2
CLK(1)
F2
C4(1)
G1
C8(1)
F1
I/O(1)
E3
PRES(1)
H2
A5
A4
B2
C2
E2
G8
E1
G5
G6
D2
G7
C4
TDA8026
F7
C5
F8
C3
E8
B3
F6
E6
H1
GND2 to GND10 D3 to D5, E4, E5,
F3 to F5, H8
TESTMODE
A3
D8
H7
D6
A2
C6
D7
A1
C5(1)
100 nF
CARD
CONNECTOR
2
VDD(INTF)
R3
GNDC(2)
0Ω
C7(1)
100 nF
VCC(2)
C8(2)
100 nF
RST(2)
C1
C2
C3
CLK(2)
I/O(2)
C9(1)
100 nF
VCC(3)
VDD(INTF)
CLK(3)
R4
I/O(3)
0Ω
STAP3
C10(2)
100 nF
C11(1)
100 nF
VCC(4)
C1
C2
C3
RST(4)
CLK(4)
C1
C2
C5
C6
C7
STAP4
R5
100 kΩ
C13(1)
R6
0Ω
C12(2)
100 nF
C14(2)
C1
C2
C3
100 nF
R8
0Ω
R7
SAM 4
C5
C6
C7
VDD(INTF)
100 kΩ
C5
C6
SAM 3
VDD(INTF)
I/O(4)
SAM 5
C3
C5
C6
C7
RST(3)
100 nF
C7
SAM 2
PRES(2)
100 kΩ
VDD(INTF)
C5
C6
C7
C8
(1) Low ESR capacitor, placed near the IC.
(2) Low ESR capacitor, placed near the C1 connector contact.
Fig 14. Application diagram: TDA8026 with one card and four SAMs
TDA8026
49 of 59
© NXP B.V. 2010. All rights reserved.
001aal093
Multiple smart card slot interface IC
R9
RST(5)
C1
D1 C7 B7 B6 B5
C8
I/O(5)
TST2
B1
CLK(5)
TST1
E7
STAP5
INHIB
C1
C2
C3
C4
VUP
LX
G4 H4
B8
GNDS
Rev. 1 — 9 March 2010
All information provided in this document is subject to legal disclaimers.
A0
INTAUX
C6(2)
100 nF
VCC(5)
DCDC_OFF
A7 A6
0Ω
C4
10 µF
GNDP
VDD
GND1
100 nF
VDD(INTREGD)
C2
VDD(INTF)
R2
C3
1 µF
NXP Semiconductors
D1
L1
10 µH
10 µF
12. Application information
TDA8026_1
Product data sheet
VDD
C1
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
13. Package outline
TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls
SOT1073-1
B
D
A
ball A1
index area
A2
A
E
A1
detail X
e1
e
1/2 e
∅v
∅w
b
M
M
C
C A B
C
y
y1 C
H
e
G
F
E
e2
D
1/2 e
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
max
nom
min
A
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
1.2
1.1
1.0
0.35
0.30
0.25
0.85
0.80
0.75
0.45
0.40
0.35
7.1
7.0
6.9
7.1
7.0
6.9
0.8
5.6
5.6
0.15
0.08
0.12
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT1073-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
08-03-06
08-03-14
Fig 15. Package outline SOT1073-1 (TFBGA64)
TDA8026_1
Product data sheet
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50 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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TDA8026
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Multiple smart card slot interface IC
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 49 and 50
Table 49.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 50.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
TDA8026_1
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TDA8026
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Multiple smart card slot interface IC
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 51.
Abbreviations and acronyms
Acronym
Description
ATR
Answer To Request
CDM
Charged Device Model
ESD
ElectroStatic Discharge
ESR
Equivalent Series Resistance
HBM
Human Body Model
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
PCB
Printed-Circuit Board
POR
Power-On Reset
POS
Point Of Sales
SAM
Security Access Module
16. Revision history
Table 52.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDA8026_1
20100309
Product data sheet
-
1.2
[1]
Versions 1.0 to 1.2 have all been superseded by this version which includes changes to symbols, pin names and drawings.
TDA8026_1
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Multiple smart card slot interface IC
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
TDA8026_1
Product data sheet
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
54 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use of
the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TDA8026_1
Product data sheet
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55 of 59
TDA8026
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Multiple smart card slot interface IC
19. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .3
TDA8026 ball map . . . . . . . . . . . . . . . . . . . . . . .5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Base addressing . . . . . . . . . . . . . . . . . . . . . . .14
Write mode addresses . . . . . . . . . . . . . . . . . .14
Register overview . . . . . . . . . . . . . . . . . . . . . .16
Bank 0 register (address: 48h) bit allocation . .18
Bank 0 bit description . . . . . . . . . . . . . . . . . . .18
Bank 1 CSb[7:0] Register0 (address 40h) card
slot 1 and card slot 2 bit allocation . . . . . . . . . .18
Bank 1 Register0 card slot 1 (address 01h) and
card slot 2 (address 02h) read mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bank 1 Register0 card slot 1 (address 01h) and
card slot 2 (address 02h) write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Bank 1 CSb[7:0] Register0 (address 42h) card
slots 1 and card slots 2 bit allocation . . . . . . . .21
Bank 1 Register1 (REG[1:0] = 00) card slot 1
(address 01h) and card slot 2 (address 02h)
Read/Write mode bit descriptions . . . . . . . . . .21
Bank 1 Register1 (REG[1:0] = 01) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Bank 1 Register1 (REG[1:0] = 01) card slot 1
(address 01h) and card slot 2 (address 02h)
Read/Write mode bit descriptions . . . . . . . . . .23
Bank 1 Register1 (REG[1:0] = 10) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Bank 1 Register1 (REG[1:0] = 10) card slot 1
(address 01h) and card slot 2 (address 02h)
Read/Write mode bit descriptions . . . . . . . . . .23
Bank 1 Register1 (REG[1:0] = 11) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Bank 1 Register1 (REG[1:0] = 11) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . .23
Bank 1 CSb[7:0] Register0 (address 40h) card
slots 3 to 5 bit allocation . . . . . . . . . . . . . . . . .24
Bank 1 Register0 card slot 3 (address 03h), card
slot 4 (address 04h) and card slot 5
(address 05h) read mode bit descriptions . . . .24
Bank 1 Register0 card slot 3 (address 03h), card
slot 4 (address 04h) and card slot 5
(address 05h) write mode bit descriptions . . . .25
Bank 1 CSb[7:0] Register1 (address 42h) card
slots 3 and 5 bit allocation . . . . . . . . . . . . . . . .26
Bank 1 Register1 (REG[1:0] = 00) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode . . . . . . .26
Bank 1 Register1 (REG[1:0] = 01) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . .27
TDA8026_1
Product data sheet
Table 27. Bank 1 Register1 (REG[1:0] = 01) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 28. Bank 1 Register1 (REG[1:0] = 10) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . . 28
Table 29. Bank 1 Register1 (REG[1:0] = 10) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 30. Bank 1 Register1 (REG[1:0] = 11) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . . 28
Table 31. Bank 1: Bank 1 Register1 (REG[1:0] = 11) card
slot 3 (address 03h), card slot 4 (address 04h) and
card slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 32. Asynchronous mode card clock settings . . . . . 29
Table 33. Synchronous mode card clock settings . . . . . . 29
Table 34. Bank 1 General registers (addresses: 40h, 42h;
CSb[7:0] = 00h, 06h) bit allocation . . . . . . . . . 30
Table 35. Bank 1 Product version register (address 40h;
CSb[7:0] = 00h) read mode bit descriptions . . 30
Table 36. Bank 1 Interrupt register (address 42h;
CSb[7:0] = 00h) read mode bit descriptions . . 31
Table 37. Bank 1 Slew rate register (address 40h;
CSb[7:0] = 06h) read/write mode
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 38. Clock Slew rate . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 39. I/O slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 40. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 41. Thermal characteristics . . . . . . . . . . . . . . . . . . 39
Table 42. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 43. Supply supervisor . . . . . . . . . . . . . . . . . . . . . . 40
Table 44. DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 41
Table 45. Card drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 46. Sequencer and clock counter . . . . . . . . . . . . . 44
Table 47. Interface signals to microcontroller . . . . . . . . . 44
Table 48. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 49. SnPb eutectic process (from J-STD-020C) . . . 52
Table 50. Lead-free process (from J-STD-020C) . . . . . . 52
Table 51. Abbreviations and acronyms . . . . . . . . . . . . . . 53
Table 52. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 53
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
56 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
20. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
TDA8026 Block diagram . . . . . . . . . . . . . . . . . . . .4
TDA8026 pin configuration for the TFBGA64
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
TDA8026 Power diagram . . . . . . . . . . . . . . . . . . . .8
The enter shutdown sequence. . . . . . . . . . . . . . .10
The exit shutdown sequence . . . . . . . . . . . . . . . .10
The voltage supervisor circuit . . . . . . . . . . . . . . .11
VDD voltage supervisor . . . . . . . . . . . . . . . . . . . .11
VDD(INTF) voltage supervisor. . . . . . . . . . . . . . . . .12
The DC-to-DC converter . . . . . . . . . . . . . . . . . . .32
The card slot activation sequence . . . . . . . . . . . .34
Deactivation sequence. . . . . . . . . . . . . . . . . . . . .35
ATR counter timing check . . . . . . . . . . . . . . . . . .36
Timing requirements for the I2C-bus . . . . . . . . . .48
Application diagram: TDA8026 with one card and
four SAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Package outline SOT1073-1 (TFBGA64). . . . . . .50
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
TDA8026_1
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57 of 59
TDA8026
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Multiple smart card slot interface IC
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.4.1
8.2.4.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
8.5.2.1
8.5.2.2
8.5.3
8.5.3.1
8.5.3.2
8.5.3.3
8.5.3.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 8
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock-stop mode. . . . . . . . . . . . . . . . . . . . . . . . 9
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 9
Entering shutdown mode . . . . . . . . . . . . . . . . . 9
Exiting shutdown mode. . . . . . . . . . . . . . . . . . 10
Voltage supervisors . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDD(INTREGD) voltage supervisor without
external divider on PORADJ pin . . . . . . . . . . . 12
I2C-bus description . . . . . . . . . . . . . . . . . . . . . 13
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 13
Bus conditions . . . . . . . . . . . . . . . . . . . . . . . . 13
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device addressing . . . . . . . . . . . . . . . . . . . . . 14
Banks and registers . . . . . . . . . . . . . . . . . . . . 15
Register overview . . . . . . . . . . . . . . . . . . . . . . 16
Bank 0 register description . . . . . . . . . . . . . . . 18
Bank 0 register (address: 48h) bit allocation . 18
Bank 0 bit description . . . . . . . . . . . . . . . . . . . 18
Bank 1 card slots 1 and 2 register
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bank 1 CSb[7:0] Register0 (address 40h) card
slot 1 and card slot 2 bit allocation . . . . . . . . . 18
Bank 1 Register0 card slot 1 (address 01h) and
card slot 2 (address 02h) read mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bank 1 Register0 card slot 1 (address 01h) and
card slot 2 (address 02h) write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bank 1 CSb[7:0] Register0 (address 42h) card
slots 1 and card slot 2 bit allocation . . . . . . . . 21
8.5.3.5
8.5.3.6
8.5.3.7
8.5.3.8
8.5.3.9
8.5.3.10
8.5.3.11
8.5.4
8.5.4.1
8.5.4.2
8.5.4.3
8.5.4.4
8.5.4.5
8.5.4.6
8.5.4.7
8.5.4.8
Bank 1 Register1 (REG[1:0] = 00) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 21
Bank 1 Register1 (REG[1:0] = 01) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bank 1 Register1 (REG[1:0] = 01) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 10) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 10) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 11) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 11) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 23
Card slots 3 to 5 register descriptions . . . . . . 24
Bank 1 CSb[7:0] Register0 (address 40h) card
slots 3 to 5 bit allocation. . . . . . . . . . . . . . . . . 24
Bank 1 Register0 card slot 3 (address 03h), card
slot 4 (address 04h) and card slot 5
(address 05h) read mode bit descriptions . . . 24
Bank 1 Register0 card slot 3 (address 03h), card
slot 4 (address 04h) and card slot 5
(address 05h) write mode bit descriptions . . . 25
Bank 1 CSb[7:0] Register1 (address 42h) card
slots 3 and 5 bit allocation . . . . . . . . . . . . . . . 26
Bank 1 Register1 (REG[1:0] = 00) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode. . . . . . . 26
Bank 1 Register1 (REG[1:0] = 01) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . 27
Bank 1 Register1 (REG[1:0] = 01) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bank 1 Register1 (REG[1:0] = 10) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . 28
continued >>
TDA8026_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
58 of 59
TDA8026
NXP Semiconductors
Multiple smart card slot interface IC
8.5.4.9
Bank 1 Register1 (REG[1:0] = 10) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5.4.10 Bank 1 Register1 (REG[1:0] = 11) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . . 28
8.5.4.11 Bank 1: Bank 1 Register1 (REG[1:0] = 11) card
slot 3 (address 03h), card slot 4 (address 04h) and
card slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5.5
Selection of asynchronous or synchronous
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5.6
General registers . . . . . . . . . . . . . . . . . . . . . . 30
8.5.6.1
Bank 1 General registers (address: 40h, 42h;
CSb[7:0] = 00h, 06h) bit allocation . . . . . . . . . 30
8.5.6.2
Bank 1 Product version register (address 40h;
CSb[7:0] = 00h) read mode bit descriptions . . 30
8.5.6.3
Bank 1 Interrupt register (address 42h;
CSb[7:0] = 00h) read mode bit descriptions . . 31
8.5.6.4
Bank 1 Slew rate register (address 40h;
CSb[7:0] = 06h) read/write mode
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 31
8.6
DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 32
8.7
VCC buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.8
Sequencer and clock counter . . . . . . . . . . . . . 32
8.8.1
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 33
8.8.2
Activation sequence . . . . . . . . . . . . . . . . . . . . 33
8.8.3
Deactivation sequence . . . . . . . . . . . . . . . . . . 34
8.9
Answer to reset counters . . . . . . . . . . . . . . . . 35
8.10
Slew rate control . . . . . . . . . . . . . . . . . . . . . . . 37
8.11
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 38
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 39
10
Thermal characteristics. . . . . . . . . . . . . . . . . . 39
11
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 40
12
Application information. . . . . . . . . . . . . . . . . . 49
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 50
14
Soldering of SMD packages . . . . . . . . . . . . . . 51
14.1
Introduction to soldering . . . . . . . . . . . . . . . . . 51
14.2
Wave and reflow soldering . . . . . . . . . . . . . . . 51
14.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 51
14.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 52
15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 53
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 53
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 54
17.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 54
17.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
17.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
17.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
18
19
20
21
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
56
57
58
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 9 March 2010
Document identifier: TDA8026_1
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