Data Sheet

PN7150
High performance full NFC Forum-compliant controller with
integrated firmware and NCI interface
Rev. 3.2 — 25 May 2016
Product data sheet
1. Introduction
This document describes the functionality and electrical specification of the NFC
Controller PN7150.
Additional documents describing the product functionality further are available for
design-in support. Refer to the references listed in this document to get access to the full
for full documentation provided by NXP.
2. General description
Best plug´n play and high-performance full NFC solution PN7150 is a full NFC controller
solution with integrated firmware and NCI interface designed for contactless
communication at 13.56 MHz. It is compatible with NFC forum requirements.
PN7150 is designed based on learnings from previous NXP NFC device generation. It is
the ideal solution for rapidly integrating NFC technology in any application, especially
those running O/S environment like Linux and Android, reducing Bill of Material (BOM)
size and cost, thanks to:
• Full NFC forum compliancy (see Ref. 1) with small form factor antenna
• Embedded NFC firmware providing all NFC protocols as pre-integrated feature
• Direct connection to the main host or microcontroller, by I2C-bus physical and NCI
protocol
• Ultra-low power consumption in polling loop mode
• Highly efficient integrated power management unit (PMU) allowing direct supply from
a battery
PN7150 embeds a new generation RF contactless front-end supporting various
transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,
MIFARE and FeliCa specifications. It embeds an ARM Cortex-M0 microcontroller core
loaded with the integrated firmware supporting the NCI 1.0 host communication. It also
allows to provide a higher output power by supplying the transmitter output stage from
3.0 V to 4.5 V.
The contactless front-end design brings a major performance step-up with on one hand a
higher sensitivity and on the other hand the capability to work in active load modulation
communication enabling the support of small antenna form factor.
Supported transmission modes are listed in Figure 1. For contactless card functionality,
the PN7150 can act autonomously if previously configured by the host in such a manner.
PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
PN7150 integrated firmware provides an easy integration and validation cycle as all the
NFC real-time constraints, protocols and device discovery (polling loop) are being taken
care internally. In few NCI commands, host SW can configure the PN7150 to notify for
card or peer detection and start communicating with them.
NFC FORUM
NFC-IP MODES
READER
(PCD - VCD)
CARD
(PICC)
READER FOR NFC FORUM
TAGS 1 TO 4
ISO/IEC 14443 A
ISO/IEC 14443 A
ISO/IEC 14443 B
ISO/IEC 14443 B
P2P ACTIVE
106 TO 424 kbps
INITIATOR AND TARGET
ISO/IEC 15693
MIFARE 1K / 4K
P2P PASSIVE
106 TO 424 kbps
INITIATOR AND TARGET
MIFARE DESFire
Sony FeliCa(1)
aaa-015868
(1) According to ISO/IEC 18092 (Ecma 340) standard.
Fig 1.
PN7150 transmission modes
3. Features and benefits
 Includes NXP ISO/IEC14443-A, Innovatron ISO/IEC14443-B and NXP MIFARE
crypto1 intellectual property licensing rights
 ARM Cortex-M0 microcontroller core
 Highly integrated demodulator and decoder
 Buffered output drivers to connect an antenna with minimum number of external
components
 Integrated RF level detector
 Integrated Polling Loop for automatic device discovery
 RF protocols supported
 NFCIP-1, NFCIP-2 protocol (see Ref. 8 and Ref. 11)
 ISO/IEC 14443A, ISO/IEC 14443B PICC mode via host interface (see Ref. 3)
 ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
protocol T4T platform and ISO-DEP (see Ref. 1)
 FeliCa PCD mode
 MIFARE PCD encryption mechanism (MIFARE 1K/4K)
 NFC Forum tag 1 to 4 (MIFARE Ultralight, Jewel, Open FeliCa tag, DESFire) (see
Ref. 1)
 ISO/IEC 15693/ICODE VCD mode (see Ref. 9)
 Supported host interfaces
 NCI protocol interface according to NFC Forum standardization (see Ref. 2)
 I2C-bus High-speed mode (see Ref. 4)
PN7150
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
 Integrated power management unit
 Direct connection to a battery (2.3 V to 5.5 V voltage supply range)
 Support different Hard Power-Down/Standby states activated by firmware
 Autonomous mode when host is shut down
 Automatic wake-up via RF field, internal timer and I2C-bus interface
 Integrated non-volatile memory to store data and executable code for customization
4. Applications
 All devices requiring NFC functionality especially those running in an Android or Linux
environment
 TVs, set-top boxes, Blu-ray decoders, audio devices
 Home automation, gateways, wireless routers
 Home appliances
 Wearables, remote controls, healthcare, fitness
 Printers, IP phones, gaming consoles, accessories
5. Quick reference data
Table 1.
Symbol
Parameter
Conditions
VBAT
battery supply voltage
Card Emulation and Passive
Target; VSS = 0 V
[1]
Reader, Active Initiator and
Active Target; VSS = 0 V
[1]
VDD
supply voltage
internal supply voltage
VDD(PAD)
VDD(PAD) supply voltage
supply voltage for host
interface
IBAT
IO(VDDPAD)
PN7150
Product data sheet
Quick reference data
battery supply current
output current on pin
VDD(PAD)
Min Typ
Max Unit
2.3
-
5.5
V
2.7
-
5.5
V
[2]
[2]
1.65 1.8
1.95 V
1.8 V host supply;
VSS = 0 V
[1]
1.65 1.8
1.95 V
3 V host supply; VSS = 0 V
[1]
3.0
-
3.6
V
[3]
-
10
14
A
in Standby state;
VBAT = 3.6 V; T = 25 °C
-
20
-
A
in Monitor state;
VBAT = 2.75 V; T = 25 °C
-
-
14
A
A
in Hard Power Down state;
VBAT = 3.6 V; T = 25 °C
in low-power polling loop;
VBAT = 3.6 V; T = 25 °C;
loop time = 500 ms
[4]
-
150
-
PCD mode at typical 3 V
[2]
-
-
190 mA
-
-
15
total current which can be
pulled on VDD(PAD) referenced
outputs
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mA
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PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
Table 1.
Quick reference data …continued
Symbol
Parameter
Conditions
Ith(Ilim)
current limit threshold
current
current limiter on VDD(TX) pin;
VDD(TX) = 3.3 V
Min Typ
Max Unit
-
180
-
Ptot
total power dissipation
Reader; IVDD(TX) = 100 mA;
VBAT = 5.5 V
-
-
420 mW
Tamb
ambient temperature
JEDEC PCB-0.5
30 -
[2]
mA
+85 C
[1]
VSS represents VSS(PAD) and VSS(TX).
[2]
The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with
another device must be taken into account).
[3]
External clock on NFC_CLK_XTAL1 must be LOW.
[4]
See Ref. 10 for computing the power consumption as it depends on several parameters.
6. Ordering information
Table 2.
Ordering information
Type number
Package
Name
PN7150B0HN/C110xx[1]
[1]
Description
Version
HVQFN40 plastic thermal enhanced very thin quad SOT618-1
flat package; no leads; 40 terminals; body
6  6  0.85 mm
xx = firmware code variant.
7. Marking
Terminal 1 index area
A :7
B1 : 6
B2 : 6
C:8
0
5
aaa-007965
Fig 2.
Table 3.
PN7150
Product data sheet
PN7150 package marking (top view)
Marking codes
Type number
Marking code
Line A
7 characters used: basic type number:
PN7150x where x is the FW variant
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
Table 3.
Marking codes …continued
Type number
Marking code
Line B1
6 characters used: diffusion batch sequence
number
Line B2
6 characters used: assembly ID number
Line C
7 characters used: manufacturing code
including:
•
diffusion center code:
– Z: SSMC
– S: Powerchip (PTCT)
•
assembly center code:
– S: APK
•
RoHS compliancy indicator:
– D: Dark Green; fully compliant RoHS
and no halogen and antimony
•
manufacturing year and week, 3 digits:
– Y: year
– WW: week code
•
product life cycle status code:
– X: means not qualified product
– nothing means released product
PN7150
Product data sheet
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
8. Block diagram
CLESS
INTERFACE UNIT
CLESS UART
RF DETECT
SENSOR
RX CODEC
DEMOD
ADC
TX CODEC
DRIVER
TxCtrl
PLL
BG
HOST INTERFACE
I2C-bus
SIGNAL
PROCESSING
ARM
CORTEX M0
DATA
MEMORY
SRAM
VMID
EEPROM
AHB to APB
POWER
MANAGEMENT UNIT
BATTERY
MONITOR
4.5 V
TX-LDO
1.8 V
DSLDO
MISCELLANEOUS
MEMORY
CONTROL
CLOCK MANAGEMENT UNIT
CODE
MEMORY
TIMERS
OSCILLATOR
380 kHz
OSCILLATOR
40 MHz
ROM
CRC
COPROCESSOR
FRACN
PLL
QUARTZ
OSCILLATOR
EEPROM
RANDOM
NUMBER
GENERATOR
aaa-016737
Fig 3.
PN7150 block diagram
PN7150
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Full NFC Forum-compliant controller with integrated firmware
9. Pinning information
32 n.c.
31 n.c.
33 n.c.
34 n.c.
35 n.c.
36 NFC_CLK_XTAL1
37 NFC_CLK_XTAL2
38 i.c.
terminal 1
index area
39 i.c.
40 CLK_REQ
9.1 Pinning
I2CADR0
1
30 VDDD
i.c.
2
29 VDD
I2CADR1
3
28 VDDA
VSS(PAD)
4
27 VSS
I2CSDA
5
VDD(PAD)
6
I2CSCL
7
IRQ
8
VSS
9
26 VBAT
PN7150
25 i.c.
24 i.c.
23 i.c.
22 VDD(TX_IN)
VSS
n.c. 20
VSS(TX) 19
TX2 18
VDD(MID) 17
RXP 16
RXN 15
VDD(TX) 14
VBAT1 13
i.c. 11
21 TX1
VBAT2 12
VEN 10
Transparent top view
Fig 4.
Table 4.
PN7150
Product data sheet
aaa-016738
Pinning
Pin description
Symbol
Pin Type[1] Refer
Description
I2CADR0
1
I
VDD(PAD)
I2C-bus address 0
i.c.
2
-
-
internally connected; must be connected to
GND
I2CADR1
3
I
VDD(PAD)
I2C-bus address 1
VSS(PAD)
4
G
n/a
pad ground
I2CSDA
5
I/O
VDD(PAD)
I2C-bus data line
VDD(PAD)
6
P
n/a
pad supply voltage
I2CSCL
7
I
VDD(PAD)
I2C-bus clock line
IRQ
8
O
VDD(PAD)
interrupt request output
VSS
9
G
n/a
ground
VEN
10
I
VBAT
reset pin. Set the device in Hard Power Down
i.c.
11
-
-
internally connected; leave open
VBAT2
12
P
n/a
battery supply voltage; must be connected to
VBAT
VBAT1
13
P
n/a
battery supply voltage; must be connected to
VBAT
VDD(TX)
14
P
n/a
transmitter supply voltage
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
Table 4.
Pin description …continued
Symbol
Pin Type[1] Refer
Description
RXN
15
I
VDD
negative receiver input
RXP
16
I
VDD
positive receiver input
VDD(MID)
17
P
n/a
receiver reference input supply voltage
TX2
18
O
VDD(TX)
antenna driver output
VSS(TX)
19
G
n/a
contactless transmitter ground
n.c.
20
-
-
not connected
TX1
21
O
VDD(TX)
antenna driver output
VDD(TX_IN)
22
P
n/a
transmitter input supply voltage; must be
connected to VDD(TX)
i.c.
23
-
-
internally connected; leave open
i.c.
24
-
-
internally connected; leave open
i.c.
25
-
-
internally connected; leave open
VBAT
26
P
n/a
battery supply voltage
VSS
27
G
n/a
ground
VDDA
28
P
n/a
analog supply voltage; must be connected to
VDD
VDD
29
P
n/a
supply voltage
VDDD
30
P
n/a
digital supply voltage; must be connected to
VDD
n.c.
31
-
-
not connected
n.c.
32
-
-
not connected
n.c.
33
-
-
not connected
n.c.
34
-
-
not connected
n.c.
35
-
-
not connected
NFC_CLK_XTAL1
36
I
VDD
oscillator input/PLL input
NFC_CLK_XTAL2
37
O
VDD
oscillator output
i.c.
38
-
-
internally connected; leave open
i.c.
39
-
-
internally connected; leave open
CLK_REQ
40
O
VDD(PAD)
clock request pin
[1]
P = power supply; G = ground; I = input, O = output; I/O = input/output.
10. Functional description
PN7150 can be connected on a host controller through I2C-bus. The logical interface
towards the host baseband is NCI-compliant Ref. 2 with additional command set for
NXP-specific product features. This IC is fully user controllable by the firmware interface
described in Ref. 5.
Moreover, PN7150 provides flexible and integrated power management unit in order to
preserve energy supporting Power Off mode.
In the following chapters you will find also more details about PN7150 with references to
very useful application note such as:
PN7150
Product data sheet
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
• PN7150 User Manual (Ref. 5):
User Manual describes the software interfaces (API) based on the NFC forum NCI
standard. It does give full description of all the NXP NCI extensions coming in addition
to NCI standard (Ref. 2).
• PN7150 Hardware Design Guide (Ref. 6):
Hardware Design Guide provides an overview on the different hardware design
options offered by the IC and provides guidelines on how to select the most
appropriate ones for a given implementation. In particular, this document highlights
the different chip power states and how to operate them in order to minimize the
average NFC-related power consumption so to enhance the battery lifetime.
• PN7150 Antenna and Tuning Design Guide (Ref. 7):
Antenna and Tuning Design Guide provides some guidelines regarding the way to
design an NFC antenna for the PN7150 chip.
It also explains how to determine the tuning/matching network to place between this
antenna and the PN7150.
Standalone antenna performances evaluation and final RF system validation (PN7150
+ tuning/matching network + NFC antenna within its final environment) are also
covered by this document.
• PN7150 Low-Power Mode Configuration (Ref. 10):
Low-Power Mode Configuration documentation provides guidance on how PN7150
can be configured in order to reduce current consumption by using Low-power polling
mode.
BATTERY/PMU
HOST
CONTROLLER
host interface
control
NFCC
ANTENNA
MATCHING
aaa-016739
Fig 5.
PN7150 connection
10.1 System modes
10.1.1 System power modes
PN7150 is designed in order to enable the different power modes from the system.
PN7150
Product data sheet
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
2 power modes are specified: Full power mode and Power Off mode.
Table 5.
System power modes description
System power mode
Description
Full power mode
the main supply (VBAT) as well as the host interface supply (VDD(PAD)) is
available, all use cases can be executed
Power Off mode
the system is kept Hard Power Down (HPD)
Full power mode
[VBAT = On && VDD(PAD) = On
VEN = On]
[VBAT = Off || VEN = Off]
Power Off mode
[VEN = Off]
Fig 6.
aaa-015871
System power mode diagram
Table 6 summarizes the system power mode of the PN7150 depending on the status of
the external supplies available in the system:
Table 6.
System power modes configuration
VBAT
VEN
Power mode
Off
X
Power Off mode
On
Off
Power Off mode
On
On
Full power mode
Depending on power modes, some application states are limited:
Table 7.
System power modes description
System power mode
Allowed communication modes
Power Off mode
no communication mode available
Full power mode
Reader/Writer, Card Emulation, P2P modes
10.1.2 PN7150 power states
Next to system power modes defined by the status of the power supplies, the power
states include the logical status of the system thus extend the power modes.
4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active.
PN7150
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PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
Table 8.
PN7150 power states
Power state name Description
Monitor
The PN7150 is supplied by VBAT which voltage is below its programmable
critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The
system power mode is Power Off mode.
Hard Power Down
The PN7150 is supplied by VBAT which voltage is above its programmable
critical level when Monitor state is enabled and PN7150 is kept in Hard
Power Down (VEN voltage is kept low by host or SW programming) to have
the minimum power consumption. The system power mode is in Power Off.
Standby
The PN7150 is supplied by VBAT which voltage is above its programmable
critical level when the Monitor state is enabled, VEN voltage is high (by host
or SW programming) and minimum part of PN7150 is kept supplied to enable
configured wake-up sources which allow to switch to Active state; RF field,
Host interface. The system power mode is Full power mode.
Active
The PN7150 is supplied by VBAT which voltage is above its programmable
critical level when Monitor state is enabled, VEN voltage is high (by host or
SW programming) and the PN7150 internal blocks are supplied. 3 functional
modes are defined: Idle, Target and Initiator. The system power mode is Full
power mode.
At application level, the PN7150 will continuously switch between different states to
optimize the current consumption (polling loop mode). Refer to Table 1 for targeted
current consumption in here described states.
The PN7150 is designed to allow the host controller to have full control over its functional
states, thus of the power consumption of the PN7150 based NFC solution and possibility
to restrict parts of the PN7150 functionality.
10.1.2.1
Monitor state
In Monitor state, the PN7150 will exit it only if the battery voltage recovers over the critical
level. Battery voltage monitor thresholds show hysteresis behavior as defined in Table 26.
10.1.2.2
Hard Power Down (HPD) state
The Hard Power Down state is entered when VDD(PAD) and VBAT are high by setting VEN
voltage < 0.4 V. As these signals are under host control, the PN7150 has no influence on
entering or exiting this state.
10.1.2.3
Standby state
Active state is PN7150’s default state after boot sequence in order to allow a quick
configuration of PN7150. It is recommended to change the default state to Standby state
after first boot in order to save power. PN7150 can switch to Standby state autonomously
(if configured by host).
In this state, PN7150 most blocks including CPU are no more supplied. Number of
wake-up sources exist to put PN7150 into Active state:
• I2C-bus interface wake-up event
• Antenna RF level detector
• Internal timer event when using polling loop (380 kHz Low-power oscillator is
enabled)
PN7150
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
If wake-up event occurs, PN7150 will switch to Active state. Any further operation
depends on software configuration and/or wake-up source.
10.1.2.4
Active state
Within the Active state, the system is acting as an NFC device. The device can be in 3
different functional modes: Idle, Poller and Target.
Table 9.
Functional modes in active state
Functional modes Description
Idle
the PN7150 is active and allows host interface communication. The RF
interface is not activated.
Listener
the PN7150 is active and is configured for listening to external device.
Poller
the PN7150 is active and is configured in Poller mode. It polls external device
Poller mode: In this mode, PN7150 is acting as Reader/Writer or NFC Initiator, searching
for or communicating with passive tags or NFC target. Once RF communication has
ended, PN7150 will switch to active battery mode (that is, switch off RF transmitter) to
save energy. Poller mode shall be used with 2.7 V < VBAT < 5.5 V and VEN
voltage > 1.1 V. Poller mode shall not be used with VBAT < 2.7 V. VDD(PAD) is within its
operational range (see Table 1).
Listener mode: In this mode, PN7150 is acting as a card or as an NFC Target. Listener
mode shall be used with 2.3 V < VBAT < 5.5 V and VEN voltage > 1.1 V.
10.1.2.5
Polling loop
The polling loop will sequentially set PN7150 in different power states (Active or Standby).
All RF technologies supported by PN7150 can be independently enabled within this
polling loop.
There are 2 main phases in the polling loop:
• Listening phase. The PN7150 can be in Standby power state or Listener mode
• Polling phase. The PN7150 is in Poller mode
PN7150
Product data sheet
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
Listening phase
Emulation
Pause
Type A
Type B
Type F
@424
ISO15693
Type F
@212
Polling phase
aaa-016741
Fig 7.
Polling loop: all phases enabled
Listening phase uses Standby power state (when no RF field) and PN7150 goes to
Listener mode when RF field is detected. When in Polling phase, PN7150 goes to Poller
mode.
To further decrease the power consumption when running the polling loop, PN7150
features a low-power RF polling. When PN7150 is in Polling phase instead of sending
regularly RF command, PN7150 senses with a short RF field duration if there is any NFC
Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms
(configurable duration, see Ref. 5) listening phase duration, the average power
consumption is around 150 A.
PN7150
Product data sheet
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PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
Listening phase
Emulation
Pause
Polling phase
aaa-016743
Fig 8.
Polling loop: low-power RF polling
Detailed description of polling loop configuration options is given in Ref. 5.
10.2 Microcontroller
PN7150 is controlled via an embedded ARM Cortex-M0 microcontroller core.
PN7150 features integrated in firmware are referenced in Ref. 5.
10.3 Host interface
PN7150 provides the support of an I2C-bus Slave Interface, up to 3.4 MBaud.
The host interface is waken-up on I2C-bus address.
To enable and ensure data flow control between PN7150 and host controller, additionally
a dedicated interrupt line IRQ is provided which Active state is programmable. See Ref. 5
for more information.
PN7150
Product data sheet
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PN7150
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Full NFC Forum-compliant controller with integrated firmware
10.3.1 I2C-bus interface
The I2C-bus interface implements a slave I2C-bus interface with integrated shift register,
shift timing generation and slave address recognition.
I2C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode
(3.4 MHz SCL) are supported.
The mains hardware characteristics of the I2C-bus module are:
•
•
•
•
Support slave I2C-bus
Standard, Fast and High-speed modes supported
Wake-up of PN7150 on its address only
Serial clock synchronization can be used by PN7150 as a handshake mechanism to
suspend and resume serial transfer (clock stretching)
The I2C-bus interface module meets the I2C-bus specification Ref. 4 except General call,
10-bit addressing and Fast mode Plus (Fm+).
10.3.1.1
I2C-bus configuration
The I2C-bus interface shares four pins with I2C-bus interface also supported by PN7150.
When I2C-bus is configured in EEPROM settings, functionality of interface pins changes
to one described in Table 10.
Table 10.
Functionality for I2C-bus interface
Pin name
Functionality
I2CADR0
I2C-bus address 0
I2CADR1
I2C-bus address 1
I2CSCL[1]
I2C-bus clock line
I2CSDA[1]
I2C-bus data line
[1]
I2CSCL and I2CSDA are not fail-safe and VDD(pad) shall always be available when using the SCL and SDA
lines connected to these pins.
PN7150 supports 7-bit addressing mode. Selection of the I2C-bus address is done by
2-pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, I2CADR1, I2CADR0,
R/W.
Table 11.
I2C-bus interface addressing
I2CADR1
I2CADR0
I2C-bus address
(R/W = 0, write)
I2C-bus address
(R/W = 1, read)
0
0
0x50
0x51
0
1
0x52
0x53
1
0
0x54
0x55
1
1
0x56
0x57
10.4 PN7150 clock concept
There are 4 different clock sources in PN7150:
• 27.12 MHz clock coming either/or from:
– Internal oscillator for 27.12 MHz crystal connection
PN7150
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– Integrated PLL unit which includes a 1 GHz VCO, taking is reference clock on pin
NFC_CLK_XTAL1
• 13.56 MHz RF clock recovered from RF field
• Low-power oscillator 40 MHz
• Low-power oscillator 380 kHz
10.4.1 27.12 MHz quartz oscillator
When enabled, the 27.12 MHz quartz oscillator applied to PN7150 is the time reference
for the RF front end when PN7150 is behaving in Reader mode or NFCIP-1 initiator.
Therefore stability of the clock frequency is an important factor for reliable operation. It is
recommended to adopt the circuit shown in Figure 9.
PN7150
NFC_CLK_XTAL1
NFC_CLK_XTAL2
c
crystal
27.12 MHz
c
aaa-016745
Fig 9.
27.12 MHz crystal oscillator connection
Table 12 describes the levels of accuracy and stability required on the crystal.
Table 12.
Crystal requirements
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fxtal
crystal frequency
ISO/IEC and FCC
compliancy
-
27.12 -
fxtal
crystal frequency accuracy
full operating range
[1]
100
-
+100 ppm
all VBAT range;
T = 20 °C
[1]
50
-
+50
ppm
all temperature range;
VBAT = 3.6 V
[1]
50
-
+50
ppm
-
50
100

MHz
ESR
equivalent series resistance
CL
load capacitance
-
10
-
pF
Pxtal
crystal power dissipation
-
-
100
W
[1]
This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and
ISO/IEC 18092, then  14 kHz apply.
10.4.2 Integrated PLL to make use of external clock
When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock
13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.
The 27.12 MHz of the PLL is used as the time reference for the RF front end when
PN7150 is behaving in Reader mode or ISO/IEC 18092 Initiator as well as in Target when
configured in Active Communication mode.
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The input clock on NFC_CLK_XTAL1 shall comply with the.following phase noise
requirements for the following input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz,
38.4 MHz and 52 MHz:
dBc/Hz
-20dBc/Hz
Input reference
noise floor
-140 dBc/Hz
Hz
Input reference noise corner
50 kHz
aaa-007232
Fig 10. Input reference phase noise characteristics
This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For
configuration of input frequency, refer to Ref. 9. There are 6 pre-programmed and
validated frequencies for the PLL: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and
52 MHz.
Table 13. PLL input requirements
Coupling: single-ended, AC coupling;
Symbol Parameter
fclk
fi(ref)acc
n
clock frequency
reference input
frequency accuracy
phase noise
Conditions
Min
Typ
Max
Unit
ISO/IEC and FCC
compliancy
-
13
-
MHz
-
19.2 -
MHz
-
24
-
MHz
-
26
-
MHz
-
38.4 -
MHz
-
52
-
MHz
full operating range;
frequencies typical values:
13 MHz, 26 MHz and
52 MHz
[1]
25
-
+25
ppm
full operating range;
frequencies typical values:
19.2 MHz, 24 MHz and
38.4 MHz
[1]
50
-
+50
ppm
140 -
-
dB/
Hz
input noise floor at 50 kHz
Sinusoidal shape
Vi(p-p)
peak-to-peak input
voltage
0.2
-
1.8
V
Vi(clk)
clock input voltage
0
-
1.8
V
0
-
1.8  10 % V
Square shape
Vi(clk)
PN7150
Product data sheet
clock input voltage
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[1]
This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and
ISO/IEC 18092, then  400 ppm limits apply.
For detailed description of clock request mechanisms, refer to Ref. 5 and Ref. 6.
10.4.3 Low-power 40 MHz  2.5 % oscillator
Low-power OSC generates a 40 MHz internal clock. This frequency is divided by two to
make the system clock.
10.4.4 Low-power 380 kHz oscillator
A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-up
PN7150 from Standby state. This allows implementation of low-power reader polling loop
at application level. Moreover, this 380 kHz is used as the reference clock for write access
to EEPROM memory.
10.5 Power concept
10.5.1 PMU functional description
The Power Management Unit of PN7150 generates internal supplies required by PN7150
out of VBAT input supply voltage:
• VDD: internal supply voltage
• VDD(TX): output supply voltage for the RF transmitter
The Figure 11 describes the main blocks available in PMU:
VBAT
VDD
VBAT1 and VBAT2
DSLDO
BANDGAP
VDD(TX)
TXLDO
NFCC
aaa-016748
Fig 11. PMU functional diagram
10.5.2 DSLDO: Dual Supply LDO
The input pin of the DSLDO is VBAT.
The Low drop-out regulator provides VDD required in PN7150.
PN7150
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10.5.3 TXLDO
Transmitter voltage can be generated by internal LDO (VDD(TX)) or come from an external
supply source VDD(TX).
The regulator has been designed to work in 2 configurations:
10.5.3.1
Configuration 1: supply connection in case the battery is used to generate RF field
The Low drop Out Regulator has been designed to generate a 3.0 V, 3.3 V or 3.6 V supply
voltage to a transmitter with a current load up to 180 mA.
The output is called VDD(TX). The input supply voltage of this regulator is a battery voltage
connected to VBAT1 pin.
VBAT1
BATTERY
VBAT2
VDD(TX)
NFCC
VDD(TX_IN)
aaa-017002
Fig 12. VBAT1 = VBAT2 (between 2.3 V and 5.5 V)
VDD(TX) value shall be chosen according to the minimum targeted VBAT value for which
reader mode shall work.
If VBAT is above 3.0 V plus the regulator voltage dropout, then VDD(TX) = 3.0 V shall be
chosen:
V BAT   3.0V + 1  load   V DD  TX  = 3.0V
3.0V  V BAT  2.3V  V DD  TX  = V BAT – 1  load
If VBAT is above 3.3 V plus the regulator voltage dropout, then VDD(TX) = 3.3 V shall be
chosen:
V BAT   3.3V + 1  load   V DD  TX  = 3.3V
3.3V  V BAT  2.3V  V DD  TX  = V BAT – 1  load
If VBAT is above 3.6 V plus the regulator voltage dropout, then VDD(TX) = 3.6 V shall be
chosen:
V BAT   3.6V + 1  load   V DD  TX  = 3.6V
3.6V  V BAT  2.3V  V DD  TX  = V BAT – 1  load
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5.0 V
VB
AT
3.6 V
Drop = 1 Ω * load
3.3 V
3.0 V
2.8 V
4.5 V
3.6 V
3.3 V
3.0 V
2.8 V
aaa-014174
Fig 13. VDD(TX) offset behavior
Figure 13 shows VDD(TX) offset disabled behavior for both cases of VDD(TX) programmed
for 3.0 V, 3.3 V or 3.6 V.
In Standby state, whenever VDD(TX) is configured for 3.0 V, 3.3 V or 3.6 V, VDD(TX) is
regulated at 2.5 V.
VBAT
2.5 V
2.5 V
aaa-009463
Fig 14. VDD(TX) behavior when PN7150 is in Standby state
Figure 14 shows the case where the PN7150 is in standby state.
10.5.3.2
Configuration 2: supply connection in case a 5 V supply is used to generate RF
field with the use of TXLDO
TXLDO has also the possibility to generate 4.75 V or 4.5 V supply in case the supply of
this regulator is an external 5 V supply.
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EXTERNAL 5 V
BATTERY
VBAT1
VBAT2
VDD(TX)
NFCC
VDD(TX_IN)
aaa-017003
Fig 15. VBAT1 = 5 V, VBAT2 between 2.3 V and 5.5 V
5.5 V
VBAT1
4.75 V
4.5 V
VDD(TX)
Drop = 1 Ω * load
aaa-017004
Fig 16. VDD(TX) behavior when PN7150 is supply using external supply on VBAT1
Figure 16 shows the behavior of VDD(TX) depending on VBAT1 value.
10.5.3.3
TXLDO limiter
The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in
reader or initiator modes.
The current limiter block compares an image of the TXLDO output current to a reference.
Once the reference is reached, the output current gets limited which is equivalent to a
typical output current of 220 mA whatever VBAT or VBAT1 value in the range of 2.3 V
to 5.5 V.
10.5.4 Battery voltage monitor
The PN7150 features low-power VBAT voltage monitor which protects mobile device
battery from being discharged below critical levels. When VBAT voltage goes below
VBATcritical threshold, then the PN7150 goes in Monitor state. Refer to Figure 17 for
principle schematic of the battery monitor.
The battery voltage monitor is enabled via an EEPROM setting.
At the first start-up, VBAT voltage monitor functionality is OFF and then enabled if properly
configured in EEPROM. The PN7150 monitors battery voltage continuously.
PN7150
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VBAT
enable
EEPROM
VBAT
MONITOR
REGISTERS
threshold
selection
POWER
MANAGEMENT
VDD
low power
SYSTEM
MANAGEMENT
VDDD
power off
POWER SWITCHES
DVDD_CPU
DIGITAL
(memories, cpu,
etc,...)
aaa-013868
Fig 17. Battery voltage monitor principle
The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM setting.
This value has a typical hysteresis around 150 mV.
10.6 Reset concept
10.6.1 Resetting PN7150
To enter reset, there are 2 ways:
• Pulling VEN voltage low (Hard Power Down state)
• if VBAT monitor is enabled: lowering VBAT below the monitor threshold (Monitor state, if
VEN voltage is kept above 1.1 V)
Reset means resetting the embedded FW execution and the registers values to their
default values. Part of these default values is defined from EEPROM data loaded values,
others are hardware defined. See Ref. 5 to know which ones are accessible to tune
PN7150 to the application environment.
To get out of reset:
• Pulling VEN voltage high with VBAT above VBAT monitor threshold if enabled
Figure 18 shows reset done via VEN pin.
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VBAT
VDD(PAD)
VEN
tw(VEN)
host
communication
possible
tboot
aaa-015878
Fig 18. Resetting PN7150 via VEN pin
See Section 14.2.2 for the timings values.
10.6.2 Power-up sequences
There are 2 different supplies for PN7150. PN7150 allows these supplies to be set up
independently, therefore different power-up sequences have to be considered.
10.6.2.1
VBAT is set up before VDD(PAD)
This is at least the case when VBAT pin is directly connected to the battery and when
PN7150 VBAT is always supplied as soon the system is supplied.
As VEN pin is referred to VBAT pin, VEN voltage shall go high after VBAT has been set.
VBAT
VDD(PAD)
tt(VDD(PAD)-VEN)
tboot
host
communication
possible
VEN
aaa-015879
Fig 19. VBAT is set up before VDD(PAD)
See Section 14.2.3 for the timings values.
10.6.2.2
VDD(PAD) and VBAT are set up in the same time
It is at least the case when VBAT pin is connected to a PMU/regulator which also supply
VDD(PAD).
PN7150
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VBAT
tt(VBAT-VEN)
VDD(PAD)
tboot
host
communication
possible
VEN
aaa-015881
Fig 20. VDD(PAD) and VBAT are set up in the same time
See Section 14.2.3 for the timings values.
10.6.2.3
PN7150 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut
off
This can be the case when VBAT pin is directly connected to the battery and when VDD(PAD)
is generated from a PMU. When the battery voltage is too low, then the PMU might no
more be able to generate VDD(PAD). When the device gets charged again, then VDD(PAD) is
set up again.
As the pins to select the interface are biased from VDD(PAD), when VDD(PAD) disappears the
pins might not be correctly biased internally and the information might be lost. Therefore it
is required to make the IC boot after VDD(PAD) is set up again.
VBAT
VDD(PAD)
tt(VDD(PAD)-VEN)
VEN
tW(VEN)
tboot
host
communication
possible
aaa-015884
Fig 21. VDD(PAD) is set up or cut-off after PN7150 has been enabled
See Section 14.2.3 for the timings values.
PN7150
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10.6.3 Power-down sequence
tVBAT(L)
VBAT
t > 0 ms
(nice to have)
t > 0 ms
VEN
VDD(PAD)
aaa-015886
Fig 22. PN7150 power-down sequence
10.7 Contactless Interface Unit
PN7150 supports various communication modes at different transfer speeds and
modulation schemes. The following chapters give more detailed overview of selected
communication modes.
Remark: all indicated modulation index and modes in this chapter are system
parameters. This means that beside the IC settings a suitable antenna tuning is required
to achieve the optimum performance.
10.7.1 Reader/Writer communication modes
Generally 5 Reader/Writer communication modes are supported:
•
•
•
•
•
10.7.1.1
PCD Reader/Writer for ISO/IEC 14443A/MIFARE
PCD Reader/Writer for Jewel/Topaz tags
PCD Reader/Writer for FeliCa cards
PCD Reader/Writer for ISO/IEC 14443B
VCD Reader/Writer for ISO/IEC 15693/ICODE
ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode
The ISO/IEC 14443A/MIFARE PCD communication mode is the general reader to card
communication scheme according to the ISO/IEC 14443A specification. This modulation
scheme is as well used for communications with Jewel/Topaz cards.
Figure 23 describes the communication on a physical level, the communication table
describes the physical parameters (the numbers take the antenna effect on modulation
depth for higher data rates).
PN7150
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PCD to PICC
100 % ASK at 106 kbit/s
> 25 % ASK at 212, 424 or 848 kbit/s
Modified Miller coded
NFCC
ISO/IEC 14443A - MIFARE
PCD mode
PICC (Card)
PICC to PCD,
subcarrier load modulation
Manchester coded at 106 kbit/s
BPSK coded at 212, 424 or 848 kbit/s
ISO/IEC 14443A - MIFARE
aaa-016749
Fig 23. ISO/IEC 14443A/MIFARE Reader/Writer communication mode diagram
Table 14.
Overview for ISO/IEC 14443A/MIFARE Reader/Writer communication mode
Communication
direction
ISO/IEC 14443A/ ISO/IEC 14443A higher transfer speeds
MIFARE/
Jewel/
Topaz
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
(16/13.56) s
100 % ASK
> 25 % ASK
> 25 % ASK
> 25 % ASK
Modified Miller
Modified Miller
Modified Miller
Modified Miller
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
Manchester
BPSK
BPSK
BPSK
PN7150  PICC
(data sent by PN7150 to a modulation on
card)
PN7150 side
bit coding
PICC  PN7150
(data received by PN7150 modulation on
from a card)
PICC side
The contactless coprocessor and the on-chip CPU of PN7150 handle the complete
ISO/IEC 14443A/MIFARE RF-protocol, nevertheless a dedicated external host has to
handle the application layer communication.
10.7.1.2
FeliCa PCD communication mode
The FeliCa communication mode is the general Reader/Writer to card communication
scheme according to the FeliCa specification. Figure 24 describes the communication on
a physical level, the communication overview describes the physical parameters.
PCD to PICC,
8 - 12 % ASK at 212 or 424 kbits/s
Manchester coded
NFCC
ISO/IEC 18092 - FeliCa
PCD mode
PICC to PCD,
load modulation
Manchester coded at 212 or 424 kbits/s
PICC (Card)
FeliCa card
aaa-016750
Fig 24. FeliCa Reader/Writer communication mode diagram
PN7150
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Table 15.
Overview for FeliCa Reader/Writer communication mode
Communication direction
FeliCa
FeliCa higher transfer speeds
Transfer speed
212 kbit/s
424 kbit/s
Bit length
(64/13.56) s
(32/13.56) s
modulation on
PN7150 side
8 %  12 % ASK
8 %  12 % ASK
bit coding
Manchester
Manchester
modulation on PICC
side
load modulation
load modulation
subcarrier frequency
no subcarrier
no subcarrier
bit coding
Manchester
Manchester
PN7150  PICC
(data sent by PN7150 to a card)
PICC  PN7150
(data received by PN7150 from a card)
The contactless coprocessor of PN7150 and the on-chip CPU handle the FeliCa protocol.
Nevertheless a dedicated external host has to handle the application layer
communication.
10.7.1.3
ISO/IEC 14443B PCD communication mode
The ISO/IEC 14443B PCD communication mode is the general reader to card
communication scheme according to the ISO/IEC 14443B specification.Figure 25
describes the communication on a physical level, the communication table describes the
physical parameters.
PCD to PICC,
8 - 14 % ASK at 106, 212, 424 or 848 kbit/s
NRZ coded
NFCC
ISO/IEC 14443 Type B
PCD mode
PICC to PCD,
subcarrier load modulation
BPSK coded at 106, 212, 424 or 848 kbit/s
PICC (Card)
ISO/IEC 14443 Type B
aaa-016751
Fig 25. ISO/IEC 14443B Reader/Writer communication mode diagram
Table 16.
Overview for ISO/IEC 14443B Reader/Writer communication mode
Communication
direction
ISO/IEC 14443B
ISO/IEC 14443B higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
(16/13.56) s
8 %  14 % ASK
8 %  14 % ASK 8 %  14 % ASK 8 %  14 % ASK
NRZ
NRZ
PN7150  PICC
(data sent by PN7150 to a modulation on
card)
PN7150 side
bit coding
NRZ
NRZ
PICC  PN7150
PN7150
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Table 16.
Overview for ISO/IEC 14443B Reader/Writer communication mode …continued
Communication
direction
ISO/IEC 14443B
ISO/IEC 14443B higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
(16/13.56) s
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
BPSK
BPSK
BPSK
BPSK
(data received by PN7150 modulation on
from a card)
PICC side
The contactless coprocessor and the on-chip CPU of PN7150 handles the complete
ISO/IEC 14443B RF-protocol, nevertheless a dedicated external host has to handle the
application layer communication.
10.7.1.4
ISO/IEC 15693 VCD communication mode
The ISO/IEC 15693 VCD Reader/Writer communication mode is the general reader to
card communication scheme according to the ISO/IEC 15693 specification. PN7150 will
communicate with VICC using only the higher data rates of the VICC (26.48 kbit/s with
single subcarrier and 26.69 kbit/s with dual subcarrier).
PN7150 supports the commands as defined by the ETSI HCI (see Ref. 13) and on top
offers the inventory of the tags (anticollision sequence) on its own.
NFCC
ISO/IEC 15693
VCD mode
VCD to VICC,
10 - 30 % or 100 % ASK at 1.65 or 26.48 kbit/s
pulse position coded
VICC to VCD,
subcarrier load modulation
Manchester coded at 26.48 or 26.69 kbit/s
Card
(VICC/TAG)
ISO/IEC 15693
aaa-016752
Fig 26. ISO/IEC 15693 VCD communication mode diagram
Figure 26 shows the communication schemes used.
2 communication schemes can be used from card to PN7150 and 2 communication
schemes can be used from PN7150 to card.
Thus, 4 communication schemes are possible.
Table 17.
Overview for ISO/IEC 15693 VCD communication mode
Communication direction
PN7150  VICC
(data sent by PN7150 to a
tag)
PN7150
Product data sheet
transfer speed
1.65 kbit/s
26.48 kbit/s
bit length
(8192/13.56) s
(512/13.56) s
modulation on
PN7150 side
10 %  30 % or 100 % ASK
10 %  30 % or 100 % ASK
bit coding
pulse position modulation 1 out of
256 mode
pulse position modulation 1 out of
4 mode
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Table 17.
Overview for ISO/IEC 15693 VCD communication mode …continued
Communication direction
VICC  PN7150
(data received by PN7150
from a tag)
transfer speed
26.48 kbit/s
26.69 kbit/s
bit length
(512/13.56) s
(508/13.56) s
modulation on VICC subcarrier load modulation
side
subcarrier load modulation
subcarrier frequency single subcarrier
dual subcarrier
bit coding
Manchester
Manchester
10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes
An NFCIP-1 communication takes place between 2 devices:
• NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1
communication.
• NFC Target: responds to NFC Initiator command either in a load modulation scheme
in Passive communication mode or using a self-generated and self-modulated RF
field for Active communication mode.
The NFCIP-1 communication differentiates between Active and Passive communication
modes.
• Active communication mode means both the NFC Initiator and the NFC Target are
using their own RF field to transmit data
• Passive communication mode means that the NFC Target answers to an NFC Initiator
command in a load modulation scheme. The NFC Initiator is active in terms of
generating the RF field.
PN7150 supports the Active Target, Active Initiator, Passive Target and Passive Initiator
communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
BATTERY
BATTERY
NFCC
NFCC
HOST
HOST
NFC Initiator: Passive or Active Communication modes
NFC Target: Passive or Active Communication modes
aaa-016755
Fig 27. NFCIP-1 communication mode
Nevertheless a dedicated external host has to handle the application layer
communication.
10.7.2.1
ACTIVE communication mode
Active communication mode means both the NFC Initiator and the NFC Target are using
their own RF field to transmit data.
PN7150
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host
1. NFC Initiator starts the communication at selected transfer speed
NFC Target
power
to generate
the field
host
host
NFCC
NFC Initiator
power
for digital
processing
host
NFCC
NFC Initiator
NFC Target
2. NFC Target answers at the same transfer speed
power
for digital
processing
power
to generate
the field
aaa-016756
Fig 28. Active communication mode
The following table gives an overview of the Active communication modes:
Table 18.
Overview for Active communication mode
Communication direction
ISO/IEC 18092, Ecma 340, NFCIP-1
Baud rate
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
modulation
100 % ASK
8 %  30 % ASK[1]
8 %  30 % ASK[1]
bit coding
Modified Miller
Manchester
Manchester
modulation
100 % ASK
8 %  30 % ASK[1]
8 %  30 % ASK[1]
bit coding
Miller
Manchester
Manchester
NFC Initiator to NFC Target
NFC Target to NFC Initiator
[1]
This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full
range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. 7.
10.7.2.2
Passive communication mode
Passive communication mode means that the NFC Target answers to an NFC Initiator
command in a load modulation scheme.
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host
1. NFC Initiator starts the communication at selected transfer speed
NFC Target
power
to generate
the field
host
host
NFCC
NFC Initiator
power
for digital
processing
host
NFCC
NFC Initiator
2. NFC Target answers using load modulation at the same transfer speed
NFC Target
power
to generate
the field
power
for digital
processing
aaa-016757
Fig 29. Passive communication mode
Table 19 gives an overview of the Passive communication modes:
Table 19.
Overview for Passive communication mode
Communication direction
ISO/IEC 18092, Ecma 340, NFCIP-1
Baud rate
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
modulation
100 % ASK
8 %  30 % ASK[1]
8 %  30 % ASK[1]
bit coding
Modified Miller
Manchester
Manchester
modulation
subcarrier load
modulation
load modulation
load modulation
subcarrier frequency
13.56 MHz/16
no subcarrier
no subcarrier
bit coding
Manchester
Manchester
Manchester
NFC Initiator to NFC Target
NFC Target to NFC Initiator
[1]
This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full
range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. 7.
10.7.2.3
NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive communication modes are
defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340.
10.7.2.4
NFCIP-1 protocol support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard.
However the datalink layer is according to the following policy:
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• Transaction includes initialization, anticollision methods and data transfer. This
sequence must not be interrupted by another transaction
• PSL shall be used to change the speed between the target selection and the data
transfer, but the speed should not be changed during a data transfer
10.7.3 Card communication modes
PN7150 can be addressed as a ISO/IEC 14443A or ISO/IEC 14443B cards. This means
that PN7150 can generate an answer in a load modulation scheme according to the
ISO/IEC 14443A or ISO/IEC 14443B interface description.
Remark: PN7150 does not support a complete card protocol. This has to be handled by
the host controller.
Table 20 and Table 21 describe the physical parameters.
10.7.3.1
Table 20.
ISO/IEC 14443A/MIFARE card communication mode
Overview for ISO/IEC 14443A/MIFARE card communication mode
Communication
direction
ISO/IEC 14443A
ISO/IEC 14443A higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
> 25 % ASK
> 25 % ASK
Modified Miller
Modified Miller
Modified Miller
subcarrier load modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
Manchester
BPSK
BPSK
PCD  PN7150
(data received by PN7150 modulation on PCD 100 % ASK
from a card)
side
bit coding
PN7150  PCD
(data sent by PN7150 to a modulation on
card)
PN7150 side
10.7.3.2
Table 21.
ISO/IEC 14443B card communication mode
Overview for ISO/IEC 14443B card communication mode
Communication
direction
ISO/IEC 14443B
ISO/IEC 14443B higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) s
(64/13.56) s
(32/13.56) s
8 %  14 % ASK
8 %  14 % ASK
NRZ
NRZ
NRZ
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
BPSK
BPSK
BPSK
PCD  PN7150
(data received by PN7150 modulation on PCD 8 %  14 % ASK
from a Reader)
side
bit coding
PN7150  PCD
(data sent by PN7150 to a modulation on
Reader)
PN7150 side
PN7150
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10.7.4 Frequency interoperability
When in communication, PN7150 is generating some RF frequencies. PN7150 is also
sensitive to some RF signals as it is looking from data in the field.
In order to avoid interference with others RF communication, it is required to tune the
antenna and design the board according to Ref. 6.
Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of
13.56 MHz  7 kHz, FCC regulation does not allow this wide spread and limits the
dispersion to  50 ppm, which is in line with PN7150 capability.
PN7150
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11. Limiting values
Table 22. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD(PAD) VDD(PAD) supply voltage
VBAT
battery supply voltage
VESD
electrostatic discharge voltage
Conditions
Min
Max
Unit
supply voltage for host
interface
-
4.35
V
-
6
V
HBM; 1500 , 100 pF;
EIA/JESD22-A114-D
-
1.5
kV
CDM; field induced model;
EIA/JESC22-C101-C
-
500
V
55
+150 C
-
600
mW
storage temperature
Tstg
[1]
Ptot
total power dissipation
VRXN(i)
RXN input voltage
0
2.5
V
VRXP(i)
RXP input voltage
0
2.5
V
[1]
all modes
The design of the solution shall be done so that for the different use cases targeted the power to be
dissipated from the field or generated by PN7150 does not exceed this value.
12. Recommended operating conditions
Table 23.
Parameter
Conditions
Tamb
ambient temperature
JEDEC PCB-0.5
VBAT
VDD(PAD)
Ptot
PN7150
Product data sheet
Operating conditions
Symbol
battery supply voltage
VDD(PAD) supply voltage
total power dissipation
Min
Typ
Max
Unit
30
+25
+85
C
battery monitor enabled;
VSS = 0 V
[1]
2.3
-
5.5
V
Card Emulation and
Passive Target;
VSS = 0 V
[1]
2.3
-
5.5
V
Reader, Active Initiator
and Active Target;
VSS = 0 V
[1]
2.7
-
5.5
V
[2]
[2]
supply voltage for host
interface
1.8 V host supply;
VSS = 0 V
[1]
1.65
1.8
1.95
V
3 V host supply;
VSS = 0 V
[1]
3.0
-
3.6
V
-
-
420
mW
Reader;
IVDD(TX) = 100 mA;
VBAT = 5.5 V
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Table 23.
Operating conditions …continued
Symbol
Parameter
Conditions
IBAT
battery supply current
in Hard Power Down
state; VBAT = 3.6 V;
T = 25 °C
Ith(Ilim)
current limit threshold
current
Min
Typ
Max
Unit
-
10
14
A
in Standby state;
VBAT = 3.6 V; T = 25 °C
-
20
-
A
in Monitor state;
VBAT = 2.75 V; T = 25 °C
-
-
14
A
-
A
[3]
in low-power polling
loop; VBAT = 3.6 V; T =
25 °C;
loop time = 500 ms
[4]
-
150
PCD mode at typical 3 V
[5]
-
-
190
mA
current limiter on VDD(TX)
pin; VDD(TX) = 3.3 V
[5]
-
180
-
mA
[1]
VSS represents VSS(PAD) and VSS(TX).
[2]
The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with
another device must be taken into account).
[3]
External clock on NFC_CLK_XTAL1 must be LOW.
[4]
See Ref. 10 for computing the power consumption as it depends on several parameters.
[5]
The antenna shall be tuned not to exceed the maximum of IBAT.
13. Thermal characteristics
Table 24.
Thermal characteristics
Symbol Parameter
Rth(j-a)
Conditions
thermal resistance from in free air with exposed pad
junction to ambient
soldered on a 4 layer JEDEC PCB
Min Typ
Max Unit
-
-
40
K/W
14. Characteristics
14.1 Current consumption characteristics
Table 25.
Current consumption characteristics for operating ambient temperature range
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IBAT
battery supply current
in Hard Power Down state;
VBAT = 3.6 V; VEN
voltage = 0 V
-
10
20
A
-
20
35
A
in Idle and Listener
modes; VBAT = 3.6 V
-
4.55
-
mA
in Poller mode;
VBAT = 3.6 V
-
150
-
mA
-
10
20
A
in Standby state;
VBAT = 3.6 V;
in Monitor state;
VBAT = 2.75 V
PN7150
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[2]
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[1]
Refer to Section 10.1.2 for the description of the power modes.
[2]
This is the same value for VBAT = 2.3 V when the monitor threshold is set to 2.3 V.
14.2 Functional block electrical characteristics
14.2.1 Battery voltage monitor characteristics
Table 26.
Battery voltage monitor characteristics
Symbol Parameter
Vth
threshold voltage
Vhys
hysteresis voltage
Conditions
Min
Typ
Max
Unit
set to 2.3 V
2.15
2.3
2.45
V
set to 2.75 V
2.6
2.75
2.9
V
100
150
200
mV
14.2.2 Reset via VEN
Table 27.
Reset timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tW(VEN)
VEN pulse width
to reset
10
-
-
s
tboot
boot time
-
-
2.5
ms
Min
Typ
Max
Unit
14.2.3 Power-up timings
Table 28.
Power-up timings
Symbol
Parameter
Conditions
tt(VBAT-VEN)
transition time from pin VBAT VBAT, VEN
to pin VEN
voltage = HIGH
0
0.5
-
ms
tt(VDDPAD-VEN)
transition time from pin
VDD(PAD) to pin VEN
VDD(PAD), VEN
voltage = HIGH
0
0.5
-
ms
tt(VBAT-VDDPAD)
transition time from pin VBAT VBAT,
to pin VDD(PAD)
VDD(PAD) = HIGH
0
0.5
-
ms
Min
Typ
Max
Unit
20
-
-
ms
14.2.4 Power-down timings
Table 29.
Power-down timings
Symbol
Parameter
tVBAT(L)
time VBAT LOW
Conditions
14.2.5 I2C-bus timings
Here below are timings and frequency specifications.
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tf(I2CSDA)
tr(I2CSDA)
tHD;DAT
I2CSDA
tSU;STA
tHD;STA
tHIGH
tSU;DAT
tLOW
I2CSCL
aaa-017006
Fig 30. I2C-bus timings
Table 30.
High-speed mode I2C-bus timings specification
Symbol
Parameter
fclk(I2CSCL) clock frequency on pin
I2CSCL
Max
Unit
SCL;
Cb < 100 pF
0
3.4
MHz
set-up time for a repeated
START condition
Cb < 100 pF
160
-
ns
tHD;STA
hold time (repeated) START
condition
Cb < 100 pF
160
-
ns
tLOW
LOW period of the SCL clock
Cb < 100 pF
160
-
ns
tHIGH
HIGH period of the SCL clock
Cb < 100 pF
60
-
ns
tSU;DAT
data set-up time
Cb < 100 pF
10
-
ns
tHD;DAT
data hold time
Cb < 100 pF
0
-
ns
tr(I2CSDA)
rise time on pin I2CSDA
I2C-bus
SDA;
Cb < 100 pF
10
80
ns
tf(I2CSDA)
fall time on pin I2CSDA
I2C-bus SDA;
Cb < 100 pF
10
80
ns
Vhys
hysteresis voltage
Schmitt trigger inputs;
Cb < 100 pF
0.1VDD(PAD) -
V
Table 31.
Fast mode I2C-bus timings specification
Symbol
Parameter
Conditions
Min
Max
Unit
I2C-bus
SCL;
Cb < 400 pF
0
400
kHz
)
Product data sheet
Min
I2C-bus
tSU;STA
fclk(I2CSCL clock frequency on pin I2CSCL
PN7150
Conditions
tSU;STA
set-up time for a repeated
START condition
Cb < 400 pF
600
-
ns
tHD;STA
hold time (repeated) START
condition
Cb < 400 pF
600
-
ns
tLOW
LOW period of the SCL clock
Cb < 400 pF
1.3
-
s
tHIGH
HIGH period of the SCL clock
Cb < 400 pF
600
-
ns
tSU;DAT
data set-up time
Cb < 400 pF
100
-
ns
tHD;DAT
data hold time
Cb < 400 pF
0
900
ns
Vhys
hysteresis voltage
Schmitt trigger inputs;
Cb < 400 pF
0.1VDD(PAD) -
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14.3 Pin characteristics
14.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins characteristics
Table 32.
Input clock characteristics on NFC_CLK_XTAL1 when using PLL
Symbol
Parameter
Vi(p-p)

Conditions
Min
Typ
Max
Unit
peak-to-peak input voltage
0.2
-
1.8
V
duty cycle
35
-
65
%
Table 33.
Pin characteristics for NFC_CLK_XTAL1 when PLL input
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIH
HIGH-level input current
VI = VDD
1
-
+1
A
IIL
LOW-level input current
VI = 0 V
1
-
+1
A
Vi
input voltage
-
-
VDD
V
Vi(clk)(p-p)
peak-to-peak clock input
voltage
200
-
-
mV
Ci
input capacitance
-
2
-
pF
Table 34.
Pin characteristics for 27.12 MHz crystal oscillator
all power modes
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ci(NFC_CLK_XTAL1)
NFC_CLK_XTAL1 input
capacitance
VDD = 1.8 V
-
2
-
pF
Ci(NFC_CLK_XTAL2)
NFC_CLK_XTAL2 input
capacitance
-
2
-
pF
Table 35.
PLL accuracy
Symbol Parameter
fo(acc)
output frequency accuracy
Conditions
Min Typ Max Unit
deviation added to
NFC_CLK_XTAL1 frequency
on RF frequency generated;
worst case whatever input
frequency
50 -
+50
ppm
14.3.2 VEN input pin characteristics
PN7150
Product data sheet
Table 36.
VEN input pin characteristics
Symbol
Parameter
VIH
VIL
IIH
HIGH-level input current
IIL
LOW-level input current
Ci
input capacitance
Conditions
Min
Typ
Max
HIGH-level input voltage
1.1
-
VBAT
V
LOW-level input voltage
0
-
0.4
V
VEN voltage = VBAT
1
-
+1
A
VEN voltage = 0 V
1
-
+1
A
-
5
-
pF
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14.3.3
Pin characteristics for IRQ and CLK_REQ
Table 37.
pin characteristics for IRQ and CLK_REQ
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output
voltage
IOH < 3 mA
VDD(PAD)  0.4
-
VDD(PAD) V
VOL
LOW-level output
voltage
IOL < 3 mA
0
-
0.4
V
CL
load capacitance
-
-
20
pF
tf
fall time
high speed
1
-
3.5
ns
slow speed
2
-
10
ns
rise time
tr
CL = 12 pF max
high speed
1
-
3.5
ns
slow speed
2
-
10
ns
0.35
-
0.85
M
Min
Typ
Max Unit
[1]
pull-down resistance
Rpd
[1]
CL = 12 pF max
Activated in HPD and Monitor states.
14.3.4 Input pin characteristics for RXN and RXP
Table 38.
Parameter
VRXN(i)
RXN input voltage
0
-
VDD
V
VRXP(i)
RXP input voltage
0
-
VDD
V
Ci(RXN)
RXN input capacitance
-
12
-
pF
RXP input capacitance
-
12
-
pF
Zi(RXN-VDDMI
input impedance between
RXN and VDD(MID)
Reader, Card and
P2P modes
0
-
15
k
Zi(RXP-VDDMID input impedance between
RXP and VDD(MID)
)
Reader, Card and
P2P modes
0
-
15
k
106 kbit/s
-
150
200
mV(p-p)
212 kbit/s to
424 kbit/s
-
150
200
mV(p-p)
106 kbit/s
-
150
200
mV(p-p)
212 kbit/s to
424 kbit/s
-
150
200
mV(p-p)
Vi(dyn)(RXN)
Vi(dyn)(RXP)
Product data sheet
Conditions
Ci(RXP)
D)
PN7150
Input pin characteristics for RXN and RXP
Symbol
RXN dynamic input voltage
RXP dynamic input voltage
Miller coded
Miller coded
Vi(dyn)(RXN)
RXN dynamic input voltage
Manchester, NRZ
or BPSK coded;
106
kbit/s to 848 kbit/s
-
150
200
mV(p-p)
Vi(dyn)(RXP)
RXP dynamic input voltage
Manchester, NRZ
or BPSK coded;
106
kbit/s to 848 kbit/s
-
150
200
mV(p-p)
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Table 38.
Input pin characteristics for RXN and RXP …continued
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Vi(dyn)(RXN)
RXN dynamic input voltage
All data coding;
106 kbit/s to
848 kbit/s
VDD
-
-
V(p-p)
Vi(dyn)(RXP)
RXP dynamic input voltage
All data coding;
106 kbit/s to
848 kbit/s
VDD
-
-
V(p-p)
Vi(RF)
RF input voltage
RF input voltage
detected; Initiator
modes
100
-
mV(p-p)
14.3.5 Output pin characteristics for TX1 and TX2
Table 39.
Output pin characteristics for TX1 and TX2
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
HIGH-level output
voltage
VDD(TX) = 3.3 V and
IOH = 30 mA;
PMOS driver fully on
VDD(TX)  150 -
-
mV
VOL
LOW-level output
voltage
VDD(TX) = 3.3 V and
IOL = 30 mA;
NMOS driver fully on
-
-
200
mV
Table 40.
Typ
Output resistance for TX1 and TX2
Conditions
Min
Typ
Max
Unit
ROL
Symbol Parameter
LOW-level output
resistance
VDD(TX)  100 mV;
CWGsN = 01h
-
-
85

ROL
LOW-level output
resistance
VDD(TX)  100 mV;
CWGsN = 0Fh
-
-
5

ROH
HIGH-level output
resistance
VDD(TX)  100 mV
-
-
4

14.3.6 Input pin characteristics for I2CADR0 and I2CADR1
Table 41.
PN7150
Product data sheet
Input pin characteristics for I2CADR0 and I2CADR1
Symbol
Parameter
Conditions
VIH
HIGH-level input
voltage
0.65VDD(PAD) -
VDD(PAD)
VIL
LOW-level input
voltage
0
-
0.35VDD(PAD) V
IIH
HIGH-level input
current
VI = VDD(PAD)
1
-
+1
A
IIL
LOW-level input
current
VI = 0 V
1
-
+1
A
Ci
input capacitance
-
5
-
pF
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Min
Typ Max
Unit
V
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14.3.7 Pin characteristics for I2CSDA and I2CSCL
Table 42.
Pin characteristics for I2CSDA and I2CSCL
Symbol Parameter
Conditions
VOL
LOW-level output IOL < 3 mA
voltage
CL
load capacitance
[1]
Min
Typ Max
Unit
0
-
0.4
V
-
-
10
pF
30
-
250
ns
tf
fall time
CL = 100 pF;
Rpull-up = 2 k;
Standard and Fast mode
[1]
tf
fall time
CL = 100 pF;
Rpull-up = 1 k;
High-speed mode
[1]
80
-
110
ns
tr
rise time
CL = 100 pF;
Rpull-up = 2 k;
Standard and Fast mode
[1]
30
-
250
ns
CL = 100 pF;
[1]
10
-
100
ns
V
Rpull-up = 1 k;
High-speed mode
VIH
HIGH-level input
voltage
0.7VDD(PAD) -
VDD(PAD)
VIL
LOW-level input
voltage
0
-
0.3VDD(PAD) V
IIH
HIGH-level input
current
VI = VDD(PAD);
high impedance
1
-
+1
A
IIL
LOW-level input
current
VI = 0 V;
high impedance
1
-
+1
A
Ci
input capacitance
-
5
-
pF
Conditions
Min
Typ
Max
Unit
VSS = 0V
1.65
1.8
1.95
V
[1]
Only for pin I2CSDA as I2CSCL is only used as input.
14.3.8 VDD pin characteristic
Table 43.
Electrical characteristic of VDD
Symbol Parameter
VDD
PN7150
Product data sheet
VDD supply voltage
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Full NFC Forum-compliant controller with integrated firmware
15. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
B
D
SOT618-1
terminal 1
index area
A
A1
E
c
detail X
e1
e
C
v
w
1/2 e b
11
20
C A B
C
y
y1 C
L
21
10
e
Eh
e2
1/2 e
1
30
terminal 1
index area
40
31
X
Dh
0
2.5
Dimensions (mm are the original dimensions)
Unit
mm
A(1)
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.21
min 0.80 0.00 0.18
5 mm
scale
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
0.2
6.1
6.0
5.9
4.25
4.10
3.95
6.1
6.0
5.9
4.25
4.10
3.95
0.5
4.5
4.5
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
SOT618-1
References
IEC
JEDEC
JEITA
sot618-1_po
European
projection
Issue date
02-10-22
13-11-05
MO-220
Fig 31. Package outline, HVQFN40, SOT618-1, MSL3
PN7150
Product data sheet
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16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Product data sheet
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Full NFC Forum-compliant controller with integrated firmware
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 44 and 45
Table 44.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 45.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
PN7150
Product data sheet
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Full NFC Forum-compliant controller with integrated firmware
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PN7150
Product data sheet
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Full NFC Forum-compliant controller with integrated firmware
17. Abbreviations
Table 46.
PN7150
Product data sheet
Abbreviations
Acronym
Description
API
Application Programming Interface
ASK
Amplitude Shift keying
ASK modulation
index
The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/
(Vmax + Vmin)  100%
Automatic device
discovery
Detect and recognize any NFC peer devices (initiator or target) like: NFC
initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Standard
and Ultralight PICC, ISO/IEC 15693 VICC
BPSK
Bit Phase Shift Keying
Card Emulation
The IC is capable of handling a PICC emulation on the RF interface including
part of the protocol management. The application handling is done by the host
controller
DEP
Data Exchange Protocol
DSLDO
Dual Supplied LDO
FW
FirmWare
HPD
Hard Power Down
LDO
Low Drop Out
LFO
Low Frequency Oscillator
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
MSL
Moisture Sensitivity Level
NCI
NFC Controller Interface
NFC
Near Field Communication
NFCC
NFC Controller, PN7150 in this data sheet
NFC Initiator
Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication
NFCIP
NFC Interface and Protocol
NFC Target
Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication
NRZ
Non-Return to Zero
P2P
Peer to Peer
PCD
Proximity Coupling Device. Definition for a Card reader/writer device
according to the ISO/IEC 14443 specification or MIFARE
PCD -> PICC
Communication flow between a PCD and a PICC according to the
ISO/IEC 14443 specification or MIFARE
PICC
Proximity Interface Coupling Card. Definition for a contactless Smart Card
according to the ISO/IEC 14443 specification or MIFARE
PICC-> PCD
Communication flow between a PICC and a PCD according to the
ISO/IEC 14443 specification or MIFARE
PMOS
P-channel MOSFET
PMU
Power Management Unit
PSL
Parameter SeLection
TXLDO
Transmitter LDO
UM
User Manual
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Rev. 3.2 — 25 May 2016
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Full NFC Forum-compliant controller with integrated firmware
Table 46.
PN7150
Product data sheet
Abbreviations …continued
Acronym
Description
VCD
Vicinity Coupling Device. Definition for a reader/writer device according to the
ISO/IEC 15693 specification
VCO
Voltage Controlled Oscillator
VICC
Vicinity Integrated Circuit Card
WUC
Wake-Up Counter
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NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
18. References
[1]
NFC Forum Device Requirements — V1.3
[2]
NFC Controller Interface (NCI) Technical Specification — V1.0
[3]
ISO/IEC 14443 — parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1
2006 (01/09/2006) and part 4: 2nd edition 2008 (15/07/2008)
[4]
I2C Specification — I2C Specification, UM10204 rev4 (13/02/2012)
[5]
PN7150 User Manual — UM10936 PN7150 User Manual
[6]
PN7150 Hardware Design Guide — AN11756 PN7150 Hardware Design Guide
[7]
PN7150 Antenna design and matching guide — AN11755 PN7150 Antenna
design and matching guide
[8]
ISO/IEC 18092 (NFCIP-1) — edition, 15/032013. This is similar to Ecma 340.
[9]
ISO/IEC15693 — part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001)
[10] PN7150 Low-Power Mode Configuration — AN11757 PN7150 Low-Power Mode
Configuration
[11] ISO/IEC 21481 (NFCIP-2) — edition, 01/07/2012. This is similar to Ecma 352.
[12] ETSI SWP — TS 102 613; UICC - Contactless Front-end (CLF) Interface; Part 1:
Physical and data link layer characteristics (Release 9)
[13] ETSI HCI — TS 102 622; UICC - Contactless Front-end (CLF) Interface; Host
Controller Interface (HCI) (Release 9)
[14] ETSI UICC — TS 102 221; UICC - Terminal Interface; Physical and logical
characteristics (Release 9)
[15] EMVCo — EMV Contactless Specifications for Payment Systems - Book D - EMV
Contactless Communication Protocol Specification”, version 2.3.1, December 2013
PN7150
Product data sheet
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19. Revision history
Table 47.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PN7150 v3.2
20160525
Product data sheet
-
PN7150 v3.1
Modifications:
•
•
•
•
•
Titles: updated.
Section 2: updated.
Section 3: updated.
Table 3: updated.
Section 11: removed.
PN7150 v3.1
20160511
Product data sheet
-
PN7150 v3.0
PN7150 v3.0
20151209
Product data sheet
-
PN7150 v2.1
PN7150 v2.1
20151127
Preliminary data sheet
-
PN7150 v2.0
PN7150 v2.0
20150701
Preliminary data sheet
-
PN7150 v1.2
PN7150 v1.2
20150625
Objective data sheet
-
PN7150 v1.1
PN7150 v1.1
20150212
Objective data sheet
-
PN7150 v1.0
PN7150 v1.0
20150129
Objective data sheet
-
-
Modifications:
PN7150
Product data sheet
•
Initial version
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20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PN7150
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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50 of 55
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NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the Near
Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481
does not convey an implied license under any patent right infringed by
implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or other
IP right) covering combinations of those products with other products,
whether hardware or software.
20.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
DESFire — is a trademark of NXP Semiconductors N.V.
MIFARE — is a trademark of NXP B.V.
MIFARE Classic — is a trademark of NXP B.V.
MIFARE Ultralight — is a trademark of NXP B.V.
ICODE and I-CODE — are trademarks of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PN7150
Product data sheet
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51 of 55
PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7
System power modes description . . . . . . . . . .10
System power modes configuration . . . . . . . . .10
System power modes description . . . . . . . . . .10
PN7150 power states . . . . . . . . . . . . . . . . . . . 11
Functional modes in active state . . . . . . . . . . .12
Functionality for I2C-bus interface . . . . . . . . . .15
I2C-bus interface addressing . . . . . . . . . . . . . .15
Crystal requirements . . . . . . . . . . . . . . . . . . . .16
PLL input requirements . . . . . . . . . . . . . . . . . .17
Overview for ISO/IEC 14443A/MIFARE
Reader/Writer communication mode . . . . . . . .26
Overview for FeliCa
Reader/Writer communication mode . . . . . . . .27
Overview for ISO/IEC 14443B Reader/Writer
communication mode . . . . . . . . . . . . . . . . . . .27
Overview for ISO/IEC 15693 VCD communication
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Overview for Active communication mode . . . .30
Overview for Passive communication mode . .31
Overview for ISO/IEC 14443A/MIFARE card
communication mode . . . . . . . . . . . . . . . . . . .32
Overview for ISO/IEC 14443B card
communication mode . . . . . . . . . . . . . . . . . . .32
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34
Operating conditions . . . . . . . . . . . . . . . . . . . .34
Thermal characteristics . . . . . . . . . . . . . . . . . .35
Current consumption characteristics for operating
ambient temperature range . . . . . . . . . . . . . . .35
Battery voltage monitor characteristics . . . . . .36
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Power-up timings . . . . . . . . . . . . . . . . . . . . . . .36
Power-down timings . . . . . . . . . . . . . . . . . . . .36
High-speed mode I2C-bus timings specification
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Fast mode I2C-bus timings specification . . . . .37
Input clock characteristics on NFC_CLK_XTAL1
when using PLL . . . . . . . . . . . . . . . . . . . . . . . .38
Pin characteristics for NFC_CLK_XTAL1 when
PLL input . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Pin characteristics for 27.12 MHz crystal
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PLL accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .38
VEN input pin characteristics . . . . . . . . . . . . . .38
pin characteristics for IRQ and CLK_REQ . . .39
Input pin characteristics for RXN and RXP . . .39
Output pin characteristics for TX1 and TX2 . . .40
Output resistance for TX1 and TX2 . . . . . . . . .40
Input pin characteristics for I2CADR0 and
I2CADR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Pin characteristics for I2CSDA and I2CSCL. . .41
Electrical characteristic of VDD . . . . . . . . . . . . .41
SnPb eutectic process (from J-STD-020C) . . .44
PN7150
Product data sheet
Table 45. Lead-free process (from J-STD-020C) . . . . . . 44
Table 46. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 47. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 49
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 25 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
52 of 55
PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
PN7150 transmission modes . . . . . . . . . . . . . . . . .2
PN7150 package marking (top view) . . . . . . . . . . .4
PN7150 block diagram . . . . . . . . . . . . . . . . . . . . .6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PN7150 connection . . . . . . . . . . . . . . . . . . . . . . . .9
System power mode diagram . . . . . . . . . . . . . . .10
Polling loop: all phases enabled . . . . . . . . . . . . .13
Polling loop: low-power RF polling. . . . . . . . . . . .14
27.12 MHz crystal oscillator connection. . . . . . . .16
Input reference phase noise characteristics . . . .17
PMU functional diagram . . . . . . . . . . . . . . . . . . .18
VBAT1 = VBAT2 (between 2.3 V and 5.5 V) . . . . . .19
VDD(TX) offset behavior. . . . . . . . . . . . . . . . . . . . .20
VDD(TX) behavior when PN7150 is in Standby
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
VBAT1 = 5 V, VBAT2 between 2.3 V and 5.5 V . . . .21
VDD(TX) behavior when PN7150 is supply using
external supply on VBAT1 . . . . . . . . . . . . . . . . . . .21
Battery voltage monitor principle . . . . . . . . . . . . .22
Resetting PN7150 via VEN pin . . . . . . . . . . . . . .23
VBAT is set up before VDD(PAD) . . . . . . . . . . . . . . .23
VDD(PAD) and VBAT are set up in the same time . .24
VDD(PAD) is set up or cut-off after PN7150 has been
enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PN7150 power-down sequence. . . . . . . . . . . . . .25
ISO/IEC 14443A/MIFARE Reader/Writer
communication mode diagram. . . . . . . . . . . . . . .26
FeliCa Reader/Writer communication mode
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
ISO/IEC 14443B Reader/Writer communication
mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ISO/IEC 15693 VCD communication mode
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
NFCIP-1 communication mode . . . . . . . . . . . . . .29
Active communication mode . . . . . . . . . . . . . . . .30
Passive communication mode . . . . . . . . . . . . . . .31
I2C-bus timings . . . . . . . . . . . . . . . . . . . . . . . . . .37
Package outline, HVQFN40, SOT618-1, MSL3. .42
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PN7150
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 25 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
53 of 55
PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
24. Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
General description . . . . . . . . . . . . . . . . . . . . . . 1
3
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
6
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
7
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
9.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
10
Functional description . . . . . . . . . . . . . . . . . . . 8
10.1
System modes . . . . . . . . . . . . . . . . . . . . . . . . . 9
10.1.1
System power modes . . . . . . . . . . . . . . . . . . . . 9
10.1.2
PN7150 power states . . . . . . . . . . . . . . . . . . . 10
10.1.2.1 Monitor state . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.1.2.2 Hard Power Down (HPD) state. . . . . . . . . . . . 11
10.1.2.3 Standby state . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.1.2.4 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.1.2.5 Polling loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.2
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . 14
10.3
Host interface . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.3.1
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 15
10.3.1.1 I2C-bus configuration . . . . . . . . . . . . . . . . . . . 15
10.4
PN7150 clock concept . . . . . . . . . . . . . . . . . . 15
10.4.1
27.12 MHz quartz oscillator . . . . . . . . . . . . . . 16
10.4.2
Integrated PLL to make use of external clock 16
10.4.3
Low-power 40 MHz ± 2.5 % oscillator . . . . . . 18
10.4.4
Low-power 380 kHz oscillator. . . . . . . . . . . . . 18
10.5
Power concept . . . . . . . . . . . . . . . . . . . . . . . . 18
10.5.1
PMU functional description . . . . . . . . . . . . . . . 18
10.5.2
DSLDO: Dual Supply LDO . . . . . . . . . . . . . . . 18
10.5.3
TXLDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.5.3.1 Configuration 1: supply connection in case the
battery is used to generate RF field . . . . . . . . 19
10.5.3.2 Configuration 2: supply connection in case
a 5 V supply is used to generate RF field
with the use of TXLDO . . . . . . . . . . . . . . . . . . 20
10.5.3.3 TXLDO limiter . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.5.4
Battery voltage monitor. . . . . . . . . . . . . . . . . . 21
10.6
Reset concept. . . . . . . . . . . . . . . . . . . . . . . . . 22
10.6.1
Resetting PN7150 . . . . . . . . . . . . . . . . . . . . . 22
10.6.2
Power-up sequences . . . . . . . . . . . . . . . . . . . 23
10.6.2.1 VBAT is set up before VDD(PAD) . . . . . . . . . . . . 23
10.6.2.2 VDD(PAD) and VBAT are set up in the same time 23
10.6.2.3 PN7150 has been enabled before VDD(PAD) is set
up or before VDD(PAD) has been cut off . . . . . . 24
10.6.3
10.7
10.7.1
10.7.1.1
Power-down sequence . . . . . . . . . . . . . . . . . 25
Contactless Interface Unit . . . . . . . . . . . . . . . 25
Reader/Writer communication modes . . . . . . 25
ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD
communication mode. . . . . . . . . . . . . . . . . . . 25
10.7.1.2 FeliCa PCD communication mode. . . . . . . . . 26
10.7.1.3 ISO/IEC 14443B PCD communication mode. 27
10.7.1.4 ISO/IEC 15693 VCD communication mode . . 28
10.7.2
ISO/IEC 18092, Ecma 340 NFCIP-1
communication modes . . . . . . . . . . . . . . . . . . 29
10.7.2.1 ACTIVE communication mode. . . . . . . . . . . . 29
10.7.2.2 Passive communication mode . . . . . . . . . . . . 30
10.7.2.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 31
10.7.2.4 NFCIP-1 protocol support . . . . . . . . . . . . . . . 31
10.7.3
Card communication modes . . . . . . . . . . . . . 32
10.7.3.1 ISO/IEC 14443A/MIFARE card communication
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.7.3.2 ISO/IEC 14443B card communication mode . 32
10.7.4
Frequency interoperability . . . . . . . . . . . . . . . 33
11
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34
12
Recommended operating conditions . . . . . . 34
13
Thermal characteristics . . . . . . . . . . . . . . . . . 35
14
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
14.1
Current consumption characteristics . . . . . . . 35
14.2
Functional block electrical characteristics . . . 36
14.2.1
Battery voltage monitor characteristics . . . . . 36
14.2.2
Reset via VEN . . . . . . . . . . . . . . . . . . . . . . . . 36
14.2.3
Power-up timings . . . . . . . . . . . . . . . . . . . . . . 36
14.2.4
Power-down timings. . . . . . . . . . . . . . . . . . . . 36
14.2.5
I2C-bus timings. . . . . . . . . . . . . . . . . . . . . . . . 36
14.3
Pin characteristics . . . . . . . . . . . . . . . . . . . . . 38
14.3.1
NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins
characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
14.3.2
VEN input pin characteristics . . . . . . . . . . . . . 38
14.3.3
Pin characteristics for IRQ and CLK_REQ . 39
14.3.4
Input pin characteristics for RXN and RXP . . 39
14.3.5
Output pin characteristics for TX1 and TX2 . . 40
14.3.6
Input pin characteristics for I2CADR0 and
I2CADR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
14.3.7
Pin characteristics for I2CSDA and I2CSCL . 41
14.3.8
VDD pin characteristic. . . . . . . . . . . . . . . . . . . 41
15
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42
16
Soldering of SMD packages . . . . . . . . . . . . . . 43
16.1
Introduction to soldering. . . . . . . . . . . . . . . . . 43
16.2
Wave and reflow soldering. . . . . . . . . . . . . . . 43
16.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43
16.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44
continued >>
PN7150
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.2 — 25 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
54 of 55
PN7150
NXP Semiconductors
Full NFC Forum-compliant controller with integrated firmware
17
18
19
20
20.1
20.2
20.3
20.4
20.5
21
22
23
24
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
48
49
50
50
50
50
51
51
51
52
53
54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 May 2016
Document identifier: PN7150
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