an1181

Application Note 1181
Author: Pengju Kong
ISL6442 Dual PWM and Linear Controller Evaluation
Board User Guide
This application note describes how to use the ISL6442EVAL1Z
(Rev. C) board to evaluate the ISL6442 dual switching
regulator, plus one linear regulator. Refer to the schematic,
BOM (Bill of Materials), and board layout (at the end of this
document), as needed. The ISL6442 datasheet is also used as
a reference.
Configuration
Quick Start Evaluation
Figure 1 shows a photo of the populated board, and Figure 2
shows a plot of the top layer for reference, and details the
available input and output connections. Two switchers share
one input VIN. The linear regulator has separate turrets for its
input (VIN3) and GND. Each output has turrets for VOUT and
GND, plus a scope probe socket, for low noise waveforms.
The outputs are set up as follows:
VIN = 6V
• Switcher VOUT1 = 1.8V @ 3A (with VIN = 6V)
• Switcher VOUT2 = 3.3V @ 3A (with VIN = 6V)
• Linear VOUT3 = 5.0V @ 0.3A (with VIN3 = 6V)
The outputs are switching at ~1.4MHz rate, based on the
resistor selected on the RT pin.
VOUT2
test
point
Iout
A
LOAD
The current range for the switcher output that is presently
supported is limited by the FETs used. The FDS6912A dual FET
(in SO-8 package) can handle up to 3A. However, the ISL6442
gate drivers are capable of driving discrete upper and lower
FETs for up to 25A output current as well, even though not
supported on this board.
VOUT1
test
point
+
_ V
Vout
VOUT1 LOAD
VOUT2 LOAD
The linear output supports ~1W. The output current capability
of the linear regulator is determined mainly by the power
dissipation of the FET as mounted:
PVOUT3 = (VIN3-VOUT3)*IOUT3.
VIN3 = 6V
VOUT3 LOAD
FIGURE 2. ISL6442EVAL1Z INPUT AND OUTPUT CONNECTIONS
Quick Start Setup (Light Load)
For a quick and easy test, one 6V supply is needed. Connect P1
(VIN) and P7 (VIN3) to each other, and to the 6V supply; connect
the supply GND to P2 and P9. Attach light loads to each
output.
Switch on the power supply; all three outputs should turn on to
their expected DC values; use a voltmeter or oscilloscope to
view them. VOUT1 and VOUT2 will have a ramp time of a few
milliseconds (VOUT3 will be much faster).
Note that the IC and all three inputs are sharing one supply
voltage in this simple example. The linear VIN3 can certainly be
different, since it has its own input posts.
Board Features and Modifications
FIGURE 1. ISL6442EVAL1Z BOARD PHOTO
November 28, 2011
AN1181.1
1
Heavier loads can be evaluated by placing them across the
appropriate output to GND. Resistors, electronic loads, or
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas Inc. 2011. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1181
actual loads can be used. It is STRONGLY recommended that the
power be turned off when attaching loads, due to the tight
spacing of the posts. The switcher outputs should be able to
provide at least 3A; monitor the FET temperature if you try to go
higher, to be sure the conditions will allow it. Make sure the input
power supply can source the amount of input current necessary
to drive the maximum loads to be tested.
start their soft-start ramps at the same time. In this case, both
outputs track each other initially; this is accomplished by
selecting the ratio of SS/EN capacitors to match their output
voltages. The ramp times shown are on the order of a few
milliseconds, as determined by the SS/EN capacitors on the
board.
The linear VOUT3 is especially sensitive to power dissipation
concerns; it will change as the user varies either the input
voltage, the output voltage, and/or the load current. The
equation used is PVOUT3 = (VIN3-VOUT3)*IOUT3. The PNP bipolar
will also be rated for how well the power is dissipated from the
package and spread out on the board; this is another variable
that the user must keep in mind for their design and layout.
CH1 VIN
(2V/DIV)
CH2 VOUT1
(2V/DIV)
CH3 VOUT2
(2V/DIV)
JP1 is used to disable VOUT1, by shorting SS/EN1 to GND. JP2
does the same function for VOUT2.
CH4 VOUT3
(5V/DIV)
The switching frequency is controlled by a resistor (R4) on the RT
pin, to GND. Refer to the datasheet for the curve of resistor
values versus frequency.
Each output voltage is determined by a resistor divider from the
output to its FB pin to GND. See the ISL6442 datasheet for the
formulas to calculate the values. Note that there are some
limitations; the switchers can approach 100% duty, but will be
limited by dead time, rDSON of the FETs at maximum load,
switching frequency, etc. The maximum values are limited by the
VIN available (if you want go higher, check the ratings of the FETs,
and other output components to be sure they can handle it). The
minimum output voltage will be just above the 0.6V internal
reference. The maximum output voltage for the linear is limited
by the VIN3 and the LCDR pin (which is biased from 5V). Thus, the
maximum output voltage is close to the 5V set on the board; it is
not recommended to go higher. The minimum voltage will also
be just above the 0.6V internal reference.
5ms/DIV; VIN3 = VIN
FIGURE 3. TYPICAL POWER-UP WAVEFORMS WITH VIN
Figure 4 shows the detail soft start waveform of PWM1 (PMW2
would be similar). The full SS/EN1 ramp is shown; the output
doesn’t start to ramp until the SS/EN passes the ~1V threshold
for Enable. The output ramps from zero to full scale, while
SS/EN1 ramps from 1.0V to 1.6V. Finally, the EN/SS1 keeps
ramping up to ~3.2V, at which point the ramp is considered done
(the PGOOD timer would start from this point, if both outputs
ramps were done).
CH1 EN/SS1
(1V/DIV)
Performance Waveforms
~3.2V
These figures depict the ISL6442EVAL1Z performance during
typical operational situations, as well as during fault conditions.
Loading of the output can be most easily done via an electronic
load; however, other methods can work as well.
Figure 3 shows a typical power-up sequence, with all inputs
connected to a single VIN = VIN3 = 6V. When VCC exceeds its
POR rising trip point (~4.4V), the IC is enabled, and the linear
VOUT3 comes up almost immediately. Meanwhile, the two SS/EN
pins start charging (not shown), but the outputs do not start
ramping until the SS/EN pins ~1V; then both switcher outputs
2
CH1 OUT1
(1V/DIV)
2ms/DIV
FIGURE 4. PWM1 SOFT-START
AN1181.1
November 28, 2011
Application Note 1181
Figures 5 and 6 show the PHASE1 signal (which has the same
timing as UGATE1) and the output voltage ripple on VOUT1 at no
load and 3A load. The switching frequency is 1.4 MHz.
CH1
SS/EN2
(2V/DIV)
CH4
ILOAD2
(5A/DIV)
CH1
PHASE1
(2V/DIV)
CH2
VOUT2
(1V/DIV)
CH2 (AC)
VOUT1
(20mV/DIV)
T0
T1
2ms/DIV; VOUT2 = 3.3V; VIN = 6V; ROCSET = 2.15kW
FIGURE 7. PWM2 OVERCURRENT HICCUP MODE
0.2µs/DIV; VOUT1 = 1.8V; VIN = 6V
FIGURE 5. PWM1 SWITCHING AND RIPPLE WAVEFORMS AT
NO LOAD
CH1
PHASE1
(2V/DIV)
Conclusion
The ISL6442EVAL1Z evaluation board showcases a simple, but
high-performance dual regulator, providing control in a variety of
applications, with emphasis on computer systems. The
high-current MOSFET drivers of the ISL6442 yield a highly
efficient power conversion solution with a reduced number of
external components in a compact footprint.
Documentation
See the following pages for more detailed information, including:
• “Schematic” of ISL6442EVAL1Z
CH2 (AC)
VOUT1
(20mV/DIV)
0.2µs/DIV; VOUT1 = 1.8V; VIN = 6V
FIGURE 6. PWM1 SWITCHING AND RIPPLE WAVEFORMS
AT 3A LOAD
Figure 7 shows the overcurrent hiccup mode already in
operation. At time T0, the SS/EN2 is discharged to GND (it may
not have time to reach GND, due to the limited size of the
discharge transistor, plus the size of the timing capacitor). Once
SS/EN2 is below ~1V, the output should shut off, and the load
current goes to zero; this occurs by time T1. Once SS/EN2 rises
above 1V again, the VOUT2 will try to turn on again. If the output
remains shorted, the output current will be limited on each clock
cycle to an average value low enough to keep the dissipation
reasonable.
3
• Table 1, “BILL OF MATERIALS” on page 5
• “ISL6442EVAL1Z Board Layout” on page 7. Note that this
board layout has not been fully optimized for performance or
minimum board area, primarily due to the various options, test
points, and other features to make testing easier. So while it
follows most of the recommended practices, it could
potentially be improved for any given single application.
References
Datasheet: ISL6442 datasheet
Visit us on the internet, at: http://www.intersil.com
AN1181.1
November 28, 2011
Schematic
VIN
OUT
F
VIN
F
1
1
1
P1
C1
100UF
NOTES:
2
2
C8
100UF
OUT
VCC5
D
GROUND &
GROUND ARE TIED TOGETHER
E
1
GND
AS CLOSE TO U1 PIN 11 AND PIN 23 AS POSSIBLE.
1
P2
E
D
G
D
7
1
S
D
8
E
1
TP3
C9
10UF
FDS6912A
C2
1
C7
2 2
5.49K
1
OCSET2
8200PF
1
C28
100UF
1
C30
100UF
C32
10UF
E
E
SP1
1
2
1
R17
DNP
0805
R23
E
R15
2
4.7
2
G
D
7
1
S
D
8
2
P4
D
E
FB1
C34
1500PF
OUT
C10
10UF
2
2
1
R25
3.24K
R19
10.5K
FDS6912A
1
TP5
GND
1
1
E
1
C36
0.1UF
0
TP8
4
3
C26
OPEN
0805
Q2
R4
10.2K
1
EN2
6
E
2
TP11
5
D
FDS6912A
D
1
47PF
D
S
2
4.7
G
1
Q1
4
3
2
ISL6442IAZ
C4
2
PGOOD
R16
2
R2
1
IN
1
11
D
1
TP6
2
1
TP10
FB2
1
0.015UF
1.5UH
2
C6
2
+1.8V
1
VOUT1
P3
3A
L1
1
0.1UF
2
2
2.1K
2
24
23
22
21
20
19
18
17
16
15
14
13
VIN
BOOT1
UGATE1
PHASE1
LGATE1
VCC
PGND
LGATE2
PHASE2
UGATE2
BOOT2
1
R1
1
OCSET1
SS1/EN1
COMP1
FB1
RT
SGND
LCDR
LCFB
FB2
COMP2
SS2/EN2
1
E
1
0.1UF
S
D
6
2.2UH
C27
OPEN
0805
FDS6912A
2
E
R18
DNP
0805
C33
10UF
E
E
E
P13
T1
FZT749
2
1
2
1
DRAWN BY:
TIM KLEMANN
2
2
C14
2
RELEASED
1
R11
1
OPEN
1
AN1181.1
November 28, 2011
R6
5.11K
1
11
4
37.4K
2
A
D
SP3
C23
0.1UF
1
D
R22
5.11K
3
R14
0
R10
1
1
2
2
C17
10UF
2
C16
68UF
B
C35
1000PF
OUT
2
+5.0V
1
VOUT3
P9
0.3A
4
1
2
1
0
FB2
D
1
1
2
SGND
P8
3
R5
1
E
R26
6.04K
R21
23.2K
1
0.1UF
B
2
C22
100UF
2
1
P6
1
2
C19
0.1UF
C13
2
GND
1
TP7
2
100
1
TP1
1
2
1
1
1
+6.0V
1
VIN3
P7
R9
4
C37
0.1UF
R24
0
1
PGOOD
2
1
SGND
P10
UPDATED
BY:
BY:
DATE:
01/24/2007
DATE:
ENGINEER:
THEJU BERNARD
TITLE:
DATE:
ISL6442
EVALUATION BOARD
SCHEMATIC
DATE:
TP2
TESTER
OPEN
D
MASK#
D
HRDWR ID
REV.
ISL6442EVAL1Z
FILENAME:
~/ISL6442/ISL6442EVAL1ZC
8
7
6
C
SP2
1
2
E
1
1
R3
36.5K
C31
100UF
2
IN
C29
100UF
22
VCC5
+3.3V
1
VOUT2
P5
3A
L2
3
3
D
1
1
5
1
D
2
G
1
4.7
C
TP14
4
2
2
1
1
Q2
1
TP4
R12
0.1UF
2
R8
2.15K
2
1
2
2
1
C12
1000PF
2
2
D
R20
5.11K
C20
D
2
C3
1
JP2
1
1
P12
5
4
3
2
SHEET
1
1
OF
A
C
1
Application Note 1181
1
2
3
4
5
6
7
8
9
10
11
12
1
1
100PF
IN
E
1
TP13
C21
1
U1
22
2
1
1
1
TP9
FB1
2
4.7
TP12
C5
1
1
0.1UF
1
2
D
2
R13
2
2
2
2
1
E
1
JP1
E
Q1
D
1UF
2
2
2
C15
R7
2.15K
1
4
P11
4.7UF
1
2
1
1
EN1
C24
OPEN
C18
C11
1000PF
Application Note 1181
TABLE 1. BILL OF MATERIALS
ITEM
QTY
PART REFERENCE
VALUE
1
4
C28-C31
100µF
2
1
C16
3
4
4
DESCRIPTION
PART #
MANUFACTURER
CAP-TANT LOWESR, SMD, D3, 100µF, 10V,
20%, POSCAP, ROHS
10TPB100M
SANYO
68µF
CAP, SMD, 6x3.2, 68µF, 10V, 20% POSCAP,
ROHS
10TPB68MC
SANYO
C2, C3, C13, C19
0.1µF
CAPACITOR, SMD, 0603, 0.10µF, 50V, 10%,
X7R
Generic
1
C18
4.7µF
CAPACITOR, SMD, 1206, 4.7µF, 16V, 10%,
X7R, ROHS
Generic
5
3
C17, C32, C33
10µF
CAP, SMD, 1210, 10µF, 25V, 20%, X7R,
ROHS
Generic
6
3
C1, C8, C22
100µF
CAP, SMD, 8X10.2, 100µF, 25V, 20%, AL.EL,
ROHS
7
2
C9, C10
10µF
CAP, SMD, 1210, 10µF, 35V, 10%, X5R,
ROHS
Generic
8
1
C5
100pF
CAP, SMD, 0603, 100pF, 50V, 5%, COG,
ROHS
Generic
9
3
C11, C12, C35
1000pF
CAP, SMD, 0603, 1000pF, 50V, 10%, X7R,
ROHS
Generic
10
5
C20, C21, C23, C36, C37
0.1µF
CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R,
ROHS
Generic
11
1
C34
1500pF
CAP, SMD, 0603, 1500pF, 50V, 10%, X7R,
ROHS
Generic
12
1
C6
15nF
CAP, SMD, 0603, .015µF, 50V, 10%, X7R,
ROHS
Generic
13
1
C4
47pF
CAP, SMD, 0603, 47pF, 50V, 5%, NPO, ROHS
Generic
14
1
C7
8200pF
CAP, SMD, 0603, 8200pF, 50V, 10%, X7R,
ROHS
Generic
15
1
C15
1µF
CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS
Generic
16
1
L1
1.5µH
COIL-PWR INDUCTOR, SMD, 6.9x6.5m,
1.5µH, 20%, 9A, ROHS
IHLP-2525CZ-ER1R5-M01
IHLP-2525CZ-ER-1R5M01
17
1
L2
2.2µH
COIL-PWR INDUCTOR, SMD, 6.9x6.5m,
2.2µH, 20%, 10A, ROHS
IHLP-2525CZ-ER2R2-M01
IHLP-2525CZ-ER-2R2M01
18
3
SP1-SP3
CONN-SCOPE PROBE TEST PT, COMPACT,
PCB MNT, ROHS
131-4353-00
131-4353-00
19
13
P1-P13
CONN-TURRET, TERMINAL POST, TH, ROHS
1514-2
1514-2
20
14
TP1-TP14
CONN-MINI TEST POINT, VERTICAL, WHITE,
ROHS
5002
5002
21
2
JP1, JP2
CONN-JUMPER, 2PIN, SHUNT, ROHS
SPC02SYAN
SPC02SYAN
22
1
U1
IC-PWM/LINEAR CONTROLLER, 24P, QSOP,
ROHS
ISL6442IAZ
ISL6442IAZ
23
2
Q1, Q2
TRANSIST-DUAL MOS, N-CHAN, 8P, SOIC,
30V, 6A, ROHS
FDS6912A
FDS6912A
24
1
T1
FZT749
FZT749
25
4
R12, R13, R15, R16
TRANSISTOR, PNP, SMD, SOT223, -25V, -3A,
ROHS
5
4.7Ω
RES, SMD, 0603, 4.7Ω, 1/10W, 1%, TF,
ROHS
EEE-FC1E101P
EEE-FC1E101P
Generic
AN1181.1
November 28, 2011
Application Note 1181
TABLE 1. BILL OF MATERIALS (Continued)
ITEM
QTY
PART REFERENCE
VALUE
26
4
R5, R14, R23, R24
0Ω
RESISTOR, SMD, 0603, 0Ω, 1/10W, TF,
ROHS
Generic
27
1
R9
100Ω
RES, SMD, 0603, 100Ω, 1/10W, 1%, TF,
ROHS
Generic
28
1
R4
10.2kΩ
RES, SMD, 0603, 10.2k, 1/10W, 1%, TF,
ROHS
Generic
29
1
R19
10.5kΩ
RES, SMD, 0603, 10.5k, 1/10W, 1%, TF,
ROHS
Generic
30
1
R1
2.1kΩ
RES, SMD, 0603, 2.1k, 1/10W, 1%, TF, ROHS
Generic
31
2
R7, R8
2.15kΩ
RES, SMD, 0603, 2.15k, 1/10W, 1%, TF,
ROHS
Generic
32
1
R21
23.2kΩ
RES, SMD, 0603, 23.2k, 1/10W, 1%, TF,
ROHS
Generic
33
1
R25
3.24kΩ
RES, SMD, 0603, 3.24k, 1/10W, 1%, TF,
ROHS
Generic
34
1
R3
36.5kΩ
RES, SMD, 0603, 36.5k, 1/10W, 1%, TF,
ROHS
Generic
35
1
R10
37.4kΩ
RES, SMD, 0603, 37.4k, 1/10W, 1%, TF,
ROHS
Generic
36
3
R6, R20, R22
5.11kΩ
RES, SMD, 0603, 5.11k, 1/10W, 1%, TF,
ROHS
Generic
37
1
R2
5.49kΩ
RES, SMD, 0603, 5.49k, 1/10W, 1%, TF,
ROHS
Generic
38
1
R26
6.04kΩ
RES, SMD, 0603, 6.04k, 1/10W, 1%, TF,
ROHS
Generic
6
DESCRIPTION
PART #
MANUFACTURER
AN1181.1
November 28, 2011
Application Note 1181
ISL6442EVAL1Z Board Layout
FIGURE 8. TOP SILKSCREEN
FIGURE 9. TOP LAYER
FIGURE 10. 2ND LAYER
FIGURE 11. 3RD LAYER
7
AN1181.1
November 28, 2011
Application Note 1181
ISL6442EVAL1Z Board Layout
FIGURE 12. BOTTOM LAYER
(Continued)
FIGURE 13. BOTTOM SILKSCREEN
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
AN1181.1
November 28, 2011
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