DATASHEET Dual 2A/1.7A Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator ISL78322 Features The ISL78322 is a high efficiency, dual synchronous step-down DC/DC regulator that can deliver up to 2A/1.7A continuous output current per channel. The channels are 180° out-of-phase for input RMS current and EMI reduction. The supply voltage range of 2.8V to 5.5V allows for the use of a single Li+ cell, three NiMH cells or a regulated 5V input. The current mode control architecture enables very low duty cycle operation at high frequency with fast transient response and excellent loop stability. The ISL78322 operates at 2.25MHz switching frequency which allows for the use of small, low cost inductors and capacitors. Each channel is optimized for generating an output voltage as low as 0.6V. • Dual 2A/1.7A high efficiency synchronous buck regulator with up to 97% efficiency, low IQ (40µA) • 180° out-of-phase outputs reduce ripple current and EMI • Start-up with prebiased output prevents negative current flow in output stage • Selectable forced PWM mode and PFM mode • External synchronization up to 8MHz • Negative current detection and protection • 100% maximum duty cycle for lowest dropout • Internal current mode compensation The ISL78322 has a user configurable mode of operation-forced PWM mode and PFM/PWM mode. The forced PWM mode reduces noise and RF interference while the PFM mode provides highest efficiency by reducing switching losses at light loads. In PFM mode of operation, both channels draw a total quiescent current of only 40µA, hence enabling high light load efficiency and maximizing battery life. • Peak current limiting, hiccup mode short circuit protection and over-temperature protection • Pb-free (RoHs compliant) • AEC-Q100 qualified component Applications The ISL78322 offers a 1ms Power-Good (PG) signal to monitor both outputs at power-up. When shut down, ISL78322 discharges the output capacitors. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL78322 is offered in a 4mmx3mm, 12 Lead DFN package with 1mm maximum height. The complete converter occupies less than 1.8cm2 area. • DC/DC POL modules • µC/µP, FPGA and DSP power • Automotive embedded processor power supply systems The ISL78322 is qualified to AEC-Q100 and specified for operation across the -40°C to +105°C (grade 2) ambient temperature range. 100 EFFICIENCY (%) 90 80 2.5VOUT1 PWM 70 2.5VOUT1 PFM 3.3VOUT2 PFM 60 50 40 3.3VOUT2 PWM 0.0 0.2 0.4 0.6 2.25MHz 5VIN AT +25°C 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT LOAD (A) FIGURE 1. CHARACTERISTIC CURVE August 26, 2014 FN7908.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78322 Typical Applications L1 1 .2 µ H O UTPU T1 2 .5 V /2 A LX1 C2 22µF C3 10pF PGND R2 316k IN P U T 2 .8 V T O 5 .5 V FB1 V IN R3 100k EN1 C1 2 x 10µF IS L 7 8 3 2 2 EN2 L2 1 .2 µ H O UTPU T2 1 .8 V /1 .7 A LX2 PG C4 22µF PGND SYNC R5 200k C5 10pF FB2 R6 100k FIGURE 2. TYPICAL APPLICATION DIAGRAM - DUAL INDEPENDENT OUTPUTS TABLE 1. COMPONENT VALUE SELECTION VOUT 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V C1 2x10µF 2x10µF 2x10µF 2x10µF 2x10µF 2x10µF C2 (or C4) 22µF 22µF 22µF 22µF 22µF 22µF C3 (or C5) 10pF 10pF 10pF 10pF 10pF 10pF L1 (or L2) 1.0~2.2µH 1.0~2.2µH 1.0~2.2µH 1.5~3.3µH 1.5~3.3µH 1.5~4.7µH R2 (or R5) 33k 100k 150k 200k 316k 450k R3 (or R6) 100k 100k 100k 100k 100k 100k In Table 1, the minimum output capacitor value is given for different output voltage to make sure the whole converter system is stable. Output capacitance should increase to support faster load transient requirement. Submit Document Feedback 2 FN7908.2 August 26, 2014 ISL78322 Block Diagram EN1 SS OoFft TS TSAta Rrt T VCC SHUTDO W N 27pF V IN 1 250k B A N D G A P 0 .6 V + SHUTDO W N P W M /P F M L O G IC CO NTROLLER P R O T E C T IO N D R IV E R + COMP EAMP 3pF PGND SLO PE COMP + + CSA1 FB1 0 .2 V 1 .6 k LX1 SCP + + OCP 1 .2 5 V + V IN O S C IL L A T O R + S K IP 0 .2 6 5 V 0 .5 4 6 V 1M N E G A T IV E C U R R E N T L IM IT PG 1m s DELAY ZERO - CRO SS S E N S IN G THERM AL SHUT DOW N SYNC SHUTDO W N VCC SHUTDOW N SHUTDO W N V IN 2 B A N D G A P 0 .6 V + EN2 27pF 250k SO So F ft TS TSAta R rt T + COMP EAMP P W M /P F M L O G IC CO NTROLLER P R O T E C T IO N D R IV E R 3pF SLO PE COMP 0 .2 V + PGND + + CSA2 FB2 1 .6 k LX2 SCP + + OCP + S K IP 1 .1 V 0 .2 6 5 V 0 .5 4 6 V N E G A T IV E C U R R E N T L IM IT ZERO- CRO SS S E N S IN G Submit Document Feedback 3 FN7908.2 August 26, 2014 ISL78322 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL78322ARZ PART TEMP. RANGE MARKING (°C) BEKA Pin Configuration PACKAGE (Pb-Free) ISL78322 (12 LD DFN) TOP VIEW PKG. DWG. # -40 to +105 12 Ld 4x3 DFN L12.4x3 NOTES: FB1 1 12 FB2 EN1 2 11 EN2 PG 3 VIN1 4 9 VIN2 LX1 5 8 LX2 PGND1 6 7 PGND2 1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020. PAD 10 SYNC 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78322. For more information on MSL please see techbrief TB363. Pin Description PIN NUMBER SYMBOL DESCRIPTION 1 FB1 The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1 regulator output voltage. 2 EN1 Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge output capacitor when driven to low. Do not leave this pin floating. 3 PG 1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the VOUT1 and VOUT2 voltages. There is an internal 1MΩ pull-up resistor. 4 VIN1 Input supply voltage for Channel 1. Connect 10µF ceramic capacitor to PGND1. 5 LX1 Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1. 6 PGND1 Negative supply for power stage 1. 7 PGND2 Negative supply for power stage 2 and system ground. 8 LX2 Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2. 9 VIN2 Input supply voltage for Channel 2 and to provide logic bias. Make sure that VIN2 is ≥ VIN1. Connect 10µF ceramic capacitor to PGND2. 10 SYNC Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode. Connect to an external function generator for synchronization. Negative edge trigger. Do not leave this pin floating. 11 EN2 Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge output capacitor when driven to low. Do not leave this pin floating. 12 FB2 The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage. - EXPOSED PAD The exposed pad must be connected to the SGND pin for proper electrical performance. Add as much vias as possible for optimal thermal performance. Submit Document Feedback 4 FN7908.2 August 26, 2014 ISL78322 Absolute Maximum Ratings (Reference to GND) Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms) EN1, EN2, PG, SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VIN + 0.3V LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 7V (20ms) FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV Machine Model(Tested per JESD22-C101E) . . . . . . . . . . . . . . . . . . 250V Charged Device Model (Tested per AEC-Q100-11) . . . . . . . . . . . . . . . 2kV Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 4x3 DFN Package (Notes 4, 5) . . . . . . . . 41 3 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 5.5V Load Current Range Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A Load Current Range Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.7A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions: TA = -40°C to +105°C, VIN = 2.8V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 1.2µH, C1 = 2 x 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply across the operating temperature range, -40°C to +105°C. PARAMETER TYP MAX (Note 6) UNITS 2.5 2.8 V 40 55 µA SYNC = GND, EN1 = EN2 = VIN, fSW = 2.25MHz, no load at the output 0.86 1 mA VIN = 5.5V, EN1 = EN2 = GND 6.5 12 µA 0.6 0.610 V SYMBOL TEST CONDITIONS MIN (Note 6) INPUT SUPPLY VIN Undervoltage Lock-out Threshold VUVLO Rising Falling Quiescent Supply Current IVIN Shutdown Supply Current ISD 2.0 SYNC = VIN, EN1 = EN2 = VIN, no switches switching 2.4 V OUTPUT REGULATION FB1, FB2 Regulation Voltage VFB_ FB1, FB2 Bias Current IFB_ 0.590 VFB = 0.55V 0.1 µA ±1.5 % Output Voltage Accuracy SYNC = VIN, Io = 0A to 2A SYNC = GND, Io = 0A to 2A ±1 % Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.8V) 0.2 %/V 1.3 ms Soft-Start Ramp Time Cycle OVERCURRENT PROTECTION Dynamic Current Limit ON-time tOCON 17 Clock pulses Dynamic Current Limit OFF-time tOCOFF 4 SS cycle Peak Overcurrent Limit Peak SKIP Limit Submit Document Feedback 5 Ipk1 2.7 3.2 3.6 A Ipk2 2.3 2.8 3.2 A Iskip1 520 610 730 mA Iskip2 520 610 730 mA FN7908.2 August 26, 2014 ISL78322 Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions: TA = -40°C to +105°C, VIN = 2.8V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 1.2µH, C1 = 2 x 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply across the operating temperature range, -40°C to +105°C. (Continued) PARAMETER MIN (Note 6) TYP MAX (Note 6) UNITS Ivalley1 -2.2 -1.6 -1 A Ivalley2 -2.2 -1.6 -1 A VIN = 5.5V, IO = 200mA Channel 1 90 115 mΩ VIN = 5.5V, IO = 200mA Channel 2 100 125 mΩ VIN = 5.5V, IO = 200mA Channel 1 80 103 mΩ 90 112 mΩ SYMBOL Negative Current Limit TEST CONDITIONS LX1, LX2 P-Channel MOSFET ON-Resistance N-Channel MOSFET ON-Resistance VIN = 5.5V, IO = 200mA Channel 2 LX_ Maximum Duty Cycle 100 PWM Switching Frequency fSW 1.8 2.25 5.4 2.7 MHz 8 MHz Synchronization Range (Note 7) Channel 1 to Channel 2 Phase Shift Rising edge to rising edge timing 180 ° LX Minimum On Time SYNC = High (forced PWM mode) 65 ns Soft Discharge Resistance RDIS_ EN = LOW 80 100 130 Ω 0.4 V 0.01 0.1 µA PG Output Low Voltage Sinking 1mA, VFB = 0.5V PG Pin Leakage Current PG = VIN = 3.6V PG Pull-up Resistor 1 MΩ Internal PGOOD Low Rising Threshold Percentage of nominal regulation voltage 85 91 97 % Internal PGOOD Low Falling Threshold Percentage of nominal regulation voltage 78 85 92 % Delay Time (Rising Edge) 0.76 Internal PGOOD Delay Time (Falling Edge) 2 ms 4 µs 0.4 V EN1, EN2, SYNC Logic Input Low Logic Input High 1.4 SYNC Logic Input Leakage Current ISYNC Enable Logic Input Leakage Current IEN_ Pulled up to 5.5V V 0.1 1 µA 0.1 1 µA Thermal Shutdown 150 °C Thermal Shutdown Hysteresis 25 °C NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. The operational frequency per switching channel will be half of the SYNC frequency. Submit Document Feedback 6 FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. 90 90 80 EFFICIENCY (%) 100 EFFICIENCY (%) 100 1.8VOUT2 1.5VOUT2 2.5VOUT1 70 1.2VOUT1 60 50 80 1.8VOUT2 70 1.2VOUT1 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 40 0.0 2.0 FIGURE 3. EFFICIENCY vs LOAD, 2.25MHz, 3.3VIN PWM 100 90 90 EFFICIENCY (%) 100 80 1.8VOUT2 2.5VOUT1 70 1.5VOUT1 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.0 FIGURE 4. EFFICIENCY vs LOAD, 2.25MHz, 5VIN PWM 1.2VOUT1 50 3.3VOUT2 80 1.8VOUT2 2.5VOUT1 70 1.5VOUT1 1.2VOUT1 60 50 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 40 0.0 2.0 FIGURE 5. EFFICIENCY vs LOAD, 2.25MHz, 3.3VIN PFM 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.0 1.23 0.75 1.22 OUTPUT VOLTAGE (V) 3.3VIN PWM 0.60 0.45 0.30 3.3VIN PFM 5 VIN PWM 0.15 0.00 0.0 0.2 FIGURE 6. EFFICIENCY vs LOAD, 2.25MHz, 5VIN PFM 0.90 POWER DISSIPATION (W) 1.5VOUT1 2.5VOUT1 50 40 0.0 EFFICIENCY (%) 3.3VOUT2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 FIGURE 7. POWER DISSIPATION vs LOAD, 2.25MHz, 1.8V, CHANNEL 2 Submit Document Feedback 7 3.3V VIN PFM 1.20 1.19 5VIN PWM 1.18 3.3V VIN PWM 5VIN PFM 0.2 5 VIN PFM 1.21 1.8 2.0 1.17 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.0 FIGURE 8. VOUT REGULATION vs LOAD, 2.25MHz, 1.2V, CHANNEL 1 FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued) 1.54 2.53 5VIN PFM 2.52 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.53 1.52 5VIN PWM 1.51 3.3V VIN PFM 1.50 1.49 5VIN PFM 2.51 2.50 0.2 0.4 3.3V VIN PWM 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.47 0.0 2.0 1.83 3.3V VIN PFM 0.6 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.0 2.53 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.4 2.54 1.82 1.81 5 VIN PFM 1.80 1.79 1.77 0.0 0.2 FIGURE 10. VOUT REGULATION vs LOAD, 2.25MHz, 2.5V CHANNEL 1 FIGURE 9. VOUT REGULATION vs LOAD, 2.25MHz, 1.5V CHANNEL 2 1.78 3.3V VIN PFM 2.48 3.3V VIN PWM 1.48 0.0 5VIN PWM 2.49 3.3V VIN PWM 5VIN PWM 0.2 0.4 0.6 2.52 0A LOAD PFM 2.51 2A LOAD 2.50 2.49 0A LOAD PWM 0.8 1.0 1.2 1.4 OUTPUT LOAD (A) 1.6 1.8 2.0 FIGURE 11. VOUT REGULATION vs LOAD, 2.25MHz, 1.8V, CHANNEL 2 2.48 2.5 2.8 3.1 3.4 1A LOAD 3.7 4.0 4.3 4.6 INPUT VOLTAGE (V) 4.9 5.2 5.5 FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN 2.5V CHANNEL 1 1.83 OUTPUT VOLTAGE (V) 1.82 0A LOAD PFM 1.81 1.80 0A LOAD PWM 1.79 0.8A LOAD 1.78 1.7A LOAD 1.77 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 INPUT VOLTAGE (V) 4.9 5.2 5.5 FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN 1.8V CHANNEL 2 Submit Document Feedback 8 FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued) LX2 2V/DIV LX1 2V/DIV VOUT2 RIPPLE 20mV/DIV VOUT1 RIPPLE 20mV/DIV IL1 0.2A/DIV TB = 200ns/DIV FIGURE 14. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 (PWM) IL2 0.2A/DIV TB = 200ns/DIV FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (PWM) LX1 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL2 0.5A/DIV IL1 0.5A/DIV TB = 500ns/DIV FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 (PFM) LX1 2V/DIV IL1 1A/DIV VOUT2 RIPPLE 20mV/DIV IL2 1A/DIV TB = 200ns/DIV FIGURE 18. STEADY STATE OPERATION AT FULL LOAD CHANNEL 1 9 FIGURE 17. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (PFM) LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV Submit Document Feedback TB = 500ns/DIV TB = 200ns/DIV FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2 FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued) VOUT2 RIPPLE 50mV/DIV VOUT1 RIPPLE 50mV/DIV PG 5V/DIV PG 5V/DIV IL1 1A/DIV IL2 1A/DIV TB = 200µs/DIV TB = 200µs/DIV FIGURE 20. LOAD TRANSIENT CHANNEL 1 (PWM) FIGURE 21. LOAD TRANSIENT CHANNEL 2 (PWM) LX2 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 50mV/DIV VOUT2 RIPPLE 50mV/DIV IL2 1A/DIV IL1 1A/DIV TB = 1ms/DIV TB = 1ms/DIV FIGURE 22. LOAD TRANSIENT CHANNEL 1 (PFM) FIGURE 23. LOAD TRANSIENT CHANNEL 2 (PFM) EN1 2V/DIV EN2 2V/DIV VOUT1 1V/DIV VOUT2 1V/DIV IL1 0.5A/DIV IL2 0.5A/DIV PG 5V/DIV TB = 500µs/DIV FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 1 (PWM) Submit Document Feedback 10 PG 5V/DIV TB = 500µs/DIV FIGURE 25. SOFT-START WITH NO LOAD CHANNEL 2 (PWM) FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued) EN1 2V/DIV EN2 2V/DIV VOUT1 1V/DIV VOUT2 1V/DIV IL1 0.5A/DIV IL2 0.5A/DIV PG 5V/DIV TB = 500µs/DIV FIGURE 26. SOFT-START AT NO LOAD CHANNEL 1 (PFM) PG 5V/DIV FIGURE 27. SOFT-START AT NO LOAD CHANNEL 2 (PFM) EN1 2V/DIV EN2 2V/DIV VOUT1 1V/DIV VOUT2 1V/DIV IL1 1A/DIV IL2 1A/DIV PG 5V/DIV TB = 500µs/DIV FIGURE 28. SOFT-START AT FULL LOAD CHANNEL 1 TB = 500µs/DIV PG 5V/DIV TB = 500µs/DIV FIGURE 29. SOFT-START AT FULL LOAD CHANNEL 2 EN2 2V/DIV EN1 2V/DIV VOUT1 1V/DIV VOUT2 1V/DIV IL1 0.2A/DIV IL2 0.2A/DIV PG 5V/DIV PG 5V/DIV TB = 200µs/DIV FIGURE 30. SOFT-DISCHARGE SHUTDOWN CHANNEL 1 Submit Document Feedback 11 TB = 200µs/DIV FIGURE 31. SOFT-DISCHARGE SHUTDOWN CHANNEL 2 FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued) LX1 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.2A/DIV IL2 0.2A/DIV SYNCH 2V/DIV SYNCH 2V/DIV TB = 100ns/DIV TB = 100ns/DIV FIGURE 32. STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 8MHz CHANNEL 1 FIGURE 33. STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 8MHz CHANNEL 2 LX1 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 1A/DIV IL2 0.5A/DIV SYNCH 2V/DIV SYNCH 2V/DIV TB = 100ns/DIV TB = 100ns/DIV FIGURE 34. STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 8MHz CHANNEL 1 FIGURE 35. STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 8MHz CHANNEL 2 PG 1V/DIV IL1 0.5A/DIV PG 1V/DIV LX1 2V/DIV IL1 0.5A/DIV VOUT1 2V/DIV LX1 2V/DIV VOUT1 2V/DIV TB = 1µs/DIV FIGURE 36. VOUT1 HARD SHORT TO VIN NEGATIVE CURRENT WAVEFORMS AT HIGH LINE CHANNEL 1 Submit Document Feedback 12 TB = 1µs/DIV FIGURE 37. RECOVERY FROM HARD SHORT NEGATIVE CURRENT WAVEFORMS VOUT1 CHANNEL 1 FN7908.2 August 26, 2014 ISL78322 Typical Operating Performance (Unless otherwise noted) operating conditions are: TA = +25°C, VVIN = 2.8V to 5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued) PG 1V/DIV PG 1V/DIV IL2 0.5A/DIV IL2 0.5A/DIV VOUT2 2V/DIV LX2 2V/DIV LX2 2V/DIV VOUT2 2V/DIV TB = 10µs/DIV FIGURE 38. VOUT2 HARD SHORT TO VIN NEGATIVE CURRENT WAVEFORMS AT HIGH LINE CHANNEL 2 TB = 1µs/DIV FIGURE 39. RECOVERY FROM HARD SHORT NEGATIVE CURRENT WAVEFORMS VOUT2 CHANNEL 2 LX1 5V/DIV LX1 5V/DIV VOUT1 2V/DIV VOUT1 2V/DIV IL1 2A/DIV PG 5V/DIV IL1 2A/DIV TB = 5µs/DIV FIGURE 40. OUTPUT SHORT CIRCUIT CHANNEL 1 PG 5V/DIV TB 1CHANNEL /DIV 1 FIGURE 41. OUTPUT SHORT CIRCUIT RECOVERY LX2 5V/DIV LX2 5V/DIV VOUT2 1V/DIV VOUT2 1V/DIV IL2 2A/DIV PG 5V/DIV IL2 2A/DIV TB = 5µs/DIV FIGURE 42. OUTPUT SHORT CIRCUIT CHANNEL 2 Submit Document Feedback 13 PG 5V/DIV TB = 1ms/DIV FIGURE 43. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 2 FN7908.2 August 26, 2014 ISL78322 Theory of Operation The ISL78322 is a dual 2A/1.7A step-down switching regulator optimized for battery-powered or mobile applications. The regulator operates at 2.25MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The two channels are 180° out-of-phase operation. The quiescent current when the outputs are not loaded is typically only 40µA. The supply current is typically only 6.5µA when the regulator is shut down. PWM Control Scheme Pulling the SYNC pin LOW (<0.4V) forces the converter into PWM mode in the next switching cycle regardless of output current. Each of the channels of the ISL78322 employ the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting shown in the “Block Diagram” on page 3. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-channel MOSFET when it is turned on and the current sense amplifier CSA1 (or CSA2 on Channel 2). The gain for the current sensing circuit is typically 0.32V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA1 (or CSA2) and the compensation slope (0.9V/µs) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and to turn on the N-channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 44 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier CSA_ output. The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage control loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately shortly. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 27pF and 250kΩ RC network. The maximum EAMP voltage output is precisely clamped to 1.8V. Submit Document Feedback 14 VEAMP VCSA DUTY CYCLE IL VOUT FIGURE 44. PWM OPERATION WAVEFORMS SKIP Mode Pulling the SYNC pin HIGH (>1.5V) enables the converter into PFM mode at low load. The ISL78322 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 45 illustrates the skip-mode operation. A zero-cross sensing circuit shown in the “Block Diagram” on page 3, monitors the N-MOSFET current for zero crossing. When 16 consecutive cycles of the N-MOSFET crossing zero are detected, the regulator enters the skip mode. During the 16 detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in the “Block Diagram” on page 3. Each pulse cycle is still synchronized by the PWM clock. The P-MOSFET is turned on at the clock and turned off when its current reaches the threshold of 600mA. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above the nominal voltage, the P-MOSFET is turned off immediately. Then the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the clock, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. Synchronization Control The frequency of operation can be synchronized up to 8MHz by an external signal applied to the SYNC pin. The 1st falling edge on the SYNC triggered the rising edge of the PWM ON pulse of Channel 1. The 2nd falling edge of the SYNC triggers the rising edge of the PWM ON pulse of the Channel 2. This process alternates indefinitely allowing 180° output phase operation between the two channels. The internal frequency will take control when the divided external sync is lower than 2.25MHz. The falling edge on the SYNC triggers the rising edge of the PWM ON pulse. FN7908.2 August 26, 2014 ISL78322 PWM PFM CLOCK 16 CYCLES PFM CURRENT LIMIT IL LOAD CURRENT 0 NOMINAL +1.5% VOUT NOMINAL FIGURE 45. SKIP MODE OPERATION WAVEFORMS Positive and Negative Overcurrent Protection UVLO CSA1 and CSA2 are used to monitor output 1 and output 2 channels respectively. The overcurrent protection is realized by monitoring the CSA_ output with the OCP threshold logic, as shown in the “Block Diagram” on page 3. The current sensing circuit has a gain of 0.32V/A, from the P-MOSFET current to the CSA_ output. When the CSA_ output reaches the threshold of 1.25V for Channel 1 and 1.1V for Channel 2, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFETs. When the input voltage is below the undervoltage lock-out (UVLO) threshold, the regulator is disabled. Upon detection of an overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the Overcurrent Fault Counter is set to 1 and the Overcurrent Condition Flag is set from LOW to HIGH. If, on the subsequent cycle, another overcurrent condition is detected, the OC Fault Counter will be incremented. If there are 17 sequential OC fault detections, the regulator will be shut down under an Overcurrent Fault Condition. An Overcurrent Fault Condition will result with the regulator attempting to restart in a hiccup mode with the delay between restarts being 4 soft-start periods. At the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away prior to the OC Fault Counter reaching a count of four, the Overcurrent Condition Flag will set back to LOW. In the event that the inductor current reaches -1.6A, the part enters Negative Overcurrent Protection. At this point, all switching stops and the part enters tri-state mode while the pull-down FET is discharging the output until it reaches normal regulation voltage, then the IC restarts switching. PG The power-good signal (PG), monitors both of the output channels. When powering up, the open-collector Power-On-Reset output holds low for about 1ms after VO1 and VO2 reaches the preset voltages. The PG output also serves as a 1ms delayed power-good signal. If one of the outputs is disabled, then PG only monitors the active channels. There is an internal 1MΩ pull-up resistor. Submit Document Feedback 15 Enable The enable (EN1, EN2) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. The regulator is enabled, there is typically a 600µs delay for waking up the bandgap reference and the soft start-up begins. Soft Start-Up The soft start-up eliminates the in-rush current during start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the feedback voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. In forced PWM mode, the IC will continue to start-up in PFM mode to support prebiased load applications. During soft-start period, the device will operate in tri-state mode, with both high-side and low-side drivers off to prevent negative inductor current flow in output stage. Once soft-start is completed, the drivers will allow negative inductor current only if SYNC is set to low for PWM mode. By this time, the output should reach regulation. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to GND through an internal 100Ω switch. Power MOSFETs The power MOSFETs are optimized for best efficiency. The ON-resistance for the P-MOSFET is typically 100mΩ and the ON-resistance for the N-MOSFET is typical 90mΩ. FN7908.2 August 26, 2014 ISL78322 100% Duty Cycle Input Capacitor Selection The ISL78322 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL78322 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET. The main functions for the input capacitor is to provide decoupling of the parasitic inductance and to provide a filtering function, which prevents the switching current from flowing back to the battery rail. One 10µF X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection per channel. An optional input inductor can be used before the ceramic capacitor to limit switching noise. It is recommended to limit the inductance less than 0.15µH. Thermal Shutdown The ISL78322 has built-in thermal protection. When the internal temperature reaches +150°C, the regulator is completely shut down. As the temperature drops to +130°C, the ISL78322 resumes operation by stepping through a soft start-up. Applications Information Output Inductor and Capacitor Selection To consider steady state and transient operation, ISL78322 typically uses a 1.2µH output inductor. Higher or lower inductor values can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V applications, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. The inductor ripple current can be expressed as in Equation 1: VO V O 1 – --------- V IN I = --------------------------------------L fS (EQ. 1) PCB Layout Recommendation The PCB layout is a very important converter design step to make sure the designed converter works well. For ISL78322, the power loop is composed of the output inductor L’s, the output capacitor COUT1 and COUT2, the LX pins, and the GND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the LX_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin and the ground of input and output capacitors should be connected as close as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. The inductor’s saturation current rating needs to be at least larger than the peak current. The ISL78322 protects the typical peak current 3.2A/2.8A. The saturation current needs to be over 3.6A for maximum output current application. ISL78322 uses internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended minimum output capacitor values for the ISL78322 are shown in Table 1 on page 2. Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to “Typical Applications” on page 2. The output voltage programming resistor, R2 (or R5 in Channel 2), will depend on the desired output voltage of the regulator. The value for the feedback resistor is typically between 0Ω and 750kΩ. Let R3 = 100kΩ, then R2 will be as shown in Equation 2: V OUT R 2 = R 3 ---------------- – 1 V FB (EQ. 2) If the output voltage desired is 0.6V, then R3 is left unpopulated and short R2. For better performance, add 10pF in parallel to R2 Submit Document Feedback 16 FN7908.2 August 26, 2014 ISL78322 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE August 26, 2014 FN7908.2 Updated the “ESD Rating” on page 5, added the test method used for HBM and MM, changed CDM test method from “JESD22-C101E” to “AEC-Q100-11”. Updated “About Intersil” on page 17 to new verbiage. January 14, 2014 FN7908.1 Page 17 - 2nd line of the disclaimer changed from: "Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted" to: "Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted" - Updated "Products" verbiage to "About Intersil" verbiage February 24, 2012 FN7908.0 Initial release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 17 FN7908.2 August 26, 2014 ISL78322 Package Outline Drawing L12.4x3 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 7/10 3.30 +0.10/-0.15 4.00 2X 2.50 A 6 PIN 1 INDEX AREA 10X 0.50 PIN #1 INDEX AREA B 6 1 12 X 0.40 ±0.10 6 1.70 +0.10/-0.15 3.00 (4X) 0.15 12 7 TOP VIEW 0.10M C A B 4 12 x 0.23 +0.07/-0.05 BOTTOM VIEW SEE DETAIL "X" ( 3.30) 6 0.10 C 1 C 1.00 MAX SEATING PLANE 0.08 C SIDE VIEW 2.80 ( 1.70 ) C 0.2 REF 5 12 X 0.60 7 12 0 . 00 MIN. 0 . 05 MAX. ( 12X 0.23 ) ( 10X 0 . 5 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. Submit Document Feedback 18 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 V4030D-4 issue E. FN7908.2 August 26, 2014