DATASHEET

Low Input Voltage and High Efficiency Synchronous
Boost Converter with 1.3A Switch
ISL78113A
Features
The ISL78113A provides a tiny and convenient boost power
supply solution to generate a regulated output up to 500mA
from any sub-5V secondary rail found in an automotive
electrical system, including battery powered applications
(NiCd, NiMH, or one-cell Li-Ion/Li-Polymer). It offers an
adjustable output (3.0V to 5.2V) supporting USB-OTG or HDMI
applications. The device is able to supply 500mA from a 3V
input and 5V output, and has a typical 1.3A peak current limit.
• Output disconnect during shutdown preventing output
precharging and uncontrolled short-circuit current
The ISL78113A is a fully integrated, internally compensated,
synchronous converter optimized to maximize efficiency and
reduce the overall solution size and bill of materials. Its high
2MHz switching frequency allows the use of tiny, low-profile
inductors and chip capacitors. It also eliminates potential
interference within the AM radio band and the external EMI
filtering needed for converters switching at lower rates. To
minimize power consumption while off, the device features an
ultra-low current shutdown mode dropping quiescent current
to 50nA typical.
• Input voltage range: 0.8V to 4.7V
• Output current: Up to 500mA (VBAT = 3V, VOUT = 5V)
• Logic control shutdown (IQ < 1µA)
• 2MHz switching frequency
• Up to 95% efficiency at typical operating conditions
• Fault protection: OVP, OCP, OTP, UVLO
• 2mmx2mm 8 Ld DFN package
• Qualified for automotive operations
Applications
• Automotive head units and infotainment systems: especially
those including portable HDMI and USB-OTG connectivity
• Automotive camera systems
ISL78113A is supplied in an 8 Ld DFN package. The device is
rated to operate over the temperature range of -40°C to
+105°C.
100
6.8 µH
VBAT = 3.6V
90
80
VBAT =
0.8V TO 4.7V
2
SW
VOUT =
5.0V/500mA
VOUT
7
VBAT
10µF
10µF
422
5
4
EN
80.6
1
ISL78113AARAZ
FIGURE 1. TYPICAL APPLICATION
May 1, 2014
FN8638.0
1
VBAT = 4.2V
VBAT = 3.4V
VBAT = 3V
60
50
VBAT = 2.3V
40
30
FB
GND
70
EFFICIENCY (%)
8
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
LOAD CURRENT ILOAD (A)
FIGURE 2. EFFICIENCY vs LOAD CURRENT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78113A
Block Diagram
C1
VOUT
VBAT
C2
7
UVLO
VINT
2
VOLTAGE
SELECTOR
START-UP
N-WELL
SWITCH
GATE
DRIVER
VOUT
SW
L1
8
OVP
AND
ANTI-CROSS
CONDUCTION
SW
ZCD
EN
VOUT
5
OFF ON
CURRENT
SENSE
CONTROL LOGIC
R1
AND
DIGITAL
SOFT-START
CURRENT
LIMIT
SLOPE COMP
FB
4
FAULT
MONITORING
gm
VOLTAGE
CLAMP
2MHz
OSCILLATOR
2
VINT
REFERENCE
GENERATOR
THERMAL
SHUTDOWN
1
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FN8638.0
May 1, 2014
ISL78113A
Pin Configuration
ISL78113A
ADJUSTABLE OUTPUT
(8 LD DFN)
TOP VIEW
PGND
1
8
SW
VOUT
2
7
VBAT
NC
3
6
AGND
FB
4
5
EN
Pin Descriptions
PIN
NUMBERS SYMBOL
PIN DESCRIPTION
1
PGND
Power ground.
2
VOUT
Device output.
3
NC
No connection.
4
FB
Feedback pin of the converter. Connect voltage divider resistors between VOUT, FB and GND for desired output.
5
EN
The EN pin is an active-HIGH logic input for enabling the device. When asserted HIGH, the boost function begins. When driven
LOW, the device is completely disabled, and current is blocked from flowing from the SW pin to the output and vice versa. This
pin may be tied either HIGH to enable the device or LOW to disable.
6
AGND
7
VBAT
Device input supply from a battery. Connect a 10µF ceramic capacitor from VBAT to power ground.
8
SW
The SW pin is the switching node of the power converter. Connect one terminal of the inductor to the SW pin and the other to
power input.
EPAD
The exposed pad must be connected to PGND pin for proper electrical performance. Place as many vias as possible under the
pad connecting to the system GND plane for optimal thermal performance.
Analog ground.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
ISL78113AARAZ-T
AAR
VOUT (V)
TEMP RANGE
(°C)
Adjustable
-40 to +105
PACKAGE
(Pb-free)
8 Ld DFN
PKG.
DWG. #
L8.2x2D
NOTES:
1. Use “-T7A” suffix for 250 pieces tape and reel. Please refer to Tech Brief TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78113A. For more information on MSL please see Tech Brief TB363.
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FN8638.0
May 1, 2014
ISL78113A
Absolute Maximum Ratings
Thermal Information
VBAT, EN, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
SW Voltage
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V
Pulse <10ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 8.0V
ESD Ratings
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per AEC-Q100-003) . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . .2.2kV
Latch Up (Tested per AEC-Q100-004; Class II, Level A) . . . . . . . . . . . 15mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld DFN Package (Notes 4, 5). . . . . . . . . .
80
15
Maximum Junction Temperature (plastic package). . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TB493
Recommended Operating Conditions
VBAT (after start-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 4.7V
VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VBAT + 0.2V) to 5.2V
Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
-40°C to +105°C.
PARAMETER
VBAT = 3.0V, VOUT = 5V, L = 4.7µH, TA = +25°C. Boldface limits apply over the operating temperature range,
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
V
Start-up Voltage
VMIN
VEN = 1.2V, RLOAD = 50Ω
0.6
0.75
0.9
Input Undervoltage Lockout
VUVLO
VEN = VBAT, RLOAD = 50Ω
0.66
0.70
0.76
V
784
800
816
mV
Feedback Voltage
VFB
VBAT = 2V
Output Voltage
Feedback Pin Input Current
3.0
5.2
V
-100
100
nA
Quiescent Current from VOUT
IQ1
VBAT = VEN = 1.2V, no load (Note 7)
5.5
10
mA
Shutdown Current from VBAT
ISD
VEN = 0V, VBAT = 1.2V, VO = 0
0.05
2.8
μA
15
μA
VEN = 0V, VBAT = 4.7V, VO = 0
Leakage Current at SW Pin
N-Channel MOSFET ON-resistance
0.20
P-Channel MOSFET ON-resistance
Ω
0.35
N-Channel MOSFET Peak Current Limit
IPK
1
1.3
Maximum Duty Cycle
DMAX
82
87.5
PWM Switching Frequency
FOSC
1.73
2
2.5V < VBAT < 4.7V
EN Logic High
VBAT < 2.5V
V
0.35
V
0.14*VBAT
V
0.2
1
ms
ILOAD = 1 to 50mA
-0.5
±0.01
0.5
%
VBAT = 3.0V to 3.6V, ILOAD = 1mA
-0.5
±0.03
0.5
%
42
49
ns
5.9
V
TSD
150
oC
25
oC
Output Overvoltage Protection Threshold
Thermal Shutdown
%
tMIN(ON)
Line Regulation
Minimum SW Low in PWM Mode
MHz
V
COUT = 4.7μF, L = 4.7μH
ΔVOUT/VOUT
Load Regulation
2.23
1.2
VBAT < 2.5V
Soft Start-up Time
A
0.48*VBAT
2.5V < VBAT < 4.7V
EN Logic Low
Ω
1.6
Thermal Shutdown Hysteresis
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. IQ1 is measured at VOUT and multiplied by VOUT/VBAT; thus, the equivalent input quiescent current is calculated.
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ISL78113A
Detailed Description
Current Mode PWM Operation
The control scheme of the device is based on the peak current
mode control and the control loop is compensated internally. The
peak current of the N-channel MOSFET switch is sensed to limit
the maximum current flowing through the switch and the
inductor. The typical current limit is set to 1.3A.
The control circuit includes a current ramp generator, slope
compensator, error amplifier and a PWM comparator (see the
“Block Diagram” on page 2). The ramp signal is derived from the
inductor current. This ramp signal is then compared to the error
amplifier output to generate the PWM gating signals for driving
both N-channel and P-channel MOSFETs. The PWM operation is
initialized by the clock from the internal oscillator (typical 2MHz).
The N-channel MOSFET is turned ON at the beginning of a PWM
cycle, the P-channel MOSFET remains OFF, and the current starts
ramping up. When the sum of the ramp and the slope
compensator output reaches the error amplifier output voltage,
the PWM comparator outputs a signal to turn OFF the N-channel
MOSFET. Here, both MOSFETs remain OFF during the dead-time
interval. Next, the P-channel MOSFET is turned ON and remains
ON until the end of this PWM cycle. During this time, the inductor
current ramps down until the next clock. At this point, following a
short dead time, the N-channel MOSFET is again turned ON,
repeating as previously described.
Synchronous Rectifier
The ISL78113A integrates one N-channel MOSFET and one
P-channel MOSFET to realize a synchronous boost converter.
Because the commonly used discrete Schottky rectifier is
replaced with the low rDS(ON) P-channel MOSFET, the power
conversion efficiency reaches a value above 90%.
VOUT Isolation
Since a typical step-up converter has a conduction path from the
input to the output via the body diode of the P-channel MOSFET,
a special circuit (see the “Block Diagram” on page 2) is used to
reverse the polarity of the P-channel body diode when the device
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5
is shut down. Thus, this configuration completely disconnects the
load from the input during shutdown of the converter. The benefit
of this feature is that the battery will not be completely depleted
during shutdown of the converter. No additional components are
needed to disconnect the battery from the output of the
converter.
Soft-Start
The soft start-up duration is the time between the device being
enabled and VOUT rising to within 3% of the target voltage. When
the device is enabled, the start-up cycle starts with a linear
operating phase. During the linear phase, the rectifying switch is
turned ON in a current limited configuration, delivering about
350mA, until the output capacitor is charged to approximately
90% of the input voltage. At this point, PWM operation begins in
boost mode. If the output voltage is below 2.3V, PWM switching
is done at a fixed duty-cycle of 75% until the output voltage
reaches 2.3V. When the output voltage exceeds 2.3V, the
closed-loop current mode PWM loop overrides the duty cycle until
the output voltage is regulated. Peak inductor current is ramped
to the current limit value (typically 1.3A) during the soft-start
period to limit in-rush current from the input source. Fault
monitoring begins approximately 2ms after the device is
enabled.
To start up with a slow VBAT ramp-up rate is likely to cause the
device to enter hiccup mode. This is a result of the input voltage
dropping due to start-up current, which causes a fault of VOUT out
of regulation, especially at high load and cold temperature.
Check the input ramp-up rate and a faster input slew rate would
help to resolve this.
Over-temperature Protection (OTP)
The device offers over-temperature protection. A temperature
sensor circuit is integrated and monitors the internal IC
temperature. Once the temperature exceeds the preset threshold
(typically +150°C), the IC shuts down immediately. The OTP has
a typical hysteresis of +25°C. When the device temperature
decreases by this, the device starts operating.
FN8638.0
May 1, 2014
ISL78113A
TABLE 1. FAULT DETECTION AND RESPONSE
FAULT CONDITION
DETECTION DETAILS
ACTION
Low Battery Voltage
VBAT < 0.7V
Shutdown until VEN or VBAT is cycled.
VOUT Out of Regulation
VOUT is 10% below the target
output voltage.
Shutdown only if VBAT and VOUT fall below 2.1V. Device automatically restarts after
200ms.
Short Circuit
VOUT falls below VBAT.
Shutdown immediately. Device automatically restarts after 200ms.
Over-temperature Protection Die temperature is > +150°C.
Switching stops. Device automatically restarts when temperature decreases to
+125°C.
Output Overvoltage
Protection
Switching stops until EN pin is toggled or power is cycled.
VOUT > 5.9V
Fault Monitoring
Fault monitoring starts 2ms after start-up. Table 1 shows the
response to different detected faults.
Printed Circuit Board Layout
Recommendations
The ISL78113A is a high frequency switching boost converter.
Accordingly, the converter has fast voltage change and high
switching current that may cause EMI and stability issues if the
layout is not done properly. Therefore, careful layout is critical to
minimize the trace inductance and reduce the area of the power
loop.
Power components such as input capacitor, inductor, and the
output capacitors should be placed as close to the device as
possible. Board traces that carry high switching current should be
routed wide and short. A solid power ground plane is important
for EMI suppression.
The switching node (SW pin) of the converter and the traces
connected to this pin are very noisy. Noise sensitive traces such
as the FB trace should be kept away from the SW node. The
voltage divider should be placed close to the FB pin to prevent
noise pickup. Figure 3 shows the recommended PCB layout.
Output Voltage Setting Resistor Selection
In the 8 Ld DFN package, the heat generated in the device is
mainly dissipated through the thermal pad. Maximizing the
copper area connected to the thermal pad is preferable. It is
recommended to add at least 4 vias within the pad to the GND
plane for the best thermal dissipation.
R 1

V OUT = V FB   1 + -------
R 2

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FIGURE 3. RECOMMENDED PCB LAYOUT
For ISL78113A, resistors R1 and R2, shown in the “Block
Diagram” on page 2, set the desired output voltage values. The
output voltage can be calculated using Equation 1:
(EQ. 1)
where VFB is the internal FB reference voltage (0.8V typical). The
current flowing through the divider resistors is calculated as
VOUT /(R1 + R2). The resistance is chosen based on the minimum
expected load for VOUT and the minimum PWM on time (PWM
Low; 42ns typical). This will provide a small constant current that
limits the VOUT and voltage in light load conditions. R1 and R2
should be placed close to the FB pin of the device to prevent
noise pickup.
FN8638.0
May 1, 2014
ISL78113A
Inductor Selection
An inductor with core material suitable for high frequency
applications (e.g., ferrite) is desirable to minimize core loss and
improve efficiency. The inductor should have a low DCR to
reduce copper loss. Moreover, the inductor saturation current
should be higher than the maximum peak current of the device;
i.e., 1.6A.
The device is designed to operate with an inductor value of 2.2µH
to 6.8µH to provide stable operation across the range of load,
input and output voltages. Table 2 shows recommended
inductors.
TABLE 2. INDUCTOR VENDOR INFORMATION
MANUFACTURER
SERIES
WEBSITE
Würth Elektronik
WE-TPC, Type S
www.we-online.com
This issue can be resolved by adding a small load (several mA) to
keep the output in regulation. The procedure to calculate the
minimum load required due to these forced PWM pulses is
elaborated in the following.
Figure 4 shows the inductor waveform in the forced PWM
operation at no load. tMIN(ON)_LFET is the time the low-side
MOSFET is forced ON.
During tMIN(ON) time, inductor current is charged with slew rate of
VIN/L. The peak inductor current at the end of tMIN(ON) can be
calculated in Equation 2.
V IN  t MIN  ON 
IL peak = ---------------------------------------L
Capacitor Selection
INPUT CAPACITOR
A minimum of a 10µF ceramic capacitor is recommended to
provide stable operation under typical operating conditions. For
input voltage less than 1.0V application, an additional 2.2µF
ceramic capacitor is recommended for better noise filtering and
EMI suppression. The input capacitor should be placed close to
the input pin, GND pin, and the non-switching terminal of the
inductor.
OUTPUT CAPACITOR
For the output capacitor, a ceramic capacitor with small ESR is
recommended to minimize output voltage ripple. A typical 10µF
should be used to provide stable operation at different typical
operating conditions. The output capacitor should be placed
close to the output pin and GND pin of the device. Table 3 shows
the recommended capacitors.
TABLE 3. CAPACITOR VENDOR INFORMATION
MANUFACTURER
SERIES
WEBSITE
AVX
X7R
www.avx.com
Murata
X7R
www.murata.com
Taiyo Yuden
X7R
www.t-yuden.com
TDK
X7R
www.tdk.com
Forced PWM Operation
The part has forced PWM operation. During a no-load condition
the low-side FET is forced ON for a short pulse with minimum
ON-time (42ns typical) in every cycle and does not allow for pulse
skipping. The part is also implemented with diode emulation
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mode to turn off the upper side MOSFET when inductor current
drops to 0 and prevents any negative inductor current. Therefore
in no load to light load (less than several mA) conditions, the
output voltage is pushed higher than regulation point, which may
be out of the user’s output voltage specifications.
7
(EQ. 2)
After tMIN(ON) time, low-side MOSFET is turned off, inductor
current is free-wheeling through the high-side MOSFET from VIN
to VOUT until the inductor current ramps down to 0 and the
high-side MOSFET is turned off. The duration of this free-wheeling
period (tFW) can be calculated in Equation 3.
IL peak  L
t FW = -------------------------------V OUT – V IN
(EQ. 3)
During this free-wheeling period, the charge to the output is
shown as Q in Figure 4 on page 8, which can be calculated as
shown by Equation 4.
(EQ. 4)
Q = 0.5  IL peak  t FW
The ISL78113A outputs charge of Q to the output every switching
cycle, therefore the average current to due to the tMIN(ON) pulses
can be calculated as shown by Equation 5.
(EQ. 5)
I OUT  AVG  = Q  F SW
where FSW is the switching frequency.
Summarizing from Equations 2 through 5, the average current
charged to the output due to the tMIN(ON) pulses can be
calculated by Equation 6.
2
0.5  F SW   V IN  t MIN  ON  
I OUT  AVG  = --------------------------------------------------------------------------------L   V OUT – V IN 
(EQ. 6)
FN8638.0
May 1, 2014
ISL78113A
ILPEAK = VIN/L* tMIN(ON)
SR = (VOUT - VIN)
SR = VIN /L
Q = 0.5 * ILPEAK * tFW
Q
IL
IOUT(AVG) = Q*FSW
IOUT(AVG) = 0.5 * (VIN/L*
tMIN(ON)
tMIN(ON))2*L/(VOUT
Q
- VIN) * FSW
tFW
tFW = ILPEAK * L/(VOUT - VIN)
1/FSW
FIGURE 4. AVERAGE OUTPUT CURRENT DUE TO FORCED PWM PULSES AT NO LOAD CONDITION
Minimum Load Required in Forced PWM
Mode
An example of the typical conditions are listed as follows:
In a no load condition, in order to maintain the output voltage in
regulation, a small load has to be added in the output to absorb
the output current due to forced PWM pulses. Equation 6 can be
used to calculate the minimum required load in worst cases.
• VOUT TYP = 5V
The worst cases refer to FSW, VIN, tMIN(ON), L, VOUT in Equation 6.
• Use the maximum VIN for the worst case.
• Specify the allowed maximum Vout voltage VIN(MAX) and use it
in the worst case calculation, basically the target is to have the
minimum load keeping the VOUT below the maximum
acceptable voltage.
• Use the maximum switching frequency of 2.23MHz specified
in the “Electrical Specifications” table on page 4. Maximum
frequency is the worst case since it delivered most pulses with
fixed charges to the output.
• Use the minimum inductor value considering inductance
variations (normally -20% of nominal value). For the inductor
selection, note the higher the inductance, the less the required
minimum load.
• VIN TYP = 3V
• FSW TYP = 2MHz
• LNOMINAL = 6.8µH
To calculate the minimum required load, the worst conditions we
can use are,
• VIN(MAX) = 3.6V (specified in customer system)
• VOUT(MAX) = 5.25V (specified in customer system)
• FSW = 2.23MHz
• LMIN = (-20%) LNOMINAL = 5.44µH
Using the above worst case parameters in Equation 6, the
calculated output current (IOUT(AVG)) is 3.87mA, which is the
minimum required load to be added in the output to absorb the
output current due to forced PWM pulses. Extra margin can be
added depending on the system worst case condition.
• Use the maximum tMIN(ON) time of 49ns specified in the
“Electrical Specifications” table on page 4. Maximum tMIN(ON)
time is the worst case since it cause higher inductor peak
current and higher charge to the output.
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FN8638.0
May 1, 2014
ISL78113A
Typical Characteristics
VIN = 3.4V, VOUT = 5V, L = 6.8µH, COUT = 10µF, R1 = 422Ω, R2 = 80.6Ω; unless otherwise noted.
Typical values are at TA = +25°C.
1.2
1.0
0.8
VOUT = 5.0V
1.0
0.4
0.8
VOUT = 4.0V
VOUT (%)
IOUT (A)
0.6
0.6
0.4
0.2
ILOAD = 1mA
0
-0.2
-0.4
ILOAD = 150mA
-0.6
0.2
-0.8
0
0.8
1.3
1.8
2.3
2.8
3.3
VBAT (V)
3.8
4.3
4.8
-1.0
0
1
2
3
4
5
VBAT (V)
FIGURE 5. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
FIGURE 6. LINE REGULATION, VOUT = 5V
ILOAD = 20mA
ILOAD = 50mA
VOUT WITH 5.0V OFFSET (10mV/DIV)
VOUT WITH 5.0V OFFSET (10mV/DIV)
SW (5V/DIV)
SW (5V/DIV)
INDUCTOR CURRENT (100mA/DIV)
INDUCTOR CURRENT (100mA/DIV)
1µs/DIV
1µs/DIV
FIGURE 7. OUTPUT RIPPLE VOLTAGE (ILOAD = 20mA)
FIGURE 8. OUTPUT RIPPLE VOLTAGE (ILOAD = 50mA)
ILOAD = 150mA
VOUT WITH 5.0V OFFSET (20mV/DIV)
ILOAD = 250mA
VOUT WITH 5.0V OFFSET (50mV/DIV)
SW (5V/DIV)
SW (5V/DIV)
INDUCTOR CURRENT (200mA/DIV)
INDUCTOR CURRENT (200mA/DIV)
1µs/DIV
FIGURE 9. OUTPUT RIPPLE VOLTAGE (ILOAD = 150mA)
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1µs/DIV
FIGURE 10. OUTPUT RIPPLE VOLTAGE (ILOAD = 250mA)
FN8638.0
May 1, 2014
ISL78113A
Typical Characteristics
VIN = 3.4V, VOUT = 5V, L = 6.8µH, COUT = 10µF, R1 = 422Ω, R2 = 80.6Ω; unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
EN (2V/DIV)
EN (2V/DIV)
VOUT (2V/DIV)
VOUT (2V/DIV)
INDUCTOR CURRENT (500mA/DIV)
INDUCTOR CURRENT (1A/DIV)
SW (5V/DIV)
SW (5V/DIV)
200µs/DIV
100µs/DIV
FIGURE 11. START-UP AFTER ENABLE (ILOAD = 250mA)
FIGURE 12. START-UP AFTER ENABLE (ILOAD = 50mA)
VOUT With 5V OFFSET
VOUT With 5V OFFSET
VOUT (50mV/DIV)
VOUT (100mV/DIV)
ILOAD (100mA/DIV)
ILOAD (200mA/DIV)
SW (5V/DIV)
1ms/DIV
1ms/DIV
FIGURE 13. LOAD TRANSIENT RESPONSE (20mA TO 150mA)
FIGURE 14. LOAD TRANSIENT RESPONSE (20mA TO 250mA)
0.5
VOUT WITH 5.0V OFFSET
0
VBAT = 4.2V
-0.5
VOUT (%)
VOUT (200mV/DIV)
VBAT = 3V
-1.0
VBAT = 3.6V
-1.5
-2.0
VBAT = 3.4V
-2.5
-3.0
ILOAD (200mA/DIV)
0
0.2
0.4
ILOAD (A)
0.6
0.8
1ms/DIV
FIGURE 15. LOAD TRANSIENT RESPONSE (100mA TO 500mA)
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FIGURE 16. LOAD REGULATION
FN8638.0
May 1, 2014
ISL78113A
Typical Characteristics
VIN = 3.4V, VOUT = 5V, L = 6.8µH, COUT = 10µF, R1 = 422Ω, R2 = 80.6Ω; unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
100
VBAT = 3.6V
90
80
VBAT = 4.2V
EFFICIENCY (%)
70
60
VBAT = 3.4V
VBAT = 2.3V
VBAT = 3V
50
40
30
20
R1 = 121k
10
0
0
R2 = 22.1k
0.1
0.2
0.3
0.4
LOAD CURRENT ILOAD (A)
0.5
0.6
FIGURE 17. EFFICIENCY vs LOAD CURRENT
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
May 1, 2014
FN8638.0
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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FN8638.0
May 1, 2014
ISL78113A
Package Outline Drawing
L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 0, 3/11
2.00
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
A
B
8
1
2.00
6x 0.50
(4X)
1.55±0.10
0.15
0.10M C A B 0.22
4
TOP VIEW
( 8x0.30 )
0.90±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.90±0.10
BASE PLANE
0 . 00 MIN.
0 . 05 MAX.
SEATING PLANE
0.08 C
SIDE VIEW
0 . 2 REF
C
DETAIL "X"
( 8x0.20 )
PACKAGE
OUTLINE
( 8x0.30 )
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
( 6x0.50 )
1.55
2.00
between 0.15mm and 0.30mm from the terminal tip.
( 8x0.22 )
0.90
2.00
TYPICAL RECOMMENDED LAND PATTERN
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5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8638.0
May 1, 2014
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