DATASHEET

DATASHEET
High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
Features
The ISL80102 and ISL80103 are low voltage, high-current, single
output LDOs specified for 2A and 3A output current, respectively.
These LDOs operate from the input voltages of 2.2V to 6V and
are capable of providing the output voltages of 0.8V to 5.5V on
the adjustable VOUT versions. Fixed output voltage options are
available in 1.8V, 2.5V. Other custom voltage options available
upon request.
• Stable with ceramic capacitors (Note 11)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
• ±1.8% VOUT accuracy guaranteed over line, load and
TJ = -40°C to +125°C
• Very low 120mV dropout voltage at 3A (ISL80103)
For applications that demand in-rush current less than the
current limit, an external capacitor on the soft-start pin provides
adjustment. The ENABLE feature allows the part to be placed into
a low quiescent current shutdown mode. A submicron BiCMOS
process is utilized for this product family to deliver the
best-in-class analog performance and overall value.
• Fixed and adjustable VOUT versions
• Very fast transient response
• Excellent 62dB PSRR
• 49µVRMS output noise
• Power-good output
These CMOS (LDOs) will consume significantly lower quiescent
current as a function of load over bipolar LDOs, which translates
into higher efficiency and the ability to consider packages with
smaller footprints. The quiescent current has been modestly
compromised to enable a leading class fast load transient
response, and hence a lower total AC regulation band for an LDO
in this category.
• Adjustable in-rush current limiting
• Short-circuit and over-temperature protection
• Available in a 10 Ld DFN
Applications
• Servers
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• Routers and switchers
ISL80102, ISL80103
2.5V ±10%
9
VIN
10
CIN
10µF
1.8V ±1.8%
1
VIN
VOUT
VIN
VOUT
2
VOUT
COUT
10µF
RPG
ON
7
OFF
6
*CSS
SENSE
ENABLE
3
4
SS
PG
100kΩ
PGOOD
GND
5
*CSS is optional, (see Note 12 on page 5).
FIGURE 1. TYPICAL APPLICATION FOR FIXED OUTPUT VOLTAGE VERSION
April 8, 2016
FN6660.7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009-2013, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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ISL80102, ISL80103
ISL80102, ISL80103
2.5V ±10%
VIN
9
CIN
10
10µF
1.8V
VIN
VOUT
VIN
VOUT
1
2
VOUT
COUT
10µF
RPG
100kΩ
R1
10kΩ
7
EN
OPEN DRAIN COMPATIBLE
6
PG
4
PGOOD
ENABLE
**CPB
SS
*CSS
ADJ
GND
3
R3
2.61kΩ
47pF
R4
5
1.0kΩ
*CSS is optional, (see Note 12 on page 5).
**CPB is optional. See “Functional Description” on page 12 for more information.
FIGURE 2. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION
Pin Descriptions
TABLE 1. COMPONENTS VALUE SELECTION
VOUT
(V)
RTOP
(kΩ)
RBOTTOM
(Ω)
CPB
(pF)
COUT
(µF)
PIN
NUMBER
PIN
NAME
5.0
2.61
287
47
10
1, 2
VOUT
3.3
2.61
464
47
10
3
2.5
2.61
649
47
10
1.8*
2.61
1.0k
47
10
1.8*
2.61
1.0k
82
22
1.5
2.61
1.3k
82
1.2
2.61
1.87k
1.0
2.61
0.8
2.61
PG
22
5
GND
150
47
6
SS
2.61k
150
47
4.32k
150
47
NOTE: *Either option could be used depending on cost/performance
requirements
Pin Configuration
ISL80102, ISL80103
(10 LD 3x3 DFN)
TOP VIEW
VOUT
1
VOUT in regulation signal. Logic low defines when
VOUT is not in regulation. Must be grounded if not
used.
GND pin
External cap adjusts in-rush current. Leave this pin
open if not used.
ENABLE VIN independent chip enable. TTL and CMOS
compatible.
8
DNC
Do not connect this pin to ground or supply. Leave
floating.
9, 10
VIN
Input supply pin
EPAD
EPAD must be connected to copper plane with as
many vias as possible for proper electrical and
optimal thermal performance.
10 VIN
VOUT
2
SENSE/ADJ
3
PG
4
7 ENABLE
GND
5
6 SS
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Output voltage pin
SENSE/ Remote voltage sense for internally fixed VOUT
ADJ
options. ADJ pin for externally set VOUT.
4
7
DESCRIPTION
9 VIN
EPAD
2
8 DNC
FN6660.7
April 8, 2016
ISL80102, ISL80103
Block Diagram
VIN
R5
10µA
10µA
IL/10,000
M4
M5
M3
M1
POWER PMOS
IL
VOUT
+
R8
R7
M6
-
R9
EN
+
EN
EN
ENABLE
R1
500mV
ADJ
+
-
M7
V TO I
SS
M8
R2
R4
EN
SENSE
500mV
EN
PG
-
+
-
M2
+
485mV
+
-
*R3
GND
*R3 is open for ADJ versions.
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
VOUT
MARKING VOLTAGE
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG
DWG. #
ISL80102IRAJZ (Note 1)
DZJA
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR18Z (Note 2)
(No longer available, recommended replacement: ISL80102IRAJZ)
DZNA
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR25Z (Note 2)
(No longer available, recommended replacement: ISL80102IRAJZ)
DZPA
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ (Note 1)
DZAA
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR18Z (Note 2)
(No longer available, recommended replacement: ISL80103IRAJZ)
DZEA
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR25Z (Note 2)
(No longer available, recommended replacement: ISL80103IRAJZ)
DZFA
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102EVAL2Z
Evaluation Board
ISL80103EVAL2Z
Evaluation Board
NOTES:
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. Add “-T” suffix for 6k unit or “-TK” suffix for 1k unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on MSL please see tech brief
TB363.
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FN6660.7
April 8, 2016
ISL80102, ISL80103
Absolute Maximum Ratings (Note 7)
Thermal Information
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS, Relative to GND. . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.2kV
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
10 Ld 3x3 DFN Package (Notes 5, 6). . . . .
45
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Note 8)
Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5.5V
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
8. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379. Boldface limits apply across the operating temperature range,
-40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
DC CHARACTERISTICS
DC Output Voltage Accuracy
VOUT
VOUT options: 1.8V.
2.2V < VIN < 6V; ILOAD = 0A
VOUT options: 1.8V.
2.2V < VIN < 6V; 0A < ILOAD < 3A
0.5
-1.8
VOUT options: 2.5V
6V < VIN < 6V; ILOAD = 0A
Feedback Pin (ADJ Version)
DC Output Load Regulation
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VOUT options: 2.5V
6V < VIN < 6V; 0A < ILOAD < full load
-1.8
%
-1.8
%
0A < ILOAD < full load
491
500
509
mV
-0.4
0.1
0.4
%
2.9V < VIN < 6V, VOUT = 2.5V
-0.8
0.1
0.8
%
(VOUT No Load - VOUT
High Load)/
VOUT No Load
ISL80103. 0A < ILOAD < 3A,
2.9V < VIN < 6V; VOUT = 2.5V for adjustable version.
VOUT = 1.8V and 2.5V for fixed version.
-0.8
-0.2
0.8
%
ISL80102. 0A < ILOAD < 2A
2.9V < VIN < 6V; VOUT = 2.5V for adjustable version.
VOUT = 1.8V and 2.5V for fixed version.
-0.6
-0.2
0.6
%
VADJ = 0.5V
IQ
4
0.5
%
2.2V < VIN < 3.6V, VOUT = 1.8V
Feedback Input Current
Ground Pin Current
1.8
(VOUT Low Line - VOUT
High Line)/
VOUT Low Line
VADJ
DC Input Line Regulation
%
0.01
1
µA
ILOAD = 0A, VOUT + 0.4V < VIN < 6V for all options.
VOUT = 2.5V for adjustable option.
7.5
9
mA
ILOAD = 3A, VOUT + 0.4V < VIN < 6V for all options.
VOUT = 2.5V for adjustable option.
8.5
12
mA
FN6660.7
April 8, 2016
ISL80102, ISL80103
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379. Boldface limits apply across the operating temperature range,
-40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits. (Continued)
PARAMETER
SYMBOL
Ground Pin Current in Shutdown
ISHDN
VDO
Dropout Voltage (Note 10)
Output Short Circuit Current
(3A Version)
ISC
Output Short Circuit Current
(2A Version)
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
EN = 0V, VIN = 5V
0.4
µA
EN = 0V, VIN = 6V
3.3
16
µA
ISL80103, ILOAD = 3A, VOUT = 2.5V
120
185
mV
ISL80102, ILOAD = 2A, VOUT = 2.5V
81
125
mV
ISL80103, ILOAD = 3A, VOUT = 5.5V
120
244
mV
ISL80102, ILOAD = 2A, VOUT = 5.5V
60
121
mV
ISL80103, VOUT = 0V
5.0
A
ISL80102, VOUT = 0V
2.8
A
Thermal Shutdown Temperature
TSD
160
°C
Thermal Shutdown Hysteresis
TSDn
15
°C
f = 1kHz, ILOAD = 1A; VIN = 2.2V
55
dB
f = 120Hz, ILOAD = 1A; VIN = 2.2V
62
dB
VIN = 2.2V, VOUT = 1.8V, ILOAD = 3A,
BW = 100Hz < f < 100kHz
49
µVRMS
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
Output Noise Voltage
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
VEN(HIGH)
2.9V < VIN < 6V for 2.5V for fixed output option.
2.2V < VIN < 6V for adjustable and 1.8V
0.616
0.8
Turn-off Threshold
VEN(LOW)
2.9V < VIN < 6V for 2.5V fixed output option.
2.2V < VIN < 6V for adjustable and 1.8V
0.463
0.6
V
Hysteresis
VEN(HYS)
2.9V < VIN < 6V for 2.5V fixed output option.
2.2V < VIN < 6V for adjustable and 1.8V
135
mV
COUT = 10µF, ILOAD = 1A
150
Enable Pin Turn-on Delay
tEN
VIN = 6V, EN = 3V
Enable Pin Leakage Current
0.95
V
µs
1
µA
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
RPD
Soft-Start Charge Current
ICHG
323
Ω
-7
-4.5
-2
µA
75
84
92
%VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
47
100
mV
0.05
1
µA
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal value.
11. Minimum cap of 10µF X5R/X7R on VIN and VOUT required for stability.
12. If the current limit for in-rush current is acceptable in application, do not use this feature (leave SS pin open). Used only when large bulk capacitance
required on VOUT for application.
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FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A.
2.0
1.8
1.8
OUTPUT VOLTAGE (V)
VOUT (%)
1.2
0.6
0
-0.6
-1.2
1.6
+125°C
1.4
1.2
-40°C
+25°C
1.0
0.8
0.6
0.4
0.2
-1.8
-50
-25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
125
0
150
FIGURE 3. VOUT vs TEMPERATURE
GROUND CURRENT (mA)
+25°C
0.0
-0.6
-40°C
-1.2
6
+125°C
0
0.5
7
6
5
4
3
2
1
1.0
1.5
2.0
2.5
0
3.0
3
2
OUTPUT CURRENT (A)
FIGURE 5. VOUT vs OUTPUT CURRENT
4
INPUT VOLTAGE (V)
9.1
12.0
8.9
11.5
11.0
8.7
-40°C
8.5
8.3
+25°C
8.1
+125°C
7.9
-40°C
10.5
10.0
9.5
+125°C
9.0
+25°C
8.0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
FIGURE 7. GROUND CURRENT vs OUTPUT CURRENT
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6
6
8.5
7.7
0
5
FIGURE 6. GROUND CURRENT vs SUPPLY VOLTAGE
CURRENT (mA)
GROUND CURRENT (mA)
5
8
0.6
7.5
3
2
4
SUPPLY VOLTAGE (V)
9
1.2
VOUT (%)
1
FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8
-1.8
0
3.0
7.5
0.8
1.4
2.0
2.6
3.2
3.8
OUTPUT VOLTAGE (V)
4.4
5.0
FIGURE 8. GROUND CURRENT vs OUTPUT VOLTAGE (VIN = VOUT + VDO)
FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
5.0
12
11
10
9
8
7
6
5
4.0
GROUND CURRENT (µA)
GROUND CURRENT (µA)
4.5
3.5
3.0
2.5
2.0
1.5
1.0
VIN = 5V
0.5
0.0
-40 -25 -10
5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
95
5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
FIGURE 10. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE
DROPOUT VOLTAGE (mV)
150
140
130
120
110
2A
100
3A
90
80
70
60
50
40
30
20
1A
10
0
-40 -25 -10
5 20 35 50 65 80
TEMPERATURE (°C)
VIN = 6V
0
-40 -25 -10
FIGURE 9. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE
DROPOUT VOLTAGE (mV)
4
3
2
1
110 125
FIGURE 11. DROPOUT VOLTAGE vs TEMPERATURE
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3.0
FIGURE 12. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
VOLTAGE (V)
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
-40 -25 -10
5
20
35
50
65
80
95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 13. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE
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FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
EN (1V/DIV)
SS (500mV/DIV)
EN (1V/DIV)
VOUT (500mV/DIV)
SS (500mV/DIV)
VOUT (500mV/DIV)
PG (1V/DIV)
PG (1V/DIV)
TIME (100µs/DIV)
TIME (6.4ms/DIV)
FIGURE 14. ENABLE START-UP SS CAP 1nF
FIGURE 15. ENABLE SHUTDOWN SS CAP 1nF
EN (1V/DIV)
EN (1V/DIV)
SS (500mV/DIV)
VOUT (500mV/DIV)
SS (1V/DIV)
VOUT (1V/DIV)
PG (1V/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (100µs/DIV)
FIGURE 16. ENABLE START-UP SS CAP 100nF
FIGURE 17. ENABLE START-UP (NO SS CAP)
300
EN (1V/DIV)
SS (1V/DIV)
VOUT (1V/DIV)
START-UP TIME (µs)
250
200
150
100
50
PG (1V/DIV)
TIME (5ms/DIV)
FIGURE 18. ENABLE SHUTDOWN (NO SS CAP)
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8
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
FIGURE 19. START-UP TIME vs SUPPLY VOLTAGE
FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
300
OUTPUT CURRENT (A)
START-UP TIME (µs)
250
200
150
100
50
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
FIGURE 20. START-UP TIME vs TEMPERATURE
OUTPUT CURRENT (A)
ISL80103
ISL80102
-40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FIGURE 21. CURRENT LIMIT vs TEMPERATURE
IOUT (1A/DIV)
ISL80103
ISL80102
VOUT (1V/DIV)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE(V)
FIGURE 22. CURRENT LIMIT vs SUPPLY VOLTAGE
TIME (10ms/DIV)
FIGURE 23. CURRENT LIMIT RESPONSE (ISL80102)
EN (1V/DIV)
IOUT (2A/DIV)
IINRUSH (2A/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
TIME (5ms/DIV)
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80103)
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PG (1V/DIV)
TIME (200µs/DIV)
FIGURE 25. IN-RUSH CURRENT WITH NO SOFT-START CAPACITOR,
COUT = 1000µF
FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
EN (1V/DIV)
VOUT (50mV/DIV)
IINRUSH (1A/DIV)
VOUT (1V/DIV)
PG (1V/DIV)
TIME (1ms/DIV)
FIGURE 26. IN-RUSH WITH 22nF SOFT-START CAPACITOR,
COUT = 1000µF
VOUT (50mV/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 28. LOAD TRANSIENT 0A TO 3A, COUT = 10µF
CERAMIC + 100µF OSCON
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 27. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC
VOUT (50mV/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 29. LOAD TRANSIENT 1A TO 3A, COUT = 10µF CERAMIC
VOUT (20mV/DIV)
VOUT (50mV/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
di/dt = 3A/µs
TIME (200µs/DIV)
FIGURE 30. LOAD TRANSIENT 1A TO 3A, COUT = 10µF
CERAMIC + 100µF OSCON
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TIME (50µs/DIV)
FIGURE 31. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC,
NO CPB (ADJ VERSION)
FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
3.2V
2.2V
VOUT (20mV/DIV)
VIN (1V/DIV)
di/dt = 3A/sec
IOUT (2A/DIV)
VOUT (10mV/DIV)
di/dt = 3A/µs
TIME (200µs/DIV)
TIME (50µs/DIV)
FIGURE 32. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC,
CPB = 1500pF (ADJ VERSION)
FIGURE 33. LINE TRANSIENT
90
90
80
80
100mA
70
PSRR (dB)
PSRR (dB)
60
NO LOAD
60
50
40
30
1000mA
300mA
20
50
100mA
40
30
1000mA
20
10
100
1k
10k
100k
0
10
1M
100
1k
FIGURE 34. PSRR vs FREQUENCY FOR VOUT = 1.0V, VIN = 2.5V;
COUT = 47µF, CPB = 150pF
90
300mA
80
100k
1M
FIGURE 35. PSRR vs FREQUENCY FOR VOUT = 1.2V; VIN = 2.5V;
COUT = 47µF, CPB = 150pF
90
100mA
1000mA
80
100mA
70
70
NO LOAD
60
60
PSRR (dB)
NO LOAD
50 2000mA
1000mA
40
30
50
40
20
10
10
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 36. PSRR vs FREQUENCY FOR VOUT = 1.5V, VIN = 2.5V;
COUT = 22µF, CPB = 82pF
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1M
2000mA
3000mA
30
20
0
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR (dB)
300mA
10
10
0
NO LOAD
70
0
10
300mA
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 37. PSRR vs FREQUENCY FOR VOUT = 1.8V, VIN = 2.5V;
COUT = 22µF, CPB = 82pF
FN6660.7
April 8, 2016
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
IL = 0A. (Continued)
90
10
100mA
80
300mA
70
50
2000mA
1000mA
NOISE µV/√Hz
PSRR (dB)
60
NO LOAD
40
30
3000mA
1
0.1
20
10
0
10
IL = 3A
100
1k
10k
100k
0.01
10
1M
100
FREQUENCY (Hz)
FIGURE 38. PSRR vs FREQUENCY FOR VOUT = 2.5V, VIN = 3.3V;
COUT = 10µF, CPB = 47pF
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs is
optimized for a true 2.5V to 1.8V conversion where the input
supply can have a tolerance of as much as ±10% for conditions
noted in the “Electrical Specifications” table on page 4. Minimum
guaranteed input voltage is 2.2V, however, due to the nature of
an LDO, VIN must be some margin higher than the output voltage
plus dropout at the maximum rated current of the application if
active filtering (PSRR) is expected from VIN to VOUT. The dropout
spec of this family of LDOs has been generously specified in
order to allow applications to design for a level of efficiency that
can accommodate the smaller outline package.
Enable Operation
The Enable turn-on threshold is typically 800mV with a hysteresis of
135mV. An internal pull-up or pull-down resistor is available upon
request. As a result, this pin must not be left floating. This pin must
be tied to VIN if it is not used. A 1kΩ to 10kΩ pull-up resistor is
required for applications that use open collector or open drain
outputs to control the Enable pin. The Enable pin may be connected
directly to VIN for applications that are always on.
Power-Good Operation
Applications not using this feature must connect this pin to
ground. The PGOOD flag is an open-drain NMOS that can sink up
to 10mA during a fault condition. The PGOOD pin requires an
external pull-up resistor, which is typically connected to the VOUT
pin. The PGOOD pin should not be pulled up to a voltage source
greater than VIN. The PGOOD fault can be caused by the output
voltage going below 84% of the nominal output voltage, or the
current limit fault, or low input voltage. The PGOOD does not
function during thermal shutdown.
10k
100k
1M
FIGURE 39. SPECTRAL NOISE DENSITY vs FREQUENCY
Soft-Start Operation (Optional)
If the current limit for in-rush current is acceptable in the
application, do not use this feature (leave SS pin open). The
soft-start circuit controls the rate at which the output voltage
comes up to regulation at power-up or LDO enable. The external
soft-start capacitor always gets discharged to ground pin
potential at the beginning of start-up or enabling. After the
capacitor discharges, it will immediately begin charging by a
constant current source. The discharge rate is the RC time
constant of RPD and CSS. See Figures 14 through 18 in the
“Typical Operating Performance Curves” beginning on page 8.
RPD is the ON-resistance of the pull-down MOSFET, M8. RPD is
323Ω typically.
The soft-start feature effectively reduces the in-rush current at
power-up or LDO enable until VOUT reaches regulation. The
in-rush current can be an issue for applications that require large,
external bulk capacitances on VOUT where high levels of charging
current can be seen for a significant period of time. The in-rush
currents can cause VIN to drop below minimum which could
cause VOUT to shutdown. Figure 26 shows the relationship
between in-rush current and CSS with a COUT of 1000µF.
5.0
IN-RUSH CURRENT LIMIT (A)
Functional Description
1k
FREQUENCY (Hz)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
CSS (nF)
80
100
FIGURE 40. IN-RUSH CURRENT vs SOFT-START CAPACITANCE
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FN6660.7
April 8, 2016
ISL80102, ISL80103
Output Voltage Selection
Current Limit Protection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 5.5V. An external
resistor divider, R3 and R4, is used to set the output voltage as
shown in Equation 1. The recommended value for R4 is 500Ω to
1kΩR3is then chosen according to Equation 2:
The ISL80102 and ISL80103 family of LDOs incorporates
protection against overcurrent due to short, overload condition
applied to the output and the in-rush current that occurs at
start-up. The LDO performs as a constant current source when
the output current exceeds the current limit threshold noted in
the “Electrical Specifications” table on page 4. If the short or
overload condition is removed from VOUT, then the output returns
to normal voltage mode regulation. In the event of an overload
condition, the LDO might begin to cycle on and off due to the die
temperature exceeding the thermal fault condition.
(EQ. 1)
V OUT
R 3 = R 4   ---------------- – 1
 0.5V

(EQ. 2)
External Capacitor Requirements
External capacitors are required for proper operation. To ensure
optimal performance careful attention must be paid to the layout
guidelines and selection of capacitor type and value.
OUTPUT CAPACITOR
The ISL80102 and ISL80103 applies state-of-the-art internal
compensation to keep selection of the output capacitor simple
for the customer. Stable operation over full temperature, VIN
range, VOUT range and load extremes are guaranteed for all
ceramic capacitors and values assuming a 10µF X5R/X7R is
used for local bypass on VOUT. This minimum capacitor (see
Table 1 components value selection) must be connected to VOUT
and Ground pins of the LDO with PCB traces no longer than
0.5cm.
Lower cost Y5V and Z5U type ceramic capacitors are acceptable
if the size of the capacitor is larger to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value in Ceramic, POSCAP or Alum/Tantalum
Electrolytic types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output voltage
tolerances.
INPUT CAPACITOR
The minimum input capacitor required for proper operation is
10µF having a ceramic dielectric. This minimum capacitor must
be connected to VIN and ground pins of the LDO with PCB traces
no longer than 0.5cm.
Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable with
10µF or larger ceramic capacitor.
Applications using the ADJ versions may see improved
performance with the addition of a small ceramic capacitor CPB
as shown in Figure 2, on page 2. The conditions where CPB may
be beneficial are: (1) VOUT > 1.5V, (2) COUT = 10µF, and (3) tight
AC voltage regulation band.
CPB introduces phase lead with the product of R3 and CPB that
results in increasing the bandwidth of the LDO. Typical R3 x CPB
should be less than 0.4μs (400ns).
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Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 8)” on page 4.
The power dissipation can be calculated by using Equation 3:
P D =  V IN – V OUT   I OUT + V IN  I GND
(EQ. 3)
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) will
determine the maximum allowable power dissipation as shown
in Equation 4:
(EQ. 4)
P D  MAX  =  T J  MAX  – T A    JA
Where JA is the junction-to-ambient thermal resistance.
For safe operation, please make sure that power dissipation
calculated in Equation 3, PD , be less than the maximum
allowable power dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for heat sinking. Figure 41 shows a curve for the JA
of the DFN package for different copper area sizes.
46
44
JA, (°C/W)
 R3

V OUT = 0.5V   ------- + 1
 R4

42
40
38
36
34
2
4
6
8
10
12
14
16
18
20
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 41. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
Thermal Fault Protection
In the event the die temperature exceeds typically +160°C, then
the output of the LDO will shut down until the die temperature
can cool down to typically +145°C. The level of power combined
with the thermal impedance of the package (+48°C/W for DFN)
will determine if the junction temperature exceeds the thermal
shutdown temperature.
FN6660.7
April 8, 2016
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have
the latest Rev.
DATE
REVISION
CHANGE
April 8, 2016
FN6660.7
Updated Ordering Information table (on page 3), Note 1 to include quantities for tape and reel options.
Changed VOUT range upper limit from “5V to 5.5V” on page 1, in the “Recommended Operating Conditions
(Note 7)” on page 4 and in the “Output Voltage Selection” on page 12
Electrical Spec table test conditions changed from: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,
ILOAD = 0A, to: 2.2V < VIN < 6V, VOUT = 0,5V, TJ = +25°C, ILOAD = 0A
Changed Test conditions in “Output Noise Voltage” on page 5 from: ILOAD = 10mA, BW = 300Hz <f< 300kHz; to:
VIN = 2.2V, VOUT = 1.8V, ILOAD = 3A, BW = 100Hz<f<100kHz and changed TYP from: 100; to: 49
Added two rows to “Dropout Voltage (Note 9)” on page 5 to show parameters for 5.5V VOUT conditions.
Updated verbiage for “About Intersil” on page 16.
Updated POD L10.3x3 to most updated revision with changes as follows:
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line up
with the centers of the corner pins.
Changed Tiebar note 4, from: Tiebar shown (if present) is a non-functional feature.
to: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
May 23, 2013
FN6660.6
Pin Descriptions on page page 2, updated EPAD section From: EPAD at ground potential. Soldering it directly to
GND plane is optional. To: EPAD must be connected to copper plane with as many vias as possible for proper
electrical and optimal thermal performance.
Removed obsolete part numbers: ISL80102IR33Z, ISL80102IR50Z, ISL80103IR33Z, ISL80103IR50Z from
ordering information table on page 3.
Added evaluation boards to ordering information table on page 3: ISL80103IR50Z and ISL80103EVAL2Z.
Features on page 1: Removed 5 Ld TO220 and 5 Ld TO263.
Input Voltage Requirements on page 12: Removed the sentence “those applications that cannot accommodate
the profile of the TO220/TO263”.
June 14, 2012
FN6660.5
In “Thermal Information” on page 4, corrected JA from 48 to 45.
February 14, 2012
FN6660.4
Increased “VEN(HIGH)” minimum limit from 0.4V to 0.616 and added the “VEN(LOW)” spec for clarity on page 5.
December 14, 2011
FN6660.3
Increased “Turn-on Threshold” minimum limit on page 5 from 0.3V to 0.4V.
Updated “Package Outline Drawing” on page 16 as follows:
Removed package outline and included center to center distance between lands on recommended land pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm
from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
March 4, 2011
FN6660.2
Converted to new template
On page 1 - first paragraph, changed "Fixed output voltage options are available in 1.5V, 1.8V, 2.5V, 3.3V and 5V"
to "Fixed output voltage options are available in 1.8V, 2.5V, 3.3V and 5V"
In “Ordering Information” table on page 2, removed ISL80102IR15Z and ISL80103IR15Z.
In Note 3 on page 2, below the “Ordering Information” table , removed '1.5V', so it reads “The 3.3V and 5V fixed
output voltages will be released in the future. Please contact Intersil Marketing for more details.”
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FN6660.7
April 8, 2016
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have
the latest Rev. (Continued)
DATE
REVISION
CHANGE
March 4, 2010
FN6660.1
Corrected Features on page 1 as follows:
-Changed bullet "• 185mV Dropout @ 3A, 125mV Dropout @ 2A" to "• Very Low 120mV Dropout at 3A"
-Changed bullet "• 65dB Typical PSRR" to "• 62dB Typical PSRR"
-Deleted 0.5% Initial VOUT Accuracy
Modified Figure 1 and placed as “TYPICAL APPLICATION” on page 1.
Moved Pinout to page 3
In “Block Diagram” on page 2, corrected resistor associated with M5 from R4 to R5
Updated “Block Diagram” on page 2 as follows”
- Added M8 from SS to ground.
Updated Figure 1 on page 1 as follows:
-Corrected Pin 6 from SS to IRSET
-Removed Note 11 callout "Minimum cap on VIN and VOUT required for stability." Added Note "*CSS is optional.
See Note 12 on Page 5." and “** CPB is optional. See “Functional Description” on page 12 for more information.”
Added "The 1.5V, 3.3V and 5V fixed output voltages will be released in the future." to Note 3 on page 2.
In “Thermal Information” on page 4, updated Theta JA from 45 to 48.
In “Soft-Start Operation (Optional)” on page 12:
-Changed "The external capacitor always gets discharged to 0V at start-up of after coming out of a chip disable.
"The external capacitor always gets discharged to ground pin potential at start-up or enabling."
-Changed "The soft-start function effectively limits the amount of in-rush current below the programmed current
limit during start-up or an enable sequence to avoid an overcurrent fault condition." to "The soft-start feature
effectively reduces the in-rush current at power-up or LDO enable until VOUT reaches regulation."
-Added "See Figures 25 through 27 in the “Typical Operating Performance Curves” beginning on page 6."
-Added “RPD is the on resistance of the pull-down MOSFET, M8. RPD is 300Ω typically.”
March 4, 2010
September 30, 2009
Added “Phase Boost Capacitor (Optional)” on page 13.
In “Typical Operating Performance” on page 11, revised figure "PSRR vs VIN" which had 3 curves with “SPECTRAL
NOISE DENSITY vs FREQUENCY” which has one curve.
Added "Figure 33. “LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC, NO CPB (ADJ VERSION)” and "Figure 34.
“LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC, CPB = 1500pF (ADJ VERSION)”
FN6660.0
Initial Release.
About Intersil
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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15
FN6660.7
April 8, 2016
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
3.00
5
PIN #1 INDEX AREA
A
B
1
5
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
(4X)
0.10 M C A B
0.415
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
0.20
2.00
(8x 0.50)
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
0.415
C
1.60
0.20 REF
4
0.05
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
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16
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6660.7
April 8, 2016
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