an1661

Application Note 1661
ISL80102, ISL80103 High Performance 2A and 3A LDOs
Evaluation Board User Guide
Description
Required Equipment
The ISL80102 and ISL80103 are high performance, low
voltage, high current low dropout linear regulator specified at
2A and 3A, respectively. Rated for an input voltage from 2.2V
to 6V, these LDOs can provide outputs from 0.8V to 5V on the
adjustable version. The ISL80103EVAL2Z provides a simple
platform to evaluate performance of the ISL80102, ISL80103.
The following equipment is recommended to perform the
tests:
The ISL80103EVAL2Z evaluation board comes with the
adjustable output version of the IC. Jumpers are provided to
set the desired output voltage. Fixed output versions are
sampled in the accompanying kit.
• 200MHz oscilloscope
The figures with operating conditions at 3A in this Application
Note are applicable only to the ISL80103. All other information
is applicable to both the ISL80102 and ISL80103.
What’s Inside
The evaluation kit contains the following:
• The ISL80103EVAL2Z
• Fixed output versions of either the ISL80102 or the
ISL80103
• 0V to 6V power supply capable of sourcing at least 5A
• Electronic load capable of sinking up to 5A
• Digital multimeters
Test Procedure
1) Select the desired output voltage by shorting one of the
jumpers from J1 through J6.
2) Ensure that output capacitor and Cpb are set according to
recommended values shown in Table 1.
3) Place jumper JP1 in the ‘enable’ position. It is
recommended to not leave the ENABLE pin floating.
4) Set the power supply for the desired input voltage and the
load as desired and connect them to the input and output of
the board, respectively.
5) Turn the power supply on and observe the output.
• The ISL80102, ISL80103 data sheet (FN6660)
• This evaluation kit document
FIGURE 1. ISL80103EVAL2Z
September 2, 2011
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1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1661
Optimizing LDO Performance
TABLE 1.
Performance of the ISL80102, ISL80103 can be optimized by
following these simple guidelines.
VOUT
RTOP
RBOTTOM
CPB
COUT
5.0V
2.61kΩ
287Ω
47pF
10µF
Phase Boost Capacitor (CPB)
3.3V
2.61kΩ
464Ω
47pF
10µF
On the adjustable version of the ISL80102, ISL80103, phase
margin and crossover frequency can be increased by placing a
small capacitor across the top resistor in the feedback resistor
divider. Cpb and Rtop as shown in Figure 2 place a zero at
Fz = 1/(2•π•RTOP•CPB)
2.5V
2.61kΩ
649Ω
47pF
10µF
1.8V*
2.61kΩ
1.0kΩ
47pF
10µF
1.8V*
2.61kΩ
1.0kΩ
82pF
22µF
1.5V
2.61kΩ
1.3kΩ
82pF
22µF
1.2V
2.61kΩ
1.87kΩ
150pF
47µF
1.0V
2.61kΩ
2.61kΩ
150pF
47µF
0.8V
2.61kΩ
4.32kΩ
150pF
47µF
The zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
VIN
VOUT
ENABLE
PG
RTOP
ISL80102,
ISL80103
C PB
ADJ
COUT
C IN
RBOTTOM
SS
FIGURE 2. ISL80102, ISL80103 TYPICAL APPLICATION
NOTE: *Either option could be used depending on cost/performance
requirements
Layout Guidelines
A good PCB layout is important to achieve expected
performance. Consideration should be taken when placing the
components and routing the trace to minimize the ground
impedance. Parasitic inductance should be kept to a minimum.
The input and output capacitors should have a good ground
connection and be placed as close to the IC as possible. The
‘SENSE’ trace in fixed voltage parts and the ‘ADJ’ trace in
adjustable voltage parts must be away from noisy planes and
traces.
Output Capacitor (COUT)
Output capacitor selection is important to achieve the desired
load transient performance. The ISL80102, ISL80103 uses stateof-the-art internal compensation to be compatible with different
types of output capacitors, including multi-layer ceramic,
POSCAP and aluminum/tantalum electrolytic.
There is a growing trend to use very-low ESR multi-layer ceramic
capacitors (MLCC) for applications because they can support fast
load transients and also bypass very high frequency noise from
other sources. However, effective capacitance of MLCC's drops
with applied voltage, age and temperature. X7R and X5R
dielectric ceramic capacitors are strongly recommended as they
typically maintain a capacitance range within ±20% of nominal
over full operating ratings of temperature and voltage.
Table 1 gives the recommended values for output capacitor
(MLCC X5R/X7R) and CPB for different voltage rails.
The right selection of output capacitor and CPB also helps to
provide better PSRR at high frequencies.
2
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150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-40
ADJ PIN VOLTAGE VARIATION (%)
DROPOUT VOLTAGE (mV)
Application Note 1661
2A
3A
1A
-25
-10
5
20
35
50
65
80
95
110
0.2
0
-0.2
-0.4
-0.6
-0.8
-40
125
-20
0
20
FIGURE 3. DROPOUT vs TEMPERATURE
80
100
120
0.10
ADJ PIN VOLTAGE VARIATION (%)
ADJ PIN VOLTAGE VARIATION (%)
60
FIGURE 4. OUTPUT VOLTAGE vs TEMPERATURE
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
2.2
40
TEMPERATURE (°C)
TEMPERATURE (°C)
0.05
0
2.7
3.2
3.7
4.2
4.7
5.2
5.7
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
FIGURE 6. OUTPUT VOLTAGE vs LOAD CURRENT
1V/DIV
ENABLE
2V/DIV
20mV/DIV
VOUT
2V/DIV
10µs/DIV
3A
10mA
PG
50µs/DIV
FIGURE 7. START-UP WAVEFORMS
3
FIGURE 8. LOAD TRANSIENCE FOR VOUT = 1.0V, COUT = 47µF,
Cpb = 150pF
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September 2, 2011
Application Note 1661
20mV/DIV
50mV/DIV
10µs/DIV
3A
10µs/DIV
3A
10mA
10mA
FIGURE 9. LOAD TRANSIENCE FOR VOUT = 1.2V, COUT = 47µF,
Cpb = 150pF
FIGURE 10. LOAD TRANSIENCE FOR VOUT = 1.5V, COUT = 22µF,
Cpb = 82pF
50mV/DIV
50mV/DIV
10µs/DIV
3A
10µs/DIV
3A
10mA
10mA
FIGURE 11. LOAD TRANSIENCE FOR VOUT = 1.8V, COUT = 22µF,
Cpb = 82pF
50mV/DIV
FIGURE 12. LOAD TRANSIENCE FOR VOUT = 1.8V, COUT = 10µF,
Cpb = 47pF
50mV/DIV
10µs/DIV
3A
10mA
FIGURE 13. LOAD TRANSIENCE FOR VOUT = 2.5V, COUT = 10µF,
Cpb = 47pF
4
10µs/DIV
3A
10mA
FIGURE 14. LOAD TRANSIENCE FOR VOUT = 3.3V, COUT = 10µF,
Cpb = 47pF
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Application Note 1661
90
90
80
80
100mA
70
NO LOAD
60
PSRR (dB)
PSRR (dB)
60
50
40
30
1000mA
300mA
20
50
100mA
40
30
1000mA
20
10
100
1k
10k
100k
0
10
1M
100
FREQUENCY (Hz)
90
300mA
80
90
100mA
1000mA
80
100k
1M
100mA
70
60
50 2000mA
1000mA
40
30
50
10
10
1k
10k
100k
300mA
0
10
1M
3000mA
30
20
100
2000mA
40
20
10
NO LOAD
60
NO LOAD
PSRR (dB)
PSRR (dB)
10k
FIGURE 16. PSRR FOR VOUT = 1.2V, COUT = 47µF, Cpb = 150pF
70
0
1k
FREQUENCY (Hz)
FIGURE 15. PSRR FOR VOUT = 1.0V, C OUT = 47µF, Cpb = 150pF
100
FREQUENCY (Hz)
90
100k
1M
90
80
300mA
70
100mA
70
60
300mA
60
2000mA
1000mA
PSRR (dB)
50
10k
FIGURE 18. PSRR FOR V OUT = 1.8V, C OUT = 22µF, Cpb = 82pF
100mA
80
1k
FREQUENCY (Hz)
FIGURE 17. PSRR FOR VOUT = 1.5V, COUT = 22µF, Cpb = 82pF
PSRR (dB)
300mA
10
10
0
NO LOAD
70
NO LOAD
40
30
3000mA
50
30
20
20
10
10
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 19. PSRR FOR VOUT = 2.5V, C OUT = 10µF, Cpb = 47pF
5
NO LOAD
40
2000mA
0
10
1000mA
3000mA
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 20. PSRR FOR VOUT = 3.3V, COUT = 10µF, Cpb = 47pF
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Application Note 1661
VOUT
VIN
VOUT
VIN
CON2
CON1
C5
C3
CPB
R1
C6
R2
ADJ
ISL80102,
ISL80103
C4
N/C
PG
EN
GND
SS
JP1
TP1
J1
J2
J3
J4
J5
J6
R3
R4
R5
R6
R7
R8
TP2
C2
CON4
CON3
TABLE 2. BILL OF MATERIALS
ITEM
QTY
REFERENCE DESIGNATOR
VALUE
1
2
C5, C6
10µF
CAP, SMD, 0805, 16V, 10%,
Generic
2
1
CPB
47pF
CAP, SMD, 0603
Generic
3
1
U1
ISL80102IRAJZ or ISL80103IRAJZ
Intersil
4
1
R1
2.61kΩ
RES, SMD, 0603, 1%
Generic
5
1
R2
100kΩ
RES, SMD, 0603, 1%
Generic
6
1
R3
1kΩ
RES, SMD, 0603, 1%
Generic
7
1
R4
464Ω
RES, SMD, 0603, 1%
Generic
8
1
R5
1.3kΩ
RES, SMD, 0603, 1%
Generic
9
1
R6
1.87kΩ
RES, SMD, 0603, 1%
Generic
10
1
R7
2.61kΩ
RES, SMD, 0603, 1%
Generic
11
1
R8
649Ω
RES, SMD, 0603, 1%
Generic
12
1
JP1
Jumper
Generic
13
6
J1, J2, J3, J4, J5, J6
Jumper
Generic
14
1
TP1
Test Point
Keystone
5007
15
4
CON1, CON2, CON3, CON4
Terminal Connector
Keystone
1514-2
C2, C3, C4, TP2
6
DESCRIPTION
MANUFACTURER
PART NUMBER
ISL80102IRAJZ or
ISL80103IRAJZ
DNP
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September 2, 2011
Application Note 1661
FIGURE 21. ISL80103EVAL2Z COMPONENT PLACEMENT
FIGURE 22. ISL80103EVAL2Z TOP LAYER
FIGURE 23. ISL80103EVAL2Z BOTTOM LAYER
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
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