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Application Note 1945
ISL85415DEMO2Z Demonstration Board User Guide
Description
Key Features
The ISL85415DEMO2Z kit is intended for use in point-of-load
applications sourcing from 3V to 36V. The kit is used to
demonstrate the performance of the ISL85415 wide VIN low
quiescent current high efficiency synchronous buck regulator
using an isolated secondary output.
• Wide input voltage range 3V to 36V
The ISL85415 is offered in a 4mmx3mm 12 Ld DFN package
with 1mm maximum height. The converter occupies
1.138cm2 area.
• Continuous output current up to 300mA (refer to Figures 10
and 11)
Specifications
• Minimal external components required
• This board has been configured and optimized for the
following operating conditions:
• VIN = 3V to 36V
• Synchronous operation for high efficiency
• Integrated high-side and low-side NMOS devices
• Programmable switching frequency (fixed or externally)
• Internal or external soft-start
• Power-good function available for primary output
Recommended Equipment
The following materials are recommended to perform testing:
• VOUT = 0.6V to 12V
• IMAX = 300mA with ±1% secondary output regulation
(at VOUT = 3.3V, VIN = 12V)
• Board temperature: +25°C
• 0V to 50V power supply with at least 1A source current
capability
• Electronic loads capable of sinking current up to 1A
• Digital Multimeters (DMMs)
References
• 100MHz quad-trace oscilloscope
Ordering Information
• ISL85415 Datasheet
PART NUMBER
ISL85415DEMO2Z
FIGURE 1. FRONT OF EVALUATION BOARD ISL85415DEMO2Z
June 1, 2015
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1
DESCRIPTION
Demonstration board with Isolated
Outputs
FIGURE 2. BACK OF EVALUATION BOARD ISL85415DEMO2Z
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas LLC 2014, 2015 All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1945
Quick Set up Guide
1. Ensure that the circuit is correctly connected to the supply and
loads prior to applying any power.
2. Connect the bias supply to VIN, the plus terminal to VIN (P4)
and the negative return to GND (P5).
3. Turn on the power supply.
4. Without any load applied on the output, verify that the output
voltage is 3.3V for VOUT1 (P7).
PCB Layout Guidelines
The ISL85415EVAL2Z PCB layout has been optimized for
electrical and thermal performance. Proper layout of the power
converter will minimize EMI and noise while insuring first pass
success of the design.
PCB layout is provided on the Intersil web site. A multilayer
printed circuit board with GND plane is recommended. The most
critical connections are to tie the PGND pin to the package GND
pad and then use vias to directly connect the GND pad to the
system GND plane. This connection of the GND pad to system
plane insures a low impedance path for all return current, as well
as an excellent thermal path to dissipate heat.
With this connection made, place the high frequency MLCC input
capacitors C1, C2 near the VIN pin and use vias directly at the
capacitor pads to tie the capacitors to the system GND plane.
Also, use vias directly at the C5, C6 output capacitor pads to tie
the capacitors to the system GND plane. These measures will
minimize the high dV/dt and dI/dt loops. Minimize the PHASE
connection by placing L1 very close to the IC. Place a 1µF MLCC
near the VCC pin and directly connect its return with a via to the
system GND plane. Keep the power components path (L1, C1, C2,
C3, C5, C6) separated from the small signal nodes (FB, COMP)
and the control components path (FS, SS) by placing the
feedback divider close to the FB pin and do not route any
feedback components near PHASE or BOOT. If external
components are used for SS, COMP or FS, the same advice
applies. Connect these control components and small signal
noise components to the system GND. Keep the small signal
nodes traces (FB, COMP) as short as possible.
If the output voltage desired is 0.6V, then R1 is shorted. Please
note that if VOUT is less than 1.8V, the switching frequency and
compensation must be changed for 300kHz operation due to
minimum on-time limitation. Please refer to datasheet ISL85415
for further information.
Table 1 shows external component selection for different desired
VOUT.
The curves in Figure 10 indicate the secondary output voltage
regulation versus the load applied in the secondary output,
without any load on the primary output for VOUT = 5V, at different
input voltages. The curves in Figure 11 indicate the secondary
output voltage regulation versus the load applied in the
secondary output, without any load on the primary output for
VOUT = 3.3V, at different input voltages.
Frequency Control
The ISL85415 has an FS pin that controls the frequency of
operation. Programmable frequency allows for optimization
between efficiency and external component size. It also allows low
frequency operation for low VOUTs when minimum on-time would
limit the operation otherwise. Default switching frequency is
500kHz when FS is tied to VCC (R10 = 0). By removing R10 the
switching frequency could be changed from 300kHz (R12 = 340k)
to 2MHz (R12 = 32.4k). Please refer to datasheet ISL85415 for
calculating the value of R12. Do not leave this pin floating.
Disabling/Enabling Function
The ISL85415DEMO2Z board has the EN pin tied to VIN via R7.
This keeps the part enabled all the time. To disable the part,
remove R7 and populate R8 with a 0Ω resistor.
SYNC Control
The ISL85415 evaluation board has a SYNC pin that allows
external synchronization frequency to be applied. Default board
configuration has R6 = 200k to VCC, which defaults to PWM
operation mode and also to the preselected switching frequency
set by R12 (see ISL85415 datasheet and previous section
“Frequency Control” for details). If this pin is tied to GND, the IC
will operate in PFM mode. For PFM operation, remove R6 and
populate R9 with 0Ω resistor.
Evaluating the Other Output Voltage
Soft-start/COMP Control
The ISL85415DEMO2Z kit output is preset to 3.3V; however,
output voltages can be adjusted from 0.6V to 15V. The output
voltage programming resistor, R2, will depend on the desired
output voltage of the regulator and the value of the feedback
resistor R1, as shown in Equation 1.
R15 selects between internal (R15 = 0) and external soft-start.
R11 selects between internal (R11 = 0) and external
compensation. Please refer to the Pin Description table of the
ISL85415 datasheet.
0.6
R 2 = R 1  ---------------------------
V

OUT – 0.6
(EQ. 1)
TABLE 1. EXTERNAL COMPONENT SELECTION
VOUT
(V)
L1
(µH)
COUT
(µF)
R1
(kΩ)
R2
(kΩ)
CFB
(pF)
RFS
(kΩ)
RCOMP
(kΩ)
CCOMP
(pF)
12
45
10
90.9
4.75
22
115
100
470
5
22
2x22
90.9
12.4
100
120
100
470
3.3
22
2x22
90.9
20
100
120
100
470
2.5
22
2x22
90.9
28.7
100
120
100
470
1.8
22
22
100
50
22
120
50
470
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Application Note 1945
ISL85415DEMO2Z Schematic
R10
P10
VCC
CSS
0.033µF
R15
VCC
C3
VIN
2
SYNC
COMP
BOOT
3
BOOT
FB
16
1
4
FS
VIN
PHASE 5
VCC
C8
FS OPEN
12
R11
OPEN
R3
100k
11 COMP
VO
R1
90.9k
10 FB
9 VCC
PHASE
PG
8 PG
PGND
EN
7 EN
13
L1
750314712
22µH
2
C2
10µF
TKSS
6
SEC
4
GND
C4
100PF
R2
20k
C9
1µF
EP
ISL85415
A
A
A
A
A
P9
1
SYNC
PRI
P5
C1
10µF
SS
0.1µF
3
C11
150µF
C7
470pF
A
U1
OPEN
VIN
P4
OPEN
R12
120k
2
GND
D1
P3
1
1N5819HW
VOUT SEC
3.3V
C10
1µF
R14
1.05k
VOUT PR
P7
VO
A
R13
1.05k
C6
22µF
C5
22µF
3.3V
A
VCC
P8
VIN
VCC
R6
200k
R7
200k
PG
P1
SYNC
EN
P2
P6
R9
OPEN
R8
OPEN
A
A
NOTE: If the IC is used in an application where the input test leads have large parasitic inductance, the input electrolytic
capacitor C11 may be added to prevent transient voltages on the input pin.
FIGURE 3. ISL85415DEMO2Z SCHEMATIC
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Application Note 1945
ISL85415DEMO2Z Bill of Materials
MANUFACTURER PART
QTY
UNIT
REFERENCE DESIGNATOR
EEE-FK1H151P
1
ea.
GRM188R71E105KA12D
1
ea.
C10
CAP, SMD, 0603, 1µF, 25V, 10%, X7R, ROHS
MURATA
04025A101FAT2A
1
ea.
C4
CAP, SMD, 0402, 100pF, 50V, 1%, NP0, ROHS
AVX
GRM36X7R333K016AQ
1
ea.
CSS
CAP, SMD, 0402, 33nF, 16V, 10%, X7R, ROHS
MURATA
ECJ-0EB1H471K
1
ea.
C7
CAP, SMD, 0402, 470pF, 50V, 10%, X7R, ROHS
PANASONIC
0
ea.
C8
CAP, SMD, 0402, DNP-PLACE HOLDER, ROHS
06035C104KAT2A
1
ea.
C3
CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS
GRM188R61C105KA12D
1
ea.
C9
CAP, SMD, 0603, 1µF, 16V, 10%, X5R, ROHS
MURATA
C3216X5R1H106K
2
ea.
C1, C2
CAP, SMD, 1206, 10µF, 50V, 10%, X5R, ROHS
TDK
ECJ-DV50J226M
2
ea.
C5, C6
CAP, SMD, 1206, 22µF, 6.3V, 20%, X5R, ROHS
PANASONIC
1514-2
5
ea.
P3, P4, P5, P7, P9
CONN-TURRET, TERMINAL POST, TH, ROHS
KEYSTONE
C11 (OPTIONAL)
DESCRIPTION
CAP, SMD, 10.3mm, 150µF, 50V, 20%, ROHS,
ALUM.ELEC.
MANUFACTURER
PANASONIC
AVX
5002
5
ea.
P1, P2, P6, P8, P10
CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS
KEYSTONE
1N5819HW-7-F
1
ea.
D1
DIODE-RECTIFIER, SMD, 2P, SOD-123, 40V, 1A,
ROHS
DIODES, INC.
ISL85415FRZ
1
ea.
U1
IC-500mA BUCK REGULATOR, 12P, DFN, 3X4, ROHS INTERSIL
750314712
1
ea.
L1
TRANSFORMER- CUSTOM, SMD, 6P, 10.16 x11.66,
22µH, 10%, 2.5A, ROHS
0
ea.
R8-R11, R15
RES, SMD, 0402, DNP, DNP, DNP, TF, ROHS
ERJ2RKF1003
1
ea.
R3
RES, SMD, 0402, 100k, 1/16W, 1%, TF, ROHS
WURTH ELECTRONICS
MIDCOM INC.
PANASONIC
ERJ-2RKF1051X
2
ea.
R13, R14
RES, SMD, 0402, 1.05k, 1/16W, 1%, TF, ROHS
PANASONIC
MCR01MZPF1203
1
ea.
R12
RES, SMD, 0402, 120k, 1/16W, 1%, TF, ROHS
ROHM
ERJ2RKF2001
1
ea.
R2
RES, SMD, 0402, 20k, 1/16W, 1%, TF, ROHS
PANASONIC
MCR01MZPF2003
2
ea.
R6, R7
RES, SMD, 0402, 200k, 1/16W, 1%, TF, ROHS
ROHM
CRCW040290K9FKED
1
ea.
R1
RES, SMD, 0402, 90.9k, 1/16W, 1%, TF, ROHS
VISHAY/DALE
D810 (212403-012)
1
ea.
PLACE ASSY IN BAG
BAG, STATIC, 3X5, ZIP LOC
INTERSIL COMMON
STOCK
LABEL-DATE CODE
1
ea.
AFFIX TO BACK OF PCB
LABEL-DATE CODE_LINE 1: YRWK/REV#,
LINE 2: BOM NAME
INTERSIL
ISL85415DEMO2ZREVAPCB
1
ea.
PWB-PCB, ISL85415DEMO2Z, REVA, ROHS
IMAGINEERING INC
ISL85415DEMO2Z Board Layout
FIGURE 4. SILKSCREEN TOP
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FIGURE 5. TOP LAYER
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Application Note 1945
ISL85415DEMO2Z Board Layout (Continued)
FIGURE 6. LAYER 2
FIGURE 7. LAYER 3
FIGURE 8. BOTTOM LAYER
FIGURE 9. SILKSCREEN BOTTOM
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Application Note 1945
Typical Performance Curves
fSW = 800kHz, TA = +25°C.
10
12
9
8
8
±%REGULATION
±%REGULATION
10
6
4
VIN = 24V
VIN = 12V
2
7
6
5
4
VIN = 5V
3
VIN = 12V
2
1
0
0
50
100
150
200
IOUT (mA)
FIGURE 10. VOUT = 5V, %REGULATION vs I OUT
250
0
0
50
100
150
200
IOUT (mA)
250
300
350
FIGURE 11. VOUT = 3.3V, %REGULATION vs I OUT
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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