PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 D D D D D D D D D D D D D D D D D (PCI) Power Management 1.0 Compliant ACPI 1.0 Compliant Packaged in GFN 256-Pin BGA or GJG MicroStar BGA PCI Local Bus Specification Revision 2.2 Compliant 1997 PC Card Standard Compliant PC 99 Compliant 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards Supports Two PC Card or CardBus Slots With Hot Insertion and Removal Uses Serial Interface to TI TPS2206 Dual Power Switch Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and the CardBus Bus Supports Serialized Interrupt Request (IRQ) With PCI Interrupts 8-Way Legacy IRQ Multiplexing System Interrupts Can Be Programmed as PCI Style or Industry Standard Architecture (ISA-IRQ) Style ISA-IRQ Interrupts Can Be Serialized Onto a Single IRQ Serial (IRQSER) Pin EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID D D D D D D D D D D D D D D Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus Supports Zoomed Video With Internal Buffering Four General Purpose I/Os Multifunction PCI Device With Separate Configuration Space for Each Socket Five PCI Memory Windows and Two I/O Windows Available for Each PC Card16 Socket Two I/O Windows and Two Memory Windows Available to Each CardBus Socket Exchangeable Card Architecture (ExCA ) Compatible Registers Are Mappable in Memory and I/O Space Supports Distributed DMA (DDMA) and PC/PCI DMA Intel 82365SL-DF Register Compatible Supports 16-Bit DMA on Both PC Card Sockets Supports Ring Indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN Advanced Submicron, Low-Power CMOS Technology Provides VGA/Palette Memory and I/O and Subtractive Decoding Options LED Activity Pins Supports PCI Bus Lock (LOCK) Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Signal Name/Terminal Number Sort Tables . . . . . . . . . . . . . . . . . 4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . 32 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . 40 PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . 40 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . 76 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . 100 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . 108 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . 115 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . 117 PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . 118 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . 119 PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Timing Requirements, (Memory Cycles) . . . . . . . . . . . . . . . . . . . . 121 Timing Requirements, (I/O Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . 121 Switching Characteristics (Miscellaneous) . . . . . . . . . . . . . . . . . . 122 PC Card Parameter Measurement Information . . . . . . . . . . . . . . . 122 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 description The TI PCI1251B is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two independent PC Card sockets compliant with the 1997 PC Card Standard. The PCI1251B provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1251B supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required. The PCI1251B is compliant with the latest PCI Bus Power Management Specification. It is also compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions. Multiple system-interrupt signaling options are provided and they include: D D D D Parallel PCI interrupts Parallel ISA interrupts Serialized ISA interrupts Serialized ISA and PCI interrupts Additionally, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1251B is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1251B internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1251B can also be programmed to accept fast posted writes to improve system-bus utilization. The PCI1251B provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading specifications. Many other features, such as socket activity light-emitting diode (LED) outputs, are designed into the PCI1251B. These features are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Unused PCI1251B inputs must be pulled up using a 43 kW resistor. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 system block diagram A simplified system block diagram using the PCI1251B is provided below. The zoomed video (ZV) capability can be used to route the ZV data directly to the VGA controller. The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode), 23 of the 68 signals are redefined to support the ZV protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. The ring indicate terminal is included in the interrupt interface because its function is to perform system wake up on incoming PC Card modem rings. Other miscellaneous system interface terminals available on the PCI1251B include: D D D Programmable general purpose multifunction terminals SUSPEND, RI_OUT/PME (power management control signal) SPKROUT PCI Bus Activity LED’s CLKRUN TPS2206 Power Switch PC Card Socket A PC Card Socket B PCI1251B ZV Enable 3 South Bridge IRQSER† DMA PME Embedded Controller Zoomed Video 68 19 Video 4 Audio 23 for ZV (See Note) VGA Controller †Interrupt Routing Options: 1) Serialized, including PCI and ISA 2) Serialized ISA and parallel PCI 3) Parallel PCI and parallel ISA 4) Parallel PCI interrupts only 68 23 for ZV NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode, 23 pins are used for routing the zoomed video signals to the VGA controller. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 signal names and terminal assignments Signal names and their terminal assignments are shown in Tables 1 through 4 sorted alphanumerically by the assigned terminal. Table 1. GFN Terminals Sorted Alphanumerically for CardBus and 16-Bit Signals GFN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 4 SIGNAL NAME GND ZV_UV3 ZV_Y7 VCCZ ZV_Y1 ZV_HREF B_RSVD//B_D2 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG/RI) B_CINT//B_READY(IREQ) B_CVS1//B_VS1 B_CAD24//B_A2 B_CAD22//B_A4 B_CAD20//B_A6 B_CAD18//B_A7 B_CIRDY//B_A15 B_CCLK//B_A16 B_CDEVSEL//B_A21 B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV5 ZV_UV4 ZV_UV1 ZV_Y6 ZV_Y4 ZV_Y0 B_CAD31//B_D10 B_CAD29//B_D1 B_CCLKRUN//B_WP(IOIS16) B_CSERR//B_WAIT B_CAD25//B_A1 B_CC/BE3//B_REG B_CAD21//B_A5 B_CVS2//B_VS2 B_CAD17//B_A24 VCCB B_CPERR//B_A14 B_CBLOCK//B_A19 B_CC/BE1//B_A8 B_CAD14//B_A9 ZV_RSVD1 ZV_SCLK ZV_UV6 ZV_UV2 ZV_Y5 ZV_Y3 ZV_VSYNC B_CAD30//B_D9 GFN C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F4 F17 F18 F19 F20 G1 G2 G3 SIGNAL NAME B_CCD2//B_CD2 VCCB B_CAD26//B_A0 B_CAD23//B_A3 B_CRST//B_RESET B_CAD19//B_A25 B_CFRAME//B_A23 B_CTRDY//B_A22 B_CSTOP//B_A20 B_CAD16//B_A17 B_CAD15//B_IOWR B_CAD11//B_OE VCCZ ZV_UV7 ZV_MCLK GND ZV_UV0 VCC ZV_Y2 GND B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR) VCC B_CREQ//B_INPACK GND B_CC/BE2//B_A12 VCC B_CGNT//B_WE GND B_CAD12//B_A11 B_CAD10//B_CE2 B_CC/BE0//B_CE1 ZV_PCLK ZV_SDATA ZV_LRCLK ZV_RSVD0 B_CAD13//B_IORD B_CAD9//B_A10 B_CAD8//B_D15 B_RSVD//B_D14 VCC VCC VCCB B_CAD5//B_D6 B_CAD3//B_D5 A_CAD2//A_D11 A_CAD0//A_D3 A_CCD1//A_CD1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GFN G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 SIGNAL NAME B_CAD7//B_D7 B_CAD6//B_D13 B_CAD4//B_D12 B_CAD1//B_D4 A_CAD3//A_D5 A_CAD4//A_D12 A_CAD1//A_D4 GND GND B_CAD2//B_D11 B_CAD0//B_D3 B_CCD1//B_CD1 A_CAD7//A_D7 A_RSVD//A_D14 A_CAD5//A_D6 A_CAD6//A_D13 PCLK CLKRUN PRST GNT A_CC/BE0//A_CE1 VCCA A_CAD8//A_D15 VCC REQ AD31 AD30 VCCP A_CAD9//A_A10 A_CAD10//A_CE2 A_CAD11//A_OE A_CAD13//A_IORD VCC AD28 AD27 AD29 A_CAD12//A_A11 A_CAD15//A_IOWR A_CAD14//A_A9 A_CAD16//A_A17 C/BE3 AD24 AD25 AD26 A_CC/BE1//A_A8 A_RSVD//A_A18 A_CPAR//A_A13 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 signal names and terminal assignments (continued) Table 1. GFN Terminals Sorted Alphanumerically for CardBus and 16-Bit Signals (Continued) GFN N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 SIGNAL NAME GND GND AD22 AD23 IDSEL A_CBLOCK//A_A19 A_CPERR//A_A14 A_CGNT//A_WE A_CTRDY//A_A22 AD17 VCCP AD20 AD21 A_CSTOP//A_A20 A_CDEVSEL//A_A21 VCCA VCC VCC AD16 AD18 AD19 A_CCLK//A_A16 A_CIRDY//A_A15 A_CC/BE2//A_A12 A_CAD19//A_A25 STOP IRDY FRAME C/BE2 A_CFRAME//A_A23 A_CAD17//A_A24 A_CVS2//A_VS2 GND A_CAD26//A_A0 VCC A_CCLKRUN//A_WP(IOIS16) GND GFN U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 SIGNAL NAME IRQMUX1 VCC PCGNT/IRQMUX6 CLOCK GND AD6 VCC AD11 GND PERR SERR TRDY A_CAD18//A_A7 A_CAD20//A_A6 A_CAD21//A_A5 A_CAD25//A_A1 A_CSERR//A_WAIT A_CSTSCHG//A_BVD1(STSCHG/RI) A_CAD28//A_D8 A_RSVD//A_D2 IRQMUX2 VCCI GPIO0/LEDA1 DATA GPIO3/INTA AD3 VCCP AD8 AD12 AD15 GPIO2/LOCK DEVSEL A_CRST//A_RESET A_CAD22//A_A4 A_CAD23//A_A3 A_CAD24//A_A2 VCCA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GFN W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 SIGNAL NAME A_CCD2//A_CD2 A_CAD29//A_D1 A_CAD31//A_D10 IRQMUX3 IRQMUX5 GPIO1/LEDA2 LATCH IRQSER/INTB AD1 AD4 AD7 AD9 AD13 C/BE1 VCCP A_CREQ//A_INPACK A_CC/BE3//A_REG A_CVS1//A_VS1 A_CINT//A_READY(IREQ) A_CAUDIO//A_BVD2(SPKR) A_CAD27//A_D0 A_CAD30//A_D9 IRQMUX0 IRQMUX4 SPKROUT SUSPEND PCREQ/IRQMUX7 RI_OUT/PME AD0 AD2 AD5 C/BE0 AD10 AD14 PAR 5 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 signal names and terminal assignments (continued) Table 2. GJG Terminals Sorted Alphanumerically for CardBus and 16-bit Signals NO. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 6 SIGNAL NAME ZV_UV6 ZV_UV4 ZV_UV2 ZV_Y6 ZV_Y3 ZV_VSYNC VCC B_CCLKRUN//B_WP(IOIS16) B_CSERR//B_WAIT B_CAD24//B_A2 B_CAD21//B_A5 B_CAD20//B_A6 B_CAD17//B_A24 VCCB B_CGNT//B_WE B_CPERR//B_A14 B_CBLOCK//B_A19 ZV_SCLK ZV_UV5 ZV_UV3 ZV_UV1 ZV_Y7 ZV_Y4 ZV_Y0 B_CAD30//B_D9 B_CCD2//B_CD2 VCCB B_CAD25//B_A1 B_CAD22//B_A4 B_CVS2//B_VS2 GND B_CIRDY//B_A15 B_CDEVSEL//B_A21 B_CSTOP//B_A20 B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV7 ZV_MCLK B_CC/BE1//B_A8 B_CAD14//B_A9 ZV_RSVD0 ZV_RSVD1 GND ZV_UV0 VCCZ GND B_RSVD//B_D2 B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR) B_CC/BE3//B_REG NO. D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F18 F19 G1 G2 G4 G5 G6 G7 G13 G14 G15 SIGNAL NAME B_CREQ//B_INPACK B_CRST//B_RESET B_CC/BE2//B_A12 B_CCLK//B_A16 B_CAD16//B_A17 B_CAD15//B_IOWR B_CAD12//B_A11 ZV_SDATA ZV_PCLK VCCZ ZV_LRCLK ZV_Y5 ZV_Y1 B_CAD31//B_D10 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG/RI) B_CAD26//B_A0 B_CAD23//B_A3 B_CAD19//B_A25 B_CFRAME//B_A23 B_CTRDY//B_A22 B_CAD13//B_IORD B_CAD11//B_OE B_CAD10//B_CE2 A_CCD1//A_CD1 A_CAD0//A_D3 NC GND VCC ZV_Y2 B_CAD29//B_D1 GND B_CINT//B_READY(IREQ) B_CVS1//B_VS1 VCC B_CAD18//B_A7 VCC B_CAD9//B_A10 B_CC/BE0//B_CE1 B_CAD8//B_D15 VCCB A_CAD4//A_D12 VCC A_CAD3//A_D5 A_CAD1//A_D4 A_CAD2//A_D11 ZV_HREF B_CAD3//B_D5 B_CAD7//B_D7 B_RSVD//B_D14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NO. G16 G18 G19 H1 H2 H4 H5 H6 H14 H15 H16 H18 H19 J1 J2 J4 J5 J6 J14 J15 J16 J18 J19 K1 K2 K4 K5 K6 K14 K15 K16 K18 K19 L1 L2 L4 L5 L6 L14 L15 L16 L18 L19 M1 M2 M4 M5 M6 M14 M15 SIGNAL NAME GND B_CAD5//B_D6 B_CAD6//B_D13 A_CAD5//A_D6 A_RSVD//A_D14 A_CAD7//A_D7 GND A_CAD6//A_D13 B_CCD1//B_CD1 B_CAD4//B_D12 B_CAD1//B_D4 B_CAD2//B_D11 B_CAD0//B_D3 A_CAD8//A_D15 A_CC/BE0//A_CE1 VCCA A_CAD9//A_A10 VCC GNT PCLK CLKRUN PRST GND A_CAD11//A_OE A_CAD13//A_IORD A_CAD12//A_A11 GND A_CAD10//A_CE2 VCCP REQ AD31 AD30 VCC A_CAD14//A_A9 A_CAD16//A_A17 A_CC/BE1//A_A8 A_RSVD//A_A18 A_CAD15//A_IOWR AD29 AD28 AD25 AD27 AD26 A_CPAR//A_A13 A_CBLOCK//A_A19 A_CPERR//A_A14 A_CSTOP//A_A20 VCC AD22 AD24 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 signal names and terminal assignments (continued) Table 2. GJG Terminals Sorted Alphanumerically for CardBus and 16-bit Signals. (Continued) NO. M16 M18 M19 N1 N2 N4 N5 N6 N7 N13 N14 N15 N16 N18 N19 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P19 R1 R2 R4 R5 SIGNAL NAME CBE3 IDSEL AD23 A_CDEVSEL//A_A21 GND A_CCLK//A_A16 A_CTRDY//A_A22 VCCA A_CGNT//A_WE AD1 GND AD19 AD21 VCCP AD20 A_CIRDY//A_A15 A_CFRAME//A_A23 A_CC/BE2//A_A12 VCC A_CAD17//A_A24 A_CAD27//A_D0 VCC VCCI SPKROUT PCREQ/IRQMUX7 RI_OUT/PME AD5 AD8 C/BE2 AD16 AD18 AD17 A_CAD18//A_A7 A_CAD19//A_A25 A_CVS2//A_VS2 A_CSERR//A_WAIT NO. R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U18 U19 V1 V2 SIGNAL NAME A_CSTSCHG//A_BVD1(STSCHG/RI) A_CAD28//A_D8 IRQMUX2 IRQMUX5 PCGNT/IRQMUX6 CLOCK AD0 GND C/BE0 VCC TRDY FRAME IRDY A_CAD20//A_A6 A_CRST//A_RESET A_CAD21//A_A5 A_CINT//A_READY(IREQ) A_CCLKRUN//A_WP(IOIS16) A_RSVD//A_D2 IRQMUX1 IRQMUX3 GPIO0/LEDA1 DATA GPI03/INTA AD4 AD7 AD11 AD15 DEVSEL STOP GND A_CAD22//A_A4 PERR SERR A_CREQ//A_INPACK A_CAD23//A_A3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NO. V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 SIGNAL NAME A_CAD25//A_A1 A_CVS1//A_VS1 A_CAUDIO//A_BVD2(SPKR) GND A_CAD29//A_D1 IRQMUX0 GND GPI01/LEDA2 LATCH VCC AD3 VCCP AD10 AD13 C/BE1 VCCP GPI02/LOCK A_CC/BE3//A_REG A_CAD24//A_A2 A_CAD26//A_A0 VCCA A_CCD2//A_CD2 A_CAD30//A_D9 A_CAD31//A_D10 IRQMUX4 SUSPEND GND IRQSER/INTB AD2 AD6 AD9 AD12 AD14 PAR 7 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 signal names and terminal assignments (continued) Table 3. CardBus Signal Names Sorted Alphanumerically for GFN and GJG Pins SIGNAL NAME A_CAD0 A_CAD1 A_CAD2 A_CAD3 A_CAD4 A_CAD5 A_CAD6 A_CAD7 A_CAD8 A_CAD9 A_CAD10 A_CAD11 A_CAD12 A_CAD13 A_CAD14 A_CAD15 A_CAD16 A_CAD17 A_CAD18 A_CAD19 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD28 A_CAD29 A_CAD30 A_CAD31 A_CAUDIO A_CBLOCK A_CC/BE0 A_CC/BE1 A_CC/BE2 A_CC/BE3 A_CCD1 A_CCD2 8 GFN G2 H3 G1 H1 H2 J3 J4 J1 K3 L1 L2 L3 M1 L4 M3 M2 M4 U2 V1 T4 V2 V3 W2 W3 W4 V4 U5 Y6 V7 W7 Y7 W8 Y5 P1 K1 N1 T3 Y2 G3 W6 GJG F2 G5 G6 G4 G1 H1 H6 H4 J1 J5 K6 K1 K4 K2 L1 L6 L2 P6 R1 R2 T1 T4 U2 V2 W3 V3 W4 P7 R7 V7 W7 W8 V5 M2 J2 L4 P4 W2 F1 W6 SIGNAL NAME A_CCLK A_CCLKRUN A_CDEVSEL A_CFRAME A_CGNT A_CINT A_CIRDY A_CPAR A_CPERR A_CREQ A_CRST A_CSERR A_CSTOP A_CSTSCHG A_CTRDY A_CVS1 A_CVS2 A_RSVD A_RSVD A_RSVD B_CAD00 B_CAD01 B_CAD02 B_CAD03 B_CAD04 B_CAD05 B_CAD06 B_CAD07 B_CAD08 B_CAD09 B_CAD10 B_CAD11 B_CAD12 B_CAD13 B_CAD14 B_CAD15 B_CAD16 B_CAD17 B_CAD18 B_CAD19 POST OFFICE BOX 655303 GFN T1 U7 R2 U1 P3 Y4 T2 N3 P2 Y1 W1 V5 R1 V6 P4 Y3 U3 J2 N2 V8 H19 G20 H18 F20 G19 F19 G18 G17 E19 E18 D19 C20 D18 E17 B20 C19 C18 B15 A15 C14 GJG N4 T6 N1 P2 N7 T5 P1 M1 M4 V1 T2 R5 M5 R6 N5 V4 R4 H2 L5 T7 H19 H16 H18 G13 H15 G18 G19 G14 F18 F15 E19 E18 D19 E16 C19 D18 D16 A14 F13 E13 • DALLAS, TEXAS 75265 SIGNAL NAME B_CAD20 B_CAD21 B_CAD22 B_CAD23 B_CAD24 B_CAD25 B_CAD26 B_CAD27 B_CAD28 B_CAD29 B_CAD30 B_CAD31 B_CAUDIO B_CBLOCK B_CCBE0 B_CCBE1 B_CCBE2 B_CCBE3 B_CCD1 B_CCD2 B_CCLK B_CCLKRUN B_CDEVSEL B_CFRAME B_CGNT B_CINT B_CIRDY B_CPAR B_CPERR B_CREQ B_CRST B_CSERR B_CSTOP B_CSTSCHG B_CTRDY B_CVS1 B_CVS2 B_RSVD B_RSVD B_RSVD GFN A14 B13 A13 C12 A12 B11 C11 D9 A8 B8 C8 B7 D10 B18 D20 B19 D14 B12 H20 C9 A17 B9 A18 C15 D16 A10 A16 A19 B17 D12 C13 B10 C17 A9 C16 A11 B14 A20 A7 E20 GJG A13 A12 B12 E12 A11 B11 E11 D9 E9 F8 B8 E8 D10 A18 F16 C18 D14 D11 H14 B9 D15 A9 B16 E14 A16 F10 B15 B18 A17 D12 D13 A10 B17 E10 E15 F11 B13 B19 D8 G15 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 signal names and terminal assignments (continued) Table 4. 16 Bit Signal Names Sorted Alphanumerically for GFN and GJG Pins SIGNAL NAME A_A00 A_A01 A_A02 A_A03 A_A04 A_A05 A_A06 A_A07 A_A08 A_A09 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_BVD1 A_BVD2 A_CD1 A_CD2 A_CE1 A_CE2 A_D00 A_D01 A_D02 A_D03 A_D04 A_D05 A_D06 A_D07 GFN U5 V4 W4 W3 W2 V3 V2 V1 N1 M3 L1 M1 T3 N3 P2 T2 T1 M4 N2 P1 R1 R2 P4 U1 U2 T4 V6 Y5 G3 W6 K1 L2 Y6 W7 V8 G2 H3 H1 J3 J1 GJG W4 V3 W3 V2 U2 T4 T1 R1 L4 L1 J5 K4 P4 M1 M4 P1 N4 L2 L5 M2 M5 N1 N5 P2 P6 R2 R6 V5 F1 W6 J2 K6 P7 V7 T7 F2 G5 G4 H1 H4 SIGNAL NAME A_D08 A_D09 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_INPACK A_IORD A_IOWR A_OE A_READY A_REG A_RESET A_VS1 A_VS2 A_WAIT A_WE A_WP B_A00 B_A01 B_A02 B_A03 B_A04 B_A05 B_A06 B_A07 B_A08 B_A09 B_A10 B_A11 B_A12 B_A13 B_A14 B_A15 B_A16 B_A17 B_A18 B_A19 POST OFFICE BOX 655303 GFN V7 Y7 W8 G1 H2 J4 J2 K3 Y1 L4 M2 L3 Y4 Y2 W1 Y3 U3 V5 P3 U7 C11 B11 A12 C12 A13 B13 A14 A15 B19 B20 E18 D18 D14 A19 B17 A16 A17 C18 A20 B18 GJG R7 W7 W8 G6 G1 H6 H2 J1 V1 K2 L6 K1 T5 W2 T2 V4 R4 R5 N7 T6 E11 B11 A11 E12 B12 A12 A13 F13 C18 C19 F15 D19 D14 B18 A17 B15 D15 D16 B19 A18 • DALLAS, TEXAS 75265 SIGNAL NAME B_A20 B_A21 B_A22 B_A23 B_A24 B_A25 B_BVD1 B_BVD2 B_CD1 B_CD2 B_CE1 B_CE2 B_D00 B_D01 B_D02 B_D03 B_D04 B_D05 B_D06 B_D07 B_D08 B_D09 B_D10 B_D11 B_D12 B_D13 B_D14 B_D15 B_INPACK B_IORD B_IOWR B_OE B_READY B_REG B_RESET B_VS1 B_VS2 B_WAIT B_WE B_WP GFN C17 A18 C16 C15 B15 C14 A9 D10 H20 C9 D20 D19 D9 B8 A7 H19 G20 F20 F19 G17 A8 C8 B7 H18 G19 G18 E20 E19 D12 E17 C19 C20 A10 B12 C13 A11 B14 B10 D16 B9 GJG B17 B16 E15 E14 A14 E13 E10 D10 H14 B9 F16 E19 D9 F8 D8 H19 H16 G13 G18 G14 E9 B8 E8 H18 H15 G19 G15 F18 D12 E16 D18 E18 F10 D11 D13 F11 B13 A10 A16 A9 9 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Table 5. Power Supply TERMINAL FUNCTION NAME GFN NO. GJG NO. GND A1, D4, D8, D13, D17, H4, H17, N4, N17, U4, U8, U13, U17 B14, D4, D7, F5, F9, G16, H5, J19, K5, N2, N14, R13, U1, V6, V9, W11 Device ground terminals VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 A8, F6, F12, F14, G2, J6, K19, M6, P5, P8, R15, V12 Power supply terminal for core logic (3.3 V) VCCA K2, R3, W5 J4, N6, W5 Clamping voltage for PC Card A interface. VCCB B16, C10, F18, A15, B10, F19 Clamping voltage for PC Card B interface. Clamping voltage for interrupt subsystem interface and miscellaneous I/O. Indicates signaling level of the following inputs and shared outputs: IRQSER, PCGNT, PCREQ, SUSPEND, SPKROUT, GPIO1:0, IRQMUX7–IRQMUX0, INTA, INTB, CLOCK, DATA, LATCH, and RI_OUT. VCCI V10 P9 VCCP K20, P18, V15, W20 K14, N18, V14, V18 VCCZ A4, D1 D6, E4 Clamping voltage for PCI signaling (3.3 V or 5 V) Clamping voltage for zoomed video interface (3.3 V or 5 V) Table 6. PC Card Power Switch TERMINAL NAME 10 GFN NO. GJG NO. I/O TYPE FUNCTION CLOCK U12 R11 I/O 3-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1251B output by using the P2CCLK bit in the system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines this terminal as an output, then CLOCK requires an external pulldown resistor. The frequency of the PCI1251B output CLOCK is derived by dividing the PCI CLK by 36. DATA V12 T11 O 3-line power switch data. DATA is used to serially communicate socket power control information to the power switch. LATCH W12 V11 O 3-line power switch latch. LATCH is asserted by the PCI1251B to indicate to the PC Card power switch that the data on the DATA line is valid. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 7. PCI System TERMINAL NAME GFN NO. GJG NO. I/O TYPE FUNCTION CLKRUN J18 J16 I/O PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI1251B responds accordingly. If CLKRUN is not implemented, then this pin should be tied low. CLKRUN is enabled by default by bit 1 (KEEPCLK) in the system control register. PCLK J17 J15 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. I PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1251B to place all output buffers in a high-impedance state and reset all internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1251B is in its default state. When the SUSPEND mode is enabled, the device is protected from the PRST, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PRST J19 J18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 8. PCI Address and Data TERMINAL NAME GFN NO. GJG NO. AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 K18 K19 L20 L18 L19 M20 M19 M18 N19 N18 P20 P19 R20 R19 P17 R18 V18 Y19 W18 V17 U16 Y18 W17 V16 W16 U14 Y16 W15 V14 Y15 W14 Y14 K16 K18 L14 L15 L18 L19 L16 M15 M19 M14 N16 N19 N15 P18 P19 P16 T16 W17 V16 W16 T15 V15 W15 P14 T14 W14 P13 T13 V13 W13 N13 R12 C/BE3 C/BE2 C/BE1 C/BE0 M17 T20 W19 Y17 M16 P15 V17 R14 PAR 12 Y20 W18 I/O TYPE FUNCTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1251B calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1251B outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 9. PCI Interface Control TERMINAL NAME GFN NO. GJG NO. I/O TYPE FUNCTION DEVSEL V20 T18 I/O PCI device select. The PCI1251B asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1251B monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the PCI1251B terminates the cycle with an initiator abort. FRAME T19 R18 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. GNT J20 J14 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1251B access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. GPIO2/LOCK V19 V19 I/O PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI LOCK and used to gain exclusive access downstream. Since this functionality is not typically used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK defaults to a general-purpose input and can be configured through the GPIO2 control register. IDSEL N20 M18 I Initialization device select. IDSEL selects the PCI1251B during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. IRDY T18 R19 I/O PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR U18 U18 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register. REQ K17 K15 O PCI bus request. REQ is asserted by the PCI1251B to request access to the PCI bus as an initiator. SERR U19 U19 O PCI system error. SERR is an output that is pulsed from the PCI1251B when enabled through the command register, indicating a system error has occurred. The PCI1251B need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the bridge control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP T17 T19 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. TRDY U20 R16 I/O PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 10. System Interrupt TERMINAL NAME GFN NO. GPIO3/INTA V13 GJG NO. T12 IRQSER/INTB W13 W12 IRQMUX7 IRQMUX6 IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0 Y12 U11 W10 Y9 W9 V9 U9 Y8 P11 R10 R9 W9 T9 R8 T8 V8 I/O TYPE FUNCTION I/O Parallel PCI interrupt. INTA can be optionally mapped to GPI03 when parallel PCI interrupts are used. See programmable interrupt subsystem on page 32 for details on interrupt signaling. GPIO3/INTA defaults to a general-purpose input. I/O Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream. See programmable interrupt subsystem on page 32 for details on interrupt signaling. This terminal can be used to signal PCI INTB when one of the parallel interrupt modes is selected in the device control register. Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide the ISA-type IRQ signaling supported by the PCI1251B. These interrupt multiplexer outputs can be mapped to any of 15 IRQs. The device control register must be programmed for the ISA IRQ interrupt mode and the IRQMUX routing register must have the IRQ routing programmed before these terminals are enabled. O All of these terminals have secondary functions, such as PCI INTB, PC/PCI DMA request/grant, ring indicate output, and zoomed video status, that can be selected with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for IRQ routing. See the IRQMUX routing register for programming options. RI_OUT/PME Y13 P12 O Ring indicate out and power management event output. Terminal provides an output for ring-indicate or PME signals. Table 11. PC/PCI DMA TERMINAL NAME GFN NO. GJG NO. I/O TYPE FUNCTION PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme. PCGNT/ IRQMUX6 U11 R10 I/O Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over PCGNT, and should not be enabled in a system using PC/PCI DMA. This terminal is also used for the serial EEPROM interface. PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the PC/PCI DMA scheme. PCREQ/ IRQMUX7 Y12 P11 O Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over PCREQ, and should not be enabled in a system using PC/PCI DMA. This terminal is also used for the serial EEPROM interface. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 12. Zoomed Video TERMINAL GJG NO. I/O AND MEMORY INTERFACE SIGNAL I/O TYPE A6 G7 A10 O Horizontal sync to the zoomed video port ZV_VSYNC C7 A7 A11 O Vertical sync to the zoomed video port ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0 A3 B4 C5 B5 C6 D7 A5 B6 B5 A5 E6 B6 A6 F7 E7 B7 A20 A14 A19 A13 A18 A8 A17 A9 O Video data to the zoomed video port in YV:4:2:2 format ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1 ZV_UV0 D2 C3 B1 B2 A2 C4 B3 D5 C1 A2 B2 A3 B3 A4 B4 D5 A25 A12 A24 A15 A23 A16 A22 A21 O Video data to the zoomed video port in YV:4:2:2 format NAME GFN NO. ZV_HREF FUNCTION ZV_SCLK C2 B1 A7 O Audio SCLK PCM ZV_MCLK D3 C2 A6 O Audio MCLK PCM ZV_PCLK E1 E2 IOIS16 O Pixel clock to the zoomed video port ZV_LRCLK E3 E5 INPACK O Audio LRCLK PCM ZV_SDATA E2 E1 SPKR O Audio SDATA PCM NC F1 F4 O Reserved. No connection. ZV_RSVD1 ZV_RSVD0 C1 E4 D2 D1 O Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0 are put into the high-impedance state by host adapter. A5 A4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 13. Miscellaneous TERMINAL NAME GPIO0/LEDA1 GFN NO. V11 GJG NO. T10 I/O TYPE FUNCTION I/O GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose input and output, GPIO0. The zoomed video enable signal (ZV_STAT) can also be routed to this signal through the GPIO0 control register. GPIO0/LEDA1 defaults to a general-purpose input. GPIO1/LEDA2 W11 V10 I/O GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be used for power switch overcurrent (OC) sensing. See GPIO1 control register for programming details. GPIO1/LEDA2 defaults to a general-purpose input. SPKROUT Y10 P10 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1251B from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR//CAUDIO inputs. SUSPEND Y11 W10 I Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See suspend mode for details. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 14. 16-bit PC Card Address and Data (slots A and B) TERMINAL GFN NO. GJG NO. I/O TYPE FUNCTION NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 T4 U2 U1 P4 R2 R1 P1 N2 M4 T1 T2 P2 N3 T3 M1 L1 M3 N1 V1 V2 V3 W2 W3 W4 V4 U5 C14 B15 C15 C16 A18 C17 B18 A20 C18 A17 A16 B17 A19 D14 D18 E18 B20 B19 A15 A14 B13 A13 C12 A12 B11 C11 R2 P6 P2 N5 N1 M5 M2 L5 L2 N4 P1 M4 M1 P4 K4 J5 L1 L4 R1 T1 T4 U2 V2 W3 V3 W4 E13 A14 E14 E15 B16 B17 A18 B19 D16 D15 B15 A17 B18 D14 D19 F15 C19 C18 F13 A13 A12 B12 E12 A11 B11 E11 O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 K3 J2 J4 H2 G1 W8 Y7 V7 J1 J3 H1 H3 G2 V8 W7 Y6 E19 E20 G18 G19 H18 B7 C8 A8 G17 F19 F20 G20 H19 A7 B8 D9 J1 H2 H6 G1 G6 W8 W7 R7 H4 H1 G4 G5 F2 T7 V7 P7 F18 G15 G19 H15 H18 E8 B8 E9 G14 G18 G13 H16 H19 D8 F8 D9 I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. † Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 15. 16-bit PC Card Interface Control (slots A and B) TERMINAL GFN NO. NAME BVD1 (STSCHG/RI) SLOT A† V6 SLOT B‡ A9 GJG NO. SLOT A† R6 SLOT B‡ E10 I/O TYPE FUNCTION I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 85 for enable bits. See ExCA card status-change register on page 84 and the ExCA interface status register on page 81 for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR) Y5 D10 V5 D10 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 85 for enable bits. See ExCA card status-change register on page 84 and the ExCA interface status register on page 81 for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1251B and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 G3 W6 H20 C9 F1 W6 H14 B9 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see ExCA interface status register on page 81. CE1 CE2 K1 L2 D20 D19 J2 K6 F16 E19 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, then the PC Card asserts this signal to indicate a request for a DMA operation. O I/O read. IORD is asserted by the PCI1251B to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1251B asserts IORD during DMA transfers from the PC Card to host memory. INPACK IORD Y1 L4 D12 E17 V1 K2 D12 E16 I/O write. IOWR is driven low by the PCI1251B to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. IOWR 18 M2 C19 L6 D18 O DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1251B asserts IOWR during transfers from host memory to the PC Card. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 15. 16-bit PC Card Interface Control (slots A and B) (continued) TERMINAL GFN NO. NAME SLOT A† SLOT B‡ GJG NO. SLOT A† SLOT B‡ I/O TYPE FUNCTION Output enable. OE is driven low by the PCI1251B to enable 16-bit memory PC Card data output during host memory read cycles. OE READY (IREQ) L3 Y4 C20 A10 K1 T5 E18 F10 O I DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1251B asserts OE to indicate TC for a DMA write operation. Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG Y2 B12 W2 D11 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1251B asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET W1 C13 T2 D13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT V5 B10 R5 A10 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE P3 D16 N7 A16 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1251B asserts WE to indicate TC for a DMA read operation. Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. WP (IOIS16) U7 B9 T6 A9 I I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. VS1 VS2 Y3 U3 A11 B14 V4 R4 F11 B13 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card. † Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 16. CardBus PC Card Interface System (slots A and B) TERMINAL GFN NO. NAME CCLK CCLKRUN CRST SLOT A† T1 U7 W1 SLOT B‡ A17 B9 C13 GJG NO. SLOT A† N4 T6 T2 SLOT B‡ D15 A9 D13 I/O TYPE FUNCTION O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD1, CCD2, and CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1251B to indicate that the CCLK frequency is decreased. CardBus clock run (CCLKRUN) follows the PCI clock run (CLKRUN) I/O CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be placed in a high impedance state, and the PCI1251B drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. † Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 17. CardBus PC Card Address and Data (slots A and B) TERMINAL GFN NO. GJG NO. NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 W8 Y7 W7 V7 Y6 U5 V4 W4 W3 W2 V3 V2 T4 V1 U2 M4 M2 M3 L4 M1 L3 L2 L1 K3 J1 J4 J3 H2 H1 G1 H3 G2 B7 C8 B8 A8 D9 C11 B11 A12 C12 A13 B13 A14 C14 A15 B15 C18 C19 B20 E17 D18 C20 D19 E18 E19 G17 G18 F19 G19 F20 H18 G20 H19 W8 W7 V7 R7 P7 W4 V3 W3 V2 U2 T4 T1 R2 R1 P6 L2 L6 L1 K2 K4 K1 K6 J5 J1 H4 H6 H1 G1 G4 G6 G5 F2 E8 B8 F8 E9 D9 E11 B11 A11 E12 B12 A12 A13 E13 F13 A14 D16 D18 C19 E16 D19 E18 E19 F15 F18 G14 G19 G18 H15 G13 H18 H16 H19 CC/BE3 CC/BE2 CC/BE1 CC/BE0 CPAR Y2 T3 N1 K1 N3 B12 D14 B19 D20 A19 W2 P4 L4 J2 M1 D11 D14 C18 F16 B18 I/O TYPE FUNCTION I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit. I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3 applies to byte 3 (CAD31–CAD24). I/O CardBus parity. In all CardBus read and write cycles, the PCI1251B calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1251B outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, when the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion. † Terminal name for slot A is preceded with A_. For example, the full name for terminal N3 is A_CPAR. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_CPAR. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Terminal Functions (Continued) Table 18. CardBus PC Card Interface Control (slots A and B) TERMINAL GFN NO. I/O TYPE FUNCTION D10 I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1251B supports the binary audio mode and outputs a binary signal from the card to SPKROUT. M2 A18 I/O F1 W6 H14 B9 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. GJG NO. NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ CAUDIO Y5 D10 V5 CBLOCK P1 B18 CCD1 CCD2 G3 W6 H20 C9 CardBus lock. CBLOCK is used to gain exclusive access to a target. CDEVSEL R2 A18 N1 B16 I/O CardBus device select. The PCI1251B asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1251B monitors CDEVSEL until a target responds. If no target responds before timeout occurs, then the PCI1251B terminates the cycle with an initiator abort. CFRAME U1 C15 P2 E14 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT P3 D16 N7 A16 I CardBus bus grant. CGNT is driven by the PCI1251B to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT Y4 A10 T5 F10 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. CIRDY T2 A16 P1 B15 I/O CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR P2 B17 M4 A17 I/O CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CREQ Y1 D12 V1 D12 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CSERR V5 B10 R5 A10 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1251B can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP R1 C17 M5 B17 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG V6 A9 R6 E10 I CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status and is used as a wake-up mechanism. CTRDY P4 C16 N5 E15 I/O CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 CVS2 Y3 U3 A11 B14 V4 R4 F11 B13 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. † Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 power supply sequencing The PCI1251B contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamping voltage. The core power supply is always 3.3 V. The clamping voltage can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended. The power-up sequence is: 1. Apply 3.3-V power to the core. 2. Assert PRST to the device to disable the outputs during power up. Output drivers must be powered up in the high-impedance state to prevent high current levels through the clamping diodes to the 5-V supply. 3. Apply the clamping voltage. The power-down sequence is: 1. Use PRST to switch outputs to a high-impedance state. 2. Remove the clamping voltage. 3. Remove the 3.3-V power from the core. I/O characteristics Figure 1 shows a 3-state bidirectional buffer. The recommended operating conditions table, on page 115, provides the electrical characteristics of the inputs and outputs. The PCI1251B meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Rev. 2.2. VCCP Tied for Open Drain OE Pad Figure 1. 3-State Bidirectional Buffer NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating. clamping voltages The clamping voltages are set to match whatever external environment the PCI1251B will be working with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1251B must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply. The PCI1251B requires five separate clamping voltages because it supports a wide range of features. The five voltages are listed and defined in the recommended operating conditions table, on page 115. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PCI interface This section describes the PCI interface of the PCI1251B and how the device responds and participates in PCI bus cycles. The PCI1251B provides all required signals for PCI master/slave devices. The PCI1251B can operate in either 5-V or 3.3-V PCI signaling environments by connecting the VCCP terminals to the desired signaling level. PCI bus lock (LOCK) The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1251B as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with the bus clock, the CardBus signal for this protocol is CBLOCK. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. loading the subsystem identification (EEPROM interface) The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC ’95 requirement. The PCI1251B offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by clearing the SUBSYSRW bit in the system control register (bit 5, offset 80h). Once this bit is cleared (0), the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial EEPROM. In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier through a serial EEPROM interface. The PCI1251B loads the doubleword of data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the PCI reset from the entire PCI1251B core, including the serial EEPROM state machine (see suspend mode, on page 37, for details on using SUSPEND). The PCI1251B provides a two-line serial bus interface to a serial EEPROM. The system designer must implement a pulldown resistor on the PCI1251B LATCH terminal to indicate the serial EEPROM mode. Only when this pulldown resistor is present will the PCI1251B attempt to load data through the serial EEPROM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL). SDA is mapped to the PCI1251B IRQMUX6 terminal and SCL is mapped to the PCI1251B IRQMUX7 terminal. Figure 2 shows a typical PCI1251B application using the serial EEPROM interface. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 loading the subsystem identification (EEPROM interface) (continued) VCC Serial EEPROM PCI1251B LATCH A0 A1 A2 SCL IRQMUX7 SDA IRQMUX6 Figure 2. Serial EEPROM Application When the PCI1251B is reset, the subsystem data is read automatically from the EEPROM. The PCI1251B masters the serial EEPROM bus and reads four bytes, as shown in Figure 3. The EEPROM is addressed at word address 00h, as shown in Figure 3, and the address automatically increments after each byte transfer according to the protocol. Thus, to provide the subsystem register with data AABBCCDDh, the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 M A = Slave acknowledgement S b6 b5 b4 b3 b2 b1 b0 Restart R/W Data Byte 0 A Data Byte 1 M Data Byte 2 M Data Byte 3 M = Master acknowledgement 1 A R/W M P S/P = Start/stop condition Figure 3. EEPROM Interface Subsystem Data Collection The serial EEPROM is addressed at slave address 1010000b by the PCI1251B. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 2) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. The serial EEPROM interface signals require pullup resistors, and the protocol is defined for the bidirectional transfers. Both SCL and SDA are placed in a high-impedance state and pulled high when the bus is not active. A high-to-low transition of the SDA line defines the start condition (S). A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as a control signal. Data is valid and stable during the clock high period. Figure 4 illustrates this protocol. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 loading the subsystem identification (EEPROM interface) (continued) SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 4. Serial EEPROM Start/Stop Conditions and Bit Transfers Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 3. When the PCI1251B transmits the addresses, it returns SDA to the high state and places the line in a high-impedance state. The PCI1251B then generates an SCL clock cycle and expects the EEPROM to pull down SDA during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI1251B transmitter and EEPROM receiver. Figure 5 illustrates the general acknowledges. During the data byte transfers from the serial EEPROM to the PCI1251B, the EEPROM clocks the SCL signal. After the EEPROM transmits the data to the PCI1251B, it returns the SDA signal to the high state and places the line in a high-impedance state. The EEPROM then generates an SCL clock cycle and expects the PCI1251B to pull down SDA during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter and PCI1251B receiver. Figure 5 illustrates the general acknowledges. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 5. Serial EEPROM Protocol – Acknowledge EEPROM interface status information is communicated through the general status register located at PCI offset 85h. The EEDETECT bit in this register indicates whether or not the PCI1251B serial EEPROM circuitry detects the pulldown resistor on LATCH. An error condition, such as a missing acknowledge, results in the DATAERR bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is busy). 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PC Card applications This section describes the following PC Card interfaces: PC Card recognition (which details the card interrogation procedure), card-powering procedure (including the protocol of the P2C power switch interface), internal zoomed video (ZV) buffering provided by the PCI1251B and programming model, standard PC Card register models, and a brief discussion of the PC Card software protocol layers. PC Card insertion/removal and recognition The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). A PC Card designer connects these four terminals in prescribed configuration determined by the type of card and the supply voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 19. Table 19. PC Card Card-Detect and Voltage-Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE Ground Ground Ground Ground Ground VOLTAGE Open Open 5V 16-bit PC Card 5V Open Ground 5V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground 5V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V Y.Y V Ground Ground Ground Open LV 16-bit PC Card Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V LV CardBus PC Card Y.Y V Connect to CVS1 Ground Open Connect to CCD2 Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved P2C power switch interface (TPS2206) A power switch with a PCMCIA-to-peripheral control (P2C) interface is required for the PC Card powering interface. The TI TPS2206 dual-slot PC Card power interface switch provides the P2C interface to the CLOCK, DATA, and LATCH terminals of the PCI1251B. Figure 6 shows the terminal assignments of the TPS2206. Figure 7 illustrates a typical application where the PCI1251B represents the PCMCIA controller. The CLOCK terminal on the PCI1251B can be an input or an output depending on whether bit 27 of the system control register is a 0 or a 1. The default is for the CLOCK terminal to be an input to control the serial interface and the PCI1251B internal state machine. The P2CCLK bit in the system control register can be set by the system BIOS to enable the PCI1251B to internally generate and drive the CLOCK from the PCI clock. When the system design implements CLOCK as an output from the PCI1251B, an external pulldown resistor is required since the CLOCK terminal defaults to an input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 P2C power switch interface (TPS2206) (continued) 5V 5V DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V NC – No internal connection Figure 6. TPS2206 Terminal Assignments Power Supply 12V 5V 3.3V 12 V 5V 3.3 V RESET RESET Supervisor 3 PCMCIA Controller TPS2206 Serial Interface OC AVPP AVCC AVCC VPP1 VPP2 VCC VCC PC Card A VPP1 VPP2 VCC VCC PC Card B AVCC BVPP BVCC BVCC BVCC Figure 7. TPS2206 Typical Application 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 zoomed video support The ZV port on the PCI1251B provides an internally buffered 16-bit ZV PC Card data path. This internal routing is programmed through the multimedia control register. Figure 8 shows the zoomed video subsystem implemented in the PCI1251B and details the bit functions found in the multimedia control register. An output port (PORTSEL) is always selected. The PCI1251B defaults to socket 0 (see the multimedia control register on page 58). When ZVOUTEN is asserted, the zoomed video output terminals are enabled to allow the PCI1251B to route the zoomed video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the multimedia control register. When the PORTSEL maps to a card port that is disabled (ZVEN0 or ZVEN1), then the zoomed video port is driven low; that is, no data is transmitted. Zoomed Video Subsystem Card Output Enable Logic ZVEN0 ZVOUTEN PC Card Socket 0 PC Card Interface ZVSTAT (see Note A) VGA PORTSEL PC Card Interface PC Card Socket 1 Card Output Enable Logic Zoomed Video Port ZVEN1 NOTES: A. ZVSTAT must be enabled through the GPIO control register. Figure 8. Zoomed Video Subsystem POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 SPKROUT usage SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR. This terminal, also used in CardBus applications, is referred to as CAUDIO. SPKR passes a TTL-level digital audio signal to the PCI1251B. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card sockets are XORed in the PCI1251B to produce SPKROUT. Figure 9 shows the SPKROUT connection. Bit 1, Card Control Register (offset 91h) Card A SPKROUT Enable Card A SPKR SPKROUT Bit 1, Card Control Register (offset 91h) Card B SPKROUT Enable Speaker Driver Card B SPKR Card A SPKROUT Enable Card B SPKROUT Enable Figure 9. SPKROUT Connection to Speaker Driver The SPKROUT signal is typically driven only by modem PC Cards. To verify SPKROUT on the PCI1251B, a sample circuit was constructed, and this simplified schematic is shown in Figure 10. NOTE: Earlier versions of the PC Card controller multiplexed SUSPEND/SPKROUT on the same pin, which meant that a pullup resistor was needed to differentiate the signals. Because the PCI1251B does not multiplex this or any other function on SPKROUT, this terminal does not require a pullup resistor. VCC VCC SPKROUT 3 7 2 6 + – 1 8 4 LM386 Figure 10. Simplified Test Schematic 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Speaker PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 LED socket activity indicators Socket activity LEDs indicate when a PC Card is being accessed. The LED signals are multiplexed with general-purpose inputs and outputs (GPIOs); the default for these terminals is GPI. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity. The active-high LED signal is driven for 64-ms periods. When the LED is not being driven high, then it is driven to a low state. Either of the two circuits shown in Figure 11 can be implemented to provide LED signaling, and the board designer can implement the circuit that best fits the application. As indicated, the LED signals are driven for 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when either SUSPEND is asserted or when the PCI clock is stopped per the CLKRUN protocol. If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven. Current Limiting R ≈ 500 Ω PCI1251B LED ApplicationSpecific Delay Current Limiting R ≈ 500 Ω PCI1251B LED Figure 11. Two Sample LED Circuits PC Card16 DMA support The PCI1251B supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. Table 20 provides the DDMA register configuration. Table 20. Distributed DMA Registers TYPE R W R W DMA BASE ADDRESS OFFSET REGISTER NAME Reserved Page Reserved Reserved R N/A W Mode R Multichannel W Mask Reserved Reserved POST OFFICE BOX 655303 Current address 00h Base address Current count 04h Base count N/A Status Request Command N/A Master clear • DALLAS, TEXAS 75265 Reserved 08h 0Ch 31 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 CardBus socket registers The PCI1251B has socket registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. Table 21 lists these CardBus socket registers. Table 21. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h programmable interrupt subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1251B. The PCI1251B provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1251B is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI1251B detects PC Card interrupts and events at the PC Card interface and notifies the host controller via one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1251B, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts. The method by which any type of PCI1251B interrupt is communicated to the host interrupt controller varies from system to system. The PCI1251B offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. Traditional ISA IRQ signaling is provided through eight IRQMUX terminals. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. PC Card functional and CSC interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change-type interrupts are defined as events at the PC Card interface that are detected by the PCI1251B and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 22 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are 16-bit memory card, 16-bit I/O card, and CardBus cards. The functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PC Card functional and CSC interrupts (continued) Table 22. PC Card Interrupt Events and Description CARD TYPE 16-bit memory 16-bit I/O CardBus All PC Cards EVENT TYPE SIGNAL DESCRIPTION BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the PC Card battery conditions. BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the PC Card battery conditions. Batteryy conditions (BVD1, BVD2) CSC Wait states (READY) CSC READY(IREQ)//CINT A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data. Change in card status (STSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of STSCHG indicates a status change on the PC Card. Interrupt request (IREQ) Functional READY(IREQ)//CINT The assertion of IREQ indicates an interrupt request from the PC Card. Change in card status (CSTSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of CSTSCHG indicates a status change on the PC Card. Interrupt request (CINT) Functional READY(IREQ)//CINT The assertion of CINT indicates an interrupt request from the PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. Card insertion or removal CSC CD1//CCD1, CD2//CCD2 A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit CardBus PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. The naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1251B when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1251B interrupt scheme can be used to notify the host system (see Table 23), denoted by the power cycle complete event. This interrupt source is considered a PCI1251B internal event, because it depends on the completion of applying power to the socket. interrupt masks and flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 23 by setting the appropriate bits in the PCI1251B. By individually masking the interrupt sources listed, software can control those events that cause a PCI1251B interrupt. Host software has some control over the system interrupt the PCI1251B asserts by programming the appropriate routing registers. The PCI1251B allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing is somewhat specific to the interrupt signaling method used, and is discussed in more detail in the following sections. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 interrupt masks and flags (continued) When an interrupt is signaled by the PCI1251B, the interrupt service routine must determine which of the events in Table 23 caused the interrupt. Internal registers in the PCI1251B provide flags that report which interrupt source was the cause of the interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 23 details the registers and bits associated with masking and reporting potential interrupts. All interrupts, except the functional PC Card interrupts, can be masked. An interrupt status flag is available for all types of interrupts. Table 23. Interrupt Mask and Flag Registers CARD TYPE 16-bit memory 16 bit I/O 16-bit All 16-bit PC Cards CardBus EVENT MASK FLAG Battery conditions (BVD1, BVD2) ExCA offset 05h/45h/805h bits 1 and 0 ExCA offset 04h/44h/804h bits 1 and 0 Wait states (READY) ExCA offset 05h/45h/805h bit 2 ExCA offset 04h/44h/804h bit 2 Change in card status (STSCHG) ExCA offset 05h/45h/805h bit 0 ExCA offset 04h/44h/804h bit 0 Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0 Power cycle complete ExCA offset 05h/45h/805h bit 3 ExCA offset 04h/44h/804h bit 3 Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0 Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0 Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1 Notice that there is not a mask bit to stop the PCI1251B from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. Various methods of clearing the interrupt flag bits are listed in Table 23. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared by two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning. legacy interrupt multiplexer The IRQ multiplexer implemented in the PCI1251B provides a mechanism to route the IRQMUX signals to any of the 15 legacy IRQ signals. IRQMUX7–IRQMUX6 share the PC/PCI DMA terminals and take precedence when routed. The other six IRQMUX signals (IRQMUX5–IRQMUX0) are available in all platforms. To use the IRQMUX interrupt signaling, software must program the device control register (PCI offset 92h) to select the legacy IRQ signaling scheme. The IRQMUX functionality describing PCREQ/IRQMUX7 is shown in Figure 12. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 legacy interrupt multiplexer (continued) System Control Register (Bit 3): When bit 3 = 0 EEPROM SCL is routed on IRQMUX7 When bit 3 = 1 PCREQ is routed on IRQMUX7 EEPROM SCL 0 0000 0001 PCREQ 1 0010 PCREQ/IRQMUX7/SCL 1111 IRQMUX Routing Register Figure 12. Interrupt Mux Functionality – Example of IRQMUX7 Routing If parallel ISA IRQs are selected in the device control register, then the IRQMUX routing register (PCI offset 8Ch) must be programmed with the associated ISA IRQ connections. The PCI1251B supports up to eight parallel ISA IRQ signal connections (IRQMUX7–IRQMUX0). Figure 13 is an example of PCI1251B IRQ implementation that provides eight ISA interrupts. The system In this example cannot support PC/PCI DMA because all eight ISA IRQs are used. In this example, IRQMUX7 and IRQMUX6 are used to signal ISA IRQs and are not available for PC/PCI DMA. For systems not using all eight IRQs, PC/PCI DMA can be implemented and can coexist with ISA IRQs by using IRQMUX6 and IRQMUX7 for PC/PCI DMA; that is, legacy IRQs and PC/PCI DMA implementation are not mutually exclusive. However, if the IRQMUX registers are programmed to use IRQMUX7–IRQMUX6, then they override PC/PCI DMA. PCI1251B IRQMUX0 IRQ3 PCI IRQMUX1 IRQ4 IRQMUX2 IRQ5 IRQMUX3 IRQ9 IRQMUX4 IRQ10 IRQMUX5 IRQ11 IRQMUX6 IRQMUX7 IRQ12 IRQ15 Figure 13. IRQ Implementation Software is responsible for programming the IRQMUX routing register to reflect the IRQ configuration shown in Figure 13. In this example, programming is accomplished by writing a doubleword of data (FCBA9543h) to the PCI1251B IRQMUX routing register, PCI offset 8Ch. In this example (FCBA9543h), F corresponds to IRQ15, C to IRQ12, B to IRQ11, A to IRQ10, 9 to IRQ9, 5 to IRQ5, 4 to IRQ4, and 3 to IRQ3. The IRQMUX routing register is shared between the two PCI1251B functions, and only one write to function 0 or function 1 is necessary to configure the IRQMUX signals. using parallel PCI interrupts Parallel PCI interrupts are available when in: parallel PCI interrupt mode, IRQMUX signaling mode, or when IRQs are serialized with the IRQSER protocol. The PCI interrupt signaling is dependent on the interrupt mode. The interrupt mode is selected via the device control register (92h). The IRQSER/INTB pin signals INTB when one of the parallel interrupt modes is selected via bits 2–1 in the device control register (92h). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 using parallel PCI interrupts (continued) PCI INTB is also available on the IRQMUX0 terminal by programming bits 3–0 to 0001b. See the IRQMUX routing register (8Ch). PCI INTA is available on the GPIO3 terminal by programming bits 7–6 in the GPIO3 control register (8Bh) to 00b. The value read from the interrupt pin register is card slot dependent. The value read also depends on the interrupt INTRTIE bit in the system control register and the signaling mode selected through the device control register. When the INTRTIE bit is set, this register reads 0x01 (INTA) for both functions. The PCI1251B defaults to signaling PCI and IRQ interrupts through IRQSER serial interrupt terminal. Refer to Table 24 for a complete description of the register contents. Table 24. Interrupt Pin Register Cross Reference INTRTIE BIT INTPIN FUNCTION 0 INTPIN FUNCTION 1 Parallel PCI interrupts only 0 0x01 (INTA) 0x02 (INTB) Parallel IRQ and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ serialized (IRQSER) and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ and PCI serialized (IRQSER) interrupts (default) 0 0x01 (INTA) 0x02 (INTB) Parallel PCI interrupts only 1 0x01 (INTA) 0x01 (INTA) Parallel IRQ and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ and PCI serialized (IRQSER) interrupts (default) 1 0x01 (INTA) 0x01 (INTA) INTERRUPT SIGNALING MODE power management overview In addition to the low-power CMOS technology process used for the PCI1251B, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section. PCI CLKRUN protocol The PCI CLKRUN feature is the primary method of power management on the PCI bus side of the PCI1251B. Since some chipsets do not implement CLKRUN, this is not always available to the system designer, and alternate power savings features are provided. If CLKRUN is not implemented, then the CLKRUN terminal should be tied low. CLKRUN is enabled by default using bit 1 (KEEPCLK) in the system control register (80h). CardBus PC Card power management The PCI1251B implements its own card power management engine that can be used to turn off the CCLK at a socket when there is no activity to the CardBus PC Card. The CCLK can also be configured as divide by 16 instead of stopped. The clock run protocol is followed on the CardBus interface to control this clock management. PCI power management (PCIPM) The PCI power management (PCIPM) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power management states that result in varying levels of power savings. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PCI power management (PCIPM) (continued) The four power management states of PCI functions are: D D D D0 – Fully-on state D1 and D2 – Intermediate states D3 – Off state Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the originating bridge device. For the operating system-driven power management, the PCI function should support four power management operations. The operations are: capabilities reporting, power status reporting, setting the power state, and system wake up. The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1 in the PCI status register, offset 06h, bit 4. The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1251B, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer are specific to the function’s capability. The PCIPM capability implements the register block outlined in Table 25. Table 25. Power Management Registers REGISTER NAME Power management capabilities Data PMCSR bridge support extensions OFFSET Next item pointer Capability ID 0 Power management control status (CSR) 4 The PMC register is a static read-only register that provides information on the capabilities of the function related to power management. The PMCSR register enables control of power management states and enables monitors power management events. The data register is an optional register that provides state-dependent power measurements, such as power consumption or heat dissipation. suspend mode The SUSPEND signal, provided for backward compatibility, gates the PCI reset (PRST) signal from the PCI1251B. However, additional functionality has been defined for SUSPEND to provide additional power management options. SUSPEND provides a mechanism to gate the PCLK from the PCI1251B, as well as gate PRST. This can potentially save power while in an idle state; however, it requires substantial design effort to implement. Some issues to consider are: D D D What if cards are present in the sockets? What if the cards in the sockets are powered? How to pass CSC (insertion/removal) events? Even without the PCI clock to the PCI1251B core, there are asynchronous-type functions (such as RI_OUT) that can pass CSC events, wake-up events, etc., back to the system. If a system designer chooses to not pass card removal events through to the system, then the PCI1251B would not be able to power down the empty socket without the power switch clock (CLOCK) generated externally. Refer to the P 2C power switch interface on page 27 for details. Figure 14 is a functional implementation diagram. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 suspend mode (continued) RST RSTIN SUSPEND PCI1251B Core SUSPENDIN GNT PCLKIN PCLK EXTERNAL SIGNALS INTERNAL SIGNALS Figure 14. SUSPEND Functional Implementation Figure 15 is a signal diagram of the suspend function. RST GNT SUSPEND PCLK External Terminals Internal Signals RSTIN SUSPENDIN PCLKIN Figure 15. Signal Diagram of Suspend Function requirements for suspend mode The PCI bus must not be parked on the PCI1251B when SUSPEND is asserted. The PCI1251B responds to SUSPEND being asserted by placing the REQ pin in a high impedance state and gates the internal clock and reset. The GPIOs, IRQMUX signals, and RI_OUT signals are active during SUSPEND unless they are disabled in the appropriate PCI1251B registers. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ring indicate The RI_OUT output is an important feature in power management and is basically used so that a system can go into a suspended mode and wake up on modem rings and other card events. RI_OUT on the PCI1251B can be asserted under any of the following conditions: D D D A 16-bit PC Card modem in a powered socket asserts RI to indicate an incoming call to the system. A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up. A CSC event, such as insertion/removal of cards, battery voltage levels, occurs. CSTSCHG from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT events are enabled separately. Figure 15 shows various enable bits for the PCI1251B RI_OUT function; however, it does not show the masking of CSC events (see interrupt masks and flags, on page 33, for a detailed description of CSC interrupt masks and flags). RI_OUT is multiplexed with PME on the same terminal. The default is for RI_OUT to be signaled on this terminal. In PCI power management systems the PME signal should be enabled by setting bit 8 (PME_EN) in the power management control/status register (A4h) and setting RIMUX 80h to 1. In addition to bit 0 in the system control register, the RIENB bit (bit 7) in the card control register (91h) must be set to enable RI_OUT. RI_OUT Function CSTSMASK PC Card Socket 0 CSC Card I/F RINGEN RI CDRESUME RIENB CSC RI_OUT CSTSMASK PC Card Socket 1 CSC Card I/F RINGEN RI CDRESUME CSC Figure 16. RI_OUT Functional Diagram Routing of CSC events to RI_OUT is enabled on a per-socket basis, and is programmed by the RIENB bit in the card control register on page 67. This bit is socket dependent (not shared), as shown in Figure 15. Ring indicate (RI) from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the ExCA interrupt and general control register on page 83. This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit, CSTSMASK, is programmed through the socket mask register (page 102) in the CardBus socket registers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PC Card controller programming model This section describes the PCI1251B PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1251B function. As noted below, some bits are global in nature and should be accessed only through function 0. PCI configuration registers (functions 0 and 1) The PCI1251B is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header, compliant with the PCI specification as a CardBus bridge header, is PC99 compliant as well. Table 26 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. Table 26. PCI Configuration Registers (Functions 0 and 1) REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch CardBus socket/ExCA base address Secondary status CardBus latency timer Subordinate bus number 10h Reserved Capability pointer 14h CardBus bus number PCI bus number 18h Memory base register 0 1Ch Memory limit register 0 20h Memory base register 1 24h Memory limit register 1 28h I/O base register 0 2Ch I/O limit register 0 30h I/O base register 1 34h I/O limit register 1 Bridge control 38h Interrupt pin Subsystem ID Interrupt line Subsystem vendor ID 40h PC Card 16-bit I/F legacy-mode base address 44h Reserved 48h–7Fh System control 80h Reserved Reserved General status Multimedia control 84h GPIO3 control GPIO2 control GPIO1 control GPIO0 control 88h Diagnostic Device control IRQMUX routing 8Ch Card control Retry status Socket DMA register 0 Data (reserved) 90h 94h Socket DMA register 1 98h Reserved 9Ah–9Fh Power management capabilities 40 3Ch Next-item pointer PMCSR bridge support extensions POST OFFICE BOX 655303 Capability ID Power management control/status • DALLAS, TEXAS 75265 A0h A4h PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 vendor ID register Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R Default 0 0 0 1 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R R R R R R R 0 1 0 0 1 1 0 0 Vendor ID Register: Type: Offset: Default: Description: Vendor ID Read-only 00h (functions 0, 1) 104Ch This 16-bit register contains a value allocated by the PCI SIG (special interest group) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch. device ID register Bit 15 14 13 12 11 10 9 8 Name 7 6 5 4 3 2 1 0 Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 Register: Type: Offset: Default: Description: Device ID Read-only 02h (functions 0, 1) AC1Fh This 16-bit register contains a value assigned to the PCI1251B by TI. The device identification for the PCI1251B is AC1F. command register Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R/W Default 0 0 0 0 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R/W R R R R/W R/W R/W 0 0 0 0 0 0 0 0 Command Register: Type: Offset: Default: Description: Command Read-only, Read/Write (see individual bit descriptions) 04h 0000h This register provides control over the PCI1251B interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification 2.2. None of the bit functions in this register are shared between the two PCI1251B PCI functions. Two command registers exist in the PCI1251B, one for each function. Software must manipulate the two PCI1251B functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the two functions, and these control bits appear separately according to their software function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 27. Command Register BIT SIGNAL TYPE 15–10 RSVD R Reserved. Bits 15–10 return 0s when read. Writes have no effect. 9 FBB_EN R Fast back-to-back enable. The PCI251 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 42 FUNCTION 8 SERR_EN R/W System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set for the PCI1251B to report address parity errors. 0 = Disable SERR output driver (default). 1 = Enable SERR output driver. 7 ADSTPNG R Address/data stepping control. The PCI1251B does not support address/data stepping, and bit 7 is hardwired to 0. Writes to this bit have no effect. 6 PERR_EN R/W Parity error response enable. Bit 6 controls the PCI1251B’s response to parity errors through PERR. Data parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR. 0 = PCI1251B ignores detected parity error (default). 1 = PCI1251B responds to detected parity errors. 5 VGA_SNP R VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette registers. The PCI1251B does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit 5 returns 0 when read. Writes to this bit have no effect. 4 MWI_EN R Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and invalidate commands. The PCI1251B controller does not support memory write and invalidate commands; it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 returns 0 when read. Writes to this bit have no effect. 3 SP_CYCL R Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1251B does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 returns 0 when read. Writes to this bit have no effect. 2 BUSMSTR R/W Bus master control. Bit 2 controls whether or not the PCI1251B can act as a PCI bus initiator (master). The PCI1251B can take control of the PCI bus only when this bit is set. 0 = Disables the PCI1251B’s ability to generate PCI bus accesses (default). 1 = Enables the PCI1251B’s ability to generate PCI bus accesses. 1 MEM_EN R/W Memory space enable. Bit 1 controls whether or not the PCI1251B can claim cycles in PCI memory space. 0 = Disables the PCI1251B’s response to memory space accesses (default). 1 = Enables the PCI1251B’s response to memory space accesses. 0 IO_EN R/W I/O space control. Bit 0 controls whether or not the PCI1251B can claim cycles in PCI I/O space. 0 = Disables the PCI1251B from responding to I/O space accesses (default). 1 = Enables the PCI1251B to respond to I/O space accesses. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 status register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R R R/W 0 0 0 0 0 0 1 R R R R R R R R 0 0 0 0 1 0 0 0 0 Name Type Default Status Register: Type: Offset: Default: Description: Status Read-only, Read/Write (see individual bit descriptions) 06h (functions 0, 1) 0210h This register provides device information to the host system. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local Bus Specification 2.2. PCI bus status is shown through each function (see Table 28). Table 28. Status Register BIT SIGNAL TYPE FUNCTION 15 PAR_ERR R/W Detected parity error. Bit 15 is set when a parity error is detected (either address or data). Write a 1 to clear this bit. 14 SYS_ERR R/W Signaled system error. Bit 14 is set when SERR is enabled and the PCI1251B signals a system error to the host. Write a 1 to clear this bit. 13 MABORT R/W Received master abort. Bit 13 is set when a cycle initiated by the PCI1251B on the PCI bus has been terminated by a master abort. Write a 1 to clear this bit. 12 TABT_REC R/W Received target abort. Bit 12 is set when a cycle initiated by the PCI1251B on the PCI bus was terminated by a target abort. Write a 1 to clear this bit. 11 TABT_SIG R/W Signaled target abort. Bit 11 is set by the PCI1251B when it terminates a transaction on the PCI bus with a target abort. Write a 1 to clear this bit. 10–9 PCI_SPEED R DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1251B asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses. Data parity error detected. Write a 1 to clear this bit. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met: a. PERR was asserted by any PCI device including the PCI1251B. b. The PCI1251B was the bus master during the data parity error. c. The parity error response bit is set in the command. 8 DATAPAR R/W 7 FBB_CAP R Fast back-to-back capable. The PCI1251B cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0. 6 UDF R User-definable feature support. The PCI1251B does not support the user-definable features; thus, bit 6 is hardwired to 0. 5 66_CAP R 66-MHz capable. The PCI1251B operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4 CAP_LST R Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power management capabilities is implemented in this function. 3–0 RSVD R Reserved. Bits 3–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 revision ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 0 Name Revision ID Register: Type: Offset: Default: Description: Revision ID Read-only 08h (functions 0, 1) 00h This register indicates the silicon revision of the PCI1251B. This data sheet reflects the PCI1251B revision is 00h silicon. PCI class code register Bit 23 22 21 20 19 18 17 16 15 14 13 12 Name 11 10 9 8 7 6 5 4 3 2 1 0 Class code Base class Sub class Programming interface Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: PCI Class code Read-only 09h (functions 0, 1) 060700h This register recognizes the PCI1251B functions 0 and 1 as a bridge device (06h), and CardBus bridge device (07h) with a 00h programming interface. cache line size register Bit 7 6 5 Name Type Default 3 2 1 0 Cache line size R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 44 4 Cache line size Read/Write 0Ch (functions 0, 1) 00h This register is programmed by host software to indicate the system cache line size. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 latency timer register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 Name Latency timer Type Default Register: Type: Offset: Default: Description: Latency timer Read/Write 0Dh 00h This register specifies the latency timer for the PCI1251B in units of PCI clock cycles. When the PCI1251B is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI1251B transaction has terminated, then the PCI1251B terminates the transaction when its GNT is deasserted. header type register Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 1 0 0 0 0 0 1 0 Name Header type Register: Type: Offset: Default: Description: Header type Read-only 0Eh (functions 0, 1) 82h This register returns 82h when read, indicating that the PCI1251B functions 0 and 1 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh are user-definable extension registers. BIST register Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name BIST Register: Type: Offset: Default: Description: BIST Read-only 0Fh (functions 0, 1) 00h Because the PCI1251B does not support a built-in self-test (BIST), this register returns the value of 00h when read. This register returns 0s for the two PCI1251B functions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 CardBus socket registers/ExCA base-address register Bit 31 30 29 28 27 26 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 CardBus socket/ExCA base address Name Type 25 CardBus socket/ExCA base address R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: CardBus socket/ExCA base address Read-only, Read/Write 10h 0000 0000h This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all 1s to this register, the value readback is FFFF F000h, indicating that at least 4 kbytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. This register is not shared by functions 0 and 1, mapping each socket control separately. capability pointer register Bit 7 6 5 Name 4 3 2 1 0 Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Type: Offset: Default: Description: 46 Capability pointer Read-only 14h A0h This register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register returns A0h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 secondary status register Bit 15 14 13 12 11 10 9 R/W R/W R/W R/W R/W R R R/W 0 0 0 0 0 0 1 0 Name Type Default 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Secondary status Register: Type: Offset: Default: Description: Secondary status Read-only, Read/Write (see individual bit descriptions) 16h 0200h This register (see Table 29) is compatible with the PCI-to-PCI bridge secondary status register and indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h), and status bits are cleared by writing a 1. This register is not shared by the two socket functions and is accessed on a per-socket basis. Table 29. Secondary Status Register BIT SIGNAL TYPE FUNCTION 15 CBPARITY R/W Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). Write a 1 to clear this bit. 14 CBSERR R/W Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1251B does not assert CSERR. Write a 1 to clear this bit. 13 CBMABORT R/W Received master abort. Bit 13 is set when a cycle initiated by the PCI1251B on the CardBus bus has been terminated by a master abort. Write a 1 to clear this bit. 12 REC_CBTA R/W Received target abort. Bit 12 is set when a cycle initiated by the PCI1251B on the CardBus bus is terminated by a target abort. Write a 1 to clear this bit. 11 SIG_CBTA R/W Signaled target abort. Bit 11 is set by the PCI1251B when it terminates a transaction on the CardBus bus with a target abort. Write a 1 to clear this bit. 10–9 CB_SPEED R CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1251B asserts CB_SPEED at a medium speed. CardBus data parity error detected. Write a 1 to clear this bit. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface. b. The PCI1251B was the bus master during the data parity error. c. The parity error response bit is set in the bridge control. 8 CB_DPAR R/W 7 CBFBB_CAP R Fast back-to-back capable. The PCI1251B cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0. 6 CB_UDF R User-definable feature support. The PCI1251B does not support the user-definable features; thus, bit 6 is hardwired to 0. 5 CB66MHZ R 66-MHz capable. The PCI1251B CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4–0 RSVD R Reserved. Bits 4–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PCI bus number register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 PCI bus number Register: Type: Offset: Default: Description: PCI bus number Read/Write 18h (functions 0, 1) 00h This register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1251B is connected. The PCI1251B uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. CardBus bus number register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus bus number Register: Type: Offset: Default: Description: CardBus bus number Read/Write 19h 00h This register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1251B is connected. The PCI1251B uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI1251B controller function. subordinate bus number register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Subordinate bus number Register: Type: Offset: Default: Description: 48 4 Subordinate bus number Read/Write 1Ah 00h This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The PCI1251B uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 CardBus latency timer register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus latency timer Type Default Register: Type: Offset: Default: Description: CardBus latency timer Read/Write 1Bh (functions 0, 1) 00h This register is programmed by the host system to specify the latency timer for the PCI1251B CardBus interface in units of CCLK cycles. When the PCI1251B is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI1251B transaction has terminated, then the PCI1251B terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory base registers 0, 1 Name Type 24 Memory base registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Memory base registers 0, 1 Read-only, Read/Write 1 Ch, 24h 0000 0000h These registers indicate the lower address of a PCI memory address range. These registers are used by the PCI1251B to determine when to forward a memory transaction to the CardBus bus, and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write which allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1251B to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 kbytes of memory to CardBus). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory limit registers 0, 1 Name Type 24 Memory limit registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Memory limit registers 0, 1 Read-only, Read/Write 20h, 24h 0000 0000h These registers indicate the upper address of a PCI memory address range. They are used by the PCI1251B to determine when to forward a memory transaction to the CardBus bus, and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1251B to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 kbytes of memory to CardBus). I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 I/O base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default I/O base registers 0, 1 Register: Type: Offset: Default: Description: I/O base registers 0, 1 Read-only, Read/Write 2Ch, 34h 0000 0000h These registers indicate the lower address of a PCI I/O address range. They are used by the PCI1251B to determine when to forward an I/O transaction to the CardBus bus, and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-kbyte page, and the upper 16 bits (31–16) are all 0, which locates this 64-kbyte page in the first page of the 32-bit PCI I/O address space. Bits 31–16 and bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary in the first 64-kbyte page of PCI I/O address space. These I/O windows are enabled when either the I/O base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus. Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions. 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 I/O limit registers 0, 1 Name Type 24 I/O limit registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: I/O limit registers 0, 1 Read-only, Read/Write 30h, 38h 0000 0000h These registers indicate the upper address of a PCI I/O address range. They are used by the PCI1251B to determine when to forward an I/O transaction to the CardBus bus, and when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-kbyte page, and the upper 16 bits are a page register that locates this 64-kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64-kbyte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries. Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI1251B assumes that the lower two bits of the limit address are 1s. These I/O windows are enabled when either the I/O base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus). Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions. interrupt line register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 1 1 1 R/W R/W R/W R/W 1 1 1 1 1 Name Type Default Interrupt line Register: Type: Offset: Default: Description: Interrupt line Read/Write 3Ch FFh This register is used to communicate interrupt line routing information. This register is not used by the PCI1251B, because there are many programmable interrupt signaling options. This register is considered reserved; however, host software may read and write to this register. Each PCI1251B function 0 and 1 has an interrupt line register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 interrupt pin register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 1 1 1 R R R R 1 1 1 1 1 Name Interrupt pin Register: Type: Offset: Default: Description: Interrupt pin Read-only 3Dh Depends on the interrupt signaling mode The value read from this register is function dependent. The value depends on the interrupt INTRTIE bit in the system control register and the signaling mode, selected through the device control register. When the INTRTIE bit is set, this register reads 0x01 (INTA) for both functions. The PCI1251B defaults to signaling PCI and IRQ interrupts through IRQSER serial interrupt terminal. Refer to Table 30 for a complete description of the register contents. Table 30. Interrupt Pin Register Cross Reference INTRTIE BIT INTPIN FUNCTION 0 INTPIN FUNCTION 1 Parallel PCI interrupts only 0 0x01 (INTA) 0x02 (INTB) Parallel IRQ and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) INTERRUPT SIGNALING MODE IRQ serialized (IRQSER) and parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ and PCI serialized (IRQSER) interrupts (default) 0 0x01 (INTA) 0x02 (INTB) Parallel PCI interrupts only 1 0x01 (INTA) 0x01 (INTA) Parallel IRQ and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ and PCI serialized (IRQSER) interrupts (default) 1 0x01 (INTA) 0x01 (INTA) bridge control register Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Bridge control Type R R R R R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W Default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 52 Bridge control Read-only, Read/Write (see individual bit descriptions) 3Eh (functions 0, 1) 0340h This register provides control over various PCI1251B bridging functions. Some bits in this register are global and should be accessed only through function 0. Refer to Table 31 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 31. Bridge Control Register BIT SIGNAL TYPE 15–11 RSVD R 10 POSTEN FUNCTION Reserved. Bits 15–11 return 0s when read. R/W Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that bursted write data can be posted, but various write transactions may not. Bit 10 is socket dependent and is not shared between functions 0 and 1. 9 PREFETCH1 R/W Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as: 0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default). 8 PREFETCH0 R/W Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as: 0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default). 7 INT_RT_EN R/W PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or the IRQ specified in the ExCA registers. 0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCA registers R/W CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a PRST assertion to CardBus. 0 = CRST deasserted 1 = CRST asserted (default) Master abort mode. Bit 5 controls how the PCI1251B responds to a master abort when the PCI1251B is an initiator on the CardBus interface. This bit is common between each socket. 0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR (if enabled) 6 CRST 5† MABTMODE R/W 4 RSVD R 3 VGAEN R/W VGA enable. Bit 3 affects how the PCI1251B responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded. 2 ISAEN R/W ISA mode enable. Bit 2 affects how the PCI1251B passes I/O cycles within the 64-kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI1251B does not forward the last 768 bytes of each 1K I/O range to CardBus. Reserved. Bit 4 returns 0 when read. 1 CSERREN R/W CSERR enable. Bit 1 controls the response of the PCI1251B to CSERR signals on the CardBus bus. This bit is separate for each socket. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR. 0 CPERREN R/W CardBus parity error response enable. Bit 0 controls the response of the PCI1251B to CardBus parity errors. This bit is separate for each socket. 0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR. † This bit is global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 subsystem vendor ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem vendor ID Register: Type: Offset: Default: Description: Subsystem vendor ID Read-only (Read/Write when bit 5 in the system control register is 0) 40h (functions 0, 1) 0000h This register is used for system and option-card identification purposes, and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. subsystem ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem ID Register: Type: Offset: Default: Description: Subsystem ID Read-only (Read/Write when bit 5 in the system control register is 0) 42h (functions 0, 1) 0000h This register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. If an EEPROM is present, then the subsystem ID and subsystem vendor ID will be loaded from EEPROM after a reset. 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PC Card 16-bit I/F legacy-mode base address register Bit 31 30 29 28 27 26 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 Name Type Default 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 2 1 0 PC Card 16-bit I/F legacy-mode base address Name Type 25 PC Card 16-bit I/F legacy-mode base address R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Type: Offset: Default: Description: PC Card 16-bit I/F legacy-mode base address Read-only, Read/Write (see individual bit descriptions) 44h (functions 0, 1) 0000 0000h The PCI1251B supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. As specified in the PCI to PCMCIA CardBus Bridge Register Description (Yenta), this register is shared by functions 0 and 1. Refer to the ExCA register set description for register offsets. system control register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 System control R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Name Type Default System control Register: Type: Offset: Default: Description: System control Read-only, Read/Write (see individual bit descriptions) 80h (functions 0, 1) 0044 9060h System-level initializations are performed through programming this doubleword register. Some of the bits are global and should be written only through function 0. Refer to Table 32 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 32. System Control Register BIT 31–30† SIGNAL SER_STEP TYPE FUNCTION R/W Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31–30 are global to both PCI1251B functions. 00 = INTA/INTB signal in INTA/INTB IRQSER slots (default) 01 = INTA/INTB signal in INTB/INTC IRQSER slots 10 = INTA/INTB signal in INTC/INTD IRQSER slots 11 = INTA/INTB signal in INTD/INTA IRQSER slots Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and are signaled as INTA. INTA can then be shifted by using the SER_STEP bits. This bit is global to both PCI1251B functions. 0 = INTA and INTB are not tied together internally (default). 1 = INTA and INTB are tied together internally. 29† INTRTIE R/W 28 RSVD R 27† P2CCLK R/W 26† SMIROUTE R/W SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes. R/W SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to bit 25 clears the status. 0= SMI interrupt signaled 1 = SMI interrupt not signaled SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled). 0 = SMI interrupt mode is disabled (default). 1 = SMI interrupt mode is enabled. 25 SMISTATUS 24† SMIENB R/W 23 RSVD R Reserved. Bit 28 returns 0 when read. P2C power switch clock. The PCI1251B defaults CLOCK as an input clock to control the serial interface and the internal state machine. Bit 27 can be set to enable the PCI1251B to generate and drive the CLOCK from the PCI clock. When in a SUSPEND state, however, CLOCK must be input to the PCI1251B to successfully power down sockets after card removal without indicating to the system the removal event. 0 = CLOCK provided externally, input to PCI1251B (default) 1 = CLOCK generated by PCI clock and driven by PCI1251B Reserved 22 CBRSVD R/W CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low when a CardBus card is inserted. When this bit is low (as default), these signals are placed in a high-impedance state. 0 = 3-state CardBus RSVD 1 = Drive Cardbus RSVD low (default) 21 VCCPROT R/W VCC protection enable. Bit 21 is socket dependent. 0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards 20 RSVD R/W Reserved. Bit 20 returns 0 when read. R/W PC/PCI DMA card enable. When bit 19 is set, the PCI1251B allows 16-bit PC Cards to request PC/PCI DMA using the DREQ signaling. DREQ is selected through the socket DMA register 0. 0 = Ignore DREQ signaling from PC Cards (default) 1 = Signal DMA request on DREQ R/W CDMACHANPC/PCI DMA channel assignment. Bits 18–16 are encoded as: 0–3 = 8-bit DMA channels 4 = PCI master; not used (default). 5–7 = 16-bit DMA channels 19 18–16 CDREQEN CDMACHAN † These bits are global and should be accessed only through function 0. 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 32. System Control Register (Continued) BIT SIGNAL TYPE FUNCTION 15† MRBURSTDN R/W Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream. 0 = MRBURSTDN downstream is disabled. 1 = MRBURSTDN downstream is enabled (default). 14† MRBURSTUP R/W Memory read burst enable upstream. When bit 14 is set, the PCI1251B allows memory read transactions to burst upstream. 0 = MRBURSTUP upstream is disabled (default). 1 = MRBURSTUP upstream is enabled. 13 SOCACTIVE R Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card, and is cleared upon read of this status bit. This bit is socket dependent. 0 = No socket activity (default) 1 = Socket activity 12 RSVD R Reserved. Bit 12 returns 1 when read. This is the power-rail bit in functions 0 and 1. R Power stream in progress status bit. When set high, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. When this bit is clear, it indicates that the power stream is complete. 0 = Power stream is complete and delay has expired. 1 = Power stream is in progress. R Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. 0 = Power-up delay has expired. 1 = Power-up stream sent to switch. Power may not be stable. R Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. 0 = Power-down delay has expired. 1 = Power-down stream sent to switch. Power may not be stable. 11† 10† 9† PWRSTREAM DELAYUP DELAYDOWN 8 INTERROGATE R Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. This bit is socket dependent. 0 = Interrogation not in progress (default) 1 = Interrogation in progress 7 RSVD R Reserved. Bit 7 returns 0 when read. 6† PWRSAVINGS R/W Power savings mode enable. When this bit is set and if a CB card is inserted, idle, and without a CB clock, then the applicable CB state machine will not be clocked. 5† SUBSYSRW R/W Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write enable. Bit 5 is shared by functions 0 and 1. 0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read-only (default). 4† CB_DPAR R/W CardBus data parity SERR signaling enable 0 = CardBus data parity not signaled on PCI SERR (default) 1 = CardBus data parity signaled on PCI SERR 3† CDMA_EN R/W PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set, and disables IRQMUX7 and IRQMUX6 signaling. 0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled 2 RSVD R 1† KEEPCLK R/W Keep clock. This bit works with PCI and CB CLKRUN protocols. 0 = Allows normal functioning of both CLKRUN protocols.(default) 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols. 0† RIMUX R/W RI_OUT/PME multiplex enable. 0 = RI_OUT and PME signals are both routed to the RI_OUT/PME terminal. If both are enabled at the same time, then RI_OUT will have precedence over PME. 1 = Only PME signals are routed to the RI_OUT/PME terminal. Reserved † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 multimedia control register Bit 7 6 5 R/W R/W R R 0 0 0 0 Name Type Default 4 3 2 1 0 R R R/W R/W 0 0 0 0 Multimedia control Register: Type: Offset: Default: Description: Multimedia control Read-only, Read/Write (see individual bit descriptions) 84h (functions 0, 1) 00h This register provides port mapping for the PCI1251B zoomed video/data ports (see zoomed video support, on page 29). Access this register only through function 0. Refer to Table 33 for a complete description of the register contents. Table 33. Multimedia Control Register BIT 7 ZVOUTEN TYPE FUNCTION R/W ZV output enable. Bit 7 enables the output for the PCI1251B outsourcing ZV terminals. When this bit is reset 0, these terminals are in a high-impedance state. 0 = PCI1251B ZV output terminals disabled (default) 1 = PCI1251B ZV output terminals enabled ZV port select. Bit 6 controls the multiplexing control over which PC Card ZV port data is driven to the outsourcing PCI1251B ZV port. 0 = Output card 0 ZV if enabled (default) 1 = Output card 1 ZV if enabled 6 PORTSEL R/W 5–2 RSVD R 1 0 58 SIGNAL ZVEN1 ZVEN0 Reserved. Bits 5–2 return 0s when read. Writes have no effect. R/W PC Card 1 ZV mode enable. Bit 1 enables the zoomed video mode for socket 1. When set, the PCI1251B inputs ZV data from the PC Card interface and disables output drivers on ZV terminals. 0 = PC Card 1 ZV disabled (default) 1 = PC Card 1 ZV enabled R/W PC Card 0 ZV mode enable. Bit 0 enables the zoomed video mode for socket 0. When set, the PCI1251B inputs ZV data from the PC Card interface and disables output drivers on ZV terminals. 0 = PC Card 0 ZV disabled (default) 1 = PC Card 0 ZV enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 general status register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 X 0 0 Name General status Register: Type: Offset: Default: Description: General status Read-only 85h (functions 0, 1) 0Xh This register provides general device status information. The status of the serial EEPROM interface is provided through this register. Refer to Table 34 for a complete description of the register contents. Table 34. General Status Register BIT SIGNAL TYPE 7–3 RSVD R Reserved. Bits 7–3 return 0s when read. R Serial EEPROM detect. When bit 2 is cleared, it indicates that the PCI1251B serial EEPROM circuitry has detected an EEPROM. A pullup resistor must be implemented on LATCH for bit 2 to be set. This status bit is encoded as: 0 = EEPROM not detected (default) 1 = EEPROM detected R Serial EEPROM data error status. Bit 1 indicates when a data error occurs on the serial EEPROM interface. Bit 2 may be set due to a missing acknowledge. This bit is cleared by writing a 1. 0 = No error detected (default) 1 = Data error detected R Serial EEPROM busy status. Bit 0 indicates the status of the PCI1251B serial EEPROM circuitry. This bit is set during the loading of the subsystem ID value. 0 = Serial EEPROM circuitry not busy (default) 1 = Serial EEPROM circuitry busy 2† 1† 0† EEDETECT DATAERR EEBUSY FUNCTION † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 GPIO0 control register Bit 7 6 5 4 3 2 1 0 R/W R/W R R/W 1 0 0 R/W R R/W R/W 0 0 0 0 0 Name Type Default GPIO0 control Register: Type: Offset: Default: Description: GPIO0 control Read-only, Read/Write (see individual bit descriptions) 88h (functions 0, 1) 80h This register is used for control of the general-purpose I/O 0 (GPIO0). This terminal defaults to a general-purpose input but can be reconfigured as the socket 0 activity LED output, a zoomed video enabled status output, or general-purpose output. Access this register only through function 0. Refer to Table 35 for a complete description of the register contents. Table 35. GPIO0 Control Register BIT 60 SIGNAL TYPE FUNCTION General-purpose 0 mode. Bits 7–6 select the functionality of LEDA1/GPIO0. These bits are encoded as: 00 = Signal LEDA1 to indicate PC Card socket 0 activity 01 = Signal ZVSTAT to indicate zoomed video output enabled 10 = General-purpose input (GPI) 11 = General-purpose output (GPO) 7–6 GP0 R/W 5 RSVD R 4 GPINTEN0 R/W GP interrupt enable. When bit 4 is set, a socket A card status change (CSC) interrupt is generated when the DELTA0 bit is set. 3 DELTA0 R/W DATAIN0 change status. Bit 3 is set when the DATAIN0 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1. 2 RSVD R 1 DATAOUT0 R/W General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output. 0 DATAIN0 R/W General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit. Reserved. Bit 5 returns 0 when read. Writes have no effect. Reserved. Bit 2 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 GPIO1 control register Bit 7 6 5 4 3 2 1 0 R/W R/W R R/W 1 0 0 R/W R R/W R/W 0 0 0 0 0 Name Type Default GPIO1 control Register: Type: Offset: Default: Description: GPIO1 control Read-only, Read/Write (see individual bit descriptions) 89h (functions 0, 1) 80h This register is used for control of the general-purpose I/O 1 (GPIO1). This terminal defaults to a general-purpose input, but can be reconfigured as the socket 1 activity LED output or general-purpose output. Access this register only through function 0. Refer to Table 36 for a complete description of the register contents. Table 36. GPIO1 Control Register BIT SIGNAL TYPE FUNCTION General-purpose 1 mode. Bits 7–6 select the functionality of LEDA2/GPIO1. These bits are encoded as: 00 = Signal LEDA2 to indicate PC Card socket 1 activity. 01 = Reserved. 10 = General-purpose input (GPI). 11 = General-purpose output (GPO). 7–6 GP1 R/W 5 RSVD R 4 GPINTEN1 R/W GP interrupt enable. When bit 4 is set, a socket A card status change (CSC) interrupt is generated when the DELTA1 bit is set. 3 DELTA1 R/W DATAIN1 change status. Bit 3 is set when the DATAIN1 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1. 2 RSVD R 1 DATAOUT1 R/W General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output. 0 DATAIN1 R/W General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit. Reserved. Bit 5 returns 0 when read. Writes have no effect. Reserved. Bit 2 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 GPIO2 control register Bit 7 6 5 4 3 2 1 0 R/W R/W R R/W 1 0 0 R/W R R/W R/W 0 0 0 0 0 Name Type Default GPIO2 control Register: Type: Offset: Default: Description: GPIO2 control Read-only, Read/Write (see individual bit descriptions) 8Ah (functions 0, 1) 80h This register is used for control of the general-purpose I/O 2 (GPIO2). This terminal defaults to a general-purpose input but can be reconfigured as PCI LOCK, a zoomed video enabled status output, or general-purpose output. Access this register only through function 0. Refer to Table 37 for a complete description of the register contents. Table 37. GPIO2 Control Register BIT 62 SIGNAL TYPE FUNCTION General-purpose 2 mode. Bits 7–6 select the functionality of LOCK/GPIO2. These bits are encoded as: 00 = Terminal is configured as PCI LOCK. 01 = Signal ZVSTAT to indicate zoomed video output is enabled. 10 = General-purpose input (GPI) 11 = General-purpose output (GPO) 7–6 GP2 R/W 5 RSVD R 4 GPINTEN2 R/W GP interrupt enable. When bit 4 is set, a socket B card status change (CSC) interrupt is generated when the DELTA2 bit is set. 3 DELTA2 R/W DATAIN2 change status. Bit 3 is set when the DATAIN2 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1. 2 RSVD R 1 DATAOUT2 R/W General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output. 0 DATAIN2 R/W General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit. Reserved. Bit 5 returns 0 when read. Writes have no effect. Reserved. Bit 2 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 GPIO3 control register Bit 7 6 5 4 3 2 1 0 R/W R/W R R/W 1 0 0 R/W R R/W R/W 0 0 0 0 0 Name Type Default GPIO3 control Register: Type: Offset: Default: Description: GPIO3 control Read-only, Read/Write (see individual bit descriptions) 8Bh (functions 0, 1) 80h This register is used for control of the general-purpose I/O 3 (GPIO3). This terminal defaults to a general-purpose input but can be reconfigured as PCI INTA or general-purpose output. Access this register only through function 0. Refer to Table 38 for a complete description of the register contents. Table 38. GPIO3 Control Register BIT SIGNAL TYPE FUNCTION General-purpose 3 mode. Bits 7–6 select the functionality of INTA/GPIO3. These bits are encoded as: 00 = Terminal is configured as PCI INTA. 01 = Reserved 10 = General-purpose input (GPI) 11 = General-purpose output (GPO) 7–6 GP3 R/W 5 RSVD R 4 GPINTEN3 R/W GP interrupt enable. When bit 4 is set, a socket B card status change (CSC) interrupt is generated when the DELTA3 bit is set. 3 DELTA3 R/W DATAIN3 change status. Bit 3 is set when the DATAIN3 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without bit 3. This bit is cleared by a write back of 1. 2 RSVD R 1 DATAOUT3 R/W General-purpose data output. When in general-purpose output mode, bit 1 represents the data. Data written to this bit in GPO mode is signaled to the output. 0 DATAIN3 R/W General-purpose data input. When in either general-purpose input or output mode, bit 0 represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit. Reserved. Bit 5 returns 0 when read. Writes have no effect. Reserved. Bit 2 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 IRQMUX routing register Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 IRQMUX routing Name Type 24 IRQMUX routing R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: IRQMUX routing Read/Write (see individual bit descriptions) 8Ch (functions 0, 1) 0000 0000h This register is used for the legacy interrupt mux routing feature of the PCI1251B, which is described in the programmable interrupt subsystem on page 32. If the parallel IRQ interrupt scheme is selected, then all PCI1251B interrupts sent to ISA IRQs are signaled on the corresponding IRQMUX7–IRQMUX0 signals. These signals are routed directly to various IRQ inputs on the system PIC, and the routing information is programmed through this register. Each terminal has at least one secondary function that can be selected by programming the bits appropriately. Access this register only through function 0. Refer to Table 39 for a complete description of the register contents. Table 39. IRQMUX Routing Register BIT SIGNAL TYPE FUNCTION IRQMUX7 routing. Bits 31–28 select one of 15 interrupts that may be routed on IRQMUX7. When these bits are 0000 and bit 3 in the system control register is set, this pin is used for PCREQ DMA signaling. NOTE: These bits must not be configured for IRQ signaling if IRQMUX7 is being used for PCREQ signaling. 31–28 IRQMUX7 R/W 0000 = EEPROM SCL routed on IRQMUX7 (default) 0000 = PCREQ routed on IRQMUX7 when bit 3 of the system control register is 1 0001 = PCREQ routed on IRQMUX7 0010 = IRQ2 routed on IRQMUX7 0011 = IRQ3 routed on IRQMUX7 : 1111 = IRQ15 routed on IRQMUX7 IRQMUX6 routing. Bits 27–24 select one of 15 interrupts that may be routed on IRQMUX6. When these bits are 0000 and bit 3 in the system control register is set, this pin is used for PCGNT DMA signaling. NOTES: 1. These bits must not be configured for IRQ signaling if IRQMUX6 is being used for PCGNT signaling. 2. An EEPROM cannot be used if IRQMUX7 and IRQMUX6 are being used for DMA PCREQ PCGNT. 27–24 64 IRQMUX6 R/W 0000 = EEPROM SDA routed on IRQMUX6 (default) 0000 = PCGNT routed on IRQMUX6 when bit 3 of the system control register is 1 0001 = IRQ1 routed on IRQMUX6 0010 = IRQ2 routed on IRQMUX6 0011 = IRQ3 routed on IRQMUX6 : 1111 = IRQ15 routed on IRQMUX6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 39. IRQMUX Routing Register (Continued) BIT 23–20 19–16 15–12 11–8 7–4 3–0 SIGNAL IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0 TYPE FUNCTION R/W IRQMUX5 routing. Bits 23–20 select one of 15 interrupts that may be routed on IRQMUX5. When these bits are 0000, then no routing is selected. 0000 = No IRQ routing selected (default) 0001 = CardBus audio (CBAUDIO) routed on IRQMUX5 0010 = IRQ2 routed on IRQMUX5 0011 = IRQ3 routed on IRQMUX5 : 1111 = IRQ15 routed on IRQMUX5 R/W IRQMUX4 routing. Bits 19–16 select one of 15 interrupts that may be routed on IRQMUX4. When these bits are 0000, then no routing is selected. 0000 = No IRQ routing selected (default) 0001 = ZVSTAT routed on IRQMUX4 0010 = RI_OUT routed on IRQMUX4 0011 = IRQ3 routed on IRQMUX4 0100 = IRQ4 routed on IRQMUX4 : 1111 = IRQ15 routed on IRQMUX4 R/W IRQMUX3 routing. Bits 15–12 select one of 15 interrupts that may be routed on IRQMUX3. When these bits are 0000, then no routing is selected. 0000 = No IRQ routing selected (default) 0001 = LEDA or LEDB routed on IRQMUX3 0010 = RI_OUT routed on IRQMUX3 0011 = IRQ3 routed on IRQMUX3 0100 = IRQ4 routed on IRQMUX3 : 1111 = IRQ15 routed on IRQMUX3 R/W IRQMUX2 routing. Bits 11–8 select one of 15 interrupts that may be routed on IRQMUX2. When these bits are 0000, then no routing is selected. 0000 = No IRQ routing selected (default) 0001 = LEDB routed on IRQMUX2 0010 = IRQ2 routed on IRQMUX2 0011 = IRQ3 routed on IRQMUX2 : 1111 = IRQ15 routed on IRQMUX2 R/W IRQMUX1 routing. Bits 7–4 select one of 15 interrupts that may be routed on IRQMUX1. When these bits are 0000, then no routing is selected. 0000 = No IRQ routing selected (default) 0001 = LEDA routed on IRQMUX1 0010 = IRQ2 routed on IRQMUX1 0011 = IRQ3 routed on IRQMUX1 : 1111 = IRQ15 routed on IRQMUX1 R/W IRQMUX0 routing. Bits 3–0 select one of 15 interrupts that may be routed on IRQMUX0. When these bits are 0000, then no routing is selected. 0000 = No IRQ routing selected (default) 0001 = INTB routed on IRQMUX0 0010 = IRQ2 routed on IRQMUX0 0011 = IRQ3 routed on IRQMUX0 : 1111 = IRQ15 routed on IRQMUX0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 retry status register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R 1 1 0 R R R/W R 0 0 0 0 0 Name Type Default Retry status Register: Type: Offset: Default: Description: Retry status Read-only, Read/Write (see individual bit descriptions) 90h (functions 0, 1) C0h This register enables the retry timeout counters and displays the retry expiration status. The flags are set when the PCI1251B retries a PCI or CardBus master request, and the master does not return within 215 PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. Access this register only through function 0. Refer to Table 40 for a complete description of the register contents. Table 40. Retry Status Register BIT SIGNAL TYPE FUNCTION 7 PCIRETRY R/W PCI retry timeout counter enable. Bit 7 is encoded: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) 6† CBRETRY R/W CardBus retry timeout counter enable. Bit 6 is encoded: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) 5 TEXP_CBB R/W CardBus target B retry expired. Write a 1 to clear bit 5. 0 = Inactive (default) 1 = Retry has expired 4 RSVD R Reserved. Bit 4 returns 0 when read. 3† TEXP_CBA R CardBus target A retry expired. Write a 1 to clear bit 3. 0 = Inactive (default) 1 = Retry has expired. 2 RSVD R Reserved. Bit 2 returns 0 when read. 1 TEXP_PCI R/W PCI target retry expired. Write a 1 to clear bit 1. 0 = Inactive (default) 1 = Retry has expired. 0 RSVD R Reserved. Bit 0 returns 0 when read. † These bits are global and should be accessed only through function 0. 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 card control register Bit 7 6 5 4 3 2 1 0 R/W R/W R R 0 0 0 R R/W R/W R/W 0 0 0 0 0 Name Type Default Card control Register: Type: Offset: Default: Description: Card control Read-only, Read/Write (see individual bit descriptions) 91h 00h This register is provided for PCI1130 compatibility. It provides the PC Card function interrupt flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI1251B multimedia control register. When this register is accessed by function 0, the ZVEN0 bit will alias with ZVENABLE. When this register is accessed by function 1, the ZVEN1 bit will alias with ZVENABLE. Setting ZVENABLE only places the PC Card socket interface ZV terminals in a high-impedance state, but does not enable the PCI1251B to drive ZV data onto the ZV terminals. RI_OUT is enabled through this register, and the enable bit is shared between functions 0 and 1. Refer to Table 41 for a complete description of the register contents. Table 41. Card Control Register BIT SIGNAL TYPE FUNCTION 7† RIENB R/W Ring indicate output enable. 0 = Disables any routing of RI_OUT signal (default). 1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal when RIMUX is set to 0, and for routing to IRQMUX3/4. 6 ZVENABLE R/W Compatibility ZV mode enable. When set, the corresponding PC Card Socket interface ZV terminals enter a high-impedance state. This bit defaults to 0. 5 RSVD R Reserved. Bit 5 returns 0 when read. 4–3 RSVD R Reserved. Bits 4–3 default to 0. 2 1 0 AUD2MUX SPKROUTEN IFG R/W CardBus Audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding IRQMUX terminal. Function 0, A_CAUDIO is routed to IRQMUX0, and function 1, B_AUDIO is routed to IRQMUX1. If this bit is set for both functions, then function 0 is routed. 0 = CAUDIO set to CAUDPWM on IRQMUX routed (default) 1 = CAUDIO is not routed. R/W Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT on the PCI bus. The SPKR signal from socket 0 is exclusive ORed with the SPKR signal from socket 1 and sent to SPKROUT. The SPKROUT terminal drives data only when either functions SPKROUTEN bit is set. This bit is encoded as: 0 = SPKR to SPKROUT not enabled 1 = SPKR to SPKROUT enabled R/W Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface and is socket dependent (i.e., not global). Write back a 1 to clear this bit. 0 = No PC Card functional interrupt detected (default) 1 = PC Card functional interrupt detected † This bit is global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 67 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 device control register Bit 7 6 5 4 3 2 1 0 Type R R/W R/W R Default 0 1 1 R/W R/W R/W R/W 0 0 1 1 0 Name Device control Register: Type: Offset: Default: Description: Device control Read-only, Read/Write (see individual bit descriptions) 92h (functions 0, 1) 66h This register is provided for PCI1130 compatibility and contains bits that are shared between functions 0 and 1. The interrupt mode select is programmed through this register which is composed of PCI1251B global bits. The socket-capable force bits are also programmed through this register. Refer to Table 42 for a complete description of the register contents. Table 42. Device Control Register BIT SIGNAL TYPE 7 RSVD R FUNCTION 6† 3VCAPABLE R/W 3-V socket capable force 0 = Not 3-V capable 1 = 3-V capable (default) 5 IO16R2 R/W Diagnostic bit. This bit defaults to 1. 4 3† RSVD R TEST R/W TI test. Only a 0 should be written to bit 3. This bit can be set to shorten the interrogation counter. Reserved. Bit 7 returns 0 when read. Reserved. Bit 4 returns 0 when read. Writes have no effect. 2–1† INTMODE R/W Interrupt mode. Bit 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupts INTA and INTB 11 = IRQ and PCI serialized interrupts (default) 0† RSVD R/W Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI1251B, and it tests only the pins that are inputs or I/Os. Any output-only terminal on the PCI1251B is excluded from the NAND tree test. † These bits are global and should be accessed only through function 0. 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 diagnostic register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 1 1 R/W R/W R/W R/W 0 0 0 0 1 Name Type Default Diagnostic Register: Type: Offset: Default: Description: Diagnostic Read/Write 93h (functions 0, 1) 61h This register is provided for internal TI test purposes. It is a read/write register, but only 0s should be written to this register. Refer to Table 43 for a complete description of the register contents. Table 43. Diagnostic Register BIT SIGNAL TYPE FUNCTION 7† TRUE_VAL R/W True value. This bit defaults to 0 when read. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads to the PCI vendor ID and PCI device ID registers 6 RSVD R/W Reserved. This bit is R/W with no function. 5 CSC R/W CSC interrupt routing control. 0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7–4 = 0000b. (default) In this case, the setting of ExCA 803 bit 4 is a “don’t care” 4† 3† DIAG R/W Diagnostic RETRY_DIS. Delayed transaction disable. DIAG R/W 2† 1† DIAG R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. DIAG R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. 0† ASYNC_CSC R/W Asynchronous interrupt generation. 0 = CSC interrupt not generated asynchronously 1 = CSC interrupt generated asynchronously (default) † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket DMA register 0 Bit 31 30 29 28 27 26 25 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 24 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket DMA register 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket DMA register 0 Read-only, Read/Write (see individual bit descriptions) 94h (functions 0, 1) 0000 0000h The socket DMA register 0 provides control over the PC Card DMA request (DREQ) signaling. Refer to Table 44 for a complete description of the register contents. Table 44. Socket DMA Register 0 BIT SIGNAL TYPE 31–2 RSVD R 1–0 70 DREQPIN R/W FUNCTION Reserved. Bits 31–2 return 0s when read. DMA request (DREQ). Bits 1–0 indicate which pin on the 16-bit PC Card interface acts as DREQ during DMA transfers. This field is encoded as: 00 = Socket not configured for DMA (default). 01 = DREQ uses SPKR. 10 = DREQ uses IOIS16. 11 = DREQ uses INPACK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket DMA register 1 Bit 31 30 29 28 27 26 25 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Default 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket DMA register 1 Name Type 24 Socket DMA register 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket DMA register 1 Read-only, Read/Write (see individual bit descriptions) 98h (functions 0, 1) 0000 0000h The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64 kbytes of PCI I/O address space. Refer to Table 45 for a complete description of the register contents. NOTE: 32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits. Table 45. Socket DMA Register 1 BIT SIGNAL TYPE 31–16 RSVD R 15–4 DMABASE R/W 3 EXTMODE R 2–1 0 XFERSIZE DDMAEN FUNCTION Reserved. Bits 31–16 return 0s when read. DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64 kbytes of I/O address space. The lower four bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary. Extended addressing. This feature is not supported by the PCI1251B and always returns a 0. R/W Transfer size. Bits 2–1 specify the width of the DMA transfer on the PC Card interface and are encoded as: 00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved R/W DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of DMABASE. 0 = Disabled (default) 1 = Enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 capability ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 1 Name Capability ID Register: Type: Offset: Default: Description: Capability ID Read-only A0h 01h This register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. next-item pointer register Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 2 1 0 R R R R 0 0 0 0 Next-item pointer Register: Type: Offset: Default: Description: 72 3 Next-item pointer Read-only A1h 00h This register is used to indicate the next item in the linked list of the PCI power management capabilities. Because the PCI1251B functions only include one capabilities item, this register returns 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 power management capabilities register Bit 15 14 13 12 11 10 Type R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 Name 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 1 0 0 0 0 1 Power management capabilities Register: Type: Offset: Default: Description: Power management capabilities Read-only (see individual bit descriptions) A2h (functions 0, 1) 7E21h This register contains information on the capabilities of the PC Card function related to power management. Both PCI1251B CardBus bridge functions support D0, D2, and D3 power states. Refer to Table 46 for a complete description of the register contents. Table 46. Power Management Capabilities Register BIT SIGNAL TYPE FUNCTION 15–11 PME_SUP R PME support. This 4-bit field indicates the power states from which the PCI1251B supports asserting PME. A 0 for any bit indicates that the CardBus function cannot assert PME from that power state. These four bits return 1110b when read. Each of these bits is described below: Bit 15 contains the value 0, indicating that PME cannot be asserted from D3cold state. Bit 14 contains the value 1, indicating that PME can be asserted from D3hot state. Bit 13 contains the value 1, indicating that PME can be asserted from D2 state. Bit 12 contains the value 1, indicating that PME can be asserted from D1 state. Bit 11 contains the value 1, indicating that PME can be asserted from the D0 state. 10 D2_SUP R D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state. 9 D1_SUP R D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state. 8–6 RSVD R Reserved. Bits 8–6 return 000b when read. 5 DSI R Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller functions require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it. R Auxiliary power source. This bit is meaningful only if bit 15 (D3cold supporting PME) is set. When set, bit 4 indicates that support for PME in D3cold requires auxiliary power. 0 = Function supplies its own auxiliary power source 1 = Support for PME in D3cold requires auxiliary power supplied to the system by a proprietary source. R PME clock. When set, bit 3 indicates that the function relies on the presence of the PCI clock for PME operation. 0 = PCI clock not required for the function to generate PME 1 = PCI function required to generate PME R Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the PCI Bus Power Management Interface Specification Revision 1.0. 4 3 2–0 AUX_PWR PMECLK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 power management control/status register Bit 15 14 13 12 11 10 R/W R R R R R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R R/W R/W 0 0 0 0 0 0 0 Power management control/status Register: Type: Offset: Default: Description: Power management control/status Read-only, Read/Write (see individual bit descriptions) A4h (functions 0, 1) 000000h This register determines and changes the current power state of the PCI1251B CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3hot to D0 state. Refer to Table 47 for a complete description of the register contents. NOTE: A transition from the D3hot state to the D0 state resets all PCI, ExCA, and CardBus registers. TI specific, PCI power management, and legacy base address registers are not affected. Table 47. Power Management Control/Status Register BIT SIGNAL TYPE FUNCTION 15 PMESTAT R/W PME status. Bit 15 is set when the CardBus function would normally assert PME, independent of the state of the PME_EN bit. Bit 15 is cleared by a write back of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. 14–13 DATASCALE R Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit. 12–9 DATASEL R Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit. 8 PME_EN R/W PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. 7–2 RSVD R 1–0 74 PWRSTATE R/W Reserved. Bits 7–2 return 0s when read. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as: 00 = D0 01 = D1 10 = D2 11 = D3hot POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 power management control/status register bridge support extensions Bit 7 6 Type R R R R R Default 1 0 0 0 0 Name 5 4 3 2 1 0 R R R 0 0 0 Power management control/status register bridge support extensions Register: Type: Offset: Default: Description: Power management control/status register bridge support extensions Read-only A6h (functions 0, 1) 80h The power management control/status register bridge support extensions support PCI bridge specific functionality and are required for all PCI-to-PCI bridges. Refer to Table 48 for a complete description of the register contents. Table 48. Power Management Control/Status Register Bridge Support Extensions BIT 7 SIGNAL BPCC_EN TYPE FUNCTION R Bus power/clock control. When read, bit 7 returns 1b. This bit is encoded as: 0 = Bus power/clock control is disabled. 1 = Bus power/clock control is enabled (default). A 0 indicates that the bus power/clock control policies defined in the PCI Power Management specification are disabled. When the bus power/clock control enable mechanism is disabled the bridge’s PMCSR PowerState field cannot be used by the system software to control the power or the clock of the bridge’s secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled. 6 B2_B3 R B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. This bit is meaningful only if bit 7 BPCC_Enable is a 1. This bit is encoded as: 0 = When the bridge is programmed to D3hot, its secondary bus has its power removed (B3) 1 = When the bridge is programmed to D3hot, its secondary bus’s PCI clock is stopped (B2). 5–0 RSVD R Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA compatibility registers (functions 0 and 1) The ExCA (Exchangeable Card Architecture) registers implemented in the PCI1251B are register-compatible with the popular Intel 82365SL–DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-Bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Figure 17 illustrates an ExCA I/O mapping. Table 49 identifies each ExCA register and its respective ExCA offset. Host I/O Space PCI1251B Configuration Registers Offset Offset CardBus Socket/ExCA Base Address 10h Index PC Card A ExCA Registers Data 16-Bit Legacy-Mode Base Address† PC Card B ExCA Registers 44h 00h 3Fh 40h 7Fh † The 16-bit legacy mode base address register is shared by functions 0 and 1 as indicated by the shading. Figure 17. ExCA Register Access Through I/O The TI PCI1251B also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus Socket Registers/ExCA Registers Base Address Register (PCI Register 10h) at memory offset 800h. Each socket has a separate base address programmable by function. Figure 18 illustrates an ExCA memory mapping. The memory offsets are 800h–844h for both functions 0 and 1. This illustration also identifies the CardBus Socket Register mapping, which is mapped into the same 4K window at memory offset 0h. 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA compatibility registers (functions 0 and 1) (continued) PCI1251B Configuration Registers Offset Host Memory Space Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address† 10h CardBus Socket A Registers 00h 20h 800h 16-Bit Legacy-Mode Base Address 44h CardBus Socket B Registers 20h ExCA Registers Card A 800h 844h ExCA Registers Card B 844h † The CardBus socket/ExCA base address mode register is separate for functions 0 and 1. Figure 18. ExCA Register Access Through Memory The ExCA interrupt registers, as defined by the 82365SL Specification, control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1251B to ensure that all possible PCI1251B interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h. Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. Memory windows have 4-kbyte granularity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 49. ExCA Registers and Offsets 78 ExCA OFFSET (HEX) PCI MEMORY ADDRESS OFFSET (HEX) CARD A CARD B Identification and revision 800 00 40 Interface status 801 01 41 Power control 802 02 42 Interrupt and general control 803 03 43 Card status change 804 04 44 Card status-change-interrupt configuration 805 05 45 Address window enable 806 06 46 I / O window control 807 07 47 I / O window 0 start-address low byte 808 08 48 REGISTER NAME I / O window 0 start-address high byte 809 09 49 I / O window 0 end-address low byte 80A 0A 4A I / O window 0 end-address high byte 80B 0B 4B I / O window 1 start-address low byte 80C 0C 4C I / O window 1 start-address high byte 80D 0D 4D I / O window 1 end-address low byte 80E 0E 4E I / O window 1 end-address high byte 80F 0F 4F Memory window 0 start-address low byte 810 10 50 Memory window 0 start-address high byte 811 11 51 Memory window 0 end-address low byte 812 12 52 Memory window 0 end-address high byte 813 13 53 Memory window 0 offset-address low byte 814 14 54 Memory window 0 offset-address high byte 815 15 55 Card detect and general control 816 16 56 Reserved 817 17 57 Memory window 1 start-address low byte 818 18 58 Memory window 1 start-address high byte 819 19 59 Memory window 1 end-address low byte 81A 1A 5A Memory window 1 end-address high byte 81B 1B 5B Memory window 1 offset-address low byte 81C 1C 5C Memory window 1 offset-address high byte 81D 1D 5D Global control 81E 1E 5E Reserved 81F 1F 5F Memory window 2 start-address low byte 820 20 60 Memory window 2 start-address high byte 821 21 61 Memory window 2 end-address low byte 822 22 62 Memory window 2 end-address high byte 823 23 63 Memory window 2 offset-address low byte 824 24 64 Memory window 2 offset-address high byte 825 25 65 Reserved 826 26 66 Reserved 827 27 67 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 49. ExCA Registers and Offsets (Continued) ExCA OFFSET (HEX) PCI MEMORY ADDRESS OFFSET (HEX) CARD A CARD B Memory window 3 start-address low byte 828 28 68 Memory window 3 start-address high byte 829 29 69 Memory window 3 end-address low byte 82A 2A 6A Memory window 3 end-address high byte 82B 2B 6B Memory window 3 offset-address low byte 82C 2C 6C Memory window 3 offset-address high byte 82D 2D 6D Reserved 82E 2E 6E Reserved 82F 2F 6F Memory window 4 start-address low byte 830 30 70 Memory window 4 start-address high byte 831 31 71 Memory window 4 end-address low byte 832 32 72 Memory window 4 end-address high byte 833 33 73 Memory window 4 offset-address low byte 834 34 74 Memory window 4 offset-address high byte 835 35 75 I/O window 0 offset-address low byte 836 36 76 I/O window 0 offset-address high byte 837 37 77 I/O window 1 offset-address low byte 838 38 78 REGISTER NAME I/O window 1 offset-address high byte 839 39 79 Reserved 83A 3A 7A Reserved 83B 3B 7B Reserved 83C 3C 7C Reserved 83D 3D 7D Reserved 83E 3E 7E Reserved 83F 3F 7F Memory window page 0 840 – – Memory window page 1 841 – – Memory window page 2 842 – – Memory window page 3 843 – – Memory window page 4 844 – – POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA identification and revision register† (index 00h) Bit 7 6 5 R/W R/W R/W R/W 1 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 1 0 0 ExCA identification and revision Register: Type: Offset: ExCA identification and revision Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 800h: Card A ExCA offset 00h Card B ExCA offset 40h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and Intel 82365SL-DF compatibility. Refer to Table 50 for a complete description of the register contents. † When bit 5 in the system control register is 1, this register is read-only. Table 50. ExCA Identification and Revision Register (Index 00h) 80 BIT SIGNAL TYPE FUNCTION 7–6 IFTYPE R/W Interface type. These bits default to 10b and identify the 16-bit PC Card support provided by the PCI1251B. The PCI1251B supports both I/O and memory 16-bit PC cards. 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation. 3–0 365REV R/W Intel 82365SL-DF revision. This read/write field stores the Intel 82365SL-DF revision supported by the PCI1251B. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. This field defaults to 0100b upon PCI1251B reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA interface status register (index 01h) Bit 7 6 5 Type R R R R Default 0 0 X X Name 4 3 2 1 0 R R R R X X X X ExCA interface status Register: Type: Offset: ExCA interface status Read-only (see individual bit descriptions) CardBus socket address + 801h: Card A ExCA offset 01h Card B ExCA offset 41h Default: 00XX XXXXb Description: This register provides information on the current status of the PC Card interface. An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. Refer to Table 51 for a complete description of the register contents. Table 51. ExCA Interface Status Register (Index 01h) BIT SIGNAL TYPE 7 RSVD R 6 CARDPWR R 5 READY R FUNCTION Reserved. Bit 7 returns 0 when read. Writes have no effect. Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the power control register has been programmed. Bit 6 is encoded as: 0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface. 0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer 4 CARDWP R Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1251B whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1251B 16-bit memory window is available by setting the appropriate bit in the memory window offset high-byte register. 0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read-only. 3 CDETECT2 R Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted. 2 CDETECT1 R Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted. 1–0 BVDSTAT R Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD1 status and bit 0 reflects BVD2. 00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 81 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA power control register (index 02h) Bit 7 6 5 4 R/W R R R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R R/W R/W 0 0 0 0 ExCA power control Register: Type: Offset: ExCA power control Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 802h: Card A ExCA offset 02h Card B ExCA offset 42h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit outputs on the socket interface and can be used for power management in 16-bit PC Card applications. Refer to Table 52 for a complete description of the register contents. Table 52. ExCA Power Control Register (Index 02h) BIT TYPE FUNCTION Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1251B. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled 7 COE R/W 6–5 RSVD R 4–3 EXCAVCC R/W 2 RSVD R 1–0 82 SIGNAL EXCAVPP R/W Reserved. Bits 6–5 return 0s when read. Writes have no effect. VCC. Bits 4–3 are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3 V Reserved. Bit 2 returns 0 when read. Writes have no effect. VPP. Bits 1–0 are used to request changes to card VPP. The PCI1251B ignores this field unless VCC to the socket is enabled (i.e., 5 V or 3.3 V). This field is encoded as: 00 = 0 V (default) 01 = VCC 10 = 12 V 11 = 0 V reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA interrupt and general-control register (index 03h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA interrupt and general control Register: Type: Offset: ExCA interrupt and general control Read/Write (see individual bit descriptions) CardBus socket address + 803h: Card A ExCA offset 03h Card B ExCA offset 43h Default: 00h Description: This register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC Card functions. Refer to Table 53 for a complete description of the register contents. Table 53. ExCA Interrupt and General-Control Register (Index 03h) BIT SIGNAL TYPE FUNCTION 7 RINGEN R/W Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled 6 CARD_RST R/W Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as 0 = RESET signal asserted (default) 1 = RESET signal deasserted 5 CARDTYPE R/W Card type. Bit 5 indicates the PC card type. This bit is encoded as: 0 = Memory PC Card installed (default) 1 = I/O PC Card installed R/W PCI Interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as: 0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. R/W Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 0000 = No interrupt routing (default). CSC interrupts routed to PCI interrupts. This bit setting is OR’ed with ExCA bit 4 for backwards compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 4 3–0 CSCROUTE INTSELECT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 83 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA card status-change register (index 04h) Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3 2 1 0 R R R R 0 0 0 0 ExCA card status change Register: Type: Offset: ExCA card status change Read-only (see individual bit descriptions) CardBus socket address + 804h: Card A ExCA offset 04h Card B ExCA offset 44h Default: 00h Description: This register reflects the status of PC Card CSC interrupt sources. The ExCA card status-change interrupt configuration register, Table 55, enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the global control register. Refer to Table 54 for a complete description of the register contents. Table 54. ExCA Card Status-Change Register (Index 04h) BIT SIGNAL TYPE 7–4 RSVD R Reserved. Bits 7–4 return 0s when read. Writes have no effect. 3 CDCHANGE R Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2 2 READYCHANGE R FUNCTION Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1251B interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = No low-to-high transition detected on READY (default) 1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0. 1 BATWARN R Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCI1251B interrupt was due to a battery-low warning condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. 0 BATDEAD R Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCI1251B interrupt was due to a battery dead condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = STSCHG deasserted (default) 1 = STSCHG asserted Ring indicate. When the PCI1251B is configured for ring indicate operation, bit 0 indicates the status of RI. 84 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA card status-change-interrupt configuration register (index 05h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA status-change-interrupt configuration Register: Type: Offset: ExCA card status-change-interrupt configuration Read/Write (see individual bit descriptions) CardBus socket address + 805h: Card A ExCA offset 05h Card B ExCA offset 45h Default: 00h Description: This register controls interrupt routing for card status-change interrupts, as well as masking CSC interrupt sources. Refer to Table 55 for a complete description of the register contents. Table 55. ExCA Card Status-Change-Interrupt Configuration Register (Index 05h) BIT SIGNAL TYPE FUNCTION 7–4 CSCSELECT R/W Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change interrupts. 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the Diagnostic register (PCI Offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the Diagnostic register (PCI Offset 93h) is set to 0b. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803 to 1b. This field is encoded as: 0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 3 CDEN R/W Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as: 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes R/W Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 2 READYEN 1 BATWARNEN R/W Battery Warning Enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 0 BATDEADEN R/W Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 85 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA address window enable register (index 06h) Bit 7 6 5 R/W R/W R R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA address window enable Register: Type: Offset: ExCA address window enable Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 806h: Card A ExCA offset 06h Card B ExCA offset 46h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI1251B does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. Refer to Table 56 for a complete description of the register contents. Table 56. ExCA Address Window Enable Register (Index 06h) BIT TYPE FUNCTION 7 IOWIN1EN R/W I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled 6 IOWIN0EN R/W I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled 5 RSVD R 4 3 2 86 SIGNAL MEMWIN4EN MEMWIN3EN MEMWIN2EN Reserved. Bit 5 returns 0 when read. Writes have no effect. R/W Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is encoded as: 0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled R/W Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as: 0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled R/W Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as: 0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled 1 MEMWIN1EN R/W Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as: 0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled 0 MEMWIN0EN R/W Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as: 0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA I/O window control register (index 07h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window control ExCA I/O window control Read/Write (see individual bit descriptions) CardBus socket address + 807h: Card A ExCA offset 07h Card B ExCA offset 47h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing. Refer to Table 57 for a complete description of the register contents. Register: Type: Offset: Table 57. ExCA I/O Window Control Register (Index 07h) BIT 7 6 5 4 3 SIGNAL WAITSTATE1 ZEROWS1 IOIS16W1 DATASIZE1 WAITSTATE0 TYPE FUNCTION R/W I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. R/W I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. R/W I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16. R/W I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16 source bit (bit 5) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. R/W I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. 2 ZEROWS0 R/W I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 1 IOIS16W0 R/W I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16. 0 DATASIZE0 R/W I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16 source bit (bit 1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 87 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA I/O window 0 and 1 start-address low-byte register (index 08h, 0Ch) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 start-address low byte Register: Offset: ExCA I/O window 0 start-address low byte CardBus socket address + 808h: Card A ExCA offset 08h Card B ExCA offset 48h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch: Card A ExCA offset 0Ch Card B ExCA offset 4Ch Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the start address. ExCA I/O window 0 and 1 start-address high-byte register (index 09h, 0Dh) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 start-address high byte Register: Offset: ExCA I/O window 0 start-address high byte CardBus socket address + 809h: Card A ExCA offset 09h Card B ExCA offset 49h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh: Card A ExCA offset 0Dh Card B ExCA offset 4Dh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the start address. 88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA I/O window 0 and 1 end-address low-byte register (index 0Ah, 0Eh) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 end-address low byte ExCA I/O window 0 end-address low byte CardBus socket address + 80Ah: Card A ExCA offset 0Ah Card B ExCA offset 4Ah Register: ExCA I/O window 1 end-address low byte Offset: CardBus socket address + 80Eh: Card A ExCA offset 0Eh Card B ExCA offset 4Eh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the end address. Register: Offset: ExCA I/O window 0 and 1 end-address high-byte register (index 0Bh, 0Fh) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 end-address high byte ExCA I/O window 0 end-address high byte CardBus socket address + 80Bh: Card A ExCA offset 0Bh Card B ExCA offset 4Bh Register: ExCA I/O window 1 end-address high byte Offset: CardBus socket address + 80Fh: Card A ExCA offset 0Fh Card B ExCA offset 4Fh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address. Register: Offset: POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 89 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address low byte Register: Offset: Register: Offset: Register: Offset: ExCA memory window 0 start-address low byte CardBus socket address + 810h: Card A ExCA offset 10h Card B ExCA offset 50h ExCA memory window 1 start-address low byte CardBus socket address + 818h: Card A ExCA offset 18h Card B ExCA offset 58h ExCA memory window 2 start-address low byte CardBus socket address + 820h: Card A ExCA offset 20h Card B ExCA offset 60h Register: Offset: ExCA memory window 3 start-address low byte CardBus socket address + 828h: Card A ExCA offset 28h Card B ExCA offset 68h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h: Card A ExCA offset 30h Card B ExCA offset 70h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address. 90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 start-address high-byte register (index 11h, 19h, 21h, 29h, 31h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address high byte Register: Offset: ExCA memory window 0 start-address high byte CardBus socket address + 811h: Card A ExCA offset 11h Card B ExCA offset 51h Register: ExCA memory window 1 start-address high byte Offset: CardBus socket address + 819h: Card A ExCA offset 19h Card B ExCA offset 59h Register: ExCA memory window 2 start-address high byte Offset: CardBus socket address + 821h: Card A ExCA offset 21h Card B ExCA offset 61h Register: ExCA memory window 3 start-address high byte Offset: CardBus socket address + 829h: Card A ExCA offset 29h Card B ExCA offset 69h Register: ExCA memory window 4 start-address high byte Offset: CardBus socket address + 831h: Card A ExCA offset 31h Card B ExCA offset 71h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. Refer to Table 58 for a complete description of the register contents. Table 58. ExCA Memory Window 0–4 Start-Address High-Byte Register (Index 11h, 19h, 21h, 29h, 31h) BIT 7 SIGNAL DATASIZE TYPE FUNCTION R/W Data size. Bit 7 controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 6 ZEROWAIT R/W Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 have no effect on memory window operation. 3–0 STAHN R/W Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 91 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 end-address low-byte register (index 12h, 1Ah, 22h, 2Ah, 32h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address low byte Register: Offset: ExCA memory window 0 end-address low byte CardBus socket address + 812h: Card A ExCA offset 12h Card B ExCA offset 52h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah: Card A ExCA offset 1Ah Card B ExCA offset 5Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h: Card A ExCA offset 22h Card B ExCA offset 62h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah: Card A ExCA offset 2Ah Card B ExCA offset 6Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h: Card A ExCA offset 32h Card B ExCA offset 72h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address. 92 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 end-address high-byte register (index 13h, 1Bh, 23h, 2Bh, 33h) Bit 7 6 5 R/W R/W R R R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address high byte Register: Offset: ExCA memory window 0 end-address high byte CardBus socket address + 813h: Card A ExCA offset 13h Card B ExCA offset 53h Register: ExCA memory window 1 end-address high byte Offset: CardBus socket address + 81Bh: Card A ExCA offset 1Bh Card B ExCA offset 5Bh Register: ExCA memory window 2 end-address high byte Offset: CardBus socket address + 823h: Card A ExCA offset 23h Card B ExCA offset 63h Register: ExCA memory window 3 end-address high byte Offset: CardBus socket address + 82Bh: Card A ExCA offset 2Bh Card B ExCA offset 6Bh Register: ExCA memory window 4 end-address high byte Offset: CardBus socket address + 833h: Card A ExCA offset 33h Card B ExCA offset 73h Type: Read-only, Read/Write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. Refer to Table 59 for a complete description of the register contents. Table 59. ExCA Memory Window 0–4 End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h) BIT SIGNAL TYPE FUNCTION 7–6 MEMWS R/W Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 5–4 RSVD R 3–0 ENDHN R/W Reserved. Bits 5–4 return 0s when read. Writes have no effect. End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 93 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 offset-address low-byte register (index 14h, 1Ch, 24h, 2Ch, 34h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address low byte Register: Offset: ExCA memory window 0 offset-address low byte CardBus socket address + 814h: Card A ExCA offset 14h Card B ExCA offset 54h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch: Card A ExCA offset 1Ch Card B ExCA offset 5Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h: Card A ExCA offset 24h Card B ExCA offset 64h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch: Card A ExCA offset 2Ch Card B ExCA offset 6Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h: Card A ExCA offset 34h Card B ExCA offset 74h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address. 94 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 offset-address high-byte register (index 15h, 1Dh, 25h, 2Dh, 35h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address high byte Default Register: Offset: ExCA memory window 0 offset-address high byte CardBus socket address + 815h: Card A ExCA offset 15h Card B ExCA offset 55h Register: ExCA memory window 1 offset-address high byte Offset: CardBus socket address + 81Dh: Card A ExCA offset 1Dh Card B ExCA offset 5Dh Register: ExCA memory window 2 offset-address high byte Offset: CardBus socket address + 825h: Card A ExCA offset 25h Card B ExCA offset 65h Register: ExCA memory window 3 offset-address high byte Offset: CardBus socket address + 82Dh: Card A ExCA offset 2Dh Card B ExCA offset 6Dh Register: ExCA memory window 4 offset-address high byte Offset: CardBus socket address + 835h: Card A ExCA offset 35h Card B ExCA offset 75h Type: Read-only, Read/Write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high six bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower six bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. Refer to Table 60 for a complete description of the register contents. Table 60. ExCA Memory Window 0–4 Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h) BIT 7 SIGNAL WINWP TYPE FUNCTION R/W Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default). 1 = Write operations are not allowed. 6 REG R/W Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. 5–0 OFFHB R/W Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 95 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA I/O window 0 and 1 offset-address low-byte register (index 36h, 38h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 offset-address low byte Register: Offset: ExCA I/O window 0 offset-address low byte CardBus socket address + 836h: Card A ExCA offset 36h Card B ExCA offset 76h Register: ExCA I/O window 1 offset-address low byte Offset: CardBus socket address + 838h: Card A ExCA offset 38h Card B ExCA offset 78h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0. ExCA I/O window 0 and 1 offset-address high-byte register (index 37h, 39h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 offset-address high byte Register: Offset: ExCA I/O window 0 offset-address high byte CardBus socket address + 837h: Card A ExCA offset 37h Card B ExCA offset 77h Register: ExCA I/O window 1 offset-address high byte Offset: CardBus socket address + 839h: Card A ExCA offset 39h Card B ExCA offset 79h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the offset address. 96 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA card detect and general-control register (index 16h) Bit 7 6 5 Type R R W R/W Default X X 0 0 Name 4 3 2 1 0 R R R/W R 0 0 0 0 ExCA I/O card detect and general control Register: Type: Offset: ExCA card detect and general control Read-only, Write-only, Read/Write (see individual bit descriptions) CardBus socket address + 816h: Card A ExCA offset 16h Card B ExCA offset 56h Default: XX00 0000b Description: This register controls how the ExCA registers for the socket respond to card removal, as well as reports the status of VS1 and VS2 at the PC Card interface. Refer to Table 61 for a complete description of the register contents. Table 61. ExCA Card Detect and General-Control Register (Index 16h) BIT 7 6 5 SIGNAL VS2STAT VS1STAT SWCSC TYPE FUNCTION R VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have a default value. 0 = VS2 low 1 = VS2 high R VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have a default value. 0 = VS1 low 1 = VS1 high W Software card detect interrupt. If the card detect enable bit in the card status change interrupt configuration register is set, then writing a 1 to bit 5 causes a card detect card status change interrupt for the associated card socket. If the card detect enable bit is cleared to 0 in the card status change interrupt configuration register, then writing a 1 to the software card detect interrupt bit has no effect. A read operation of bit 5 always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the global control register is set and a 1 is written to clear bit 3 of the ExCA card status change interrupt register, then this bit also is cleared. Card detect resume enable. If bit 4 is set to 1 and once a card detect change has been detected on CD1 and CD2 inputs, then RI_OUT goes from high to low. RI_OUT remains low until the card status change bit in the card status change register is cleared. If this bit is a 0, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled 4 CDRESUME R/W 3–2 RSVD R 1 REGCONFIG R/W 0 RSVD R Reserved. Bits 3–2 return 0s when read. Writes have no effect. Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers on card removal (default) 1 = Reset ExCA registers on card removal Reserved. Bit 0 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 97 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA global-control register (index 1Eh) Bit 7 6 5 4 Type R R R R/W Default 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA global control Register: Type: Offset: ExCA global control Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 81Eh: Card A ExCA offset 1Eh Card B ExCA offset 5Eh Default: 00h Description: This register controls both PC Card sockets and is not duplicated for each socket. The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. Refer to Table 62 for a complete description of the register contents. Table 62. ExCA Global-Control Register (Index 1Eh) BIT SIGNAL TYPE 7–5 RSVD R 4 INTMODEB R/W Level/edge interrupt mode select – card B. Bit 4 selects the signaling mode for the PCI1251B host interrupt for card B interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. R/W Level/edge interrupt mode select – card A. Bit 3 selects the signaling mode for the PCI1251B host interrupt for card A interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. R/W Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA card status change register. This bit is encoded as: 0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit write back of 1. R/W Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1251B host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. R/W Power-down mode select. When bit 0 is set to 1, the PCI1251B is in power-down mode. In power-down mode, the PCI1251B card outputs are placed in a high-impedance state until an active cycle is executed on the card interface. Following an active cycle, the outputs are again placed in a high-impedance state. The PCI1251B still receives DMA requests, functional interrupts, and/or card status change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded as: 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled. 3 2 1 0 98 INTMODEA IFCMODE CSCMODE PWRDWN FUNCTION Reserved. Bits 7–5 returns 0s when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 ExCA memory window 0–4 page register (index 40h, 41h, 42h, 43h, 44h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA memory window 0–4 page Register: Type: Offset: Default: Description: ExCA memory window 0–4 page Read/Write CardBus socket address + 840h 841h, 842h, 843h, 844h 00h The upper eight bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16-Mbyte regions in the 4-Gbyte PCI address space. These registers are only accessible when the ExCA registers are memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 99 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 CardBus socket registers (functions 0 and 1) The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1251B provides the CardBus socket/ExCA base address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate base address register for accessing the CardBus socket registers (see Figure 18). Table 63 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. The PCI1251B implements an additional register at offset 20h that provides power management control for the socket. Host Memory Space PCI1251B Configuration Registers Offset Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address CardBus Socket A Registers 10h 00h 20h 800h 16-Bit Legacy-Mode Base Address CardBus Socket B Registers 20h ExCA Registers Card A 44h 800h 844h ExCA Registers Card B 844h NOTE: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1. Figure 19. Accessing CardBus Socket Registers Through PCI Memory Table 63. CardBus Socket Registers REGISTER NAME 100 OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket event Name Socket event Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket event Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 00h 0000 0000h This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an interrupt is generated (but not masked) based on any bit set. Refer to Table 64 for a complete description of the register contents. Table 64. Socket Event Register BIT SIGNAL TYPE FUNCTION 31–4 RSVD R 3 PWREVENT R/W Power cycle. Bit 3 is set when the PCI1251B detects that the PWRCYCLE bit in the socket present-state register has changed. This bit is cleared by writing a 1. 2 CD2EVENT R/W CCD2. Bit 2 is set when the PCI1251B detects that the CDETECT2 field in the socket present-state register has changed. This bit is cleared by writing a 1. 1 CD1EVENT R/W CCD1. Bit 3 is set when the PCI1251B detects that the CDETECT1 field in the socket present-state register has changed. This bit is cleared by writing a 1. 0 CSTSEVENT R/W CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1. Reserved. Bits 31–4 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 101 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket mask register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket mask Name Socket mask Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket mask Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 04h 0000 0000h This register allows software to control the CardBus card events that generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register. Refer to Table 65 for a complete description of the register contents. Table 65. Socket Mask Register BIT SIGNAL TYPE 31–4 RSVD R 3 2–1 0 102 PWRMASK CDMASK CSTSMASK FUNCTION Reserved. Bits 31–4 return 0s when read. R/W Power cycle. Bit 3 masks the PWRCYCLE bit in the socket present state register from causing a status change interrupt. 0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt. R/W Card detect mask. Bits 2–1 mask the CDETECT1 and CDETECT2 bits in the socket present-state register from causing a CSC interrupt. 00 = Insertion/removal does not cause CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes CSC interrupt. R/W CSTSCHG mask. Bit 0 masks the CARDSTS field in the socket present-state register from causing a CSC interrupt. 0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket present-state register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 1 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket present state Name Socket present state Type R R R R R R R R R R R R R/W R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X Register: Type: Offset: Default: Description: Socket present state Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 08h 3000 000Xh This register reports information about the socket interface. Writes to the socket force event register are reflected here, as well as general socket interface status. Information about PC Card VCC support and card type is only updated at each insertion. Also, the PCI1251B uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected in this register. Refer to Table 66 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 103 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 66. Socket Present-State Register BIT SIGNAL TYPE FUNCTION 31 YVSOCKET R YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI1251B does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event register. This bit is hardwired to 0. 30 XVSOCKET R XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI1251B does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event register. This bit is hardwired to 0. 29 3VSOCKET R 3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The PCI1251B does support 3.3-V VCC; therefore, this bit is always set unless overridden by bit 6 of the device control register. 28 5VSOCKET R 5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The PCI1251B does support 5-V VCC; therefore, this bit is always 1. 27–14 RSVD R Reserved. Bits 27–14 return 0s when read. 13 YVCARD R YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V. This bit can be set by writing to the corresponding bit in the socket force event register. 12 XVCARD R XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V. This bit can be set by writing to the corresponding bit in the socket force event register. 11 3VCARD R 3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V. This bit can be set by writing to the corresponding bit in the socket force event register. 10 5VCARD R 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V. This bit can be set by writing to the corresponding bit in the socket force event register. 9 BADVCCREQ R Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software 8 DATALOST R Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1251B. 0 = Normal operation (default) 1 = Potential data loss due to card removal R Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected 7 104 NOTACARD 6 IREQCINT R READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface. 0 = READY(IREQ)//CINT low 1 = READY(IREQ)//CINT high 5 CBCARD R CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 4 16BITCARD R 16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 3 PWRCYCLE R/W Power cycle. Bit 3 indicates that the status of each card powering request. This bit is encoded as: 0 = Socket powered down (default) 1 = Socket powered up 2 CDETECT2 R CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 low (PC Card may be present) 1 = CCD2 high (PC Card not present) 1 CDETECT1 R CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 low (PC Card may be present) 1 = CCD1 high (PC Card not present) 0 CARDSTS R CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface. 0 = CSTSCHG low 1 = CSTSCHG high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket force event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket force event Name Socket force event Type R W W W W W W W W R W W W W W W Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Type: Offset: Default: Description: Socket force event Read-only, Write-only (see individual bit descriptions) CardBus socket address + 0Ch 0000 00XXh This register is used to force changes to the socket event register and the socket present state register. The CVSTEST bit in this register must be written when forcing changes that require card interrogation. Refer to Table 67 for a complete description of the register contents. Table 67. Socket Force Event Register BIT SIGNAL TYPE 31–15 RSVD R Reserved. Bits 31–15 return 0s when read. FUNCTION 14 CVSTEST W Card VS test. When bit 14 is set, the PCI1251B reinterrogates the PC Card, updates the socket present state register, and reenables the socket power control. 13 FYVCARD W Force YV card. Writes to bit 13 cause the YVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 12 FXVCARD W Force XV card. Writes to bit 12 cause the XVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 11 F3VCARD W Force 3-V card. Writes to bit 11 cause the 3VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 10 F5VCARD W Force 5-V card. Writes to bit 10 cause the 5VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 9 FBADVCCREQ W Force bad VCC request. Changes to the BADVCCREQ bit in the socket present state register can be made by writing to bit 9. 8 FDATALOST W Force data lost. Writes to bit 8 cause the DATALOST bit in the socket present state register to be written. 7 FNOTACARD W Force not a card. Writes to bit 7 cause the NOTACARD bit in the socket present state register to be written. 6 RSVD R Reserved. Bit 6 returns 0 when read. 5 FCBCARD W Force CardBus card. Writes to bit 5 cause the CBCARD bit in the socket present state register to be written. 4 F16BITCARD W Force 16-bit card. Writes to bit 4 cause the 16BITCARD bit in the socket present state register to be written. 3 FPWRCYCLE W Force power cycle. Writes to bit 3 cause the PWREVENT bit in the socket event register to be written, and the PWRCYCLE bit in the socket present state register is unaffected. 2 FCDETECT2 W Force CCD2. Writes to bit 2 cause the CD2EVENT bit in the socket event register to be written, and the CDETECT2 bit in the socket present state register is unaffected. 1 FCDETECT1 W Force CCD1. Writes to bit 1 cause the CD1EVENT bit in the socket event register to be written, and the CDETECT1 bit in the socket present state register is unaffected. 0 FCARDSTS W Force CSTSCHG. Writes to bit 0 cause the CSTSEVENT bit in the socket event register to be written, and the CARDSTS bit in the socket present state register is unaffected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 105 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket control register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket control Name Socket control Type R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket control Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 10h 0000 0000h This register provides control of the voltages applied to the socket and instructions for CB CLKRUN protocol. The PCI1251B ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. Refer to Table 68 for a complete description of the register contents. Table 68. Socket Control Register BIT SIGNAL TYPE 31–8 RSVD R 7 STOPCLK R/W VCC control. Bits 6–4 are used to request card VCC changes. 000 = Request power off (default) 001 = Reserved 010 = Request VCC = 5 V 011 = Request VCC = 3.3 V 100 = Request VCC = X.X V 101 = Request VCC = Y.Y V 110 = Reserved 111 = Reserved VCCCTRL R/W 3 RSVD R 106 VPPCTRL Reserved. Bits 31–8 return 0s when read. CB CLKRUN protocol instructions. 0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock. 1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle. 6–4 2–0 FUNCTION R/W Reserved. Bit 3 returns 0 when read. VPP control. Bits 2–0 are used to request card VPP changes. 000 = Request power off (default) 001 = Request VPP = 12 V 010 = Request VPP = 5 V 011 = Request VPP = 3.3 V 100 = Request VPP = X.X V 101 = Request VPP = Y.Y V 110 = Reserved 111 = Reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 socket power management register Bit 31 30 29 28 27 26 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 25 24 23 22 21 20 19 18 17 16 R R R R R R R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket power management Name Socket power management Type R R R R R R R R R R R R R R R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket power management Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 20h 0000 0000h This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. Table 69. Socket Power Management Register BIT SIGNAL TYPE FUNCTION 31–26 RSVD R Reserved. Bits 31–26 return 0s when read. 25 SKTACCES R Socket access status. This bit provides information on when a socket access has occurred. This bit is cleared by a read access. 0 = A PC card access has not occurred (default). 1 = A PC card access has occurred. 24 SKTMODE R Socket mode status. This bit provides clock mode information. 0 = Clock is operating normally. 1 = Clock frequency has changed. 23–17 RSVD R Reserved. Bits 23–17 return 0s when read. 16 CLKCTRLEN R/W 15–1 RSVD R 0 CLKCTRL R/W CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled. 0 = Clock control is disabled (default). 1 = Clock control is enabled. Reserved. Bits 15–1 return 0s when read. CardBus clock control. This bit determines whether the CB CLKRUN protocol will attempt to stop or slow the CB clock during idle states. Bit 16 enables this bit. 0 = Allows CB CLKRUN protocol to stop the CB clock (default). 1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 107 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 distributed DMA (DDMA) registers The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in PCI I/O space where the DDMA registers reside. The names and locations of these registers are summarized in Table 70. These PCI1251B register definitions are identical to those registers of the same name in the Intel 8237 DMA controller; however, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. The similarity between the register models retains some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when it forwards legacy DMA writes to DMA channels. While the DMA register definitions are identical to those in the 8237 of the same name, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases, the PCI1251B implements these obsolete register bits as read-only nonfunctional bits. The reserved registers shown in Table 70 are implemented as read-only and return 0s when read. Writes to reserved registers have no effect. Table 70. DDMA Registers TYPE R W R W 108 DMA BASE ADDRESS OFFSET REGISTER NAME Reserved Page Reserved Reserved R N/A W Mode R Multichannel W Mask Reserved Reserved Current address 00h Base address Current count 04h Base count N/A Status Request Command N/A Master clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Reserved 08h 0Ch PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 DMA current address/base address register Bit 15 14 13 R/W R/W R/W R/W Default 0 0 0 0 Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DMA current address/base address Name Type 12 DMA current address/base address Register: Type: Offset: Default: Size: Description: DMA current address/base address Read/Write DMA base address + 00h 0000h Two bytes This register is used to set the starting (base) memory address of a DMA transfer. Reads from this register indicate the current memory address of a direct memory transfer. For the 8-bit DMA transfer mode, the current address register contents are presented on AD15–AD0 of the PCI bus during the address phase. Bits 7–0 of the page register are presented on AD23–AD16 of the PCI bus during the address phase. For the 16-bit DMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the page register are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored. DMA page register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 Name Type Default DMA page Register: Type: Offset: Default: Size: Description: DMA page Read/Write DMA base address + 02h 00h One byte This register is used to set the upper byte of the address of a DMA transfer. Details of the address represented by this register are explained in DMA current address/base address register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 109 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 DMA current count/base count register Bit 15 14 13 R/W R/W R/W R/W Default 0 0 0 0 Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name 12 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DMA current count/base count Type Name DMA current count/base count Type Default Register: Type: Offset: Default: Size: Description: DMA current count/base count Read/Write DMA base address + 04h 0000h Two bytes This register is used to set the total transfer count, in bytes, of a direct memory transfer. Reads to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer and decremented by 2 after each transfer in the 16-bit transfer mode. DMA command register Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 3 2 1 0 R R/W R R 0 0 0 0 DMA command Register: Type: Offset: Default: Size: Description: DMA command Read-only, Read/Write (see individual bit descriptions) DMA base address + 08h 00h One byte This register is used to enable and disable the DMA controller. Bit 2, the only read/write bit, defaults to 0, enabling the DMA controller. All other bits are reserved. Refer to Table 71 for a complete description of the register contents. Table 71. DMA Command Register BIT TYPE 7–3 R 2 R/W 1–0 R 110 FUNCTION Reserved. Bits 7–3 return 0s when read. DMA controller enable. Bit 2 enables and disables the distributed DMA slave controller in the PCI1251B and defaults to the enabled state. 0 = DMA controller enabled (default) 1 = DMA controller disabled Reserved. Bits 1–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 DMA status register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 0 Name DMA status Register: Type: Offset: Default: Size: Description: DMA status Read-only (see individual bit descriptions) DMA base address + 08h 00h One byte This register indicates the terminal count and DMA request (DREQ) status. Refer to Table 72 for a complete description of the register contents. Table 72. DMA Status Register BIT 7–4 3–0 SIGNAL TYPE FUNCTION R Channel request. In the 8237, bits 7–4 indicate the status of DREQ of each DMA channel. In the PCI1251B, these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set when the PC Card asserts DREQ and are reset when DREQ is deasserted. The status of the mask bit in the multichannel mask register has no effect on these bits. R Channel terminal count. The 8327 uses bits 3–0 to indicate the TC status of each of its four DMA channels. In the PCI1251B, these bits report information about a single DMA channel; therefore, all four of these register bits indicate the TC status of the single socket being serviced by this register. All four bits are set when the TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset. DREQSTAT TC DMA request register Bit 7 6 5 4 3 2 1 0 Type W W W W W W W W Default 0 0 0 0 0 0 0 0 Name DMA request Register: Type: Offset: Default: Size: Description: DMA request Write-only DMA base address + 09h 00h One byte This register is used to request a DDMA transfer through software. Any write to this register enables software requests, and this register is to be used in block mode only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 111 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 DMA mode register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R 0 0 0 0 0 Name Type Default DMA mode Register: Type: Offset: Default: Size: Description: DMA mode Read-only, Read/Write (see individual bit descriptions) DMA base address + 0Bh 00h One byte This register is used to set the DMA transfer mode. to Table 73 for a complete description of the register contents. Table 73. DMA Mode Register BIT 7–6 SIGNAL DMAMODE TYPE R/W 5 INCDEC R/W Address increment/decrement. The PCI1251B uses bit 5 to select the memory address in the current address/base address register to increment or decrement after each data transfer. This is in accordance with the 8237 use of this register bit, and is encoded as follows: 0 = Addresses increment (default). 1 = Addresses decrement. 4 AUTOINIT R/W Auto initialization 0 = Auto initialization disabled (default) 1 = Auto initialization enabled Transfer type. Bits 3–2 select the type of direct memory transfer to be performed. A memory write transfer moves data from the PCI1251B PC Card interface to memory, and a memory read transfer moves data from memory to the PCI1251B PC Card interface. The field is encoded as: 00 = No transfer selected (default) 01 = Write transfer 10 = Read transfer 11 = Reserved 3–2 XFERTYPE R/W 1–0 RSVD R 112 FUNCTION Mode select. The PCI1251B uses bits 7–6 to determine the transfer mode. 00 = Demand mode select (default) 01 = Single mode select 10 = Block mode select 11 = Reserved Reserved. Bits 1–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 DMA master clear register Bit 7 6 5 4 Type W W W W Default 0 0 0 0 Name 3 2 1 0 W W W W 0 0 0 0 DMA master clear Register: Type: Offset: Default: Size: Description: DMA master clear Write-only DMA base address + 0Dh 00h One byte This register is used to reset the DDMA controller and resets all DDMA registers. DMA multichannel/mask register Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3 2 1 0 R R R R 0 0 0 0 DMA multichannel/mask Register: Type: Offset: Default: Size: Description: DMA multichannel/mask Read-only (see individual bit descriptions) DMA base address + 0Fh 00h One byte The PCI1251B uses only the least significant bit of this register to mask the PC Card DMA channel. The PCI1251B sets the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket’s DMA controller or reenabling the mask bit. Refer to Table 74 for a complete description of the register contents. Table 74. DMA Multichannel/Mask Register BIT SIGNAL TYPE 7–1 RSVD R Reserved. Bits 7–1 returns 0s when read. FUNCTION 0 MASKBIT R Mask select. Bit 0 masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally. 0 = DDMA service provided on card DREQ 1 = Socket DREQ signal ignored (default) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 113 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Clamping voltage range, VCCP, VCCA, VCCB, VCCZ, VCCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCB + 0.5 V ZV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCZ + 0.5 V MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCB + 0.5 V ZV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCZ + 0.5 V MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. ZV terminals are measured with respect to VCCZ, and miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. ZV terminals are measured with respect to VCCZ, and miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 114 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 recommended operating conditions (see Note 3) OPERATION VCC Commercial Core voltage VCCP PCI I/O clamping voltage Commercial VCC(A/B) PC Card I/O clamping voltage Commercial VCCZ ZV port I/O clamping voltage Commercial VCCI Miscellaneous I/O clamping voltage Commercial MAX 3.3 V 3 3.3 3.6 3.3 V 3 3.3 3.6 4.75 5 5.25 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V 5V 3.3 V PC Card Hi h l l input i t voltage lt High-level NOM 3.3 V PCI VIH† MIN 5V ZV Input transition time (tr and tf) TA TJ# Operating ambient temperature range 5.25 3 3.3 3.6 4.75 5 5.25 0.5 VCCP 2 0.475 VCCA/B 2.4 VCCA/B VCCZ 5V 0 0.8 3.3 V 0 0.325 VCCA/B 5V 0 0.8 0 0.8 0 0.8 0 0.8 PCI 0 PC Card 0 ZV 0 VCCP VCCA/B VCCZ MISC‡ 0 Fail safe§ 0 PCI 0 PC Card 0 ZV 0 MISC‡ 0 Fail safe§ 0 PCI and PC Card 1 VCC 4 ZV, miscellaneous, and fail safe 0 6 0 V V V V VCCA/B 0.3 VCCP 3.3 V V VCCP VCCP 0 Fail safe§ tt 3.6 5 3.3 V MISC‡ Output voltage 3.3 VCCI VCC ZV VO¶ 3 4.75 2 PC Card Input voltage 5.25 2 PCI VI 3.6 5 3.3 V Fail safe§ L l l iinputt voltage lt Low-level 3.3 2 MISC‡ VIL† 3 4.75 UNIT V V V VCCI VCC VCC VCC VCC VCC 25 70 V ns °C °C † Applies to external inputs and bidirectional buffers without hysteresis ‡ Miscellaneous GFN pins are V13, W13, Y13, U12, V12, W12, U11, V11, W11, Y11, Y10, W10, Y09, W09, V09, U09, Y08, all IRQMUXx pins, LEDAx pins, SUSPEND, SPKROUT, RI_OUT, INTA, INTB, and power switch control pins. § Fail-safe GFN pins are A11, B14, C09, G03, H20, U03, W06, and Y03 (card detect and voltage sense pins). ¶ Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. Virtual junction temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 115 115 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS OPERATION 3.3 V PCI 5V VOH High level output voltage (see Note 4) High-level IOH = –2 mA 5V IOH = –0.15 mA 2.4 ZV IOH = –4 mA VCC–0.6 MISC IOH = –4 mA VCC–0.6 IOL = 6 mA V 0.1 VCC 0.55 3.3 V IOL = 0.7 mA 0.1 VCC 5V IOL = 0.7 mA 0.55 PC Card Low-level output voltage IOL = 1.5 mA ZV IOL = 4 mA 0.5 MISC IOL = 4 mA 0.5 IOL = 12 mA 0.5 VI = VCC VI = VCC –1 VI = VCC† VI = VCC† 10 SERR IOZL 3-state output,, high-impedance g state current (see Note 4) Output pins IOZH 3-state output,, high-impedance g state current Output pins IIL Low-level input current 3.6 V 5.25 V 3.6 V 5.25 V –1 25 Input pins VI = GND –1 I/O pins VI = GND –10 Latch –2 3.6 V VI = GND VI = VCC‡ 5.25 V VI = VCC‡ 20 3.6 V VI = VCC‡ VI = VCC‡ 10 Input pins High-level input current (see Note 5) I/O pins Fail-safe pins 5.25 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V µA µA µA 10 25 VI = VCC 10 † For PCI pins, VI = VCCP. For PC Card pins, VI = VCC(A/B). For ZV pins, VI = VCCZ. For miscellaneous pins, VI = VCCI. ‡ For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. NOTES: 4. VOH and IOL are not tested on SERR (GFN pin U19)and RI_OUT (GFN pin Y13) because they are open-drain outputs. 5. IIH is not tested on LATCH (GFN pin W12) because it is pulled up with an internal resistor. 116 3.6 V UNIT 2.4 0.9 VCC 5V MAX 0.9 VCC IOH = –0.15 mA 3.3 V IIH IOH = –0.5 mA MIN 3.3 V PC Card PCI VOL TEST CONDITIONS µA PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 20 and 21) ALTERNATE SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns ∆v/∆t Slew rate, PCLK tr, tf 1 tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN 100 ms trst-clk 4 V/ns PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4 and Figures 19 and 22) ALTERNATE SYMBOL PARAMETER tpd d g Propagation delayy time,, See Note 6 PCLK-to-shared signal valid delay time tval PCLK-to-shared signal invalid delay time tinv ten tdis Enable time, high impedance-to-active delay time from PCLK tsu th Setup time before PCLK valid Disable time, active-to-high impedance delay time from PCLK Hold time after PCLK high TEST CONDITIONS CL = 50 pF,, See Note 7 MIN MAX UNIT 11 ns 2 ton toff 2 ns tsu th 7 ns 0 ns 28 ns NOTES: 6. PCI shared signals are AD31–AD0, C/BE3–0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 117 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD‡ (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL From Output Under Test Test Point VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance. IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT VCC Timing Input (see Note A) 50% VCC High-Level Input 0V th tsu 90% VCC Data Input 10% VCC 50% VCC 50% VCC Low-Level Input 0V tf VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES 50% VCC tpd 50% VCC VOH 50% VCC VOL tpd Waveform 1 (see Notes B and C) VOH 50% VCC VOL Waveform 2 (see Notes B and C) tPLZ 50% VCC tPHZ tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 50% VCC 0V tpd 50% VCC VCC 50% VCC 0V VCC tPZL 50% VCC tpd Out-of-Phase Output Output Control (low-level enabling) 0V In-Phase Output 50% VCC VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC VCC 50% VCC 0V tw VCC tr Input (see Note A) 50% VCC 50% VCC VCC ≅ 50% VCC VOL + 0.3 V VOL VOH VOH – 0.3 V ≅ 50% VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values. Figure 20. Load Circuit and Voltage Waveforms 118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PCI BUS PARAMETER MEASUREMENT INFORMATION thigh tlow 2V 2 V MIN Peak-to-Peak 0.8 V tf tr tcyc Figure 21. PCLK Timing Waveform PCLK trst RSTIN tsrst-clk Figure 22. RSTIN Timing Waveforms PCLK 1.5 V tval PCI Output tinv 1.5 V Valid ton toff PCI Input Valid tsu th Figure 23. Shared Signals Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 119 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PC Card cycle timing The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. The PC Card address setup and hold times are a function of the wait-state bits. Table 75 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 76 and Table 77 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 78 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 75. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 3/90 Memory WS1 0 2/60 Memory WS1 1 4/120 Table 76. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles WAIT-STATE BITS ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 19/570 1 X 23/690 0 1 7/210 00 0 19/570 01 X 23/690 10 X 23/690 11 X 23/690 00 1 7/210 WS I/O Memory Table 77. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles WAIT-STATE BITS WS I/O Memory 120 ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 7/210 1 X 11/330 0 1 N/A 00 0 9/270 01 X 13/390 10 X 17/510 11 X 23/630 00 1 5/150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 Table 78. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 2/60 Memory WS1 0 2/60 Memory WS1 1 3/90 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 5 and Figure 24) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, CE1 and CE2 before WE/OE low T1 60 ns Setup time, CA25–CA0 before WE/OE low T2 ns tsu tpd Setup time, REG before WE/OE low T3 tsu(A)+2PCLK 90 Propagation delay time, WE/OE low to WAIT low T4 tw th Pulse duration, WE/OE low T5 Hold time, WE/OE low after WAIT high T6 th tsu Hold time, CE1 and CE2 after WE/OE high T7 Setup time (read), CDATA15–CDATA0 valid before OE high T8 th th Hold time (read), CDATA15–CDATA0 valid after OE high T9 0 ns Hold time, CA25–CA0 and REG after WE/OE high T10 ns tsu th Setup time (write), CDATA15–CDATA0 valid before WE low T11 th(A)+1PCLK 60 Hold time (write), CDATA15–CDATA0 valid after WE low T12 240 ns ns ns 200 ns ns 120 ns ns ns NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock. timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 25) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, REG before IORD/IOWR low T13 Setup time, CE1 and CE2 before IORD/IOWR low tsu tpd Setup time, CA25–CA0 valid before IORD/IOWR low Propagation delay time, IOIS16 low after CA25–CA0 valid T16 tpd tw Propagation delay time, IORD low to WAIT low T17 35 ns Pulse duration, IORD/IOWR low T18 TcA ns th th Hold time, IORD low after WAIT high T19 Hold time, REG low after IORD high T20 th th Hold time, CE1 and CE2 after IORD/IOWR high Hold time, CA25–CA0 after IORD/IOWR high tsu th Setup time (read), CDATA15–CDATA0 valid before IORD high T23 Hold time (read), CDATA15–CDATA0 valid after IORD high tsu th Setup time (write), CDATA15–CDATA0 valid before IOWR low Hold time (write), CDATA15–CDATA0 valid after IOWR high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 60 ns T14 60 ns T15 tsu(A)+2PCLK ns 35 ns ns 0 ns T21 120 ns T22 th(A)+1PCLK 10 ns T24 0 ns T25 90 ns T26 90 ns ns 121 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 26) ALTERNATE SYMBOL PARAMETER BVD2 low to SPKROUT low tpd d BVD2 high to SPKROUT high Propagation delay time IREQ to IRQ15–IRQ3 30 30 30 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T10 REG CE1, CE2 T1 WE, OE T5 T7 T3 T2 T6 T4 WAIT T12 T11 CDATA15–CDATA0 (write) T8 T9 CDATA15–CDATA0 (read) With no wait state With wait state Figure 24. PC Card Memory Cycle 122 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 30 T27 T28 STSCHG to IRQ15–IRQ3 MIN ns PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T16 T22 IOIS16 REG T20 CE1, CE2 T14 IORD, IOWR T13 T15 T18 T21 T19 T17 WAIT T26 T25 CDATA15–CDATA0 (write) T23 T24 CDATA15–CDATA0 (read) With no wait state With wait state Figure 25. PC Card I/O Cycle BVD2 T27 SPKROUT IREQ T28 IRQ15–IRQ3 Figure 26. Miscellaneous PC Card Delay Times POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 123 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 MECHANICAL DATA GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 24,70 SQ 24,00 24,13 TYP 1,27 0,635 0,635 1,27 Y W V U T R P N M L K J H G F E D C B A 1 3 2 2,32 1,92 5 4 7 6 9 8 10 11 13 15 17 19 12 14 16 18 20 0,40 0,30 Seating Plane 0,70 0,50 0,80 0,60 0,10 M 0,15 4040185-2/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 124 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 MECHANICAL DATA GJG (S-PBGA-N257) PLASTIC BALL GRID ARRAY 16,10 SQ 15,90 14,40 TYP 0,80 W V U T R P N M L K J H G F E D C B A 0,80 1 3 2 0,95 0,85 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4173511/A 08/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration Micro Star is a trademark of Texas Instruments Incorporated. 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