TI PCI1510GVF

 Data Manual
December 2004
Connectivity Solutions
SCPS071E
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Contents
Section
1
2
3
Title
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
1.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
1.5
Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
1.6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.7
PCI1510 Data Manual Document History . . . . . . . . . . . . . . . . . . . . . . . 1−3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1
PCI1510 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
2.2
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1
Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.2
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.3
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.4
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3−2
3.4.1
PCI GRST Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.4.2
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
3.4.3
Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . . 3−3
3.5
PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3.5.1
PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3−4
3.5.2
Parallel Power-Switch Interface (TPS2211A) . . . . . . . . . . . 3−4
3.5.3
Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3.5.4
Standardized Zoomed-Video Register Model . . . . . . . . . . . 3−6
3.5.4.1
Zoomed-Video Card Insertion and Configuration
Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.5.5
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.5.6
Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.5.7
SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3−8
3.5.8
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.5.9
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.6
Serial-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.6.1
Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . 3−9
3.6.2
Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
3.6.3
Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3−12
3.6.4
Accessing Serial-Bus Devices Through Software . . . . . . . 3−13
iii
Section
3.7
4
iv
Title
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
PC Card Functional and Card Status Change Interrupts .
3.7.2
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5
Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . .
3.7.6
SMI Support in the PCI1510 Controller . . . . . . . . . . . . . . . .
3.8
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Integrated Low-Dropout Voltage Regulator (LDO-VR) . . . .
3.8.2
Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3
CardBus PC Card Power Management . . . . . . . . . . . . . . . .
3.8.4
16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . .
3.8.5
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.6
Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . .
3.8.7
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8
PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9
CardBus Bridge Power Management . . . . . . . . . . . . . . . . . .
3.8.10
ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.11
Master List of PME Context Bits and Global Reset-Only
Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
3−13
3−13
3−15
3−15
3−16
3−16
3−16
3−17
3−17
3−17
3−17
3−17
3−18
3−18
3−19
3−19
3−20
3−21
3−22
4−1
4−1
4−2
4−2
4−3
4−4
4−4
4−5
4−5
4−5
4−5
4−6
4−6
4−6
4−7
4−8
4−8
4−8
4−8
4−9
4−9
4−10
Section
4.22
4.23
4.24
4.25
4.26
4.27
4.28
4.29
4.30
4.31
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
5
Title
I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card 16-Bit I/F Legacy-Mode Base Address Register . . . . . . . . .
System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . .
Power-Management Control/Status Register . . . . . . . . . . . . . . . . . . . .
Power-Management Control/Status Register Bridge Support
Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . .
4.42 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . .
4.43 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 Serial-Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 Serial-Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial-Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial-Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . .
5.2
ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . .
5.5
ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
ExCA Card Status-Change Interrupt Configuration Register . . . . . . .
5.7
ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . .
5.8
ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . .
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers . . .
Page
4−10
4−11
4−11
4−12
4−13
4−13
4−13
4−14
4−16
4−17
4−18
4−19
4−20
4−20
4−20
4−21
4−22
4−23
4−23
4−24
4−25
4−26
4−26
4−27
4−27
4−28
4−29
5−1
5−4
5−5
5−6
5−8
5−9
5−10
5−11
5−12
5−13
5−13
5−13
5−13
5−14
v
Section
6
7
8
vi
Title
Page
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers . . . 5−14
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers . . . . 5−15
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers . . . 5−15
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers . . 5−16
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers . 5−16
5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5−17
5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−18
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5−19
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5−19
5.23 ExCA Memory Windows 0−4 Page Registers . . . . . . . . . . . . . . . . . . . 5−19
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
6.1
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
6.2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3
6.3
Socket Present-State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4
6.4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5
6.5
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7
6.6
Socket Power-Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . 6−8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
7.1
Absolute Maximum Ratings Over Operating Temperature Ranges . 7−1
7.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2
7.3
Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3
7.4
PCI Clock/Reset Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 7−3
7.5
PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . 7−4
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1
List of Illustrations
Figure
2−1
2−2
2−3
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
3−11
3−12
3−13
3−14
3−15
3−16
3−17
5−1
5−2
6−1
Title
PCI1510 GGU-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
PCI1510 GVF-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
PCI1510 PGE-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
PCI1510 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TPS2211A Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zoomed Video Implementation Using the PCI1510 Controller . . . . . . . . .
Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . .
Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . .
Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Protocol − Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Protocol − Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . .
IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . .
Page
2−1
2−2
2−3
3−1
3−2
3−5
3−5
3−6
3−8
3−9
3−10
3−10
3−11
3−11
3−11
3−12
3−16
3−18
3−19
3−21
5−1
5−1
6−1
vii
List of Tables
Table
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
2−10
2−11
2−12
2−13
2−14
2−15
2−16
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
3−11
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
viii
Title
Signal Names Sorted by PGE Terminal Number . . . . . . . . . . . . . . . . . . . .
Signal Names Sorted by GGU Terminal Number . . . . . . . . . . . . . . . . . . . .
Signal Names Sorted by GVF Terminal Number . . . . . . . . . . . . . . . . . . . .
CardBus PC Card Signal Names Sorted Alphabetically to Device
Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit PC Card Signal Names Sorted Alphabetically to Device
Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . .
16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . .
CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . .
CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . .
CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . .
PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . .
Zoomed-Video Card Interrogation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register- and Bit-Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI1510 Registers Used to Program Serial-Bus Devices . . . . . . . . . . . . .
Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . .
SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements for Internal/External 2.5-V Core Power Supply . . . . . . . . .
Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multifunction Routing Register Description . . . . . . . . . . . . . . . . . . . . . . . . .
Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
2−4
2−6
2−8
2−11
2−13
2−15
2−15
2−16
2−17
2−18
2−19
2−20
2−21
2−22
2−23
2−24
3−4
3−7
3−7
3−9
3−12
3−13
3−14
3−14
3−16
3−17
3−20
4−1
4−2
4−3
4−4
4−7
4−12
4−14
4−16
4−17
Table
Title
Page
4−10
4−11
4−12
4−13
4−14
4−15
Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Management Capabilities Register Description . . . . . . . . . . . . . . .
Power-Management Control/Status Register Description . . . . . . . . . . . . .
Power-Management Control/Status Register Bridge Support Extensions
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . .
General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . .
General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . .
Serial-Bus Control and Status Register Description . . . . . . . . . . . . . . . . . .
ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Identification and Revision Register Description . . . . . . . . . . . . . . .
ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Power Control Register Description—82365SL Support . . . . . . . .
ExCA Power Control Register Description—82365SL-DF Support . . . . .
ExCA Interrupt and General Control Register Description . . . . . . . . . . . .
ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . .
ExCA Card Status-Change Interrupt Configuration Register
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . .
ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . .
ExCA Memory Windows 0−4 Start-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Memory Windows 0−4 End-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Card Detect and General Control Register Description . . . . . . . . .
ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . .
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket Present-State Register Description . . . . . . . . . . . . . . . . . . . . . . . . .
Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket Power-Management Register Description . . . . . . . . . . . . . . . . . . .
4−18
4−19
4−20
4−21
4−22
4−16
4−17
4−18
4−19
4−20
4−21
4−22
4−23
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
5−13
5−14
5−15
6−1
6−2
6−3
6−4
6−5
6−6
6−7
4−23
4−24
4−25
4−26
4−26
4−27
4−27
4−28
4−29
5−2
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
5−14
5−15
5−16
5−17
5−18
6−1
6−2
6−3
6−4
6−6
6−7
6−8
ix
x
1 Introduction
1.1 Description
The Texas Instruments PCI1510 device, a 144-terminal or a 209-terminal single-slot CardBus controller designed
to meet the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges, is an ultralow-power
high-performance PCI-to-CardBus controller that supports a single PC card socket compliant with the PC Card
Standard (rev. 7.2). The controller provides features that make it the best choice for bridging between PCI and PC
Cards in both notebook and desktop computers. The PC Card Standard retains the 16-bit PC Card specification
defined in the PCI Local Bus Specification and defines the 32-bit PC Card, CardBus, capable of full 32-bit data
transfers at 33 MHz. The controller supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.
The controller is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The
controller is also compliant with PCI Bus Power Management Interface Specification (rev. 1.1).
All card signals are internally buffered to allow hot insertion and removal without external buffering. The controller
is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The controller internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting.
The controller can also be programmed to accept fast posted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1510 controller, such as a socket activity light-emitting
diode (LED) outputs, are discussed in detail throughout this document.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.
1.2 Features
The controller supports the following features:
•
A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball-grid array (GGU/ZGU) package,
or a 209-terminal PBGA (GVF/ZVF) package
•
2.5-V core logic and 3.3-V I/O with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling
environments
•
Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5-V power supply
•
Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
•
A single PC Card or CardBus slot with hot insertion and removal
•
Parallel interface to TI TPS2211A single-slot PC Card power switch
•
Burst transfers to maximize data throughput with CardBus Cards
•
Interrupt configurations: parallel PCI, serialized PCI, parallel ISA, and serialized ISA
•
Serial EEPROM interface for loading subsystem ID, subsystem vendor ID, and other configuration registers
•
Pipelined architecture for greater than 130-Mbps throughput from CardBus-to-PCI and from PCI-toCardBus
1−1
•
Up to five general-purpose I/Os
•
Programmable output select for CLKRUN
•
Five PCI memory windows and two I/O windows available for the 16-bit interface
•
Two I/O windows and two memory windows available to the CardBus socket
•
Exchangeable-card-architecture- (ExCA-) compatible registers are mapped in memory and I/O space
•
Intel 82365SL-DF and 82365SL register compatible
•
Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN
•
Socket activity LED terminal
•
PCI bus lock (LOCK)
•
Internal ring oscillator
1.3 Related Documents
•
•
•
•
•
•
•
•
Advanced Configuration and Power Interface (ACPI) Specification (revision 1.1)
PCI Bus Power Management Interface Specification (revision 1.1)
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (revision 0.6)
PCI to PCMCIA CardBus Bridge Register Description (Yenta) (revision 2.1)
PCI Local Bus Specification (revision 2.2)
PCI Mobile Design Guide (revision 1.0)
PC Card Standard (revision 7.2)
Serialized IRQ Support for PCI Systems (revision 6)
1.4 Trademarks
Intel is a trademark of Intel Corporation.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
1.5 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are listed
below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit
hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical
NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. RSVD indicates that the referenced item is reserved.
6. In Sections 4 through 6, the configuration space for the controller is defined. For each register bit, the
software access method is identified in an access column. The legend for this access column includes the
following entries:
r – read-only access
1−2
ru – read-only access with updates by the controller internal hardware
rw – read and write access
rcu – read access with the option to clear an asserted bit with a write-back of 1b including updates by
the controller internal hardware.
1.6 Ordering Information
ORDERING NUMBER
PCI1510
NAME
PC Card controller
VOLTAGE
3.3 V, 5-V tolerant I/Os
PACKAGE
144-terminal LQFP
144-ball PBGA (GGU or ZGU)
209-ball PBGA (GVF or ZVF)
1.7 PCI1510 Data Manual Document History
DATE
PAGE NUMBER
01/2003
2−23
Modified terminal number of CAD30 from 143 to 142 for PGE package
REVISION
01/2003
3−2
Added new subsection 3.4.1 to describe GRST during power up
01/2003
3−11
Modified byte-read diagram (Figure 3−12) to better reflect a read transaction to the EEPROM
01/2003
3−20
Modified the description of the power management capabilities register. This register is not a static
read-only register.
08/2003
1−3
Added lead-free (Pb, atomic number 82) MicroStar BGA package (ZGU) to ordering information
08/2003
2−1
Added description for ZGU package
08/2003
8−4
Added ZGU mechanical drawing
10/2003
1−1
Added GVF package to features
10/2003
1−3
Added GVF package to ordering information
10/2003
2−8
Added GVF terminal descriptions, Table 2−3
10/2003
8−2
Added GVF mechanical drawing.
07/2004
Chapters 1, 2, 8
Added RGVF, RZVF, and ZVF packages and pinout.
12/2004
Chapters 1, 2, 8
Removed RGVF and RZVF packages and pinout.
Added Section 1.5, Document Conventions
1−3
1−4
2 Terminal Descriptions
The PCI1510 controller is available in five packages, a 144-terminal quad flatpack (PGE), two 144-terminal MicroStar
BGA packages (GGU/ZGU), and two 209-terminal PBGA packages (GVF/ZVF). The GGU and ZGU packages are
mechanically and electrically identical, but the ZGU is a lead-free (Pb, atomic number 82) design. Throughout the
remainder of this manual, only the GGU package designator is used for either the GGU or ZGU package. The terminal
layout for the GGU package is shown in Figure 2−1. The GVF and ZVF packages are mechanically and electrically
identical, but the ZVF is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual, only
the GVF package designator is used for either the GVF or ZVF package. The terminal layout for the GVF package
is shown in Figure 2−2. The terminal layout with signal names for the PGE package is shown in Figure 2−3.
GGU PACKAGE
(TOP VIEW)
C
C
C
C
C
C
ÎÎ
ÎÎ
C
C
C
C
C
T
C
C
C
C
C
C
C
C
C
C
C
C
C
M
C
C
C
C
C
C
C
C
C
C
13
C
C
12
ÎÎ
ÎÎ
C
C
C
C
C
C
C
C
C
9
C
8
C
11
10
C
7
6
C
C
C
5
C
C
C
4
C
C
C
C
P
C
P
P
P
P
A
B
C
3
2
1
ÎÎ
ÎÎ
C
ÎÎ
ÎÎ
T
M
M
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Î
Î
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
F
G
H
J
K
L
P
PCI Interface
C
PC Card Interface
T
TPS Power Switch
M
MFUNC Pins
ÎÎ
ÎÎ
M
P
P
E
M
M
M
P
D
C
T
T
P
ÎÎ
ÎÎ
ÎÎ
Î
Î
P
P
M
N
VCC
Ground (GND)
Miscellaneous
Figure 2−1. PCI1510 GGU-Package Terminal Diagram
2−1
19
C
C
18
C
C
17
C
C
16
15
14
Î
Î
Î
Î
GVF PACKAGE
(TOP VIEW)
C
C
C
C
C
C
C
ÎÎ
ÎÎ
C
C
C
N
N
N
N
N
N
ÎÎ
ÎÎ
N
N
N
N
N
N
C
C
13
C
C
C
C
C
C
N
N
N
C
C
C
C
C
C
C
N
N
N
C
C
C
C
C
C
C
C
N
N
N
N
N
N
N
N
N
N
N
N
12
C
C
C
C
C
N
N
N
N
N
11
C
C
C
C
N
N
N
N
N
10
Î
C
C
C
C
C
N
N
N
N
N
9
C
C
C
C
C
N
P
P
P
P
8
Î
Î
C
C
C
C
P
P
P
P
N
N
N
N
P
P
P
P
N
N
T
N
M
P
P
P
T
T
N
M
M
P
P
7
6
N
5
4
M
P
P
P
P
P
P
P
P
P
P
P
P
T
3
N
M
P
2
P
P
N
Î
Î
M
M
P
P
D
E
F
H
J
A
P
ÎÎ
P
P
1
B
C
G
P
P
P
ÎÎ
ÎÎ
P
P
K
L
P
PCI Interface
C
PC Card Interface
T
TPS Power Switch
M
MFUNC Pins
P
P
P
ÎÎ
ÎÎ
M
P
N
P
P
P
P
P
P
P
R
ÎÎ
ÎÎ
VCC
Ground (GND)
Miscellaneous
N
No Connection
Figure 2−2. PCI1510 GVF-Package Terminal Diagram
2−2
N
T
U
V
W
2.1 PCI1510 Terminal Assignments
Figure 2−3 and Table 2−1 show the terminal assignments for the PGE package. Table 2−2 and Table 2−3 list the
terminal assignments for the GGU and GVF packages, respectively. The signal names for the PC Card slot are given
in a CardBus // 16-bit signal format. All tables are arranged in order by increasing terminal designator, which is
numeric for the PGE package and alphanumeric for the other packages. Table 2−4 and Table 2−5 list the CardBus
and 16-bit signal names, respectively, in alphanumerical order with the corresponding terminal numbers for each
package.
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
CTRDY//A22
CCLK//A16
CDEVSEL//A21
CGNT//WE
VCC
CSTOP//A20
CPERR//A14
CBLOCK//A19
CPAR//A13
CRSVD//A18
CC/BE1//A8
CAD16//A17
CAD14//A9
CAD15//IOWR
CAD13//IORD
GND
CAD12//A11
CAD11//OE
CAD10//CE2
CAD9//A10
CC/BE0//CE1
CAD8//D15
CAD7//D7
CLK_48_RSVD
CRSVD//D14
CAD5//D6
CAD6//D13
CAD3//D5
GND
CAD4//D12
CAD1//D4
CAD2//D11
CAD0//D3
CCD1//CD1
VCCD1
VCCD0
PGE PACKAGE
(TOP VIEW)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
143
144
VPPD1
VPPD0
VCC
MFUNC6
MFUNC5
MFUNC4
GRST
SUSPEND
MFUNC3
MFUNC2
VR_PORT
SPKROUT
GND
MFUNC1
MFUNC0
RI_OUT/PME
AD0
AD1
VCC
AD2
AD3
AD4
AD5
AD6
AD7
C/BE0
AD8
AD9
AD10
AD11
AD12
AD13
GND
AD14
AD15
C/BE1
REQ
GNT
AD31
AD30
AD29
AD28
AD27
GND
AD26
AD25
AD24
VCC
C/BE3
IDSEL
AD23
AD22
AD21
AD20
PRST
PCLK
GND
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
VCC
PERR
SERR
PAR
VCCP
VCCCB
CIRDY//A15
CFRAME//A23
GND
CC/BE2//A12
CAD17//A24
CAD18//A7
CAD19//A25
CVS2//VS2
CAD20//A6
CRST//RESET
CAD21//A5
CAD22//A4
CREQ//INPACK
CAD23//A3
CC/BE3//REG
VR_EN
VCC
CAD24//A2
CAD25//A1
CAD26//A0
CVS1//VS1
CINT//READY(IREQ)
GND
CSERR//WAIT
CAUDIO//BVD2(SPKR)
CSTSCHG//BVD1(STSCHG/RI)
CCLKRUN//WP(IOIS16)
VCC
CCD2//CD2
CAD27//D0
CAD28//D8
CAD29//D1
CAD30//D9
CRSVD//D2
CAD31//D10
Figure 2−3. PCI1510 PGE-Package Terminal Diagram
2−3
Table 2−1. Signal Names Sorted by PGE Terminal Number
SIGNAL NAME
TERMINAL
2−4
CARDBUS
SIGNAL NAME
16-BIT
TERMINAL
CARDBUS
16-BIT
1
REQ
REQ
43
AD11
AD11
2
GNT
GNT
44
AD10
AD10
3
AD31
AD31
45
AD9
AD9
4
AD30
AD30
46
AD8
AD8
5
AD29
AD29
47
C/BE0
C/BE0
6
AD28
AD28
48
AD7
AD7
7
AD27
AD27
49
AD6
AD6
8
GND
GND
50
AD5
AD5
9
AD26
AD26
51
AD4
AD4
10
AD25
AD25
52
AD3
AD3
11
AD24
AD24
53
AD2
AD2
12
VCC
VCC
54
VCC
VCC
13
C/BE3
C/BE3
55
AD1
AD1
14
IDSEL
IDSEL
56
AD0
AD0
15
AD23
AD23
57
RI_OUT/PME
RI_OUT/PME
16
AD22
AD22
58
MFUNC0
MFUNC0
17
AD21
AD21
59
MFUNC1
MFUNC1
18
AD20
AD20
60
GND
GND
19
PRST
PRST
61
SPKROUT
SPKROUT
20
PCLK
PCLK
62
VR_PORT
VR_PORT
21
GND
GND
63
MFUNC2
MFUNC2
22
AD19
AD19
64
MFUNC3
MFUNC3
23
AD18
AD18
65
SUSPEND
SUSPEND
24
AD17
AD17
66
GRST
GRST
25
AD16
AD16
67
MFUNC4
MFUNC4
26
C/BE2
C/BE2
68
MFUNC5
MFUNC5
27
FRAME
FRAME
69
MFUNC6
MFUNC6
28
IRDY
IRDY
70
VCC
VCC
29
TRDY
TRDY
71
VPPD0
VPPD0
30
DEVSEL
DEVSEL
72
VPPD1
VPPD1
31
STOP
STOP
73
VCCD0
VCCD0
32
VCC
VCC
74
VCCD1
VCCD1
33
PERR
PERR
75
CCD1
CD1
34
SERR
SERR
76
CAD0
D3
35
PAR
PAR
77
CAD2
D11
36
VCCP
VCCP
78
CAD1
D4
37
C/BE1
C/BE1
79
CAD4
D12
38
AD15
AD15
80
GND
GND
39
AD14
AD14
81
CAD3
D5
40
GND
GND
82
CAD6
D13
41
AD13
AD13
83
CAD5
D6
42
AD12
AD12
84
CRSVD
D14
Table 2−1. Signal Names Sorted by PGE Terminal Number (Continued)
SIGNAL NAME
TERMINAL
CARDBUS
SIGNAL NAME
16-BIT
TERMINAL
CARDBUS
16-BIT
85†
CLK_48_RSVD
CLK_48_RSVD
115
CAD18
A7
86
CAD7
D7
116
CAD19
A25
87
CAD8
D15
117
CVS2
VS2
88
CC/BE0
CE1
118
CAD20
A6
89
CAD9
A10
119
CRST
RESET
90
CAD10
CE2
120
CAD21
A5
91
CAD11
OE
121
CAD22
A4
92
CAD12
A11
122
CREQ
INPACK
93
GND
GND
123
CAD23
A3
94
CAD13
IORD
124
CC/BE3
REG
95
CAD15
IOWR
125
VR_EN
VR_EN
96
CAD14
A9
126
97
CAD16
A17
127
VCC
CAD24
VCC
A2
98
CC/BE1
A8
128
CAD25
A1
99
CRSVD
A18
129
CAD26
A0
100
CPAR
A13
130
CVS1
VS1
101
CBLOCK
A19
131
CINT
READY(IREQ)
102
CPERR
A14
132
GND
GND
103
CSTOP
A20
133
CSERR
WAIT
104
VCC
CGNT
VCC
WE
134
CAUDIO
BVD2(SPKR)
105
135
CSTSCHG
BVD1(STSCHG/RI)
106
CDEVSEL
A21
136
CCLKRUN
WP(IOIS16)
107
CCLK
A16
137
108
CTRDY
A22
138
VCC
CCD2
VCC
CD2
109
VCCCB
CIRDY
VCCCB
A15
139
CAD27
D0
110
140
CAD28
D8
111
CFRAME
A23
141
CAD29
D1
112
GND
GND
142
CAD30
D9
113
CC/BE2
A12
143
CRSVD
D2
114
CAD17
A24
144
CAD31
D10
† Terminal 85 is an NC on the PCI1510 to allow for terminal compatibility with the next generation of devices.
2−5
Table 2−2. Signal Names Sorted by GGU Terminal Number
SIGNAL NAME
TERMINAL
CARDBUS
16-BIT
SIGNAL NAME
TERMINAL
A01
C/BE3
C/BE3
D05
A02
GND
GND
A03
CRSVD
A04
CAD27
A05
CARDBUS
D06
VCC
BVD2(SPKR)
D2
D07
CAD25
A1
D0
D08
CRST
RESET
CCLKRUN
WP(IOIS16)
D09
CC/BE2
A12
A06
CINT
READY(IREQ)
D10
CAD23
A3
A07
VCC
REG
D11
CDEVSEL
A21
A08
VCC
CC/BE3
D12
CPERR
A14
A09
CVS2
VS2
D13
CGNT
WE
A10
CFRAME
A23
E01
A11
GND
GND
E02
VCC
AD25
VCC
AD25
A12
CAD18
A7
E03
AD31
AD31
A13
CBLOCK
A19
E04
AD29
AD29
B01
AD27
AD27
E10
CSTOP
A20
B02
CVS1
VS1
E11
CC/BE1
A8
B03
CAD31
D10
E12
CPAR
A13
B04
CAD30
D9
E13
CRSVD
A18
B05
CCD2
CD2
F01
AD22
AD22
B06
CSERR
WAIT
F02
IDSEL
IDSEL
B07
CAD24
A2
F03
AD24
AD24
B08
CREQ
INPACK
F04
AD26
AD26
B09
CAD19
A25
F10
CAD16
A17
B10
CAD17
A24
F11
CAD14
A9
B11
VCCCB
CAD22
VCCCB
A4
F12
CAD13
IORD
B12
F13
GND
GND
B13
CCLK
A16
G01
PCLK
PCLK
C01
GNT
GNT
G02
AD20
AD20
C02
REQ
REQ
G03
PRST
PRST
C03
AD23
AD23
G04
AD21
AD21
C04
CAD29
D1
G10
CAD11
OE
C05
CAD28
D8
G11
CAD9
A10
C06
CSTSCHG
BVD1(STSCHG/RI)
G12
CAD12
A11
C07
CAD26
A0
G13
CAD10
CE2
C08
CAD21
A5
H01
AD17
AD17
C09
CAD20
A6
H02
AD19
AD19
C10
CIRDY
A15
H03
AD18
AD18
C11
CAD15
IOWR
H04
GND
GND
C12
CTRDY
A22
H10†
CLK_48_RSVD
CLK_48_RSVD
C13
VCC
GND
H11
CAD8
D15
D01
VCC
GND
H12
CAD7
D7
D02
AD28
AD28
H13
CC/BE0
CE1
D03
AD30
AD30
J01
FRAME
FRAME
D04
VR_EN
VR_EN
J02
C/BE2
C/BE2
† Terminal H10 is not bonded out in the packaged parts in order to have pin compatibility with future devices.
2−6
16-BIT
VCC
CAUDIO
Table 2−2. Signal Names Sorted by GGU Terminal Number (Continued)
SIGNAL NAME
TERMINAL
CARDBUS
SIGNAL NAME
16-BIT
TERMINAL
CARDBUS
16-BIT
J03
TRDY
TRDY
L11
GRST
GRST
J04
AD16
AD16
L12
VCCD1
VCCD1
J10
CAD5
D6
L13
CCD1
CD1
J11
CAD4
D12
M01
J12
CRSVD
D14
M02
VCC
AD9
VCC
AD9
J13
CAD3
D5
M03
C/BE1
C/BE1
K01
IRDY
IRDY
M04
AD15
AD15
K02
DEVSEL
DEVSEL
M05
AD10
AD10
K03
PERR
PERR
M06
AD5
AD5
K04
AD4
AD4
M07
AD1
AD1
K05
AD13
AD13
M08
RI_OUT/PME
RI_OUT/PME
K06
C/BE0
C/BE0
M09
SPKROUT
SPKROUT
K07
MFUNC0
MFUNC0
M10
MFUNC4
MFUNC4
K08
GND
GND
M11
VPPD1
VPPD1
K09
VPPD0
VPPD0
M12
CAD2
D11
K10
MFUNC3
MFUNC3
M13
GND
GND
K11
CAD0
D3
N01
PAR
PAR
K12
CAD1
D4
N02
GND
GND
K13
CAD6
D13
N03
AD12
AD12
L01
STOP
STOP
N04
AD8
AD8
L02
SERR
SERR
N05
AD7
AD7
L03
VCCP
AD11
N06
AD3
AD3
L04
VCCP
AD11
N07
L05
AD14
AD14
N08
VCC
AD0
VCC
AD0
L06
AD6
AD6
N09
MFUNC1
MFUNC1
L07
AD2
AD2
N10
SUSPEND
SUSPEND
L08
VR_PORT
VR_PORT
N11
L09
MFUNC2
MFUNC2
N12
VCC
MFUNC5
VCC
MFUNC5
L10
MFUNC6
MFUNC6
N13
VCCD0
VCCD0
2−7
Table 2−3. Signal Names Sorted by GVF Terminal Number
SIGNAL NAME
TERMINAL
CARDBUS
SIGNAL NAME
16-BIT
TERMINAL
CARDBUS
VPPD0
VPPD0
E07
NC
NC
A05
VCC
NC
VCC
NC
E08
CAD31
D10
A06
E09
CAD28
D8
A07
GND
GND
E10
CSERR
WAIT
A08
VCC
CSTSCHG
VCC
BVD1(STSCHG/RI)
E11
CAD25
A1
A09
E12
CAD21
A5
A10
GND
GND
E13
CAD18
A7
A11
VCCCB
CAD23
VCCCB
A3
E14
CTRDY
A22
E17
CSTOP
A20
VCC
A25
E18
CBLOCK
A19
A14
VCC
CAD19
E19
A15
GND
GND
F01
VCC
MFUNC5
VCC
MFUNC5
A16
CDEVSEL
A21
F02
MFUNC3
MFUNC3
B05
VCCD1
VCCD1
F03
MFUNC2
MFUNC2
B06
NC
NC
F05
MFUNC0
MFUNC0
B07
NC
NC
F06
NC
NC
B08
CAD29
D1
F07
NC
NC
B09
CCLKRUN
WP(IOIS16)
F08
CRSVD
D2
B10
CVS1
VS1
F09
CAD27
D0
B11
CC/BE3
REG
F10
CAUDIO
BVD2(SPKR)
B12
CREQ
INPACK
F11
CAD26
A0
B13
CRST
RESET
F12
CVS2
VS2
B14
CAD17
A24
F13
CIRDY
A15
B15
CFRAME
A23
F14
CPAR
A13
C05
VPPD1
VPPD1
F15
CPERR
A14
C06
NC
NC
F17
CRSVD
A18
C07
NC
NC
F18
CAD16
A17
C08
CAD30
D9
F19
CAD14
A9
C09
CCD2
CD2
G01
C10
CINT
READY(IREQ)
G02
VCC
VR_PORT
VCC
VR_PORT
C11
CAD24
A2
G03
SUSPEND
SUSPEND
C12
CAD22
A4
G05
MFUNC4
MFUNC4
C13
CAD20
A6
G06
MFUNC1
MFUNC1
C14
CC/BE2
A12
G14
C15
CCLK
A16
G15
VCCCB
CC/BE1
VCCCB
A8
D01
NC
NC
G17
CAD15
IOWR
D19
CGNT
WE
G18
CAD13
IORD
E01
GND
GND
G19
GND
GND
E02
SPKROUT
SPKROUT
H01
PCLK
PCLK
E03
NC
NC
H02
GRST
GRST
E05
NC
NC
H03
PRST
PRST
E06
VCCD0
VCCD0
H05
VR_EN
VR_EN
A12
A13
† Terminal F06 is not bonded out in the packaged parts in order to have pin compatibility with future devices.
2−8
16-BIT
A04
Table 2−3. Signal Names Sorted by GVF Terminal Number (Continued)
SIGNAL NAME
TERMINAL
CARDBUS
SIGNAL NAME
16-BIT
TERMINAL
CARDBUS
16-BIT
H06
MFUNC6
MFUNC6
M17
NC
NC
H14
CAD11
OE
M18
NC
NC
H15
CAD12
A11
M19
NC
NC
H17
CAD10
CE2
N01
GND
GND
H18
CAD9
A10
N02
AD19
AD19
H19
VCC
GNT
VCC
GNT
N03
AD18
AD18
J01
N05
FRAME
FRAME
J02
REQ
REQ
N06
AD17
AD17
J03
RI_OUT/PME
RI_OUT/PME
N14
NC
NC
J05
AD31
AD31
N15
NC
NC
J06
AD30
AD30
N17
NC
NC
J14
CAD8
D15
N18
NC
NC
J15
CC/BE0
CE1
N19
NC
NC
J17
CAD7
D7
P01
AD16
AD16
J18
CRSVD
D14
P02
C/BE2
C/BE2
J19
CAD5
D6
P03
IRDY
IRDY
K01
GND
GND
P05
STOP
STOP
K02
AD29
AD29
P06
TRDY
TRDY
K03
AD28
AD28
P07
AD14
AD14
K05
AD27
AD27
P08
AD9
AD9
K06
AD26
AD26
P09
NC
NC
K14
CAD6
D13
P10
NC
NC
K15
CAD3
D5
P11
NC
NC
K17
CAD4
D12
P12
NC
NC
K18
CAD1
D4
P13
NC
NC
K19
GND
GND
P14
NC
NC
L01
VCCP
AD25
VCCP
AD25
P15
NC
NC
L02
P17
NC
NC
L03
AD24
AD24
P18
NC
NC
L05
IDSEL
IDSEL
P19
GND
GND
L06
C/BE3
C/BE3
R01
L14
CAD2
D11
R02
VCC
DEVSEL
VCC
DEVSEL
L15
CAD0
D3
R03
PERR
PERR
L17
CCD1
CD1
R06
AD15
AD15
L18
VR_PORT
VR_PORT
R07
AD10
AD10
L19
VCC
VCC
R08
AD6
AD6
M01
VCC
VCC
R09
AD0
AD0
M02
AD23
AD23
R10
NC
NC
M03
AD22
AD22
R11
NC
NC
M05
AD20
AD20
R12
NC
NC
M06
AD21
AD21
R13
NC
NC
M14
NC
NC
R14
NC
NC
M15
NC
NC
R17
NC
NC
2−9
Table 2−3. Signal Names Sorted by GVF Terminal Number (Continued)
SIGNAL NAME
TERMINAL
2−10
CARDBUS
SIGNAL NAME
16-BIT
R18
NC
NC
R19
NC
T01
SERR
T19
TERMINAL
CARDBUS
16-BIT
V10
NC
NC
NC
V11
NC
NC
SERR
V12
NC
NC
NC
NC
V13
NC
NC
U05
C/BE1
C/BE1
V14
NC
NC
U06
AD12
AD12
V15
NC
NC
U07
AD8
AD8
W04
PAR
PAR
U08
AD5
AD5
W05
U09
AD1
AD1
W06
VCCP
GND
VCCP
GND
U10
NC
NC
W07
AD7
AD7
U11
NC
NC
W08
U12
NC
NC
W09
VCC
AD3
VCC
AD3
U13
NC
NC
W10
NC
NC
U14
NC
NC
W11
NC
NC
U15
NC
NC
W12
NC
NC
V05
AD13
AD13
W13
NC
NC
V06
AD11
AD11
W14
NC
NC
V07
C/BE0
C/BE0
W15
NC
NC
V08
AD4
AD4
W16
NC
NC
V09
AD2
AD2
Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
PGE
GGU
GVF
PGE
GGU
GVF
AD0
56
N08
R09
CAD11
91
G10
H14
AD1
55
M07
U09
CAD12
92
G12
H15
AD2
53
L07
V09
CAD13
94
F12
G18
AD3
52
N06
W09
CAD14
96
F11
F19
AD4
51
K04
V08
CAD15
95
C11
G17
AD5
50
M06
U08
CAD16
97
F10
F18
AD6
49
L06
R08
CAD17
114
B10
B14
AD7
48
N05
W07
CAD18
115
A12
E13
AD8
46
N04
U07
CAD19
116
B09
A14
AD9
45
M02
P08
CAD20
118
C09
C13
AD10
44
M05
R07
CAD21
120
C08
E12
AD11
43
L04
V06
CAD22
121
B12
C12
AD12
42
N03
U06
CAD23
123
D10
A12
AD13
41
K05
V05
CAD24
127
B07
C11
AD14
39
L05
P07
CAD25
128
D07
E11
AD15
38
M04
R06
CAD26
129
C07
F11
AD16
25
J04
P01
CAD27
139
A04
F09
AD17
24
H01
N06
CAD28
140
C05
E09
AD18
23
H03
N03
CAD29
141
C04
B08
AD19
22
H02
N02
CAD30
142
B04
C08
AD20
18
G02
M05
CAD31
144
B03
E08
AD21
17
G04
M06
CAUDIO
134
D06
F10
AD22
16
F01
M03
C/BE0
47
K06
V07
AD23
15
C03
M02
C/BE1
37
M03
U05
AD24
11
F03
L03
C/BE2
26
J02
P02
AD25
10
E02
L02
C/BE3
13
A01
L06
AD26
9
F04
K06
CBLOCK
101
A13
E18
AD27
7
B01
K05
CC/BE0
88
H13
J15
AD28
6
D02
K03
CC/BE1
98
E11
G15
AD29
5
E04
K02
CC/BE2
113
D09
C14
AD30
4
D03
J06
CC/BE3
124
A08
B11
AD31
3
E03
J05
CCD1
75
L13
L17
CAD0
76
K11
L15
CCD2
138
B05
C09
CAD1
78
K12
K18
CCLK
107
B13
C15
CAD2
77
M12
L14
CCLKRUN
136
A05
B09
CAD3
81
J13
K15
CDEVSEL
106
D11
A16
CAD4
79
J11
K17
CFRAME
111
A10
B15
CAD5
83
J10
J19
CGNT
105
D13
D19
CAD6
82
K13
K14
CINT
131
A06
C10
CAD7
86
H12
J17
CIRDY
110
C10
F13
CAD8
87
H11
J14
CLK_48_RSVD
85
H10
—
CAD9
89
G11
H18
CPAR
100
E12
F14
CAD10
90
G13
H17
CPERR
102
D12
F15
2−11
Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals (Continued)
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
PGE
GGU
GVF
PGE
GGU
GVF
CREQ
122
B08
B12
MFUNC4
67
M10
G05
CRST
119
D08
B13
MFUNC5
68
N12
F01
CRSVD
84
A03
F08
MFUNC6
69
L10
H06
CRSVD
99
E13
F17
PAR
35
N01
W04
CRSVD
143
J12
J18
PCLK
20
G01
H01
CSERR
133
B06
E10
PERR
33
K03
R03
CSTOP
103
E10
E17
PRST
19
G03
H03
CSTSCHG
135
C06
A09
REQ
1
C02
J02
CTRDY
108
C12
E14
RI_OUT/PME
57
M08
J03
CVS1
130
B02
B10
SERR
34
L02
T01
CVS2
117
A09
F12
SPKROUT
61
M09
E02
DEVSEL
30
K02
R02
STOP
31
L01
P05
FRAME
27
J01
N05
SUSPEND
65
N10
G03
GNT
2
C01
J01
TRDY
29
J03
P06
GRST
66
L11
H02
VCCD0
73
N13
E06
IDSEL
14
F02
L05
VCCD1
74
L12
B05
IRDY
28
K01
P03
VPPD0
71
K09
A04
MFUNC0
58
K07
F05
VPPD1
72
M11
C05
MFUNC1
59
N09
G06
VR_EN
125
D04
H05
MFUNC2
63
L09
F03
VR_PORT
62
L08
G02, L18
MFUNC3
64
K10
F02
2−12
Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically to Device Terminals
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
PGE
GGU
GVF
AD0
56
N08
R09
A11
PGE
GGU
GVF
92
G12
H15
AD1
55
M07
U09
AD2
53
L07
V09
A12
113
D09
C14
A13
100
E12
F14
AD3
52
N06
AD4
51
K04
W09
A14
102
D12
F15
V08
A15
110
C10
F13
AD5
50
AD6
49
M06
U08
A16
107
B13
C15
L06
R08
A17
97
F10
AD7
48
F18
N05
W07
A18
99
E13
F17
AD8
AD9
46
N04
U07
A19
101
A13
E18
45
M02
P08
A20
103
E10
E17
AD10
44
M05
R07
A21
106
D11
A16
AD11
43
L04
V06
A22
108
C12
E14
AD12
42
N03
U06
A23
111
A10
B15
AD13
41
K05
V05
A24
114
B10
B14
AD14
39
L05
P07
A25
116
B09
A14
AD15
38
M04
R06
BVD1(STSCHG/RI)
135
C06
A09
AD16
25
J04
P01
BVD2(SPKR)
134
D06
F10
AD17
24
H01
N06
C/BE0
47
K06
V07
AD18
23
H03
N03
C/BE1
37
M03
U05
AD19
22
H02
N02
C/BE2
26
J02
P02
AD20
18
G02
M05
C/BE3
13
A01
L06
AD21
17
G04
M06
CD1
75
L13
L17
AD22
16
F01
M03
CD2
138
B05
C09
AD23
15
C03
M02
CE1
88
H13
J15
AD24
11
F03
L03
CE2
90
G13
H17
AD25
10
E02
L02
CLK_48_RSVD
85
H10
—
AD26
9
F04
K06
DEVSEL
30
K02
R02
AD27
7
B01
K05
D0
139
A04
F09
AD28
6
D02
K03
D1
141
C04
B08
AD29
5
E04
K02
D2
143
A03
F08
AD30
4
D03
J06
D3
76
K11
L15
AD31
3
E03
J05
D4
78
K12
K18
A0
129
C07
F11
D5
81
J13
K15
A1
128
D07
E11
D6
83
J10
J19
A2
127
B07
C11
D7
86
H12
J17
A3
123
D10
A12
D8
140
C05
E09
A4
121
B12
C12
D9
142
B04
C08
A5
120
C08
E12
D10
144
B03
E08
A6
118
C09
C13
D11
77
M12
L14
A7
115
A12
E13
D12
79
J11
K17
A8
98
E11
G15
D13
82
K13
K14
A9
96
F11
F19
D14
84
J12
J18
A10
89
G11
H18
D15
87
H11
J14
2−13
Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically to Device Terminals (Continued)
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
PGE
GGU
GVF
27
J01
N05
REG
GNT
2
C01
J01
REQ
GRST
66
L11
H02
RESET
IDSEL
14
F02
L05
RI_OUT/PME
57
INPACK
122
B08
B12
SERR
34
L02
T01
IORD
94
F12
G18
SPKROUT
61
M09
E02
IOWR
95
C11
G17
STOP
31
L01
P05
IRDY
28
K01
P03
SUSPEND
65
N10
G03
MFUNC0
58
K07
F05
TRDY
29
J03
P06
MFUNC1
59
N09
G06
VCCD0
73
N13
E06
MFUNC2
63
L09
F03
VCCD1
74
L12
B05
MFUNC3
64
K10
F02
VPPD0
71
K09
A04
MFUNC4
67
M10
G05
VPPD1
72
M11
C05
MFUNC5
68
N12
F01
VR_EN
125
D04
H05
MFUNC6
69
L10
H06
VR_PORT
62
L08
G02, L18
OE
91
G10
H14
VS1
130
B02
B10
PAR
35
N01
W04
VS2
117
A09
F12
PCLK
20
G01
H01
WAIT
133
B06
E10
PERR
33
K03
R03
WE
105
D13
D19
PRST
19
G03
H03
WP(IOIS16)
136
A05
B09
READY(IREQ)
131
A06
C10
FRAME
2−14
PGE
GGU
GVF
124
A08
B11
1
C02
J02
119
D08
B13
M08
J03
2.2 Terminal Descriptions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2−6. Power Supply Terminals
TERMINAL
NUMBER
NAME
PGE
I/O
DESCRIPTION
GGU
GVF
Device ground terminals
GND
8, 21, 40,
60, 80, 93,
112, 132
A02, A11, D01,
F13, H04, K08,
M13, N02
A07, A10, A15,
E01, G19, K01,
K19, N01, P19,
W06
VCC
12, 32, 54,
70, 104,
126, 137
A07, C13, D05,
E01, M01, N07,
N11
A05, A08, A13,
E19, G01, H19,
L19, M01, R01,
W08
Power supply terminals for I/O and internal voltage regulator
VCCCB
109
B11
A11, G14
Clamp voltage for PC Card interface. Matches card signaling
environment, 5 V or 3.3 V
VCCP
VR_EN
36
L03
L01, W05
125
D04
H05
VR_PORT
62
L08
G02, L18
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
I
Internal voltage regulator enable. Active-low
Internal voltage regulator input/output. When VR_EN is low, the
regulator is enabled and this terminal is an output. An external
bypass capacitor is required on this terminal. When VR_EN is high,
the regulator is disabled and this terminal is an input for an external
2.5-V core power source.
Table 2−7. PC Card Power Switch Terminals
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
PGE
GGU
GVF
VCCD0
VCCD1
73
74
N13
L12
E06
B05
O
Logic controls to the TPS2211A PC Card power interface switch to control AVCC
VPPD0
VPPD1
71
72
K09
M11
A04
C05
O
Logic controls to the TPS2211A PC Card power interface switch to control AVPP
2−15
Table 2−8. PCI System Terminals
TERMINAL
NUMBER
NAME
GRST
PGE
66
GGU
L11
I/O
DESCRIPTION
GVF
H02
I
Global reset. When the global reset is asserted, the GRST signal causes the controller to
place all output buffers in a high-impedance state and reset all internal registers. When GRST
is asserted, the device is completely in its default state. For systems that require wake-up
from D3, GRST normally is asserted only during initial boot. PRST must be asserted following
initial boot so that PME context is retained during the transition from D3 to D0.
When the SUSPEND mode is enabled, the device is protected from GRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
PCLK
PRST
20
19
G01
G03
H01
H03
I
I
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are
sampled at the rising edge of PCLK.
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all
output buffers in a high-impedance state and reset internal registers. When PRST is asserted,
the device can generate the PME signal only if it is enabled. After PRST is deasserted, the
controller is in a default state.
When the SUSPEND mode is enabled, the device is protected from PRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
2−16
Table 2−9. PCI Address and Data Terminals
TERMINAL
NUMBER
NAME
PGE
GGU
GVF
J05
AD31
3
E03
AD30
4
D03
J06
AD29
5
E04
K02
AD28
6
D02
K03
AD27
7
B01
K05
AD26
9
F04
K06
AD25
10
E02
L02
AD24
11
F03
L03
AD23
15
C03
M02
AD22
16
F01
M03
AD21
17
G04
M06
AD20
18
G02
M05
AD19
22
H02
N02
AD18
23
H03
N03
AD17
24
H01
N06
AD16
25
J04
P01
AD15
38
M04
R06
AD14
39
L05
P07
AD13
41
K05
V05
AD12
42
N03
U06
AD11
43
L04
V06
AD10
44
M05
R04
AD9
45
M02
P08
AD8
46
N04
U07
AD7
48
N05
W07
AD6
49
L06
R08
AD5
50
M06
U08
AD4
51
K04
V08
AD3
52
N06
W09
AD2
53
L07
V09
AD1
55
M07
U09
AD0
56
N08
R09
C/BE3
13
A01
L06
C/BE2
26
J02
P02
C/BE1
37
M03
U05
C/BE0
47
K06
V07
PAR
35
N01
W04
I/O
DESCRIPTION
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary-bus PCI cycle, AD31–AD0 contain a
32-bit address or other destination information. During the data phase, AD31–AD0 contain data.
I/O
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a primary-bus PCI cycle, C/BE3–C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable
determines which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to
byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2
(AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).
I/O
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across
the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the controller outputs
this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller
compares its calculated parity to the parity indicator of the initiator. A compare error results in the
assertion of a parity error (PERR).
2−17
Table 2−10. PCI Interface Control Terminals
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
R02
I/O
PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device.
As a PCI initiator on the bus, the controller monitors DEVSEL until a target responds. If no
target responds before timeout occurs, then the controller terminates the cycle with an initiator
abort.
J01
N05
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When FRAME is deasserted, the PCI bus transaction is in the final data phase.
2
C01
J01
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI
bus after the current data transaction has completed. GNT may or may not follow a PCI bus
request, depending on the PCI bus parking algorithm.
14
F02
L05
I
Initialization device select. IDSEL selects the controller during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
PGE
GGU
GVF
DEVSEL
30
K02
FRAME
27
GNT
IDSEL
IRDY
28
K01
P03
I/O
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK where both
IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states
are inserted.
PERR
33
K03
R03
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity
does not match PAR when PERR is enabled through bit 6 of the command register (PCI offset
04h, see Section 4.4).
REQ
1
C02
J02
O
PCI bus request. REQ is asserted by the controller to request access to the PCI bus as an
initiator.
SERR
34
L02
T01
O
PCI system error. SERR is an output that is pulsed from the controller when enabled through
bit 8 of the command register (PCI offset 04h, see Section 4.4) indicating a system error has
occurred. The controller need not be the target of the PCI cycle to assert this signal. When
SERR is enabled in the command register, this signal also pulses, indicating that an address
parity error has occurred on a CardBus interface.
STOP
31
L01
P05
I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK when both
IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are
inserted.
TRDY
2−18
29
J03
P06
Table 2−11. Multifunction and Miscellaneous Terminals
TERMINAL
NUMBER
NAME
CLK_48_RSVD
MFUNC0
I/O
DESCRIPTION
PGE
GGU
GVF
85
H10
—
No connect. These terminals have no connection anywhere within the package.
Terminals H10 on the GGU package and 85 on the PGE package will be used as a
48-MHz clock input on future-generation devices.
F05
Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA,
GPI0, GPO0, socket activity LED output, ZV switching output, CardBus audio PWM,
GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for
configuration details.
58
K07
I/O
Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity
LED output, D3_STAT, ZV switching output, CardBus audio PWM, GPE, or a parallel
IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
Serial data (SDA). When VCCD0 and VCCD1 are detected high after a global reset, the
MFUNC1 terminal provides the SDA signaling for the serial bus interface. The
two-terminal serial interface loads the subsystem identification and other register
defaults from an EEPROM after a global reset. See Section 3.6.1, Serial Bus Interface
Implementation, for details on other serial bus applications.
MFUNC1
59
N09
G06
I/O
MFUNC2
63
L09
F03
I/O
Multifunction terminal 2. MFUNC2 can be configured as GPI2, GPO2, socket activity
LED output, ZV switching output, CardBus audio PWM, GPE, RI_OUT, D3_STAT, or a
parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC3/
IRQSER
64
K10
F02
I/O
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized
interrupt signal IRQSER. This terminal is IRQSER by default. See Section 4.30,
Multifunction Routing Register, for configuration details.
Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket
activity LED output, ZV switching output, CardBus audio PWM, GPE, D3_STAT,
RI_OUT, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for
configuration details.
MFUNC4
67
M10
G05
I/O
MFUNC5
68
N12
F01
I/O
Multifunction terminal 5. MFUNC5 can be configured as GPI4, GPO4, socket activity
LED output, ZV switching output, CardBus audio PWM, D3_STAT, GPE, or a parallel
IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC6/
CLKRUN
69
L10
H06
I/O
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel
IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
RI_OUT / PME
57
M08
J03
O
Ring indicate out and power management event output. Terminal provides an output for
ring- indicate or PME signals.
SPKROUT
61
M09
E02
O
Speaker output. SPKROUT is the output to the host system that can carry SPKR or
CAUDIO through the controller from the PC Card interface. SPKROUT is driven as the
exclusive-OR combination of card SPKR//CAUDIO inputs.
SUSPEND
65
N10
G03
I
Suspend. SUSPEND protects the internal registers from clearing when the GRST or
PRST signal is asserted. See Section 3.8.5, Suspend Mode, for details.
Serial clock (SCL). When VCCD0 and VCCD1 are detected high after a global reset, the
MFUNC4 terminal provides the SCL signaling for the serial bus interface. The
two-terminal serial interface loads the subsystem identification and other register
defaults from an EEPROM after a global reset. See Section 3.6.1, Serial Bus Interface
Implementation, for details on other serial bus applications.
2−19
Table 2−12. 16-Bit PC Card Address and Data Terminals
TERMINAL
NUMBER
NAME
2−20
I/O
PGE
GGU
GVF
A25
116
B09
A14
A24
114
B10
B14
A23
111
A10
B15
A22
108
C12
E14
A21
106
D11
A16
A20
103
E10
E17
A19
101
A13
E18
A18
99
E13
F17
A17
97
F10
F18
A16
107
B13
C15
A15
110
C10
F13
A14
102
D12
F15
A13
100
E12
F14
A12
113
D09
C14
A11
92
G12
H15
A10
89
G11
H18
A9
96
F11
F19
A8
98
E11
G15
A7
115
A12
E13
A6
118
C09
C13
A5
120
C08
E12
A4
121
B12
C12
A3
123
D10
A12
A2
127
B07
C11
A1
128
D07
E11
A0
129
C07
F11
D15
87
H11
J14
D14
84
J12
J18
D13
82
K13
K14
D12
79
J11
K17
D11
77
M12
L14
D10
144
B03
E08
D9
142
B04
C08
D8
140
C05
E09
D7
86
H12
J17
D6
83
J10
J19
D5
81
J13
K15
D4
78
K12
K18
D3
76
K11
L15
D2
143
A03
F08
D1
141
C04
B08
D0
139
A04
F09
DESCRIPTION
O
PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
I/O
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
Table 2−13. 16-Bit PC Card Interface Control Terminals
TERMINAL
NUMBER
NAME
BVD1
(STSCHG/RI)
PGE
135
GGU
C06
I/O
DESCRIPTION
GVF
A09
I
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include
batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is
low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the
battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Status change. STSCHG is used to alert the system to a change in the READY, write protect,
or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
BVD2(SPKR)
134
D06
F10
I
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include
batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is
low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the
battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Speaker. SPKR is an optional binary audio signal available only when the card and socket
have been configured for the 16-bit I/O interface.
I
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC
Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal
status, see Section 5.2, ExCA Interface Status Register.
O
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address
bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered
address bytes.
B12
I
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read
cycle at the current address.
F12
G18
O
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during
host I/O read cycles.
95
C11
G17
O
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards
during host I/O write cycles.
91
G10
H14
O
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data
output during host memory read cycles.
CD1
75
L13
L17
CD2
138
B05
C09
CE1
88
H13
J15
CE2
90
G13
H17
INPACK
122
B08
IORD
94
IOWR
OE
READY
(IREQ)
131
A06
C10
I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host
socket are configured for the memory-only interface. READY is driven low by the 16-bit
memory PC Cards to indicate that the memory card circuits are busy processing a previous
write command. READY is driven high when the 16-bit memory PC Card is ready to accept a
new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a
device on the 16-bit I/O PC Card requires service by the host software. IREQ is high
(deasserted) when no interrupt is requested.
REG
124
A08
B11
O
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE or WE active) and to the I/O space
(IORD or IOWR active). Attribute memory is a separately accessed section of card memory
and is generally used to record card capacity and other configuration and attribute
information.
RESET
119
D08
B13
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
2−21
Table 2−13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NUMBER
NAME
I/O
PGE
GGU
GVF
VS1
130
B02
B10
VS2
117
A09
F12
WAIT
133
B06
WE
105
D13
WP
(IOIS16)
136
A05
DESCRIPTION
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
E10
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or
I/O in progress.
D19
O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.
B09
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)
function.
I
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of 16-bit accesses.
Table 2−14. CardBus PC Card Interface System Terminals
TERMINAL
NUMBER
NAME
PGE
GGU
I/O
DESCRIPTION
GVF
CCLK
107
B13
C15
O
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1,
CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are
defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but
it can be stopped in the low state or slowed down for power savings.
CCLKRUN
136
A05
B09
I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the controller to indicate that the CCLK frequency is going to be
decreased.
O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals
to a known state. When CRST is asserted, all CardBus PC Card signals are placed in a
high-impedance state, and the controller drives these signals to a valid logic level. Assertion
can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.
CRST
2−22
119
D08
B13
Table 2−15. CardBus PC Card Address and Data Terminals
TERMINAL
NUMBER
NAME
PGE
GGU
CAD31
144
B03
E08
CAD30
142
B04
C08
CAD29
141
C04
B08
CAD28
140
C05
E09
CAD27
139
A04
F09
CAD26
129
C07
F11
CAD25
128
D07
E11
CAD24
127
B07
C11
CAD23
123
D10
A12
CAD22
121
B12
C12
CAD21
120
C08
E12
CAD20
118
C09
C13
CAD19
116
B09
A14
CAD18
115
A12
E13
CAD17
114
B10
B14
CAD16
97
F10
F18
CAD15
95
C11
G17
CAD14
96
F11
F19
CAD13
94
F12
G18
CAD12
92
G12
H15
CAD11
91
G10
H14
CAD10
90
G13
H17
CAD9
89
G11
H18
CAD8
87
H11
J14
CAD7
86
H12
J17
CAD6
82
K13
K14
CAD5
83
J10
J19
CAD4
79
J11
K17
CAD3
81
J13
K15
CAD2
77
M12
L14
CAD1
78
K12
K18
CAD0
76
K11
L15
CC/BE3
124
A08
B11
CC/BE2
113
D09
C14
CC/BE1
98
E11
G15
CC/BE0
88
H13
J15
CPAR
100
E12
I/O
DESCRIPTION
I/O
CardBus address and data. These signals make up the multiplexed CardBus address and data
bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0
contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain
data. CAD31 is the most significant bit.
I/O
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same
CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 define the
bus command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable
determines which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies
to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2
(CAD23–CAD16), and CC/BE3 applies to byte (CAD31–CAD24).
I/O
CardBus parity. In all CardBus read and write cycles, the controller calculates even parity
across the CAD and CC/BE buses. As an initiator during CardBus cycles, the controller outputs
CPAR with a one-CCLK delay. As a target during CardBus cycles, the controller compares its
calculated parity to the parity indicator of the initiator; a compare error results in a parity error
assertion.
GVF
F14
2−23
Table 2−16. CardBus PC Card Interface Control Terminals
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
F10
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
controller supports the binary audio mode and outputs a binary signal from the card to
SPKROUT.
A13
E18
I/O
75
L13
L17
138
B05
C09
PGE
GGU
GVF
CAUDIO
134
D06
CBLOCK
101
CCD1
CCD2
CDEVSEL
CFRAME
106
111
D11
A10
A16
B15
CardBus lock. CBLOCK is used to gain exclusive access to a target.
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with
CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating
voltage and card type.
I/O
CardBus device select. The controller asserts CDEVSEL to claim a CardBus cycle as the
target device. As a CardBus initiator on the bus, the controller monitors CDEVSEL until a
target responds. If no target responds before timeout occurs, then the controller terminates
the cycle with an initiator abort.
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME
is asserted to indicate that a bus transaction is beginning, and data transfers continue while
this signal is asserted.
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CGNT
105
D13
D19
O
CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to
the CardBus bus after the current data transaction has been completed.
CINT
131
A06
C10
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.
CIRDY
110
C10
F13
I/O
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK
when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled
asserted, wait states are inserted.
CPERR
102
D12
F15
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except
during special cycles. It is driven low by a target two clocks following the data cycle during
which a parity error is detected.
CREQ
122
B08
B12
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of
the CardBus bus as an initiator.
CSERR
133
B06
E10
I
CardBus system error. CSERR reports address parity errors and other system errors that
could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but
deasserted by a weak pullup; deassertion may take several CCLK periods. The controller
can report CSERR to the system by assertion of SERR on the PCI interface.
CSTOP
103
E10
E17
I/O
CSTSCHG
135
C06
A09
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is
used as a wake-up mechanism.
CTRDY
108
C12
E14
I/O
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK,
when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.
CVS1
130
B02
B10
CVS2
117
A09
F12
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in
conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to
determine the operating voltage and card type.
2−24
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the
current CardBus transaction. CSTOP is used for target disconnects, and is commonly
asserted by target devices that do not support burst data transfers.
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1510 controller. Figure 3−1 shows a simplified block diagram of
the controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface
includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface
terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power-management control signal), and
SPKROUT.
PCI Bus
INTA
Interrupt
Controller
Activity LED
TPS2211A
Power
Switch
IRQSER
PCI1510
4
PCI950
IRQSER
Deserializer
IRQ2−15
3
PC Card
Socket
Zoomed Video
68
23
19
VGA
Controller
Multiplexer
Zoomed Video
External ZV Port
4
Audio
Subsystem
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode, 23 terminals are used for routing the ZV signals
to the VGA controller and audio subsystem.
Figure 3−1. PCI1510 Simplified Block Diagram
3.1 Power Supply Sequencing
The controller contains 3.3-V I/O buffers with 5-V tolerance requiring an I/O power supply and an LDO-VR power
supply for core logic. The core power supply, which is always 2.5 V, can be supplied through the VR_PORT terminal
(when VR_EN is high) or from the integrated LDO-VR. The LDO-VR needs a 3.3-V power supply via the VCC
terminals. The clamping voltages (VCCCB and VCCP) can be either 3.3 V or 5 V, depending on the interface. The
following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Assert GRST to the device to disable the outputs during power up. Output drivers must be powered up in
the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping rails
(VCCCB and VCCP).
2. Apply 3.3-V power to VCC.
3. Apply the clamp voltage.
The power-down sequence is:
1. Assert GRST to the device to disable the outputs during power down. Output drivers must be powered down
in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping
rails (VCCCB and VCCP).
3−1
2. Remove the clamp voltage.
3. Remove the 3.3-V power from VCC.
NOTE: The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The
voltage difference between VCC and the clamp voltage must remain within 3.6 V.
3.2 I/O Characteristics
Figure 3−2 shows a 3-state bidirectional buffer. Section 7.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs.
NOTE: The controller meets the ac specifications of the PC Card Standard and PCI Local Bus
Specification.
VCCP
Tied for Open Drain
OE
Pad
Figure 3−2. 3-State Bidirectional Buffer
NOTE: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the controller is interfaced with, 3.3 V or 5 V.
The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals.
The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the controller must reliably accommodate both voltage levels. This is accomplished by
using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires
a 5-V PCI bus, then VCCP can be connected to a 5-V power supply.
The controller requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in Section 7.2, Recommended Operating Conditions. GRST, SUSPEND, PME, and
CSTSCHG are not clamped to any of them.
3.4 Peripheral Component Interconnect (PCI) Interface
The controller is fully compliant with the PCI Local Bus Specification. The controller provides all required signals for
PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP
terminal to the desired voltage level. In addition to the mandatory PCI signals, the controller provides the optional
interrupt signal INTA.
3.4.1
PCI GRST Signal
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100 µs after PCLK
is stable. PRST can be deasserted at the same time as GRST or any time thereafter.
3−2
3.4.2
PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the controller as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal by
setting the appropriate values in bits 19−16 of the multifunction routing register. See Section 4.30, Multifunction
Routing Register, for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the
downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus
signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A
complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete
bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked
operation is in progress.
The controller supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus
bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential
deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target
supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using
LOCK.
3.4.3
Loading Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for
system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The controller offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism
relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers
is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control register (PCI offset 80h,
see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification value into the registers at
PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem
ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically
erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The controller loads the data from the serial EEPROM
after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire core, including the
serial-bus state machine (see Section 3.8.5, Suspend Mode, for details on using SUSPEND).
The controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See Section 3.6,
Serial-Bus Interface, for details on the two-wire serial-bus controller and applications.
3−3
3.5 PC Card Applications
This section describes the PC Card interfaces of the controller.
•
•
•
•
•
3.5.1
Card insertion/removal and recognition
Zoomed video support
Speaker and audio applications
LED socket activity indicators
CardBus socket registers
PC Card Insertion/Removal and Recognition
The PC Card Standard (release 7.2) addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the PC Card
Standard (release 7.2) and in Table 3−1.
Table 3−1. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2
CD1//CCD1
VS2//CVS2
VS1//CVS1
KEY
INTERFACE
VOLTAGE
Ground
Ground
Open
Open
5V
16-bit PC Card
5V
Ground
Ground
Open
Ground
5V
16-bit PC Card
5 V and 3.3 V
Ground
Ground
Ground
Ground
5V
16-bit PC Card
5 V, 3.3 V, and X.X V
Ground
Ground
Open
Ground
LV
16-bit PC Card
3.3 V
Ground
Connect to CVS1
Open
Connect to CCD1
LV
CardBus PC Card
3.3 V
Ground
Ground
Ground
Ground
LV
16-bit PC Card
3.3 V and X.X V
Connect to CVS2
Ground
Connect to CCD2
Ground
LV
CardBus PC Card
3.3 V and X.X V
Connect to CVS1
Ground
Ground
Connect to CCD2
LV
CardBus PC Card
3.3 V, X.X V, and Y.Y V
X.X V
Ground
Ground
Ground
Open
LV
16-bit PC Card
Connect to CVS2
Ground
Connect to CCD2
Open
LV
CardBus PC Card
X.X V
Ground
Connect to CVS2
Connect to CCD1
Open
LV
CardBus PC Card
X.X V and Y.Y V
LV
CardBus PC Card
Y.Y V
Connect to CVS1
Ground
Open
Connect to CCD2
Ground
Connect to CVS1
Ground
Connect to CCD1
Reserved
Ground
Connect to CVS2
Connect to CCD1
Ground
Reserved
3.5.2
Parallel Power-Switch Interface (TPS2211A)
The controller provides a parallel interface for control of the PC Card power switch. The VCCD and VPPD terminals
are used with the TI TPS2211A single-slot PC Card power-switch interface to provide power-switch support.
Figure 3−3 illustrates a typical application, where the controller represents the PC Card controller.
3−4
Power Supply
12 V
5V
3.3 V
TPS2211A
12V
5V
3.3V
AVPP
SHDN
SHDN
Supervisor
AVCC
VCCD0
VCCD1
VPPD0
VPPD1
PCI1510
(PC Card
Controller)
VPP1
VPP2
VCC
VCC
PC Card
Figure 3−3. TPS2211A Typical Application
3.5.3
Zoomed Video Support
The controller allows for the implementation of zoomed video (ZV) for PC Cards. Zoomed video is supported by
setting bit 6 (ZVENABLE) in the card control register (PCI offset 91h, see Section 4.32). Setting this bit puts 16-bit
PC Card address lines A25−A4 of the PC Card interface in the high-impedance state. These lines can then transfer
video and audio data directly to the appropriate controller. Card address lines A3−A0 can still access PC Card CIS
registers for PC Card configuration. Figure 3−4 illustrates a ZV implementation.
Speakers
CRT
Motherboard
PCI Bus
VGA
Controller
Audio
Codec
Zoomed Video
Port
19
PCI1510
PCM
Audio
Input
4
PC Card
19
PC Card
Interface
Video
Audio
4
Figure 3−4. Zoomed Video Implementation Using the PCI1510 Controller
Not shown in Figure 3−4 is the multiplexing scheme used to route a socket ZV source to the graphics controller. The
controller provides ZVSTAT and ZVSEL0 signals on the multifunction terminals to switch external bus drivers.
Figure 3−5 shows an implementation for switching between two ZV streams using external logic.
3−5
PCI1510
ZVSTAT
ZVSEL0
Figure 3−5. Zoomed Video Switching Application
Figure 3−5 illustrates an implementation using standard three-state bus drivers with active-low output enables.
ZVSEL0 is an active-low output indicating that the socket ZV mode is enabled.
3.5.4
Standardized Zoomed-Video Register Model
The standardized zoomed-video register model is defined for the purpose of standardizing the ZV port control for PC
Card controllers across the industry. The following list summarizes the standardized zoomed-video register model
changes to the existing PC Card register set.
•
Socket present state register (CardBus socket address + 08h, see Section 6.3)
Bit 27 (ZVSUPPORT) has been added. The platform BIOS can set this bit via the socket force event register
(CardBus socket address + 0Ch, see Section 6.4) to define whether zoomed video is supported on the
socket by the platform.
•
Socket force event register (CardBus socket address + 0Ch, see Section 6.4)
Bit 27 (FZVSUPPORT) has been added. The platform BIOS can use this bit to set the ZVSUPPORT bit in
the socket present state register (CardBus socket address + 08h, see Section 6.3) to define whether
zoomed video is supported on the socket by the platform.
•
Socket control register (CardBus socket address +10h, see Section 6.5)
Bit 11 (ZV_ACTIVITY) has been added. This bit is set when zoomed video is enabled for the PC Card socket.
Bit 10 (STDZVREG) has been added. This bit defines whether the PC Card controller supports the
standardized zoomed-video register model.
Bit 9 (ZVEN) is provided for software to enable or disable zoomed video.
If the STDZVEN bit (bit 0) in the diagnostic register (PCI offset 93h, see Section 4.34) is 1b, then the standardized
zoomed video register model is disabled. For backward compatibility, even if the STDZVEN bit is 0b (enabled), the
controller allows software to access zoomed video through the legacy address in the card control register (PCI offset
91h, see Section 4.32), or through the new register model in the socket control register (CardBus socket address +
10h, see Section 6.5).
3.5.4.1 Zoomed-Video Card Insertion and Configuration Procedure
1. A zoomed-video PC Card is inserted into an empty slot.
2. The card is detected and interrogated appropriately.
3−6
There are two types of PC Card controllers to consider.
•
Legacy controller not using the standardized ZV register model
Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to
determine if the standardized zoomed-video register model is supported. If the bit returns 0b, then software
must use legacy code to enable zoomed video.
•
Newer controller that uses the standardized ZV register model
Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to
determine if the standardized zoomed-video register model is supported. If the bit returns 1b, then software
can use the process/register model detailed in Table 3−2 to enable zoomed video.
Table 3−2. Zoomed-Video Card Interrogation
ZVSUPPORT
ZV_ACTIVITY
1
0
Set ZVEN to enable zoomed video.
1
1
Display a user message such as, The zoomed video protocol required by this PC Card application is already in use by another card.
0
X
Display a user message such as, This platform does not support the zoomed-video protocol required by
this PC Card application.
3.5.5
ACTION
Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the controller so that neither the PCI clock nor an
external clock is required in order for the controller to power down a socket or interrogate a PC Card. This internal
oscillator can be enabled by setting bit 27 (P2CCLK) of the system control register (PCI offset 80h, see Section 4.29)
to 1b. This function is enabled by default.
3.5.6
Integrated Pullup Resistors
The PC Card Standard (release 7.2) requires pullup resistors on various terminals to support both CardBus and 16-bit
card configurations. Unlike the PCI12XX, PCI1450, and PCI4450 controllers which required external pullup resistors,
the PCI1510 controller has integrated all of these pullup resistors. The I/O buffer on the BVD1(STSCHG)//CSTSCHG
terminal has the capability to switch either pullup or pulldown. The pullup resistor is turned on when a 16-bit PC Card
is inserted, and the pulldown resistor is turned on when a CardBus PC Card is inserted. This prevents unexpected
CSTSCHG signal assertion. The integrated pullup resistors are listed in Table 3−3.
Table 3−3. Integrated Pullup Resistors
TERMINAL NUMBER
SIGNAL NAME
TERMINAL NUMBER
SIGNAL NAME
PGE
GGU
GVF
PGE
GGU
GVF
A14/CPERR
102
D12
F15
CD2/CCD2
138
B05
C09
A15/CIRDY
110
C10
F13
INPACK/CREQ
122
B08
B12
A19/CBLOCK
101
A13
E18
READY/CINT
131
A06
C10
A20/CSTOP
103
E10
E17
RESET/CRST
119
D08
B13
A21/CDEVSEL
106
D11
A16
VS1/CVS1
130
B02
B10
A22/CTRDY
108
C12
E14
VS2/CVS2
117
A09
F12
BVD1(STSCHG)/CSTSCHG
135
C06
A09
WAIT/CSERR
133
B06
E10
BVD2(SPKR)/CAUDIO
134
D06
F10
WP(IOIS16)/CCLKRUN
136
A05
B09
CD1/CCD1
75
L13
L17
3−7
3.5.7
SPKROUT and CAUDPWM Usage
SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for
I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and
is referred to as CAUDIO. SPKR passes a TTL-level digital audio signal to the controller. The CardBus CAUDIO signal
also can pass a single-amplitude binary waveform. The binary audio signal from the PC Card socket is used in the
controller to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card control register (PCI offset
91h, see Section 4.32).
Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips
may not support both modes on one terminal and may have a separate terminal for binary and PWM. The
implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2
(AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal to
CAUDPWM. See Section 4.30, Multifunction Routing Register, for details on configuring the MFUNC terminals.
Figure 3−6 provides an illustration of a sample application using SPKROUT and CAUDPWM.
System
Core Logic
BINARY_SPKR
SPKROUT
Speaker
Subsystem
PCI1510
CAUDPWM
PWM_SPKR
Figure 3−6. Sample Application of SPKROUT and CAUDPWM
3.5.8
LED Socket Activity Indicators
The socket activity LED is provided to indicate when a PC Card is being accessed. The LED_SKT signal can be routed
to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate
socket activity. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction
terminals.
The active-high LED signal is driven for 64-ms. When the LED is not being driven high, it is driven to a low state. Either
of the two circuits shown in Figure 3−7 can be implemented to provide LED signaling, and the board designer must
implement the circuit that best fits the application.
The LED activity signal is valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, IRDY,
or CREQ are active.
3−8
Current Limiting
R ≈ 500 Ω
LED
PCI1510
ApplicationSpecific Delay
Current Limiting
R ≈ 500 Ω
LED
PCI1510
Figure 3−7. Two Sample LED Circuits
As indicated, the LED signal is driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.
3.5.9
CardBus Socket Registers
The controller contains all registers for compatibility with the PC Card Standard. These registers exist as the CardBus
socket registers and are listed in Table 3−4.
Table 3−4. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present state
08h
Socket force event
0Ch
Socket control
Reserved
Socket power management
10h
14h−1Ch
20h
3.6 Serial-Bus Interface
The controller provides a serial-bus interface to load subsystem identification information and selected register
defaults from a serial EEPROM, and to provide a PC Card power-switch interface alternative. The serial-bus interface
is compatible with various I2C and SMBus components.
3.6.1
Serial-Bus Interface Implementation
To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the
appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4
terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (PCI offset
B3h, see Section 4.48) is set. The SBDETECT bit is cleared by a writeback of 1b.
The controller implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). When
pullup resistors are provided on the VCCD0 and VCCD1 terminals, the SCL signal is mapped to the MFUNC4 terminal
and the SDA signal is mapped to the MFUNC1 terminal. The controller drives SCL at nearly 100 kHz during data
3−9
transfers, which is the maximum specified frequency for standard-mode I2C. The serial EEPROM must be located
at address A0h. Figure 3−8 illustrates an example application implementing the two-wire serial bus.
VCC
Serial
EEPROM
5V
PCI1510
A2
VCCD0
A1
VCCD1
A0
SCL
MFUNC4
SDA
MFUNC1
Figure 3−8. Serial EEPROM Application
Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other
devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches
are discussed in the sections that follow.
3.6.2
Serial-Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−8.
The controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I2C using 7-bit
addressing.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to low state while SCL is in the high state, as illustrated
in Figure 3−9. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3−9. Data on SDA must remain stable during the
high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
SDA
SCL
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 3−9. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−10
illustrates the acknowledge protocol.
3−10
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−10. Serial-Bus Protocol Acknowledge
The controller is a serial bus master; all other devices connected to the serial bus external to the controller are slave
devices. As the bus master, the controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL
in a high-impedance state (zero frequency) during idle states.
Typically, the controller masters byte reads and byte writes under software control. Doubleword reads are performed
by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See
Section 3.6.3, Serial-Bus EEPROM Application, for details on how the controller automatically loads the subsystem
identification and other register defaults through a serial-bus EEPROM.
Figure 3−11 illustrates a byte write. The controller issues a start condition and sends the 7-bit slave device address
and the command bit zero. A 0b in the R/W command bit indicates that the data transfer is a write. The slave device
acknowledges if it recognizes the address. If no acknowledgment is received by the controller, then an appropriate
status bit is set in the serial-bus control and status register (PCI offset B3h, see Section 4.48). The word address byte
is then sent by the controller, and another slave acknowledgment is expected. Then the controller delivers the data
byte MSB first and expects a final acknowledgment before issuing the stop condition.
Slave Address
S
Word Address
b6 b5 b4 b3 b2 b1 b0
0
A
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
A b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3−11. Serial-Bus Protocol − Byte Write
Figure 3−12 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1b to indicate a read-data transfer. In addition, the master must acknowledge reception of the read
bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL
signal remains driven by the master.
Slave Address
S
Start
Word Address
b6 b5 b4 b3 b2 b1 b0
0
R/W
A
b7 b6 b5 b4 b3 b2 b1 b0
Slave Address
A
S
b6 b5 b4 b3 b2 b1 b0
Restart
1
A
R/W
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
M
P
Stop
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−12. Serial-Bus Protocol − Byte Read
Figure 3−13 illustrates EEPROM interface doubleword data collection protocol.
3−11
Slave Address
S
1
0
1
0
0
Word Address
0
0
Start
0
A
Slave Address
b7 b6 b5 b4 b3 b2 b1 b0
M
A = Slave Acknowledgement
S
1
0
1
0
0
Data Byte 2
M
Data Byte 1
M
M = Master Acknowledgement
Data Byte 0
0
0
1
A
R/W
Restart
R/W
Data Byte 3
A
M
P
S/P = Start/Stop Condition
Figure 3−13. EEPROM Interface Doubleword Data Collection
3.6.3
Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the controller attempts to read the subsystem
identification and other register defaults from a serial EEPROM. The registers and corresponding bits that can be
loaded with defaults through the EEPROM are provided in Table 3−5.
Table 3−5. Register- and Bit-Loading Map
EEPROM OFFSET
REGISTER OFFSET
00h
Flag
01h
PCI 04h
REGISTER BITS LOADED FROM EEPROM
01h: Load / FFh: do not load
Command register, bit 8, 6−5, 2−0
Note: bits loaded per following:
bit 8 ← bit 7
bit 6 ← bit 6
bit 5 ← bit 5
bit 2 ← bit 2
bit 1 ← bit 1
bit 0 ← bit 0
3−12
02h
PCI 40h
Subsystem vendor ID bits 7−0 ← bits 7−0
03h
PCI 40h
Subsystem vendor ID bits 15−8 ← bits 7−0
04h
PCI 42h
Subsystem ID bits 7−0 ← bits 7−0
05h
PCI 42h
Subsystem ID bits 15−8 ← bits 7−0
06h
PCI 44h
PC Card 16-bit I/F LBAR bits 7−1 ← bits 7−1
07h
PCI 44h
PC Card 16-bit I/F LBAR bits 15−8 ← bits 7−0
08h
PCI 44h
PC Card 16-bit I/F LBAR bits 23−16 ← bits 7−0
09h
PCI 44h
PC Card 16-bit I/F LBAR bits 31−24 ← bits 7−0
0Ah
PCI 80h
System control bits 7−0 ← bits 7−0
0Bh
PCI 80h
System control bits 15−8 ← bits 7−0
0Ch
PCI 80h
System control bits 23−16 ← bits 7−0
0Dh
PCI 80h
System control bits 31−24 ← bits 7−0
0Eh
PCI 8Ch
Multifunction routing bits 7−0 ← bits 7−0
0Fh
PCI 8Ch
Multifunction routing bits 15−8 ← bits 7−0
10h
PCI 8Ch
Multifunction routing bits 23−16 ← bits 7−0
11h
PCI 8Ch
Multifunction routing bits 27−24 ← bits 3−0
12h
PCI 90h
Retry status bits 7, 6 ← bits 7, 6
13h
PCI 91h
Card control bit 7 ← bit 7
14h
PCI 92h
Device control bits 6, 3−0 ← bits 6, 3−0
15h
PCI 93h
Diagnostic bits 7, 4–0 ← bits 7, 4−0
16h
PCI A2h
Power management capabilities bit 15 ← bit 7
17h
ExCA 00h
18h
CB Socket + 0Ch
ExCA identification and revision bits 7–0 ← bits 7−0
Socket force event, bit 27 ← bit 3
This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must be
considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3−8) assumes the 1010b high-address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
3.6.4
Accessing Serial-Bus Devices Through Software
The controller provides a programming mechanism to control serial bus devices through software. The programming
is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−6 lists the registers used
to program a serial-bus device through software.
Table 3−6. PCI1510 Registers Used to Program Serial-Bus Devices
PCI OFFSET
REGISTER NAME
DESCRIPTION
B0h
Serial-bus data
Contains the data byte to send on write commands or the received data byte on read commands.
B1h
Serial-bus index
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B2h
Serial-bus slave
address
Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W command selector are programmed through this register.
B3h
Serial-bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
controller. The controller provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and
industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The controller is, therefore,
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller using
one of several interrupt signaling protocols. To simplify the discussion of interrupts in the controller, PC Card interrupts
are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of interrupt is communicated to the host interrupt controller varies from system to
system. The controller offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type
IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel
PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All
interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6.
3.7.1
PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
controller and may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from the PC Card socket, as well as transitions of certain PC Card signals.
3−13
Table 3−7 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards
that can be inserted into any PC Card socket are:
•
•
•
16-bit memory card
16-bit I/O card
CardBus cards
Table 3−7. Interrupt Mask and Flag Registers
CARD TYPE
16-bit memory
16-bit I/O
All 16-bit PC
Cards
CardBus
EVENT
MASK
FLAG
Battery conditions (BVD1, BVD2)
ExCA offset 05h/45h/805h bits 1 and 0
ExCA offset 04h/44h/804h bits 1 and 0
Wait states (READY)
ExCA offset 05h/45h/805h bit 2
ExCA offset 04h/44h/804h bit 2
Change in card status (STSCHG)
ExCA offset 05h/45h/805h bit 0
ExCA offset 04h/44h/804h bit 0
Interrupt request (IREQ)
Always enabled
PCI configuration offset 91h bit 0
Power cycle complete
ExCA offset 05h/45h/805h bit 3
ExCA offset 04h/44h/804h bit 3
Change in card status (CSTSCHG)
Socket mask bit 0
Socket event bit 0
Interrupt request (CINT)
Always enabled
PCI configuration offset 91h bit 0
Power cycle complete
Socket mask bit 3
Socket event bit 3
Card insertion or removal
Socket mask bits 2 and 1
Socket event bits 2 and 1
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type.
Table 3−8. PC Card Interrupt Events and Description
CARD TYPE
16-bit
memory
16-bit I/O
CardBus
All PC Cards
EVENT
TYPE
SIGNAL
DESCRIPTION
BVD1(STSCHG)//CSTSCHG
A transition on BVD1 indicates a change in the
PC Card battery conditions.
BVD2(SPKR)//CAUDIO
A transition on BVD2 indicates a change in the
PC Card battery conditions.
Battery conditions
(BVD1, BVD2)
CSC
Wait states
(READY)
CSC
READY(IREQ)//CINT
Change in card
status (STSCHG)
CSC
BVD1(STSCHG)//CSTSCHG
The assertion of STSCHG indicates a status change
on the PC Card.
Interrupt request
(IREQ)
Functional
READY(IREQ)//CINT
The assertion of IREQ indicates an interrupt request
from the PC Card.
Change in card
status (CSTSCHG)
CSC
BVD1(STSCHG)//CSTSCHG
Interrupt request
(CINT)
Functional
READY(IREQ)//CINT
Card insertion
or removal
CSC
CD1//CCD1,
CD2//CCD2
Power cycle
complete
CSC
N/A
A transition on READY indicates a change in the
ability of the memory PC Card to accept or provide
data.
The assertion of CSTSCHG indicates a status
change on the PC Card.
The assertion of CINT indicates an interrupt request
from the PC Card.
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or
CardBus PC Card.
An interrupt is generated when a PC Card power-up
cycle has completed.
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
3−14
The PC Card Standard describes the power-up sequence that must be followed by the controller when an insertion
event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up
sequence, the interrupt scheme can be used to notify the host system (see Table 3−8), denoted by the power cycle
complete event. This interrupt source is considered an internal event, because it depends on the completion of
applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2
Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−8 by setting
the appropriate bits in the controller. By individually masking the interrupt sources listed, software can control those
events that cause an interrupt. Host software has some control over the system interrupt the controller asserts by
programming the appropriate routing registers. The controller allows host software to route PC Card CSC and PC
Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling
method used is discussed in more detail in the following sections.
When an interrupt is signaled by the controller, the interrupt service routine must determine which of the events listed
in Table 3−7 caused the interrupt. Internal registers in the controller provide flags that report the source of an interrupt.
By reading these status bits, the interrupt service routine can determine the action to be taken.
Table 3−7 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the controller from passing PC Card functional interrupts through to the
appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never
be a card interrupt that does not require service after proper initialization.
Table 3−7 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1b to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by
bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to
the flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1b to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software should not program the chip through both register sets when a CardBus card is functioning.
3.7.3
Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the controller can be routed to obtain a
subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel
ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see
Section 4.33), to select the parallel IRQ signaling scheme. See Section 4.30, Multifunction Routing Register, for
details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11,
and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the
MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3−14. Not shown is
that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel
PCI interrupts to the host.
3−15
PCI1510
MFUNC1
IRQ3
PIC
MFUNC2
IRQ4
MFUNC3
IRQ5
MFUNC4
IRQ10
MFUNC5
IRQ11
MFUNC6
IRQ15
Figure 3−14. IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration
of a system implementing the controller. See Section 4.30, Multifunction Routing Register, for details on configuring
the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the controller makes available.
3.7.4
Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. Socket functional interrupts can be routed to INTA.
3.7.5
Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the controller uses a single terminal to communicate all interrupt
status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple
interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data
describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on
the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6
SMI Support in the PCI1510 Controller
The controller provides a mechanism for interrupting the system when power changes have been made to the PC
Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme.
SMI interrupts are generated by the controller, when enabled, after a write cycle to either the socket control register
(CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset
02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−9 describes the SMI control
bits function.
Table 3−9. SMI Control
BIT NAME
FUNCTION
SMIROUTE
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
SMISTAT
This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back 1b.
SMIENB
When set, SMI interrupt generation is enabled.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing register (PCI offset 8Ch, see Section 4.30).
3−16
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the controller, various features are designed into
the device to allow implementation of popular power-saving techniques. These features and techniques are
discussed in this section.
3.8.1
Integrated Low-Dropout Voltage Regulator (LDO-VR)
The controller requires 2.5-V core voltage. The core power can be supplied by the controller itself using the internal
LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal.
Table 3−10 lists the requirements for both the internal core power supply and the external core power supply.
Table 3−10. Requirements for Internal/External 2.5-V Core Power Supply
SUPPLY
VR_EN
VR_PORT
Internal
VCC
3.3 V
GND
2.5-V output
Internal 2.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
External
3.3 V
VCC
2.5-V input
Internal 2.5-V LDO-VR is disabled. An external 2.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.
3.8.2
NOTE
Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the controller.
CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this
is not always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the PCI Mobile Design Guide.
The controller does not permit the central resource to stop the PCI clock under any of the following conditions:
•
•
•
•
•
•
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
The 16-bit PC Card- resource manager is busy.
The CardBus master state machine is busy. A cycle may be in progress on CardBus.
The master is busy. There may be posted data from CardBus to PCI in the controller.
Interrupts are pending.
The CardBus CCLK for either socket has not been stopped by the CCLKRUN manager.
The controller restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
• A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
•
A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket.
•
A CardBus attempts to start the CCLK using CCLKRUN.
•
A CardBus card arbitrates for the CardBus bus using CREQ.
3.8.3
CardBus PC Card Power Management
The controller implements its own card power-management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface
to control this clock management.
3.8.4
16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) bits are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3−17
3.8.5
Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the controller. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the controller
in order to minimize power consumption.
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor
an external clock is routed to the serial-interrupt state machine. Figure 3−15 is a signal diagram of the suspend
function.
RESET
GNT
SUSPEND
PCLK
External Terminals
Internal Signals
RESETIN
SUSPENDIN
PCLKIN
Figure 3−15. Signal Diagram of Suspend Function
3.8.6
Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which
would require the reconfiguration of the controller by software. Asserting the SUSPEND signal places the PCI outputs
of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI
transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the controller
when SUSPEND is asserted, because the outputs are in a high-impedance state.
The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the
appropriate registers.
3−18
3.8.7
Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT on the controller can be asserted under any of the following conditions:
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an
incoming call.
•
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.
•
A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3−16 shows various enable bits for the RI_OUT function; however, it does not show the masking of CSC
events. See Table 3−7 for a detailed description of CSC interrupt masks and flags.
RI_OUT Function
CSTSMASK
RIENB
PC Card
Socket
Card
I/F
RINGEN
RI_OUT
CDRESUME
Figure 3−16. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA offset 03h/43h/803h, see Section 5.4). This is only applicable when a 16-bit card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the
CardBus socket registers.
RI_OUT can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT
function is enabled by setting RIENB in the card control register (PCI offset 91h, see Section 4.32). The PME function
is enabled by setting PMEEN in the power management control/status register (PCI offset A4h, see Section 4.38).
When RIMUX in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, both the RI_OUT function
and the PME function are routed to the RI_OUT/PME terminal. If both functions are enabled and RIMUX is set to 0b,
the RI_OUT/PME terminal becomes RI_OUT only and PME assertions will never be seen. Therefore, in a system
using both the RI_OUT function and the PME function, RIMUX must be set to 1b and RI_OUT must be routed to either
MFUNC2 or MFUNC4.
3.8.8
PCI Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required to let the operating system control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of seven power-management states, resulting in varying levels of power savings.
The seven power-management states of PCI functions are:
•
•
•
•
D0-uninitialized − Before device configuration, device not fully functional
D0-active − Fully functional state
D1 − Low-power state
D2 − Low-power state
3−19
•
•
•
D3hot − Low-power state. Transition state before D3cold
D3cold − PME signal-generation capable. Main power is removed and VAUX is available.
D3off − No power and completely non-functional
NOTE:
In the D0-uninitialized state, the controller does not generate PME and/or interrupts. When the IO_EN and
MEM_EN bits (bits 0 and 1) of the command register (PCI offset 04h, see Section 4.4) are both set, the
controller switches the state to D0-active. Transition from D3cold to the D0-uninitialized state happens at
the deassertion of PRST. The assertion of GRST forces the controller to the D0-uninitialized state
immediately.
The PWR_STATE bits (bits 0−1) of the power-management control/status register (PCI offset A4h, see
Section 4.38) only code for four power states, D0, D1, D2, and D3hot. The differences between the three
D3 states is invisible to the software because the controller is not accessible in the D3cold or D3off state.
Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the device power states on the PCI bus, the PCI function should support
four power-management operations. These operations are:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1b in bit 4 (CAPLIST) of the status register
(PCI offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the controller, a CardBus
bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first
byte of each capability register block is required to be a unique ID of that capability. PCI power management has been
assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more
items in the list, then the next item pointer must be set to 0b. The registers following the next item pointer are specific
to the capability of the function. The PCI power-management capability implements the register block outlined in
Table 3−11.
Table 3−11. Power-Management Registers
REGISTER NAME
Power-management capabilities
Power-management data
Power-management
control/status bridge
support extensions
OFFSET
Next-item pointer
Capability ID
Power-management control/status
A0h
A4h
The power management capabilities register (PCI offset A2h, see Section 4.37) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI offset
A4h, see Section 4.38) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.9
CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3hot or D3cold
without losing wake-up context (also called PME context).
3−20
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake up are as follows:
•
Preservation of device context. The specification states that a reset must occur during the transition from
D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
•
Power source in D3cold if wake-up support is required from this state.
The PCI1510 controller addresses these D3 wake-up issues in the following manner:
•
•
Two resets are provided to handle preservation of PME context bits:
−
Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
controller in its default state and requires BIOS to configure the device before becoming fully functional.
−
PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled,
then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.11.
Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an
auxiliary power source must be supplied to the VCC terminals. Consult the PCI14xx Implementation Guide
for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for
further information.
3.8.10 ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The controller offers a generic interface that is compliant with
ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI configuration space at offset A8h. The
programming model is broken into status and control functions. In compliance with ACPI, the top level event status
and enable bits reside in the general-purpose event status register (PCI offset A8h, see Section 4.41) and
general-purpose event enable register (PCI offset AAh, see Section 4.42). The status and enable bits are
implemented as defined by ACPI and illustrated in Figure 3−17.
Status Bit
Event Input
Enable Bit
Event Output
Figure 3−17. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3−21
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits
If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see section 4.38) is
asserted, then the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted,
then the PME context bits are cleared with PRST. The PME context bits are:
•
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh): bit 6
System control register (PCI offset 80h): bits 10, 9, 8
Power-management control/status register (PCI offset A4h): bits 15, 8
ExCA power control register (ExCA offset 802h): bits 7, 5†, 4−3, 1−0 († 82365SL mode only)
ExCA interrupt and general control register (ExCA offset 803h): bits 6−5
ExCA card status change register (ExCA offset 804h): bits 11−8, 3−0
ExCA card status-change-interrupt configuration register (ExCA offset 805h): bits 3−0
CardBus socket event register (CardBus offset 00h): bits 3−0
CardBus socket mask register (CardBus offset 04h): bits 3−0
CardBus socket present state register (CardBus offset 08h): bits 13−7, 5−1
CardBus socket control register (CardBus offset 10h): bits 6−4, 2−0
Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST signal
is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally,
thus preserving all register contents. The registers cleared only by GRST are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3−22
Status register (PCI offset 06h): bits 15−11, 8
Secondary status register (PCI offset 16h): bits 15−11, 8
Interrupt pin register (PCI offset 3Dh): bits 1,0
Subsystem vendor ID register (PCI offset 40h): bits 15–0
Subsystem ID register (PCI offset 42h): bits 15–0
PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1
System control register (PCI offset 80h): bits 31–29, 27–13, 11, 6−0
Multifunction routing register (PCI offset 8Ch): bits 27−0
Retry status register (PCI offset 90h): bits 7−5, 3, 1
Card control register (PCI offset 91h): bits 7−5, 2−0
Device control register (PCI offset 92h): bits 7−5, 3−0
Diagnostic register (PCI offset 93h): bits 7−0
Power management capabilities register (PCI offset A2h): bit 15
General-purpose event status register (PCI offset A8h): bits 15−14
General-purpose event enable register (PCI offset AAh): bits 15−14, 11, 8, 4−0
General-purpose output (PCI offset AEh): bits 4−0
Serial bus data (PCI offset B0h): bits 7−0
Serial bus index (PCI offset B1h): bits 7−0
Serial bus slave address register (PCI offset B2h): bits 7−0
Serial bus control and status register (PCI offset B3h): bits 7, 5−0
ExCA identification and revision register (ExCA offset 00h): bits 7−0
ExCA global control register (ExCA offset 1Eh): bits 2−0
Socket present state register (CardBus offset 08h): bit 29
Socket power management register (CardBus offset 20h): bits 25−24
4 PC Card Controller Programming Model
This chapter describes the PCI1510 PCI configuration registers that make up the 256-byte PCI configuration header.
4.1 PCI Configuration Registers
The configuration header is compliant with the PCI Local Bus Specification as a CardBus bridge header and is PC 99
compliant as well. Table 4−1 shows the PCI configuration header, which includes both the predefined portion of the
configuration space and the user-definable registers.
Table 4−1. PCI Configuration Registers
REGISTER NAME
OFFSET
Device ID
Vendor ID
Status
00h
Command
Class code
BIST
Header type
Latency timer
04h
Revision ID
08h
Cache line size
0Ch
CardBus socket/ExCA base address
Secondary status
CardBus latency timer
Subordinate bus number
10h
Reserved
Capability pointer
CardBus bus number
PCI bus number
1Ch
CardBus Memory limit register 0
20h
CardBus Memory base register 1
24h
CardBus Memory limit register 1
28h
CardBus I/O base register 0
2Ch
CardBus I/O limit register 0
30h
CardBus I/O base register 1
34h
CardBus I/O limit register 1
38h
Interrupt pin
Subsystem ID
Interrupt line
Subsystem vendor ID
3Ch
40h
PC Card 16-bit I/F legacy-mode base address
44h
Reserved
48h−7Ch
System control
80h
Reserved
84h−88h
Multifunction routing
8Ch
Device control
Card control
Retry status
Reserved
Power-management capabilities
Power-management data
18h
CardBus Memory base register 0
Bridge control
Diagnostic
14h
Next-item pointer
Power-management
control/status bridge
support extensions
90h
94h−9Ch
Capability ID
Power-management control/status
A0h
A4h
General-purpose event enable
General-purpose event status
A8h
General-purpose output
General-purpose input
ACh
Serial bus control/status
Serial bus slave address
Reserved
Serial bus index
Serial bus data
B0h
B4h−FCh
4−1
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.
Table 4−2. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
R
Read
Field may be read by software.
W
Write
Field may be written by software to any value.
S
Set
C
Clear
U
Update
MEANING
Field may be set by a write of 1b. Writes of 0b have no effect.
Field may be cleared by a write of 1b. Writes of 0b have no effect.
Field may be autonomously updated by the controller.
4.2 Vendor ID Register
This 16-bit register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the manufacturer
of the PCI device. The vendor ID assigned to TI is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
Register:
Offset:
Type:
Default:
Vendor ID
00h
Read-only
104Ch
4.3 Device ID Register
This 16-bit register contains a value assigned to the controller by TI. The device identification for the controller is
AC56h.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
0
1
0
1
1
0
0
0
1
0
1
0
1
1
0
Register:
Offset:
Type:
Default:
4−2
Device ID
02h
Read-only
AC56h
4.4 Command Register
The command register provides control over the controller interface to the PCI bus. All bit functions adhere to the
definitions in PCI Local Bus Specification. See Table 4−3 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 4−3. Command Register Description
BIT
SIGNAL
TYPE
15−10
RSVD
R
Reserved. Bits 15−10 return 00 0000b when read.
FUNCTION
9
FBB_EN
R
Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, bit 9
returns 0b when read.
8
SERR_EN
RW
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can
be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the
controller to report address parity errors.
0 = Disable SERR output driver (default)
1 = Enable SERR output driver
7
STEP_EN
R
Address/data stepping control. The controller does not support address/data stepping; therefore, bit 7 is
hardwired to 0b.
6
PERR_EN
RW
Parity error response enable. Bit 6 controls the controller response to parity errors through PERR. Data
parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting
SERR.
0 = The controller ignores detected parity error (default)
1 = The controller responds to detected parity errors
5
VGA_EN
RW
VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette
registers.
4
MWI_EN
R
Memory write-and-invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory
write-and-Invalidate commands. The controller does not support memory write-and-invalidate commands,
but uses memory write commands instead; therefore, this bit is hardwired to 0b.
3
SPECIAL
R
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The controller does
not respond to special cycle operations; therefore, this bit is hardwired to 0b.
2
MAST_EN
RW
Bus master control. Bit 2 controls whether or not the controller can act as a PCI bus initiator (master). The
controller can take control of the PCI bus only when this bit is set.
0 = Disables the controller from generating PCI bus accesses (default)
1 = Enables the controller to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. Bit 1 controls whether or not the controller can claim cycles in PCI memory space.
0 = Disables the controller from responding to memory space accesses (default)
1 = Enables the controller to respond to memory space accesses
0
IO_EN
RW
I/O space control. Bit 0 controls whether or not the controller can claim cycles in PCI I/O space.
0 = Disables the controller from responding to I/O space accesses (default)
1 = Enables the controller to respond to I/O space accesses
4−3
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1b is written to that bit location; a 0b written to a bit location has no effect. All
bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 4−4 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Register:
Offset:
Type:
Default:
Status
06h
Read-only, Read/Clear
0210h
Table 4−4. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
PAR_ERR
RC
Detected parity error. Bit 15 is set when a parity error is detected (either address or data).
14
SYS_ERR
RC
Signaled system error. Bit 14 is set when SERR is enabled and the controller signals a system error to the host.
13
MABORT
RC
Received master abort. Bit 13 is set when a cycle initiated by the controller on the PCI bus is terminated by a
master abort.
12
TABT_REC
RC
Received target abort. Bit 12 is set when a cycle initiated by the controller on the PCI bus is terminated by a
target abort.
11
TABT_SIG
RC
Signaled target abort. Bit 11 is set by the controller when it terminates a transaction on the PCI bus with a target
abort.
10−9
PCI_SPEED
R
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the controller
asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
Data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred, and the following conditions were met:
a. PERR was asserted by any PCI device including the controller.
b. The controller was the bus master during the data parity error.
c. The parity error response bit is set in the command register (PCI offset 04h, see Section 4.4).
8
DATAPAR
RC
7
FBB_CAP
R
Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, bit 7 is
hardwired to 0b.
6
UDF
R
User-definable feature support. The controller does not support the user-definable features; therefore, bit 6 is
hardwired to 0b.
5
66MHZ
R
66-MHz capable. The controller operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is
hardwired to 0b.
4
CAPLIST
R
Capabilities list. Bit 4 returns 1b when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
3−0
RSVD
R
Reserved. Bits 3−0 return 0h when read.
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the controller.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4−4
Revision ID
08h
Read-only
00h
4.7 PCI Class Code Register
The class code register recognizes the controller as a bridge device (06h) and a CardBus bridge device (07h), with
a 00h programming interface.
Bit
23
22
21
0
0
0
Name
Default
20
19
18
17
16
15
14
13
1
1
0
0
0
0
Base class
Register:
Offset:
Type:
Default:
0
0
12
11
10
9
8
7
6
1
1
1
0
0
Subclass
0
0
5
4
3
2
1
0
0
0
Programming interface
0
0
0
0
PCI class code
09h
Read-only
06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Cache line size
0Ch
Read/Write
00h
4.9 Latency Timer Register
The latency timer register specifies the latency time for the controller in units of PCI clock cycles. When the controller
is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires
before the transaction has terminated, then the controller terminates the transaction when its GNT is deasserted.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Latency timer
0Dh
Read/Write
00h
4.10 Header Type Register
This register returns 02h when read, indicating that the configuration space adheres to the CardBus bridge PCI
header. The CardBus bridge PCI header ranges from PCI register 00h to 7Fh, and 80h to FFh is user-definable
extension registers.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
0
Register:
Offset:
Type:
Default:
Header type
0Eh
Read-only
02h
4−5
4.11 BIST Register
Because the controller does not support a built-in self-test (BIST), this register returns the value of 00h when read.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
BIST
0Fh
Read-only
00h
4.12 CardBus Socket/ExCA Base-Address Register
The CardBus socket/ExCA base-address register is programmed with a base address referencing the CardBus
socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write and allow the base address
to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only,
returning 000h when read. When software writes FFFF FFFFh to this register, the value read back is FFFF F000h,
indicating that at least 4 Kbytes of memory address space are required. The CardBus registers start at offset 000h,
and the memory-mapped ExCA registers begin at offset 800h.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
CardBus socket/ExCA base-address
10h
Read-only, Read/Write
0000 0000h
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI
power-management register block resides. PCI header doublewords at A0h and A4h provide the power-management
(PM) registers. This register returns A0h when read.
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
4−6
Capability pointer
14h
Read-only
A0h
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates
CardBus-related device information to the host system. This register is very similar to the status register (offset 06h,
see Section 4.5); status bits are cleared by writing a 1b. See Table 4−5 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Secondary status
16h
Read-only, Read/Clear
0200h
Table 4−5. Secondary Status Register Description
BIT
SIGNAL
TYPE
15
CBPARITY
RC
Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data).
FUNCTION
14
CBSERR
RC
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The controller does not
assert CSERR.
13
CBMABORT
RC
Received master abort. Bit 13 is set when a cycle initiated by the controller on the CardBus bus has been
terminated by a master abort.
12
REC_CBTA
RC
Received target abort. Bit 12 is set when a cycle initiated by the controller on the CardBus bus is terminated
by a target abort.
11
SIG_CBTA
RC
Signaled target abort. Bit 11 is set by the controller when it terminates a transaction on the CardBus bus
with a target abort.
10−9
CB_SPEED
R
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the
controller asserts CB_SPEED at a medium speed.
CardBus data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
b. The controller was the bus master during the data parity error.
c. The parity error response bit is set in the bridge control.
8
CB_DPAR
RC
7
CBFBB_CAP
R
Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, bit 7
is hardwired to 0b.
6
CB_UDF
R
User-definable feature support. The controller does not support user-definable features; therefore, bit 6
is hardwired to 0b.
5
CB66MHZ
R
66-MHz capable. The CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore,
bit 5 is hardwired to 0b.
4−0
RSVD
R
Reserved. Bits 4−0 return 00000b when read.
4−7
4.15 PCI Bus Number Register
This register is programmed by the host system to indicate the bus number of the PCI bus to which the controller is
connected. The controller uses this register in conjunction with the CardBus bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
PCI bus number
18h
Read/Write
00h
4.16 CardBus Bus Number Register
This register is programmed by the host system to indicate the bus number of the CardBus bus to which the controller
is connected. The controller uses this register in conjunction with the PCI bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
CardBus bus number
19h
Read/Write
00h
4.17 Subordinate Bus Number Register
This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The
controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine
when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subordinate bus number
1Ah
Read/Write
00h
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the CardBus interface in units of CCLK
cycles. When the controller is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting.
If the latency timer expires before the transaction has terminated, then the controller terminates the transaction at
the end of the next data phase. A recommended minimum value for this register is 40h, which allows most
transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4−8
CardBus latency timer
1Bh
Read/Write
00h
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used
by the controller to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the controller to claim any memory transactions through CardBus memory windows (that is, these windows are
not enabled by default to pass the first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Memory base registers 0, 1
1Ch, 24h
Read-only, Read/Write
0000 0000h
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used
by the controller to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the controller to claim any memory transactions through CardBus memory windows; that is, these windows are
not enabled by default to pass the first 4 Kbytes of memory to CardBus.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Memory limit registers 0, 1
20h, 28h
Read-only, Read/Write
0000 0000h
4−9
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the
upper 16 bits (31−16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31−2
are read/write. Bits 1 and 0 are read-only and always return 00b, forcing I/O windows to be aligned on a natural
doubleword boundary.
NOTE: Either the I/O base register or the I/O limit register must be nonzero to enable any I/O
transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 0000h
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the
controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16
bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15−2 are read/write and
allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31−16 of the appropriate
I/O base) on doubleword boundaries.
Bits 31−16 are read-only and always return 0000h when read. The page is set in the I/O base register. Bits 1 and 0
are read-only and always return 00b, forcing I/O windows to be aligned on a natural doubleword boundary. Write
transactions to read-only bits have no effect. The controller assumes that the lower 2 bits of the limit address are 11b.
NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4−10
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 0000h
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information.
Bit
7
6
5
4
3
2
1
0
Default
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Default:
Interrupt line
3Ch
Read/Write
FFh
4.24 Interrupt Pin Register
The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode,
selected through bits 2−1 (INTMODE field) of the device control register (PCI offset 92h, see Section 4.33).
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Interrupt pin
3Dh
Read-only
01h
4−11
4.25 Bridge Control Register
The bridge control register provides control over various bridging functions. See Table 4−6 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Bridge control
3Eh
Read-only, Read/Write
0340h
Table 4−6. Bridge Control Register Description
BIT
SIGNAL
TYPE
15−11
RSVD
R
10
POSTEN
RW
Write posting enable. Enables write posting to and from the CardBus socket. Write posting enables posting
of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles.
Note that burst write data can be posted, but various write transactions may not.
RW
Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. Bit 9 is encoded
as:
0 = Memory window 1 is nonprefetchable
1 = Memory window 1 is prefetchable (default)
9
8
PREFETCH0
RW
Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
0 = Memory window 0 is nonprefetchable
1 = Memory window 0 is prefetchable (default)
7
INTR
RW
PCI interrupt − IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI
interrupts or the IRQ specified in the ExCA registers.
0 = Functional interrupts routed to PCI interrupts (default)
1 = Functional interrupts routed by ExCAs
6
CRST
RW
CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted
by passing a PRST assertion to CardBus.
0 = CRST deasserted
1 = CRST asserted (default)
Master abort mode. Bit 5 controls how the controller responds to a master abort when the controller is an
initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default)
1 = Signal target abort on PCI and SERR (if enabled)
5
MABTMODE
RW
4
RSVD
R
3
VGAEN
RW
VGA enable. Bit 3 affects how the controller responds to VGA addresses. When this bit is set, accesses
to VGA addresses are forwarded.
2
ISAEN
RW
ISA mode enable. Bit 2 affects how the controller passes I/O cycles within the 64-Kbyte ISA range. When
this bit is set, the controller does not forward the last 768 bytes of each 1K I/O range to CardBus.
1
CSERREN
RW
CSERR enable. Bit 1 controls the response of the controller to CSERR signals on the CardBus bus.
0 = CSERR is not forwarded to PCI SERR
1 = CSERR is forwarded to PCI SERR
RW
CardBus parity error response enable. Bit 0 controls the response of the controller to CardBus parity
errors.
0 = CardBus parity errors are ignored
1 = CardBus parity errors are reported using CPERR
0
4−12
PREFETCH1
FUNCTION
Reserved. Bits 15−11 return 00 0000b when read.
CPERREN
Reserved. Bit 4 returns 0b when read.
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system and option-card identification purposes and may be required
for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem vendor ID
40h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
4.27 Subsystem ID Register
The subsystem ID register is used for system and option-card identification purposes and may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem ID
42h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register
The controller supports the index/data scheme of accessing the ExCA registers, which are mapped by this register.
An address written to this register is the address for the index register and the address + 1 is the data address. Using
this access method, applications requiring index/data ExCA access can be supported. The base address can be
mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1b when read. See
Section 5, ExCA Compatibility Registers, for register offsets.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
PC Card 16-bit I/F legacy-mode base address
44h
Read-only, Read/Write
0000 0001h
4−13
4.29 System Control Register
System-level initializations are performed by programming this doubleword register. See Table 4−7 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
BIT
SIGNAL
System control
80h
Read-only, Read/Write, Read/Clear
0844 9060h
Table 4−7. System Control Register Description
TYPE
FUNCTION
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling
and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots.
00 = INTA signal in INTA IRQSER slots
01 = INTA signal in INTB IRQSER slots
10 = INTA signal in INTC IRQSER slots
11 = INTA signal in INTD IRQSER slots
31−30
SER_STEP
RW
29−28
RSVD
R
27
OSEN
R/W
Internal oscillator enable.
0 = Internal oscillator is disabled
1 = Internal oscillator is enabled (default)
26
SMIROUTE
RW
SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card
socket.
0 = PC Card power change interrupts routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes
Reserved. Bit 28 returns 0b when read.
25
SMISTATUS
RC
SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket power.
Writing a 1b to bit 25 clears the status.
0 = SMI interrupt signaled (default)
1 = SMI interrupt not signaled
24
SMIENB
RW
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt
signaling is enabled and generates an interrupt. This bit defaults to 0b (disabled).
23
RSVD
R
Reserved. Bit 23 returns 0b when read.
22
CBRSVD
RW
CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus
terminals are driven low. When this bit is 0b, these terminals are placed in a high-impedance state.
0 = Place CardBus RSVD terminals in a high-impedance state
1 = Drive Cardbus RSVD terminals low (default)
21
VCCPROT
RW
VCC protection enable.
0 = VCC protection enabled for 16-bit cards (default)
1 = VCC protection disabled for 16-bit cards
20
REDUCEZV
RW
Reduced zoomed video enable. When this bit is enabled, terminals A25−A22 of the card interface for PC
Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This
bit is encoded as:
0 = Reduced zoomed video disabled (default)
1 = Reduced zoomed video enabled
19−16
RSVD
RW
Reserved. Do not change the default value.
4−14
Table 4−7. System Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
15
MRBURSTDN
RW
Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to
burst downstream.
0 = Downstream memory read burst is disabled
1 = Downstream memory read burst is enabled (default)
14
MRBURSTUP
RW
Memory read burst enable upstream. When bit 14 is set, the controller allows memory read transactions
to burst upstream.
0 = Upstream memory read burst is disabled (default)
1 = Upstream memory read burst is enabled
13
SOCACTIVE
R
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and
is cleared upon read of this status bit.
0 = No socket activity (default)
1 = Socket activity
12
RSVD
R
Reserved. Bit 12 returns 1b when read.
11
PWRSTREAM
R
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream is
complete.
0 = Power stream is complete and delay has expired
1 = Power stream is in progress
10
DELAYUP
R
Power-up delay in progress status. When set, bit 10 indicates that a power-up stream has been sent to
the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay
has expired.
9
DELAYDOWN
R
Power-down delay in progress status. When set, bit 9 indicates that a power-down stream has been sent
to the power switch and proper power may not yet be stable. This bit is cleared when the power-down
delay has expired.
R
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when
interrogation completes.
0 = Interrogation not in progress (default)
1 = Interrogation in progress
8
INTERROGATE
7
AUTOPWRSWEN
R/W
Auto power-switch enable
0 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is disabled (default)
1 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is enabled
6
PWRSAVINGS
RW
Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,
then the applicable CB state machine will not be clocked.
5
SUBSYSRW
RW
Subsystem ID (PCI offset 42h, see Section 4.27), subsystem vendor ID (PCI offset 40H, see
Section 4.26), ExCA identification and revision (ExCA offset 00h/40h/800h, see Section 5.1) registers
read/write enable.
0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write
1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only
(default)
4
CB_DPAR
RW
CardBus data parity SERR signaling enable
0 = CardBus data parity not signaled on PCI SERR
1 = CardBus data parity signaled on PCI SERR
3
RSVD
RW
Reserved. Do not change the default value.
2
EXCAPOWER
RW
ExCA power-control bit.
0 = Enables 3.3 V
1 = Enables 5 V
1
KEEPCLK
RW
Keep clock. This bit works with PCI and CB CLKRUN protocols.
0 = Allows normal functioning of both CLKRUN protocols (default)
1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols
0
RIMUX
RW
RI_OUT/PME multiplex enable.
0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both functions are are enabled
at the same time, the terminal becomes RI_OUT only and PME assertions are not seen.
1 = Only PME is routed to the RI_OUT/PME terminal.
4−15
4.30 Multifunction Routing Register
The multifunction routing register is used to configure the MFUNC0−MFUNC6 terminals. These terminals may be
configured for various functions. All multifunction terminals default to the general-purpose input configuration. This
register is intended to be programmed once at power-on initialization. The default value for this register can also be
loaded through a serial bus EEPROM. See Table 4−8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Multifunction routing
8Ch
Read-only, Read/Write
0000 1000h
Table 4−8. Multifunction Routing Register Description
BIT
SIGNAL
TYPE
31−28
RSVD
R
27−24
23−20
MFUNC6
MFUNC5
FUNCTION
Bits 31−28 return 0h when read.
RW
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD†
0100 = IRQ4
1000 = IRQ8
1100 = IRQ12
0001 = CLKRUN
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
RW
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4†
0100 = IRQ4
1000 = CAUDPWM
1100 = LED_SKT
0001 = GPO4
0101 = D3_STAT 1001 = D3_STAT
1101 = LED_SKT
0010 = PCGNT
0110 = ZVSTAT
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0
1011 = IRQ11
1111 = IRQ15
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
19−16
MFUNC4
RW
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC4 terminal provides the SCL signaling.
0000 = GPI3†
0001 = GPO3
0010 = LOCK PCI
0011 = IRQ3
15−12
11−8
4−16
MFUNC3
MFUNC2
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
1111 = D3_STAT
RW
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
1100 = IRQ12
0001 = IRQSER†
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
RW
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2†
0100 = IRQ4
1000 = CAUDPWM
1100 = RI_OUT
0001 = GPO2
0101 = IRQ5
1001 = IRQ9
1101 = D3_STAT
0010 = PCREQ
0110 = ZVSTAT
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0
1011 = IRQ11
1111 = IRQ7
Table 4−8. Multifunction Routing Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
7−4
MFUNC1
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC1 terminal provides the SDA signaling.
RW
0000 = GPI1†
0001 = GPO1
0010 = D3_STAT
0011 = IRQ3
3−0
MFUNC0
RW
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = IRQ13
1110 = GPE
1111 = IRQ15
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0†
0100 = IRQ4
1000 = CAUDPWM
1100 = LED_SKT
0001 = GPO0
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = INTA
0110 = ZVSTAT
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0
1011 = IRQ11
1111 = IRQ15
† Default value
4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set
when the controller retries a PCI or CardBus master request and the master does not return within 215 PCI clock
cycles. The flags are cleared by writing a 1b to the bit. These bits are expected to be incorporated into the PCI
command, PCI status, and bridge control registers by the PCI SIG. See Table 4−9 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Retry status
90h
Read-only, Read/Write, Read/Clear
C0h
Table 4−9. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
PCIRETRY
RW
PCI retry timeout counter enable. Bit 7 is encoded:
0 = PCI retry counter disabled
1 = PCI retry counter enabled (default)
6
CBRETRY
RW
CardBus retry timeout counter enable. Bit 6 is encoded:
0 = CardBus retry counter disabled
1 = CardBus retry counter enabled (default)
5
TEXP_CBB
RC
CardBus target B retry expired. Write a 1b to clear bit 5.
0 = Inactive (default)
1 = Retry has expired
4
RSVD
R
3
TEXP_CBA
RC
2
RSVD
R
1
TEXP_PCI
RC
0
RSVD
R
Reserved. Bit 4 returns 0b when read.
CardBus target A retry expired. Write a 1b to clear bit 3.
0 = Inactive (default)
1 = Retry has expired
Reserved. Bit 2 returns 0b when read.
PCI target retry expired. Write a 1b to clear bit 1.
0 = Inactive (default)
1 = Retry has expired
Reserved. Bit 0 returns 0b when read.
4−17
4.32 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See
Table 4−10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Card control
91h
Read-only, Read/Write, Read/Clear
00h
Table 4−10. Card Control Register Description
BIT
TYPE
FUNCTION
7
RIENB
RW
Ring indicate output enable.
0 = Disables any routing of RI_OUT signal (default)
1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when RIMUX is set to 0b,
and for routing to MFUNC2 or MFUNC4
6
ZVENABLE
RW
Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter
a high-impedance state. This bit defaults to 0b.
5
RSVD
RW
Reserved. Do not change default value.
4−3
RSVD
R
2
AUD2MUX
RW
CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding
multifunction terminal which may be configured for CAUDPWM.
RW
Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The
SPKROUT terminal drives data only when the SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT not enabled
1 = SPKR to SPKROUT enabled
RC
Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a
functional interrupt is signaled from a PC Card interface. Write back a 1b to clear this bit.
0 = No PC Card functional interrupt detected (default).
1 = PC Card functional interrupt detected.
1
0
4−18
SIGNAL
SPKROUTEN
IFG
Reserved. Bits 4 and 3 return 00b when read.
4.33 Device Control Register
The device control register is provided for PCI1130 compatibility. See Table 4−11 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
1
1
0
0
1
1
0
Register:
Offset:
Type:
Default:
Device control
92h
Read-only, Read/Write
66h
Table 4−11. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
SKTPWR_LOCK
RW
Socket power lock bit. When this bit is set to 1b, software cannot power down the PC Card socket while
in D3. This may be necessary to support wake on LAN or RING if the operating system is programmed
to power down a socket when the CardBus controller is placed in the D3 state.
6
3VCAPABLE
RW
3-V socket capable force
0 = Not 3-V capable
1 = 3-V capable (default)
5
IO16V2
RW
Diagnostic bit. This bit defaults to 1b.
4
RSVD
R
Reserved. Bit 4 returns 0b when read.
3
TEST
RW
TI test. Only a 0b should be written to bit 3.
2−1
INTMODE
RW
Interrupt signaling mode. Bits 2 and 1 select the interrupt signaling mode. The interrupt signaling
mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Parallel IRQ and parallel PCI interrupts
10 = IRQ serialized interrupts and parallel PCI interrupt
11 = IRQ and PCI serialized interrupts (default)
0
RSVD
RW
Reserved. Bit 0 is reserved for test purposes. Only 0b should be written to this bit.
4−19
4.34 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 00h should be
written to it. See Table 4−12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
Diagnostic
93h
Read/Write
60h
Table 4−12. Diagnostic Register Description
BIT
SIGNAL
TYPE
7
TRUE_VAL
RW
6
RSVD
R
FUNCTION
This bit defaults to 0b. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default)
1 = Reads all 1s in reads from the PCI vendor ID and PCI device ID registers
Reserved. Bit 6 returns 1b when read.
5
CSC
RW
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1b
1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default)
In this case, the setting of ExCA 803 bit 4 is a don’t care.
4
DIAG4
RW
Diagnostic RETRY_DIS. Delayed transaction disable.
3
DIAG3
RW
2
DIAG2
RW
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215.
1
DIAG1
RW
Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.
0
STDZVEN
RW
Standardized zoomed video register model enable.
0 = Enable the standardized zoomed video register model (default)
1 = Disable the standardized zoomed video register model
4.35 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Capability ID
A0h
Read-only
01h
4.36 Next-Item Pointer Register
The next-item pointer register indicates the next item in the linked list of the PCI power-management capabilities.
Because the controller function includes only one capabilities item, this register returns 00h when read.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4−20
Next-item pointer
A1h
Read-only
00h
4.37 Power-Management Capabilities Register
This register contains information on the capabilities of the PC Card function related to power management. The
CardBus bridge supports the D0, D1, D2, and D3 power states. See Table 4−13 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
Register:
Offset:
Type:
Default:
Power-management capabilities
A2h
Read/Write, Read-only
FE12h
Table 4−13. Power-Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the controller function may assert PME.
A 0b for any bit indicates that the function cannot assert the PME signal while in that power state. These
five bits return 11111b when read. Each of these bits is described below:
15
PME_Support
RW
14−11
PME_Support
R
10
D2_Support
R
D2 support. Bit 10 returns a 1b when read, indicating that the CardBus function supports the D2 device
power state.
9
D1_Support
R
D1 support. Bit 9 returns a 1b when read, indicating that the CardBus function supports the D1 device
power state.
8−6
RSVD
R
Reserved. Bits 8−6 return 000b when read.
5
DSI
R
Device-specific initialization. Bit 5 returns 1b when read, indicating that the CardBus controller function
requires special initialization (beyond the standard PCI configuration header) before the generic-class
device driver is able to use it.
4
AUX_PWR
R
Auxiliary power source. Bit 4 is tied to bit 15. When bit 4 is set, it indicates that support for PME in D3cold
requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. When bit 4 is 0b,
it indicates that the function supplies its own auxiliary power source.
3
PMECLK
R
PME clock. Bit 3 returns 0b when read, indicating that no host bus clock is required for the controller to
generate PME.
2−0
VERSION
R
Version. Bits 2−0 return 010b when read, indicating that the power-management registers (PCI offsets
A4h−A7h, see Sections 4.38−4.40) are defined in the PCI Bus Power Management Interface Specification
version 1.1.
Bit 15 defaults to 1b indicating the PME signal can be asserted from the D3cold state. This bit is R/W
because wake-up support from D3cold is contingent on the system providing an auxiliary power source to
the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC
terminals for D3cold wake-up support, then BIOS should write a 0b to this bit.
Bit 14 contains the value 1b, indicating that the PME signal can be asserted from D3hot state.
Bit 13 contains the value 1b, indicating that the PME signal can be asserted from D2 state.
Bit 12 contains the value 1b, indicating that the PME signal can be asserted from D1 state.
Bit 11 contains the value 1b, indicating that the PME signal can be asserted from the D0 state.
4−21
4.38 Power-Management Control/Status Register
The power-management control/status register determines and changes the current power state of the controller
CardBus function. The contents of this register are not affected by the internally-generated reset caused by the
transition from D3hot to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3hot to D0 state
transition. TI-specific registers, PCI power-management registers, and the PC Card 16-bit legacy-mode base
address register (PCI offset 44h, see Section 4.28) are not reset. See Table 4−14 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power-management control/status
A4h
Read-only, Read/Write, Read/Clear
0000h
Table 4−14. Power-Management Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
PMESTAT
RC
PME status. Bit 15 is set when the CardBus function would normally assert PME, independent
of the state of bit 8 (PME_EN). Bit 15 is cleared by a writeback of 1b, and this also clears the PME
signal if PME was asserted by this function. Writing a 0b to this bit has no effect.
14−13
DATASCALE
R
Data scale. This 2-bit field returns 00b when read. The CardBus function does not return any
dynamic data.
12−9
DATASEL
R
Data select. This 4-bit field returns 0h when read. The CardBus function does not return any
dynamic data.
8
PME_EN
RW
PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME
is disabled.
7−2
RSVD
R
1−0
4−22
PWR_STATE
RW
Reserved. Bits 7−2 return 000000b when read.
Power state. This 2-bit field is used both to determine the current power state of a function and
to set the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
11 = D3hot
4.39 Power-Management Control/Status Register Bridge Support Extensions
The power-management control/status register bridge support extensions support PCI bridge specific functionality.
See Table 4−15 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power-management control/status register bridge support extensions
A6h
Read-only
C0h
Table 4−15. Power-Management Control/Status Register Bridge Support Extensions Description
BIT
7
SIGNAL
BPCC_EN
TYPE
FUNCTION
R
BPCC_Enable. Bus power/clock control enable. This bit returns 1b when read.
This bit is encoded as:
0 = Bus power/clock control is disabled
1 = Bus power/clock control is enabled (default)
A 0b indicates that the bus power/clock control policies defined in the PCI Bus Power Management
Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled,
the bridge power-management control/status register power state field (see Section 4.38, bits 1−0)
cannot be used by the system software to control the power or the clock of the bridge secondary bus. A
1b indicates that the bus power/clock control mechanism is enabled.
6
B2_B3
R
B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of
programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1b. This bit is
encoded as:
0 = When the bridge is programmed to D3hot, its secondary bus has its power removed (B3)
1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock is
stopped (B2) (default)
5−0
RSVD
R
Reserved. Bits 5−0 return 000000b when read.
4.40 Power-Management Data Register
The power-management data register returns 00h when read, because the CardBus function does not report dynamic
data.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power-management data
A7h
Read-only
00h
4−23
4.41 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when events occur that are controlled by
the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1b
to the corresponding bit location. The status bits in this register do not depend upon the states of corresponding bits
in the general-purpose enable register. See Table 4−16 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose event status
A8h
Read-only, Read/Clear
0000h
Table 4−16. General-Purpose Event Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PC Card socket 0 ZV status. Bit 15 is set on a change in status of bit 6 (ZVENABLE) in the function 0 card
control register (PCI offset 91h, see Section 4.32).
15
ZV_STS
RC
14−12
RSVD
R
11
PWR_STS
RC
10−9
RSVD
R
8
VPP12_STS
RC
7−5
RSVD
R
4
GP4_STS
RC
GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level.
3
GP3_STS
RC
GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level.
2
GP2_STS
RC
GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level.
1
GP1_STS
RC
GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level.
0
GP0_STS
RC
GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.
4−24
Reserved. Bits 14−12 return 000b when read.
Power-change status. Bit 11 is set when software has changed the power state of the socket. A change
in either VCC or VPP causes this bit to be set.
Reserved. Bits 10 and 9 return 00b when read.
12-V VPP request status. Bit 8 is set when software has changed the requested VPP level to or from 12 V
for the PC Card socket.
Reserved. Bits 7−5 return 000b when read.
4.42 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven
until the corresponding status bit is cleared and the event is serviced. The GPE can only be signaled if one of the
multifunction terminals, MFUNC6−MFUNC0, is configured for GPE signaling. See Table 4−17 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose event enable
AAh
Read-only, Read/Write
0000h
Table 4−17. General-Purpose Event Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
PC Card ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE) in
the card control register (PCI offset 91h, see Section 4.32).
15
ZV0_EN
RW
14−12
RSVD
R
11
PWR_EN
RW
10−9
RSVD
R
8
VPP12_EN
RW
7−5
RSVD
R
4
GP4_EN
RW
GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5
terminal input level if configured as GPI4.
3
GP3_EN
RW
GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4
terminal input level if configured as GPI3.
2
GP2_EN
RW
GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2
terminal input if configured as GPI2.
1
GP1_EN
RW
GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1
terminal input if configured as GPI1.
0
GP0_EN
RW
GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0
terminal input if configured as GPI0.
Reserved. Bits 14−12 return 000b when read.
Power change enable. When bit 11 is set, a GPE is signaled on when software has changed the power
state.
Reserved. Bits 10 and 9 return 00b when read.
12-V VPP request enable. When bit 8 is set, a GPE is signaled when software has changed the requested
VPP level to or from 12 V.
Reserved. Bits 7−5 return 000b when read.
4−25
4.43 General-Purpose Input Register
The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5,
MFUNC4, and MFUNC2−MFUNC0. See Table 4−18 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
Register:
Offset:
Type:
Default:
General-purpose input
ACh
Read-only
00XXh
Table 4−18. General-Purpose Input Register Description
BIT
SIGNAL
TYPE
15−5
RSVD
R
Reserved. Bits 15−5 return 0s when read.
FUNCTION
4
GPI4_DATA
R
GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal.
3
GPI3_DATA
R
GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal.
2
GPI2_DATA
R
GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal.
1
GPI1_DATA
R
GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal.
0
GPI0_DATA
R
GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal.
4.44 General-Purpose Output Register
The general-purpose output register is used for control of the general-purpose outputs. See Table 4−19 for a
complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose output
AEh
Read-only, Read/Write
0000h
Table 4−19. General-Purpose Output Register Description
4−26
BIT
SIGNAL
TYPE
15−5
RSVD
R
FUNCTION
4
GPO4_DATA
RW
GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5
terminal if configured as GPO4. Read transactions return the last data value written.
3
GPO3_DATA
RW
GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4
terminal if configured as GPO3. Read transactions return the last data value written.
2
GPO2_DATA
RW
GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2
terminal if configured as GPO2. Read transactions return the last data value written.
1
GPO1_DATA
RW
GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1
terminal if configured as GPO1. Read transactions return the last data value written.
0
GPO0_DATA
RW
GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0
terminal if configured as GPO0. Read transactions return the last data value written.
Reserved. Bits 15−5 return 0s when read.
4.45 Serial-Bus Data Register
The serial-bus data register is for programmable serial-bus byte reads and writes. This register represents the data
when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data,
the serial bus index register must be programmed with the byte address, the serial-bus slave address must be
programmed with the 7-bit slave address, and the read/write indicator bit must be reset.
On byte reads, the byte address is programmed into the serial-bus index register, the serial bus slave address register
must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the
serial bus control and status register (PCI offset B3h, see Section 4.48) must be polled until clear. Then the contents
of this register are valid read data from the serial bus interface. See Table 4−20 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial-bus data
B0h
Read/Write
00h
Table 4−20. Serial-Bus Data Register Description
BIT
SIGNAL
TYPE
FUNCTION
7−0
SBDATA
RW
Serial-bus data. This bit field represents the data byte in a read or write transaction on the serial interface.
On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.
4.46 Serial-Bus Index Register
The serial-bus index register is for programmable serial-bus byte reads and writes. This register represents the byte
address when generating cycles on the serial-bus interface. To write a byte, the serial-bus data register must be
programmed with the data, this register must be programmed with the byte address, and the serial-bus slave address
register must be programmed with both the 7-bit slave address and the read/write indicator bit.
On byte reads, the word address is programmed into this register, the serial-bus slave address must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial-bus control and
status register (see Section 4.48) must be polled until clear. Then the contents of the serial-bus data register are valid
read data from the serial-bus interface. See Table 4−21 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial-bus index
B1h
Read/Write
00h
Table 4−21. Serial-Bus Index Register Description
BIT
SIGNAL
TYPE
FUNCTION
7−0
SBINDEX
RW
Serial-bus index. This bit field represents the byte address in a read or write transaction on the serial interface.
4−27
4.47 Serial-Bus Slave Address Register
The serial-bus slave address register is for programmable serial-bus byte read and write transactions. To write a byte,
the serial-bus data register must be programmed with the data, the serial-bus index register must be programmed
with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write
indicator bit.
On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial-bus control and
status register (PCI offset B3h, see Section 4.48) must be polled until clear. Then the contents of the serial-bus data
register are valid read data from the serial-bus interface. See Table 4−22 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial-bus slave address
B2h
Read/Write
00h
Table 4−22. Serial-Bus Slave Address Register Description
4−28
BIT
SIGNAL
TYPE
FUNCTION
7−1
SLAVADDR
RW
Serial-bus slave address. This bit field represents the slave address of a read or write transaction on the
serial interface.
0
RWCMD
RW
Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read
and write accesses.
0 = A byte write access is requested to the serial bus interface
1 = A byte read access is requested to the serial bus interface
4.48 Serial-Bus Control and Status Register
The serial-bus control and status register communicates serial-bus status information and selects the quick
command protocol. Bit 5 (REQBUSY) in this register must be polled during serial-bus byte reads to indicate when
data is valid in the serial-bus data register. See Table 4−23 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial-bus control and status
B3h (function 0)
Read-only, Read/Write, Read/Clear
00h
Table 4−23. Serial-Bus Control and Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte
protocol is used on read commands. The word-address byte in the serial-bus index register (PCI offset B1h,
see Section 4.46) is not output by the controller when bit 7 is set.
7
PROT_SEL
RW
6
RSVD
R
Reserved. Bit 6 returns 0b when read.
R
Requested serial-bus access busy. Bit 5 indicates that a requested serial-bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial-bus slave address register (PCI
offset B2h, see Section 4.47). Bit 5 must be polled on reads from the serial interface. After the byte read
access has been requested, the read data is valid in the serial-bus data register.
R
Serial EEPROM busy status. Bit 4 indicates the status of the serial EEPROM circuitry. Bit 4 is set during
the loading of the subsystem ID and other default values from the serial-bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
5
4
REQBUSY
ROMBUSY
3
SBDETECT
RC
Serial-bus detect. When bit 3 is set, it indicates that the serial-bus interface is detected through pullup
resistors on the VCCD0 and VCCD1 terminals after reset. If bit 3 is reset, then the MFUNC4 and MFUNC1
terminals can be used for alternate functions such as general-purpose inputs and outputs.
0 = Serial-bus interface not detected
1 = Serial-bus interface detected
2
SBTEST
RW
Serial-bus test. When bit 2 is set, the serial-bus clock frequency is increased for test purposes.
0 = Serial-bus clock at normal operating frequency, 100 kHz (default)
1 = Serial-bus clock frequency increased for test purposes
1
REQ_ERR
RC
Requested serial-bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle, and can be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1b.
0 = No error detected during user-requested byte read or write cycle
1 = Data error detected during user-requested byte read or write cycle
RC
EEPROM data-error status. Bit 0 indicates when a data error occurs on the serial interface during the
auto-load from the serial-bus EEPROM, and can be set due to a missing acknowledge. Bit 0 is also set on
invalid EEPROM data formats. See Section 3.6.1, Serial Bus Interface Implementation, for details on
EEPROM data format. Bit 0 is cleared by a writeback of 1b.
0 = No error detected during auto-load from serial-bus EEPROM
1 = Data error detected during auto-load from serial-bus EEPROM
0
ROM_ERR
4−29
4−30
5 ExCA Compatibility Registers
The ExCA registers implemented in the PCI1510 controller are register-compatible with the Intel 82365SL−DF
PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data
scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the
register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O
base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy-mode base address
register (PCI offset 44h, see Section 4.28). The offsets from this base address run contiguously from 00h to 3Fh. See
Figure 5−1 for an ExCA I/O mapping illustration.
Host I/O Space
PCI1510 Configuration Registers
Offset
Offset
00h
CardBus Socket/ExCA Base Address
10h
PC Card A
ExCA
Registers
Index
3Fh
Data
16-Bit Legacy-Mode Base Address
44h
Figure 5−1. ExCA Register Access Through I/O
The controller also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI memory
space. They are located through the CardBus socket/ExCA base-address register (PCI offset 10h, see Section 4.12)
at memory offset 800h. See Figure 5−2 for an ExCA memory mapping illustration. This illustration also identifies the
CardBus socket register mapping, which is mapped into the same 4-K window at memory offset 00h.
PCI1510 Configuration Registers
Offset
Host
Memory Space
Offset
00h
CardBus Socket/ExCA Base Address
10h
CardBus
Socket
Registers
20h
800h
16-Bit Legacy-Mode Base Address
44h
ExCA
Registers
844h
Figure 5−2. ExCA Register Access Through Memory
The interrupt registers in the ExCA register set, as defined by the 82365SL−DL specification, control such card
functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing
registers and the host interrupt signaling method selected for the controller to ensure that all possible interrupts can
potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt
5−1
signaling are the ExCA interrupt and general control register (ExCA offset 03h/43h/803h, see Section 5.4) and the
ExCA card status-change interrupt configuration register (05h/45h/805h, see Section 5.6).
Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.
Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. Table 5−1 identifies each
ExCA register and its respective ExCA offset. Memory windows have 4-Kbyte granularity.
Table 5−1. ExCA Registers and Offsets
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
(HEX)
Identification and revision
800
00
Interface status
801
01
Power control
802
02
Interrupt and general control
803
03
Card status change
804
04
Card status-change interrupt configuration
805
05
Address window enable
806
06
I / O window control
807
07
I / O window 0 start-address low byte
808
08
I / O window 0 start-address high byte
809
09
I / O window 0 end-address low byte
80A
0A
EXCA REGISTER NAME
5−2
I / O window 0 end-address high byte
80B
0B
I / O window 1 start-address low byte
80C
0C
I / O window 1 start-address high byte
80D
0D
I / O window 1 end-address low byte
80E
0E
I / O window 1 end-address high byte
80F
0F
Memory window 0 start-address low byte
810
10
Memory window 0 start-address high byte
811
11
Memory window 0 end-address low byte
812
12
Memory window 0 end-address high byte
813
13
Memory window 0 offset-address low byte
814
14
Memory window 0 offset-address high byte
815
15
Card detect and general control
816
16
Reserved
817
17
Memory window 1 start-address low byte
818
18
Memory window 1 start-address high byte
819
19
Memory window 1 end-address low byte
81A
1A
Memory window 1 end-address high byte
81B
1B
Memory window 1 offset-address low byte
81C
1C
Memory window 1 offset-address high byte
81D
1D
Global control
81E
1E
Reserved
81F
1F
Memory window 2 start-address low byte
820
20
Memory window 2 start-address high byte
821
21
Memory window 2 end-address low byte
822
22
Table 5−1. ExCA Registers and Offsets (Continued)
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
(HEX)
Memory window 2 end-address high byte
823
23
Memory window 2 offset-address low byte
824
24
Memory window 2 offset-address high byte
825
25
Reserved
826
26
Reserved
827
27
Memory window 3 start-address low byte
828
28
EXCA REGISTER NAME
Memory window 3 start-address high byte
829
29
Memory window 3 end-address low byte
82A
2A
Memory window 3 end-address high byte
82B
2B
Memory window 3 offset-address low byte
82C
2C
Memory window 3 offset-address high byte
82D
2D
Reserved
82E
2E
Reserved
82F
2F
Memory window 4 start-address low byte
830
30
Memory window 4 start-address high byte
831
31
Memory window 4 end-address low byte
832
32
Memory window 4 end-address high byte
833
33
Memory window 4 offset-address low byte
834
34
Memory window 4 offset-address high byte
835
35
I/O window 0 offset-address low byte
836
36
I/O window 0 offset-address high byte
837
37
I/O window 1 offset-address low byte
838
38
I/O window 1 offset-address high byte
839
39
Reserved
83A
3A
Reserved
83B
3B
Reserved
83C
3C
Reserved
83D
3D
Reserved
83E
3E
Reserved
83F
3F
Memory window page 0
840
−
Memory window page 1
841
−
Memory window page 2
842
−
Memory window page 3
843
−
Memory window page 4
844
−
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.
5−3
5.1 ExCA Identification and Revision Register
The ExCA identification and revision register provides host software with information on 16-bit PC Card support and
Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5
(SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). See Table 5−2 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
1
0
0
0
0
1
0
0
Register:
Offset:
Type:
Default:
ExCA identification and revision
CardBus socket address + 800h; ExCA offset 00h
Read-only, Read/Write
84h
Table 5−2. ExCA Identification and Revision Register Description
BIT
5−4
SIGNAL
TYPE
FUNCTION
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
controller. The controller supports both I/O and memory 16-bit PC cards.
7−6
IFTYPE
R
5−4
RSVD
RW
Reserved. Bits 5 and 4 can be used for Intel 82365SL-DF emulation.
3−0
365REV
RW
Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the controller. Host
software can read this field to determine compatibility to the Intel 82365SL-DF register set. Writing 0010b to
this field puts the controller in 82365SL mode.
5.2 ExCA Interface Status Register
The ExCA interface status register provides information on the current status of the PC Card interface. An X in the
default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See
Table 5−3 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
ExCA interface status
CardBus socket address + 801h; ExCA offset 01h
Read-only
00XX XXXXb
Table 5−3. ExCA Interface Status Register Description
BIT
SIGNAL
TYPE
7
RSVD
R
6
CARDPWR
R
5
READY
R
4
CARDWP
FUNCTION
Reserved. Bit 7 returns 0b when read.
Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the ExCA
power control register (ExCA offset 02h/42h/802h, see Section 5.3) is programmed. Bit 6 is encoded as:
0 = VCC and VPP to the socket turned off (default)
1 = VCC and VPP to the socket turned on
Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.
0 = PC Card not ready for data transfer
1 = PC Card ready for data transfer
R
Card write protect (WP). Bit 4 indicates the current status of WP at the PC Card interface. This signal reports
to the controller whether or not the memory card is write protected. Furthermore, write protection for an entire
16-bit memory window is available by setting the appropriate bit in the memory window offset-address
high-byte register.
0 = WP is 0b. PC Card is read/write.
1 = WP is 1b. PC Card is read-only.
3
CDETECT2
R
Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and bit 2
(CDETECT1) to determine if a PC Card is fully seated in the socket.
0 = CD2 is 1b. No PC Card is inserted.
1 = CD2 is 0b. PC Card is at least partially inserted.
2
CDETECT1
R
Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and bit 3
(CDETECT2) to determine if a PC Card is fully seated in the socket.
0 = CD1 is 1b. No PC Card is inserted.
1 = CD1 is 0b. PC Card is at least partially inserted.
1−0
BVDSTAT
R
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0
reflects BVD1.
00 = Battery dead
01 = Battery dead
10 = Battery low; warning
11 = Battery good
When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the
PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.
5−5
5.3 ExCA Power Control Register
The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output
enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See
Table 5−4 and Table 5−5 for a complete description of the register contents.
The controller supports both the 82365SL and 82365SL-DF register models. Bits 3−0 (365REV) of the ExCA
identification and revision register (ExCA offset 00h, see Section 5.1) control which register model is supported.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA power control—82365SL support
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
00h
Table 5−4. ExCA Power Control Register Description—82365SL Support
BIT
SIGNAL
TYPE
FUNCTION
7
COE
RW
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller. This bit is
encoded as:
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
6
RSVD
R
5
AUTOPWRSWEN
RW
Auto power switch enable.
0 = Automatic socket power switching based on card detects is disabled
1 = Automatic socket power switching based on card detects is enabled
PC Card power enable.
0 = VCC = No connection
1 = VCC is enabled and controlled by bit 2 (EXCAPOWER) of the system control register
(PCI offset 80h, see Section 4.29)
4
CAPWREN
RW
3−2
RSVD
R
1−0
5−6
EXCAVPP
RW
Reserved. Bit 6 returns 0b when read.
Reserved. Bits 3 and 2 return 00b when read.
PC Card VPP power control. Bits 1 and 0 request changes to card VPP. The controller ignores this field
unless VCC to the socket is enabled. This field is encoded as:
00 = No connection (default)
01 = VCC
10 = 12 V
11 = Reserved
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA power control—82365SL-DF support
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
00h
Table 5−5. ExCA Power Control Register Description—82365SL-DF Support
BIT
SIGNAL
TYPE
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller. This bit is encoded as:
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
7
COE
RW
6−5
RSVD
R
4−3
EXCAVCC
RW
2
RSVD
R
1−0
EXCAVPP
RW
Reserved. Bits 6 and 5 return 00b when read.
VCC. Bits 4 and 3 request changes to card VCC. This field is encoded as:
00 = 0 V (default)
01 = 0 V reserved
10 = 5 V
11 = 3.3 V
Reserved. Bit 2 returns 0b when read.
VPP. Bits 1 and 0 request changes to card VPP. The controller ignores this field unless VCC to the socket is
enabled. This field is encoded as:
00 = No connection (default)
01 = VCC
10 = 12 V
11 = Reserved
5−7
5.4 ExCA Interrupt and General Control Register
The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical
16-bit PC Card functions. See Table 5−6 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA interrupt and general control
CardBus socket address + 803h; ExCA offset 03h
Read/Write
00h
Table 5−6. ExCA Interrupt and General Control Register Description
BIT
TYPE
FUNCTION
7
RINGEN
RW
Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
6
RESET
RW
Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6
affects 16-bit cards only. This bit is encoded as:
0 = RESET signal asserted (default)
1 = RESET signal deasserted
5
CARDTYPE
RW
Card type. Bit 5 indicates the PC card type. This bit is encoded as:
0 = Memory PC Card installed (default)
1 = I/O PC Card installed
RW
PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed
to PCI interrupts. When low, the card status change interrupts are routed using bits 7−4 (CSCSELECT field)
in the ExCA card status-change interrupt configuration register (ExCA offset 05h/45h/805h, see
Section 5.6). This bit is encoded as:
0 = CSC interrupts are routed by ExCA registers (default)
1 = CSC interrupts are routed to PCI interrupts
RW
Card interrupt select for I/O PC Card functional interrupts. Bits 3−0 select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No interrupt routing (default). CSC interrupts are routed to PCI interrupts. This bit setting is
ORed with bit 4 (CSCROUTE) for backward compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0100 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
4
3−0
5−8
SIGNAL
CSCROUTE
INTSELECT
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0b. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit write back of 1b to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (ExCA offset 1E/5E/81E, see
Section 5.20). See Table 5−7 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card status-change
CardBus socket address + 804h; ExCA offset 04h
Read-only
00h
Table 5−7. ExCA Card Status-Change Register Description
BIT
SIGNAL
TYPE
7−4
RSVD
R
Reserved. Bits 7−4 return 0h when read.
3
CDCHANGE
R
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface.
This bit is encoded as:
0 = No change detected on either CD1 or CD2
1 = Change detected on either CD1 or CD2
2
READYCHANGE
R
FUNCTION
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of an
interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now
ready to accept new data. This bit is encoded as:
0 = No low-to-high transition detected on READY (default)
1 = Detected low-to-high transition on READY
When a 16-bit I/O card is installed, bit 2 is always 0b.
1
BATWARN
R
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the
source of an interrupt was due to a battery-low warning condition. This bit is encoded as:
0 = No battery warning condition (default)
1 = Detected battery warning condition
When a 16-bit I/O card is installed, bit 1 is always 0b.
0
BATDEAD
R
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates
whether the source of an interrupt was due to a battery dead condition. This bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the controller is configured for ring indicate operation, bit 0 indicates the status of
RI.
5−9
5.6 ExCA Card Status-Change Interrupt Configuration Register
The ExCA card status-change interrupt configuration register controls interrupt routing for card status-change
interrupts, as well as masking CSC interrupt sources. See Table 5−8 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card status-change interrupt configuration
CardBus socket address + 805h; ExCA offset 05h
Read/Write
00h
Table 5−8. ExCA Card Status-Change Interrupt Configuration Register Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. Bits 7−4 select the interrupt routing for card status-change
interrupts.
0000 = CSC interrupts routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (PCI offset 93h, see
Section 4.34) is set to 1b. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register
(ExCA offset 03h/43h/803h, see Section 5.4) is a don’t care. This is the default setting.
0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register is set to 0b (see Section 4.34). In
this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the ExCA interrupt
and general control register (ExCA offset 03h/43h/803h, see Section 5.4) to 1b.
7−4
3
2
1
0
5−10
CSCSELECT
CDEN
READYEN
BATWARNEN
BATDEADEN
RW
This field is encoded as:
0000 = No interrupt routing (default)
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
RW
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
RW
Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host
interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
RW
Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
RW
Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By
default, all windows to the card are disabled. The controller does not acknowledge PCI memory or I/O cycles to the
card if the corresponding enable bit in this register is 0b, regardless of the programming of the memory or I/O window
start/end/offset address registers. See Table 5−9 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA address window enable
CardBus socket address + 806h; ExCA offset 06h
Read-only, Read/Write
00h
Table 5−9. ExCA Address Window Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
IOWIN1EN
RW
I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:
0 = I/O window 1 disabled (default)
1 = I/O window 1 enabled
6
IOWIN0EN
RW
I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:
0 = I/O window 0 disabled (default)
1 = I/O window 0 enabled
5
RSVD
R
4
MEMWIN4EN
RW
Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is
encoded as:
0 = Memory window 4 disabled (default)
1 = Memory window 4 enabled
RW
Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is
encoded as:
0 = Memory window 3 disabled (default)
1 = Memory window 3 enabled
RW
Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is
encoded as:
0 = Memory window 2 disabled (default)
1 = Memory window 2 enabled
RW
Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is
encoded as:
0 = Memory window 1 disabled (default)
1 = Memory window 1 enabled
RW
Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is
encoded as:
0 = Memory window 0 disabled (default)
1 = Memory window 0 enabled
3
2
1
0
MEMWIN3EN
MEMWIN2EN
MEMWIN1EN
MEMWIN0EN
Reserved. Bit 5 returns 0b when read.
5−11
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5−10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA I/O window control
CardBus socket address + 807h; ExCA offset 07h
Read/Write
00h
Table 5−10. ExCA I/O Window Control Register Description
BIT
7
WAITSTATE1
TYPE
FUNCTION
RW
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles are extended by one equivalent ISA wait state
6
ZEROWS1
RW
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles are reduced to equivalent of three ISA cycles
5
IOIS16W1
RW
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width determined by DATASIZE1, bit 4 (default)
1 = Window data width determined by IOIS16
4
DATASIZE1
RW
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
RW
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles are extended by one equivalent ISA wait state
3
5−12
SIGNAL
WAITSTATE0
2
ZEROWS0
RW
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles are reduced to equivalent of three ISA cycles
1
IOIS16W0
RW
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE0, bit 0 (default)
1 = Window data width is determined by IOIS16
0
DATASIZE0
RW
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 start-address low-byte
CardBus socket address + 808h; ExCA offset 08h
ExCA I/O window 1 start-address low-byte
CardBus socket address + 80Ch; ExCA offset 0Ch
Read/Write
00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 start-address high-byte
CardBus socket address + 809h; ExCA offset 09h
ExCA I/O window 1 start-address high-byte
CardBus socket address + 80Dh; ExCA offset 0Dh
Read/write
00h
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 end-address low-byte
CardBus socket address + 80Ah; ExCA offset 0Ah
ExCA I/O window 1 end-address low-byte
CardBus socket address + 80Eh; ExCA offset 0Eh
Read/Write
00h
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the upper 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 end-address high-byte
CardBus socket address + 80Bh; ExCA offset 0Bh
ExCA I/O window 1 end-address high-byte
CardBus socket address + 80Fh; ExCA offset 0Fh
Read/write
00h
5−13
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the start address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 start-address low-byte
CardBus socket address + 810h; ExCA offset 10h
ExCA memory window 1 start-address low-byte
CardBus socket address + 818h; ExCA offset 18h
ExCA memory window 2 start-address low-byte
CardBus socket address + 820h; ExCA offset 20h
ExCA memory window 3 start-address low-byte
CardBus socket address + 828h; ExCA offset 28h
ExCA memory window 4 start-address low-byte
CardBus socket address + 830h; ExCA offset 30h
Read/Write
00h
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5−11 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 start-address high-byte
CardBus socket address + 811h; ExCA offset 11h
ExCA memory window 1 start-address high-byte
CardBus socket address + 819h; ExCA offset 19h
ExCA memory window 2 start-address high-byte
CardBus socket address + 821h; ExCA offset 21h
ExCA memory window 3 start-address high-byte
CardBus socket address + 829h; ExCA offset 29h
ExCA memory window 4 start-address high-byte
CardBus socket address + 831h; ExCA offset 31h
Read/Write
00h
Table 5−11. ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description
BIT
7
5−14
SIGNAL
DATASIZE
TYPE
FUNCTION
RW
Data size. Bit 7 controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
6
ZEROWAIT
RW
Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing
emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default)
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
16-bit cycles are reduced to equivalent of two ISA cycles.
5−4
SCRATCH
RW
Scratch pad bits. Bits 5 and 4 have no effect on memory window operation.
3−0
STAHN
RW
Start-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window
start address.
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 end-address low-byte
CardBus socket address + 812h; ExCA offset 12h
ExCA memory window 1 end-address low-byte
CardBus socket address + 81Ah; ExCA offset 1Ah
ExCA memory window 2 end-address low-byte
CardBus socket address + 822h; ExCA offset 22h
ExCA memory window 3 end-address low-byte
CardBus socket address + 82Ah; ExCA offset 2Ah
ExCA memory window 4 end-address low-byte
CardBus socket address + 832h; ExCA offset 32h
Read/Write
00h
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5−12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 end-address high-byte
CardBus socket address + 813h; ExCA offset 13h
ExCA memory window 1 end-address high-byte
CardBus socket address + 81Bh; ExCA offset 1Bh
ExCA memory window 2 end-address high-byte
CardBus socket address + 823h; ExCA offset 23h
ExCA memory window 3 end-address high-byte
CardBus socket address + 82Bh; ExCA offset 2Bh
ExCA memory window 4 end-address high-byte
CardBus socket address + 833h; ExCA offset 33h
Read-only, Read/Write
00h
Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these two bits.
7−6
MEMWS
RW
5−4
RSVD
R
3−0
ENDHN
RW
Reserved. Bits 5 and 4 return 00b when read.
End-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window end
address.
5−15
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the offset address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 offset-address low-byte
CardBus socket address + 814h; ExCA offset 14h
ExCA memory window 1 offset-address low-byte
CardBus socket address + 81Ch; ExCA offset 1Ch
ExCA memory window 2 offset-address low-byte
CardBus socket address + 824h; ExCA offset 24h
ExCA memory window 3 offset-address low-byte
CardBus socket address + 82Ch; ExCA offset 2Ch
ExCA memory window 4 offset-address low-byte
CardBus socket address + 834h; ExCA offset 34h
Read/Write
00h
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5−13 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 offset-address high-byte
CardBus socket address + 815h; ExCA offset 15h
ExCA memory window 1 offset-address high-byte
CardBus socket address + 81Dh; A ExCA offset 1Dh
ExCA memory window 2 offset-address high-byte
CardBus socket address + 825h; ExCA offset 25h
ExCA memory window 3 offset-address high-byte
CardBus socket address + 82Dh; ExCA offset 2Dh
ExCA memory window 4 offset-address high-byte
CardBus socket address + 835h; ExCA offset 35h
Read/Write
00h
Table 5−13. ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description
BIT
7
5−16
SIGNAL
WINWP
TYPE
FUNCTION
RW
Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as:
0 = Write operations are allowed (default)
1 = Write operations are not allowed
6
REG
RW
Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded
as:
0 = Memory window is mapped to common memory (default)
1 = Memory window is mapped to attribute memory
5−0
OFFHB
RW
Offset-address high byte. Bits 5−0 represent the upper address bits A25−A20 of the memory window
offset address.
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card
removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5−14 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
X
X
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card detect and general control
CardBus socket address + 816h; ExCA offset 16h
Read-only, Read/Write
XX00 0000b
Table 5−14. ExCA Card Detect and General Control Register Description
BIT
7
6
5
SIGNAL
VS2STAT
VS1STAT
SWCSC
TYPE
FUNCTION
R
VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have
a default value.
0 = VS2 low
1 = VS2 high
R
VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have
a default value.
0 = VS1 low
1 = VS1 high
RW
Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change interrupt configuration
register (ExCA offset 05h/45h/805, see Section 5.6) is set, then writing a 1b to bit 5 causes a card-detect
card-status change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card
status-change-interrupt configuration register (ExCA offset 05h/45h/805, see Section 5.6) is cleared to 0b,
then writing a 1b to bit 5 has no effect. A read operation of this bit always returns 0b.
Card detect resume enable. If bit 4 is set to 1b, then once a card detect change has been detected on CD1
and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in
the ExCA card status-change register is cleared (see Section 5.5). If this bit is a 0b, then the card detect
resume functionality is disabled.
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
4
CDRESUME
RW
3−2
RSVD
R
1
REGCONFIG
RW
0
RSVD
R
Reserved. Bits 3 and 2 return 00b when read.
Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card
removal event. This bit is encoded as:
0 = No change to ExCA registers on card removal (default)
1 = Reset ExCA registers on card removal
Reserved. Bit 0 returns 0b when read.
5−17
5.20 ExCA Global Control Register
The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 5−15 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA global control
CardBus socket address + 81Eh; ExCA offset 1Eh
Read-only, Read/Write
00h
Table 5−15. ExCA Global Control Register Description
BIT
SIGNAL
TYPE
7−5
RSVD
R
4
INTMODEB
RW
Level/edge interrupt mode select − card B. Bit 4 selects the signaling mode for the controller host interrupt
for card B interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
3
INTMODEA
RW
Level/edge interrupt mode select − card A. Bit 3 selects the signaling mode for the controller host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
RW
Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register (ExCA offset 04h/44h/804h, see Section 5.5). This bit is encoded as:
0 = Interrupt flags are cleared by read of CSC register (default)
1 = Interrupt flags are cleared by explicit writeback of 1b
RW
Card status change level/edge mode select. Bit 1 selects the signaling mode for the controller host interrupt
for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
RW
Power-down mode select. When bit 0 is set to 1b, the controller is in power-down mode. In power-down
mode, the controller card outputs are high-impedance until an active cycle is executed on the card interface.
Following an active cycle, the outputs are again high-impedance. The controller still receives functional
interrupts and/or card status-change interrupts; however, an actual card access is required to wake up the
interface. This bit is encoded as:
0 = Power-down mode is disabled (default)
1 = Power-down mode is enabled
2
1
0
5−18
IFCMODE
CSCMODE
PWRDWN
FUNCTION
Reserved. Bits 7−5 return 000b when read.
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0b.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 offset-address low-byte
CardBus socket address + 836h; ExCA offset 36h
ExCA I/O window 1 offset-address low-byte
CardBus socket address + 838h; ExCA offset 38h
Read-only, Read/Write
00h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 offset-address high-byte
CardBus socket address + 837h; ExCA offset 37h
ExCA I/O window 1 offset-address high-byte
CardBus socket address + 839h; ExCA offset 39h
Read/Write
00h
5.23 ExCA Memory Windows 0−4 Page Registers
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256
16-Mbyte regions in the 4-Gbyte PCI address space. These registers are only accessible when the ExCA registers
are memory-mapped; that is, these registers cannot be accessed using the index/data I/O scheme.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA memory windows 0−4 page
CardBus socket address + 840h, 841h, 842h, 843h, 844h
Read/Write
00h
5−19
5−20
6 CardBus Socket Registers
The PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control
socket-specific functions. The PCI1510 controller provides the CardBus socket/ExCA base-address register (PCI
offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Table 6−1 gives
the location of the socket registers in relation to the CardBus socket/ExCA base address.
The controller implements an additional register at offset 20h that provides power management control for the socket.
PCI1510 Configuration Registers
Offset
Host
Memory Space
Offset
00h
CardBus Socket/ExCA Base Address
10h
CardBus
Socket
Registers
20h
800h
16-Bit Legacy-Mode Base Address
44h
ExCA
Registers
844h
Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory
Table 6−1. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present-state
08h
Socket force event
0Ch
Socket control
10h
Reserved
Socket power-management
14h−1Ch
20h
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.
6−1
6.1 Socket Event Register
The socket event register indicates a change in socket status has occurred. These bits do not indicate what the
change is, only that one has occurred. Software must read the socket present-state register (CB offset 08h, see
Section 6.3) for current status. Each bit in this register can be cleared by writing a 1b to that bit. The bits in this register
can be set to a 1b by software by writing a 1b to the corresponding bit in the socket force event register (CB offset
0Ch, see Section 6.4). All bits in this register are cleared by PCI reset. They can be immediately set again, if, when
coming out of PC Card reset, the bridge finds the status unchanged (that is, CSTSCHG reasserted or card detect
is still true). Software must clear this register before enabling interrupts. If it is not cleared when interrupts are enabled,
then an interrupt is generated (but not masked) based on any bit set. See Table 6−2 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket event
CardBus socket address + 00h
Read-only, Read/Write, Read/Clear
0000 0000h
Table 6−2. Socket Event Register Description
BIT
SIGNAL
TYPE
31−4
RSVD
R
3
PWREVENT
R/C
Power cycle. Bit 3 is set when the controller detects that bit 3 (PWRCYCLE) in the socket present-state
register (CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1b.
2
CD2EVENT
R/C
CCD2. Bit 2 is set when the controller detects that bit 2 (CDETECT2) in the socket present-state register
(CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1b.
1
CD1EVENT
R/C
CCD1. Bit 1 is set when the controller detects that bit 1 (CDETECT1) in the socket present-state register
(CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1b.
0
CSTSEVENT
R/C
CSTSCHG. Bit 0 is set when bit 0 (CARDSTS) in the socket present-state register (CB offset 08h, see
Section 6.3) has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit
PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1b.
6−2
FUNCTION
Reserved. Bits 31−4 return 000 0000h when read.
6.2 Socket Mask Register
The socket mask register allows software to control the CardBus card events that generate a status change interrupt.
The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (CB
offset 00h, see Section 6.1). See Table 6−3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket mask
CardBus socket address + 04h
Read-only, Read/Write
0000 0000h
Table 6−3. Socket Mask Register Description
BIT
SIGNAL
TYPE
31−4
RSVD
R
3
PWRMASK
FUNCTION
Reserved. Bits 31−4 return 000 0000b when read.
RW
Power cycle. Bit 3 masks bit 3 (PWRCYCLE) in the socket present-state register (CB offset 08h, see
Section 6.3) from causing a status change interrupt.
0 = PWRCYCLE event does not cause CSC interrupt (default)
1 = PWRCYCLE event causes CSC interrupt
2−1
CDMASK
RW
Card detect mask. Bits 2 and 1 mask bits 1 and 2 (CDETECT1 and CDETECT2) in the socket present-state
register (CB offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause CSC interrupt (default)
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal causes CSC interrupt
0
CSTSMASK
RW
CSTSCHG mask. Bit 0 masks bit 0 (CARDSTS) in the socket present-state register (CB offset 08h, see
Section 6.3) from causing a CSC interrupt.
0 = CARDSTS event does not cause CSC interrupt (default)
1 = CARDSTS event causes CSC interrupt
6−3
6.3 Socket Present-State Register
The socket present-state register reports information about the socket interface. Write transactions to the socket force
event register (CB offset 0Ch, see Section 6.4) are reflected here, as well as general socket interface status.
Information about PC Card VCC support and card type is only updated at each insertion. Also note that the controller
uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected
in this register. See Table 6−4 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
X
0
0
0
X
X
X
Register:
Offset:
Type:
Default:
Socket present-state
CardBus socket address + 08h
Read-only
3000 00XXh
Table 6−4. Socket Present-State Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
YVSOCKET
R
YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The controller
does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event
register (CB offset 0Ch, see Section 6.4). This bit is hardwired to 0b.
30
XVSOCKET
R
XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The controller
does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event
register (CB offset 0Ch, see Section 6.4). This bit is hardwired to 0b.
29
3VSOCKET
R
3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The controller
does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event
register (CB offset 0Ch, see Section 6.4).
28
5VSOCKET
R
5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The controller
does support 5-V VCC; therefore, this bit is always set unless overridden by the socket force event register
(CB offset 0Ch, see Section 6.4).
27
ZVSUPPORT
R
Zoomed-video support. This bit indicates whether or not the socket has support for zoomed video.
0 = Zoomed video is not supported
1 = Zoomed video is supported
26−14
RSVD
R
Reserved. Bits 26−14 return 0s when read.
13
YVCARD
R
12
XVCARD
R
11
3VCARD
R
6−4
YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V.
0 = Y.Y-V VCC is not supported
1 = Y.Y-V VCC is supported
XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V.
0 = X.X-V VCC is not supported
1 = X.X-V VCC is supported
3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V.
0 = 3.3-V VCC is not supported
1 = 3.3-V VCC is supported
Table 6−4. Socket Present-State Register (Continued)
BIT
SIGNAL
TYPE
10
5VCARD
R
5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V.
0 = 5-V VCC is not supported.
1 = 5-V VCC is supported.
R
Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an
invalid voltage.
0 = Normal operation (default)
1 = Invalid VCC request by host software
R
Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did
not terminate properly or because write data still resides in the controller.
0 = Normal operation (default)
1 = Potential data loss due to card removal
9
8
BADVCCREQ
DATALOST
FUNCTION
7
NOTACARD
R
Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not
updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
6
IREQCINT
R
READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface.
0 = READY(IREQ)//CINT low
1 = READY(IREQ)//CINT high
5
CBCARD
R
CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
4
16BITCARD
R
16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated
until another card interrogation sequence occurs (card insertion).
3
PWRCYCLE
R
Power cycle. Bit 3 indicates the status of each card powering request. This bit is encoded as:
0 = Socket powered down (default)
1 = Socket powered up
2
CDETECT2
R
CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD2 low (PC Card may be present)
1 = CCD2 high (PC Card not present)
1
CDETECT1
R
CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD1 low (PC Card may be present)
1 = CCD1 high (PC Card not present)
0
CARDSTS
R
CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.
0 = CSTSCHG low
1 = CSTSCHG high
6.4 Socket Force Event Register
The socket force event register is used to force changes to the socket event register (CB offset 00h, see Section 6.1)
and the socket present-state register (see Section 6.3). Bit 14 (CVSTEST) in this register must be written when
forcing changes that require card interrogation. See Table 6−5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket force event
CardBus socket address + 0Ch
Read-only, Write-only
0000 0000h
6−5
Table 6−5. Socket Force Event Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−28
RSVD
R
Reserved. Bits 31−28 return 0h when read.
27
FZVSUPPORT
W
Zoomed-video support. This bit indicates whether or not the socket has support for zoomed video.
26−15
RSVD
R
Reserved. Bits 26−15 return 000h when read.
14
CVSTEST
W
Card VS test. When bit 14 is set, the controller re-interrogates the PC Card, updates the socket present-state
register (CB offset 08h, see Section 6.3), and enables the socket control register (CB offset 10h, see
Section 6.5).
13
FYVCARD
W
Force YV card. Write transactions to bit 13 cause bit 13 (YVCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
12
FXVCARD
W
Force XV card. Write transactions to bit 12 cause bit 12 (XVCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
11
F3VCARD
W
Force 3-V card. Write transactions to bit 11 cause bit 11 (3VCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
10
F5VCARD
W
Force 5-V card. Write transactions to bit 10 cause bit 10 (5VCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
9
FBADVCCREQ
W
Force bad VCC request. Changes to bit 9 (BADVCCREQ) in the socket present-state register (CB offset 08h,
see Section 6.3) can be made by writing to bit 9.
8
FDATALOST
W
Force data lost. Write transactions to bit 8 cause bit 8 (DATALOST) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written.
7
FNOTACARD
W
Force not-a-card. Write transactions to bit 7 cause bit 7 (NOTACARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
6
RSVD
R
Reserved. Bit 6 returns 0b when read.
5
FCBCARD
W
Force CardBus card. Write transactions to bit 5 cause bit 5 (CBCARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
4
F16BITCARD
W
Force 16-bit card. Write transactions to bit 4 cause bit 4 (16BITCARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
3
FPWRCYCLE
W
Force power cycle. Write transactions to bit 3 cause bit 3 (PWREVENT) in the socket event register (CB
offset 00h, see Section 6.1) to be written, and bit 3 (PWRCYCLE) in the socket present-state register (CB
offset 08h, see Section 6.3) is unaffected.
2
FCDETECT2
W
Force CCD2. Write transactions to bit 2 cause bit 2 (CD2EVENT) in the socket event register (CB offset 00h,
see Section 6.1) to be written, and bit 2 (CDETECT2) in the socket present-state register (CB offset 08h,
see Section 6.3) is unaffected.
1
FCDETECT1
W
Force CCD1. Write transactions to bit 1 cause bit 1 (CD1EVENT) in the socket event register (CB offset 00h,
see Section 6.1) to be written, and bit 1 (CDETECT1) in the socket present-state register (CB offset 08h,
see Section 6.3) is unaffected.
0
FCARDSTS
W
Force CSTSCHG. Write transactions to bit 0 cause bit 0 (CSTSEVENT) in the socket event register (CB
offset 00h, see Section 6.1) to be written, and bit 0 (CARDSTS) in the socket present-state register (CB
offset 08h, see Section 6.3) is unaffected.
6−6
6.5 Socket Control Register
The socket control register provides control of the voltages applied to the socket and instructions for the CB CLKRUN
protocol. The controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is
inserted. See Table 6−6 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket control
CardBus socket address + 10h
Read-only, Read/Write
0000 0400h
Table 6−6. Socket Control Register Description
BIT
SIGNAL
TYPE
31−12
RSVD
R
Reserved. These bits return 00000h when read. A write to these bits has no effect.
11
ZV_ACTIVITY
R
Zoomed video activity. This bit returns 0b when the ZVEN bit is 0b (disabled). If the ZVEN bit is set to
1b, the ZV_ACTIVITY bit returns 1b.
10
STDZVREG
R
Standardized zoomed video register model support. This bit returns 1b when the STDZVEN bit (bit 0)
in the diagnostic register is cleared (PCI offset 93h, see Section 4.34).
9
ZVEN
RW
8
RSVD
R
7
STOPCLK
RW
CB CLKRUN protocol instructions.
0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the
PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock
1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle
VCC control. Bits 6−4 request card VCC changes.
000 = Request power off (default)
100 = Request VCC = X.X V
001 = Reserved
101 = Request VCC = Y.Y V
010 = Request VCC = 5 V
110 = Reserved
011 = Request VCC = 3.3 V
111 = Reserved
6−4
VCCCTRL
RW
3
RSVD
R
2−0
VPPCTRL
RW
FUNCTION
Zoomed video enable. This bit enables zoomed video for this socket.
Reserved. ThIs bit returns 0b when read. A write to thIs bit has no effect.
Reserved. Bit 3 returns 0b when read.
VPP control. Bits 2−0 request card VPP changes.
000 = Request power off (default)
100 = Request VPP = X.X V
001 = Request VPP = 12 V
101 = Request VPP = Y.Y V
010 = Request VPP = 5 V
110 = Reserved
011 = Request VPP = 3.3 V
111 = Reserved
6−7
6.6 Socket Power-Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Socket power-management
Read-only, Read/Write
CardBus socket address + 20h
0000 0000h
Table 6−7. Socket Power-Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−26
RSVD
R
Reserved. Bits 31−26 return 00 0000b when read.
25
SKTACCES
R
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
0 = A PC card access has not occurred (default)
1 = A PC card access has occurred
24
SKTMODE
R
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally
1 = Clock frequency has changed
23−17
RSVD
R
Reserved. Bits 23−17 return 000 0000b when read.
16
CLKCTRLEN
RW
15−1
RSVD
R
0
6−8
CLKCTRL
RW
CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled.
0 = Clock control is disabled (default)
1 = Clock control is enabled
Reserved. Bits 15−1 return 0s when read.
CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock
during idle states. Bit 16 (CLKCTRLEN) enables this bit.
0 = Allows CB CLKRUN protocol to stop the CB clock (default)
1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16
7 Electrical Characteristics
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Clamping voltage range, VCCP, VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input voltage range, VI: PCI, miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCP + 0.5 V
PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VCCCB + 0.5 V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO: PCI, miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCP + 0.5 V
PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VCCCB + 0.5 V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous
terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. The limit
specified applies for a dc condition.
2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous
terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. The limit
specified applies for a dc condition.
7−1
7.2 Recommended Operating Conditions (see Note 3)
OPERATION
VCC
Core voltage
Commercial
VCCP
PCI and miscellaneous I/O clamp
voltage
Commercial
VCCCB
PC Card I/O clamp voltage
Commercial
MIN
NOM
MAX
3.3 V
3
3.3
3.6
3.3 V
3
3.3
3.6
4.75
5
5.25
5V
3.3 V
PCI
VIH†
High-level input voltage
PC Card
3
3.3
3.6
5V
4.75
5
5.25
3.3 V
0.5 VCCP
5V
0.475 VCCCB
5V
2.4
Miscellaneous‡
PCI
VIL†
VI
VO§
Low-level input voltage
Input voltage
Output voltage
tt
Input transition time (tr and tf)
TA
TJ¶
Operating ambient temperature range
PC Card
VCCCB
VCCCB
2
3.3 V
0
5V
0
3.3 V
0
5V
0
V
V
V
VCC
0.3 VCCP
0.8
0.325 VCCCB
V
0.8
Miscellaneous‡
0
PCI
0
PC Card
Miscellaneous‡
0
PCI
0
PC Card
Miscellaneous‡
0
0
VCC
VCC
PCI and PC Card
Miscellaneous‡
1
4
0
6
0.8
VCCP
VCCCB
0
0
V
VCCP
VCCP
2
3.3 V
UNIT
V
VCC
VCC
25
70
V
ns
°C
Virtual junction temperature
0
25
115
°C
† Applies to external inputs and bidirectional buffers without hysteresis
‡ Miscellaneous terminals are 65, 66, 75, 117, 130, and 138 for the PGE-packaged device; A09, B02, B05, L11, L13, and N10 for the
GGU-packaged device; and B10, C09, F12, G03, H02, and L17 for the GVF-packaged device (SUSPEND, GRST, CDx, and VSx terminals).
§ Applies to external output buffers
¶ These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
7−2
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TERMINALS
OPERATION
PCI
VOH
High-level output voltage
PC Card
IOH = −0.15 mA
0.9 VCC
5V
IOH = −0.15 mA
2.4
IOH = −4 mA
Low-level output voltage
PC Card
0.1 VCC
IOL = 6 mA
0.55
3.3 V
IOL = 0.7 mA
0.1 VCC
5V
IOL = 0.7 mA
0.55
3.6 V
5.25 V
VI = VCC
−1
3.6 V
VI = VCC†
VI = VCC†
10
Input terminals
VI = GND
−1
I/O terminals
VI = GND
−10
Pullup terminals
−330
3.6 V
VI = GND
VI = VCC‡
5.25 V
VI = VCC‡
20
3.6 V
VI = VCC‡
VI = VCC‡
VI = VCC‡
10
Output terminals
IOZH
High-impedance, high-level output
current
Output terminals
Input terminals
IIH
V
0.5
High-impedance, low-level output
current
Low-level input current
V
IOL = 4 mA
VI = VCC
IOZL
High-level input current
I/O terminals
Pulldown
5.25 V
5.25 V
5.25 V
UNIT
VCC−0.6
IOL = 1.5 mA
5V
Miscellaneous
IIL
MAX
2.4
3.3 V
3.3 V
VOL
MIN
0.9 VCC
IOH = −2 mA
5V
Miscellaneous
PCI
TEST CONDITIONS
IOH = −0.5 mA
3.3 V
−1
25
V
µA
A
µA
A
µA
10
µA
25
30
† For PCI and miscellaneous terminals, VI = VCCP. For PC Card terminals, VI = VCCCB.
‡ For I/O terminals, input leakage (IIL and IIH) includes IOZ leakage of the disabled output.
7.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
PARAMETER
tc
tw(H)
Cycle time, PCLK
tw(L)
tr, tf
tw
tsu
Pulse duration (width), PRST
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
30
ns
11
ns
Pulse duration (width), PCLK low
tcyc
thigh
tlow
11
ns
Slew rate, PCLK
∆v/∆t
1
trst
1
ms
100
ms
Pulse duration (width), PCLK high
Setup time, PCLK active at end of PRST
trst-clk
4
V/ns
7−3
7.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A
indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time,
td (ten, tdis) = delay time, tsu = setup time, and th = hold time.
ALTERNATE
SYMBOL
PARAMETER
tpd
Propagation delay time, See Note 4
PCLK-to-shared signal
valid delay time
tval
PCLK-to-shared signal
invalid delay time
tinv
ten
tdis
Enable time, high impedance-to-active delay time from PCLK
tsu
th
Setup time before PCLK valid
Disable time, active-to-high impedance delay time from PCLK
Hold time after PCLK high
TEST CONDITIONS
MIN
CL = 50 pF,
See Note 4
UNIT
11
ns
2
ton
toff
2
tsu
th
7
ns
0
ns
NOTE 4: PCI shared signals are AD31−AD0, C/BE3−C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
7−4
MAX
ns
28
ns
8 Mechanical Information
The PCI1510 is packaged in either a 144-ball GGU or ZGU BGA, 209-ball GVF or ZVF BGA, or a 144-pin PGE
package. The following shows the mechanical dimensions for the GGU, GVF, PGE, ZGU, and ZVF packages.
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
12,10
SQ
11,90
9,60 TYP
0,80
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,12
0,08
0,55
0,45
0,08 M
0,45
0,35
0,10
4073221-2/B 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments.
8−1
GVF (S−PBGA−N209)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
8−2
PLASTIC BALL GRID ARRAY
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°−ā 7°
0,75
0,45
1,45
1,35
Seating Plane
1,60 MAX
0,08
4040147 / C 10/96
NOTES: C. All linear dimensions are in millimeters.
D. This drawing is subject to change without notice.
E. Falls within JEDEC MS-026
8−3
ZGU (S−PBGA−N144)
PLASTIC BALL GRID ARRAY
12,10
SQ
11,90
9,60 TYP
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
0,80
1 2 3 4 5 6 7 8 9 10 11 12 13
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4204394/A 04/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
D. This package is lead-free.
8−4
ZVF (S−PBGA−N209)
PLASTIC BALL GRID ARRAY
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package is lead-free.
8−5
8−6