DATASHEET

1.2A High Efficiency Buck-Boost Regulator
ISL9110A
Features
The ISL9110A is a highly-integrated Buck-Boost switching
regulator that accepts input voltages either above or below the
regulated output voltage. Unlike other Buck-Boost regulators, this
regulator automatically transitions between operating modes
without significant output disturbance.
• Accepts Input Voltages Above or Below Regulated Output
Voltage
This part is capable of delivering up to 1.2A output current, and
provides excellent efficiency due to its fully synchronous 4-switch
architecture. No-load quiescent current of only 35µA also
optimizes efficiency under light-load conditions. Forced PWM
and/or synchronization to an external clock may also be selected
for noise sensitive applications.
• Automatic and Seamless Transitions Between Buck and Boost
Modes
• Input Voltage Range: 1.8V to 5.5V
• Output Current: Up to 1.2A
• High Efficiency: Up to 95%
• 35µA Quiescent Current Maximizes Light-load Efficiency
• 2.5MHz Switching Frequency Minimizes External Component
Size
The ISL9110A is designed for standalone applications and
supports 3.3V and 5V fixed output voltages or variable output
voltages with an external resistor divider. Output voltages as low
as 1V, or as high as 5.2V are supported using an external resistor
divider.
• Selectable Forced-PWM Mode and External Synchronization
The ISL9110A requires only a single inductor and very few
external components. Power supply solution size is minimized by
a 2.4mm x 1.6mm WLCSP package and a 2.5MHz switching
frequency, which further reduces the size of external
components.
Applications
• Fully Protected for Overcurrent, Over-temperature and
Undervoltage
• Small 2.4mmx1.6mm WLCSP Package
• Regulated 3.3V from a Single Li-Ion Battery
• Smart Phones and Tablet Computers
• Handheld Devices
• Point-of-Load Regulators
Related Literature
• See AN1750 “ISL9110A Evaluation Board User Guide”
100
ISL9110AIITNZ
A1
B1
PVIN
LX1
A2
B2
LX2
A4
B4
VOUT
A5
B5
C1
10µF
STATUS
OUTPUTS
D2
D1
MODE
EN
BAT
PG
D4
C5
GND
FB
D5
L1
2.2µH
VOUT = 3.3V/1A
C2
10µF
PGND
C4
C2
C3
D3
VIN
A3
B3
C1
95
EFFICIENCY (%)
VIN = 1.8V TO 5.5V
90
VIN = 5V
85
80
VIN = 3V
VIN = 2.5V
75
VOUT = 3.3V
70
0.01
0.05
0.25
1.25
IOUT (A)
FIGURE 1. TYPICAL APPLICATION
June 8, 2012
FN8299.1
1
FIGURE 2. EFFICIENCY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9110A
Block Diagram
LX1
A2 B2
A1
B1
A5
VOUT
B5
EN C2
VIN C1
GATE
DRIVERS
& ANTISHOOT THRU
EN
VREF
SOFT
DISCHARGE
REVERSE
CURRENT
PVIN
LX2
A4 B4
EN
EN
BAT D2
A3 PGND
B3
C3
C4
PVIN
MONITOR
THERMAL
SHUTDOWN
MODE/SYNC D3
VOUT
CLAMP
PWM
CONTROL
CURRENT
DETECT
EN
EN
D1 PG
VOUT
MONITOR
D5 FB
EN
OSC
REF
ERROR
AMP
VOLTAGE
PROG.
C5 D4
GND
Pin Configurations
ISL9110A
(20 BALL WLCSP)
TOP VIEW
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
A5
B5
C5
D5
2
Pin Descriptions
PIN #
PIN
NAMES
A5, B5
VOUT
Buck/boost output. Connect a 10µF capacitor to
PGND.
A4, B4
LX2
Inductor connection, output side.
A3, B3,
C3, C4
PGND
A2, B2
LX1
Inductor connection, input side.
A1, B1
PVIN
Power input. Range: 1.8V to 5.5V. Connect a 10µF
capacitor to PGND.
C1
VIN
Supply input. Range: 1.8V to 5.5V.
D1
PG
Open drain output. Provides output-power-good
status.
D2
BAT
Open drain output. Provides input-power-good
status.
C2
EN
Logic input, drive high to enable device.
D3
MODE/
SYNC
C5, D4
GND
D5
FB
DESCRIPTION
Power ground for high switching current.
Logic input, high for auto PFM mode. Low for forced
PWM operation.
Ext. clock sync input. Range: 2.75MHz to 3.25MHz.
Analog ground pin.
Voltage feedback pin.
FN8299.1
June 8, 2012
ISL9110A
Ordering Information
PART NUMBER
(Note 3)
PART MARKING
VOUT
(V)
TEMP RANGE
(°C)
PACKAGE
Tape and Reel
(Pb-free)
PKG.
DWG. #
ISL9110AIITNZ-T (Notes 1, 2)
DZBE
3.3
-40 to +85
20 Ball WLCSP
W4x5.20A
ISL9110AIITAZ-T (Notes 1, 2)
DZBD
ADJ
-40 to +85
20 Ball WLCSP
W4x5.20A
ISL9110AIITNZ-EVAL1Z
Evaluation Board
ISL9110AIITAZ-EVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and
SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9110A. For more information on MSL please see techbrief TB363.
3
FN8299.1
June 8, 2012
ISL9110A
Table of Contents
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Internal Supply and References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
POR Sequence and Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Short Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PG Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BAT Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ultrasonic Mode (Available Upon Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Buck-Boost Conversion Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PFM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operation With VIN Close to VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Voltage Programming, Adj. Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Feed-Forward Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Non-Adjustable Version FB Pin Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PVIN and VOUT Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
FN8299.1
June 8, 2012
ISL9110A
Absolute Maximum Ratings
Thermal Information
PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
LX1, LX2 (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
FB (Adjustable Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
FB (Fixed VOUT Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
GND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
20 Ball WLSCP Package (Notes 4, 5) . . . .
66
1
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
5. For θJC, the “case temp” location is taken at the package top center.
6. LX1 and LX2 pins can withstand switching transients of -1.5V for 100ns, and 7V for 20ms.
Analog Specifications VVIN = VPVIN = VEN = 3.6V, VOUT = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 7) (Note 8) (Note 7)
UNITS
POWER SUPPLY
VIN
VUVLO
Input Voltage Range
1.8
VIN Undervoltage Lockout Threshold
Rising
Falling
IVIN
VIN Supply Current
PFM mode, no external load on Vout (Note 9)
ISD
VIN Supply Current, Shutdown
EN = GND, VIN = 3.6V
5.5
1.725
1.550
V
1.775
1.650
V
V
35
60
µA
0.05
1.0
µA
OUTPUT VOLTAGE REGULATION
VOUT
Output Voltage Range
ISL9110AIITAZ, IOUT = 100mA
Output Voltage Accuracy
VIN = 3.7V, VOUT = 3.3V, IOUT = 0mA, PWM mode
VIN = 3.7V, VOUT = 3.3V, IOUT = 1mA, PFM mode
1.00
5.20
V
-2
+2
%
+4
%
-3
VFB
FB Pin Voltage Regulation
For adjustable output version
0.79
0.80
IFB
FB Pin Bias Current
For adjustable output version
ΔVOUT/
ΔVIN
Line Regulation, PWM Mode
IOUT = 500mA, VOUT = 3.3V, MODE = GND, VIN step
from 2.3V to 5.5V
±0.005
mV/mV
ΔVOUT/
ΔIOUT
Load Regulation, PWM Mode
VIN = 3.7V, VOUT = 3.3V, MODE = GND, IOUT step
from 0mA to 500mA
±0.005
mV/mA
ΔVOUT/
ΔVI
Line Regulation, PFM Mode
IOUT = 100mA, VOUT = 3.3V, MODE = VIN, VIN step
from 2.3V to 5.5V
±12.5
mV/V
ΔVOUT/
ΔIOUT
Load Regulation, PFM Mode
VIN = 3.7V, VOUT = 3.3V, MODE = VIN, IOUT step from
0mA to 100mA
±0.4
mV/mA
VCLAMP
Output Voltage Clamp
Rising, VIN = 3.6V
Output Voltage Clamp Hysteresis
VIN = 3.6V
5.25
0.81
V
1
µA
5.95
400
V
mV
DC/DC SWITCHING SPECIFICATIONS
fSW
tONMIN
Oscillator Frequency
2.25
Minimum On Time
2.50
2.75
80
MHz
ns
IPFETLEAK
LX1 Pin Leakage Current
-1
1
µA
INFETLEAK
LX2 Pin Leakage Current
-1
1
µA
5
FN8299.1
June 8, 2012
ISL9110A
Analog Specifications VVIN = VPVIN = VEN = 3.6V, VOUT = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
MIN
TYP
MAX
(Note 7) (Note 8) (Note 7)
UNITS
Time from when EN signal asserts to when output
voltage ramp starts.
1
ms
Time from when output voltage ramp starts to
when output voltage reaches 95% of its nominal
value with device operating in buck mode.
VIN = 4V, VOUT = 3.3V, IO = 200mA
1
ms
Time from when output voltage ramp starts to
when output voltage reaches 95% of its nominal
value with device operating in boost mode.
VIN = 2V, VOUT = 3.3V, IO = 200mA
2
ms
VIN = 3.6V, EN < VIL
120
Ω
VIN = 3.6V, IO = 200mA
0.10
0.17
Ω
VIN = 2.5V, IO = 200mA
0.13
0.23
Ω
VIN = 3.6V, IO = 200mA
0.09
0.15
Ω
VIN = 2.5V, IO = 200mA
0.11
0.23
Ω
2.4
2.8
A
PARAMETER
TEST CONDITIONS
SOFT-START and SOFT DISCHARGE
tSS
RDISCHG
Soft-start Time
VOUT Soft-Discharge ON-Resistance
POWER MOSFET
RDSON_P
RDSON_N
IPK_LMT
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
P-Channel MOSFET Peak Current Limit
VIN = 3.6V
2.0
PFM/PWM TRANSITION
Load Current Threshold, PFM to PWM
VIN = 3.6V, VOUT = 3.3V
200
mA
Load Current Threshold, PWM to PFM
VIN = 3.6V, VOUT = 3.3V
75
mA
External Synchronization Frequency Range
2.75
3.25
MHz
Thermal Shutdown
155
°C
Thermal Shutdown Hysteresis
30
°C
BATTERY MONITOR AND POWER GOOD COMPARATORS
VTBMON
Battery Monitor Voltage Threshold
VHBMON
Battery Monitor Voltage Hysteresis
100
Battery Monitor Debounce Time
25
µs
PG Delay Time (Rising)
1
ms
20
µs
tBMON
1.85
PG Delay Time (Falling)
Minimum Supply Voltage for Valid PG Signal
EN = VIN
2.0
2.15
V
mV
1.2
V
PGRNGLR
PG Range - Lower (Rising)
Percentage of programmed voltage
90
%
PGRNGLF
PG Range - Lower (Falling)
Percentage of programmed voltage
87
%
PGRNGUR
PG Range - Upper (Rising)
Percentage of programmed voltage
112
%
PGRNGUF
PG Range - Upper (Falling)
Percentage of programmed voltage
110
%
Compliance Voltage - PG, BAT
VIN = 3.6V, ISINK = 1mA
0.3
V
1
µA
LOGIC INPUTS
ILEAK
Input Leakage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.05
1.4
V
0.4
V
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Typical values are for TA = +25°C and VIN = 3.6V.
9. Quiescent current measurements are taken when the output is not switching.
6
FN8299.1
June 8, 2012
ISL9110A
Typical Performance Curves
100
100
VIN = 4V
VIN = 3V
95
VIN = 4.5V
EFFICIENCY (%)
EFFICIENCY (%)
95
90
85
VIN = 2V
80
75
VIN = 5V
90
VIN = 5V
VIN = 4V
85
80
VIN = 2V
VIN = 3V
VIN = 2.5V
75
VIN = 2.5V
VOUT = 2.0V
70
0.01
VIN = 4.5V
0.05
0.25
VOUT = 3.3V
70
0.01
1.25
0.05
FIGURE 3. EFFICIENCY vs OUTPUT CURRENT, VOUT = 2V
100
2.5
VOUT = 2V
2.0
VIN = 4.5V
85
80
IOUT (A)
EFFICIENCY (%)
95
90
VIN = 2V
VIN = 2.5V
VOUT = 4.0V
70
0.01
0.05
0.25
VOUT = 3.3V
1.5
1.0
VOUT = 5V
VIN = 3V
0.5
75
0.0
1.5
1.25
2.0
2.5
FIGURE 5. EFFICIENCY vs OUTPUT CURRENT, VOUT = 4V
4.0
4.5
5.0
5.5
60
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (mA)
3.5
FIGURE 6. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
9
8
+85°C
+25°C
6
5
3.0
VIN (V)
IOUT (A)
7
1.25
FIGURE 4. EFFICIENCY vs OUTPUT CURRENT, VOUT = 3.3V
VIN = 4V
VIN = 5V
0.25
IOUT (A)
IOUT (A)
0°C
-40°C
VOUT = 3.3V
4
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIN (V)
FIGURE 7. PWM MODE QUIESCENT CURRENT, VOUT = 3.3V,
NO LOAD
7
5.5
55
50
+85°C
+25°C
45
40
35
0°C
-40°C
VOUT = 3.3V
30
1.5
2.5
3.5
4.5
5.5
VIN (V)
FIGURE 8. PFM MODE QUIESCENT CURRENT, VOUT = 3.3V,
NO LOAD
FN8299.1
June 8, 2012
ISL9110A
Typical Performance Curves
(Continued)
VIN = 4.5V → 2.5V
VOUT = 3.3V
IOUT = 500mA
LX1
5V/DIV
VIN = 2.5V → 4.5V
VOUT = 3.3V
IOUT = 500mA
LX1
5V/DIV
LX2
5V/DIV
LX2
5V/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
INDUCTOR
CURRENT
0.5A/DIV
400µs/DIV
400µs/DIV
FIGURE 9. STEADY STATE TRANSITION FROM BUCK TO BOOST
FIGURE 10. STEADY STATE TRANSITION FROM BOOST TO BUCK
LX1
2V/DIV
VOUT
50mV/DIV
LX2
2V/DIV
VIN
2V/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
VIN = 4.5V → 2.5V → 4.5V
VOUT = 3.3V
IOUT = 400mA
VIN = 3.6V
VOUT = 3.3V
IOUT = 0.6A
50µs/DIV
400ns/DIV
FIGURE 11. STEADY STATE VIN NEAR VOUT
FIGURE 12. INPUT TRANSIENT
LX1
5V/DIV
LX1
5V/DIV
LX2
5V/DIV
LX2
5V/DIV
VOUT
0.1V/DIV
VOUT
0.1V/DIV
INDUCTOR
CURRENT
0.5A/DIV
VIN = 2V
VOUT = 3.3V
IOUT = 0A TO 0.4A
100µs/DIV
FIGURE 13. TRANSIENT LOAD RESPONSE
8
INDUCTOR
CURRENT
0.5A/DIV
VIN = 3.6V
VOUT = 3.3V
IOUT = 0A TO 1A
100µs/DIV
FIGURE 14. TRANSIENT LOAD RESPONSE
FN8299.1
June 8, 2012
ISL9110A
Typical Performance Curves
(Continued)
LX1
2V/DIV
LX1
5V/DIV
LX2
2V/DIV
LX2
5V/DIV
VOUT
10mV/DIV
VOUT
10mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
VIN = 2.5V
VOUT = 3.3V
IOUT = 500mA
INDUCTOR
CURRENT
0.5A/DIV
VIN = 4.5V
VOUT = 3.3V
IOUT = 1A
400ns/DIV
400ns/DIV
FIGURE 16. SWITCHING WAVEFORMS, BUCK MODE
0.25
0.25
0.20
0.20
+40°C
0.15
RDS(ON) (Ω)
RDS(ON) (Ω)
FIGURE 15. SWITCHING WAVEFORMS, BOOST MODE
+85°C
0.10
0.00
1.5
2.0
2.5
+85°C
0.15
0.10
-40°C
0°C
-40°C
0.05
+40°C
0.05
0°C
3.0
3.5
4.0
4.5
5.0
0.00
1.5
5.5
2.0
2.5
VIN (V)
0.805
3.285
VOUT (V)
VREF (V)
3.290
0.800
3.275
0.790
-40
I
= 0.4A (PWM)
3.270 OUT
1.5
2.5
40
60
80
TEMPERATURE (°C)
FIGURE 19. VREF vs TEMPERATURE, TA = -40°C TO +85°C
9
4.5
5.0
5.5
100
NO LOAD
(PFM)
IOUT = 0.1A
(PFM)
3.280
0.795
20
4.0
FIGURE 18. PFET rDS(ON) vs INPUT VOLTAGE
0.810
0
3.5
VIN (V)
FIGURE 17. NFET rDS(ON) vs INPUT VOLTAGE
-20
3.0
IOUT = 0.8A (PWM)
IOUT = 1.2A
(PWM)
3.5
4.5
5.5
VIN (V)
FIGURE 20. OUTPUT VOLTAGE vs VIN VOLTAGE (VOUT = 3.3V)
FN8299.1
June 8, 2012
ISL9110A
Typical Performance Curves
(Continued)
VIN = 4V
VOUT = 3.3V
LX1 I
= 200mA
2V/DIV OUT
LX1
2V/DIV
LX2
2V/DIV
LX2
2V/DIV
VOUT
2V/DIV
VOUT
2V/DIV
EN
2V/DIV
VIN = 2V
VOUT = 3.3V
IOUT = 200mA
EN
2V/DIV
400µs/DIV
400µs/DIV
FIGURE 21. SOFT-START, VIN = 4V, VOUT = 3.3V
FIGURE 22. SOFT-START, VIN = 2V, VOUT = 3.3V
3.315
3.310
3.310
3.305
LOAD CURRENT FALLING
VOUT (V)
3.300
3.300
3.295
LOAD CURRENT RISING
3.285
3.285
3.280
0.0
3.295
3.290
LOAD CURRENT RISING
3.290
0.1
0.2
0.3
0.4
LOAD CURRENT FALLING
3.280
0.0
0.1
0.2
0.5
IOUT (mA)
0.3
0.4
0.5
IOUT (mA)
FIGURE 23. OUTPUT VOLTAGE vs LOAD CURRENT
(VIN = 2.5V, VOUT = 3.3V, AUTO PFM/PWM MODE)
FIGURE 24. OUTPUT VOLTAGE vs LOAD CURRENT
(VIN = 4.5V, VOUT = 3.3V, AUTO PFM/PWM MODE)
0.25
VIN = 3.7V
VOUT = 3.3V
EN
1V/DIV
PFM to PWM TRANSITION
0.20
IOUT (A)
VOUT (V)
3.305
0.15
0.10
PWM to PFM TRANSITION
0.05
VOUT
1V/DIV
0.00
2.0
4ms/DIV
FIGURE 25. OUTPUT SOFT-DISCHARGE
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
FIGURE 26. PFM to PWM MODE CHANGE THRESHOLD CURRENT
vs INPUT VOLTAGE (VOUT = 3.3V)
FN8299.1
June 8, 2012
ISL9110A
Functional Description
Functional Overview
Refer to the “Block Diagram” on page 2. The ISL9110A
implements a complete buck boost switching regulator, with
PWM controller, internal switches, references, protection
circuitry, and control inputs.
The PWM controller automatically switches between buck and
boost modes as necessary to maintain a steady output voltage,
with changing input voltages and dynamic external loads.
The ISL9110A provides output-power-good and input-power-good
open-drain status outputs on pins 7 and 8.
Internal Supply and References
Referring to the “Block Diagram” on page 2, the ISL9110A
provides two power input pins. The PVIN pin supplies input power
to the DC/DC converter, while the VIN pin provides operating
voltage source required for stable VREF generation. Separate
ground pins (GND and PGND) are provided to avoid problems
caused by ground shift due to the high switching currents.
Enable Input
A master enable pin EN allows the device to be enabled. Driving
EN low invokes a power-down mode, where most internal device
functions, including input and output power good detection, are
disabled.
Soft Discharge
When the device is disabled by driving EN low, an internal resistor
between VOUT and GND is activated. This internal resistor has a
typical 120Ω resistance.
POR Sequence and Soft-start
Bringing the EN pin high allows the device to power-up. A number
of events occur during the start-up sequence. The internal voltage
reference powers up, and stabilizes. The device then starts
operating. There is a typical 1ms delay between assertion of the
EN pin and the start of switching regulator soft-start ramp.
The soft-start feature minimizes output voltage overshoot and
input inrush currents. During soft-start, the reference voltage is
ramped to provide a ramping VOUT voltage. While output voltage
is lower than approximately 20% of the target output voltage,
switching frequency is reduced to a fraction of the normal
switching frequency to aid in producing low duty cycles necessary
to avoid input inrush current spikes. Once the output voltage
exceeds 20% of the target voltage, switching frequency is
increased to its nominal value.
When the target output voltage is higher than the input voltage,
there will be a transition from buck mode to boost mode during
the soft-start sequence. At the time of this transition, the ramp
rate of the reference voltage is decreased, such that the output
voltage slew rate is decreased. This provides a slower output
voltage slew rate.
The VOUT ramp time is not constant for all operating conditions.
Soft-start into boost mode will take longer than soft-start into
buck mode. The total soft-start time into buck operating mode is
11
typically 2ms, whereas the typical soft-start time into boost
mode operating mode is typically 3ms. Increasing the load
current will increase these typical soft-start times.
Overcurrent Protection
When the current in the P-Channel MOSFET is sensed to reach
the current limit for 16 consecutive switching cycles, the internal
protection circuit is triggered, and switching is stopped for
approximately 20ms. The device then performs a soft-start cycle.
If the external output overcurrent condition exists after the
soft-start cycle, the device will again detect 16 consecutive
switching cycles reaching the peak current threshold. The
process will repeat as long as the external overcurrent condition
is present. This behavior is called ‘hiccup mode’.
Short Circuit Protection
The ISL9110A provides short-circuit protection by monitoring the
feedback voltage. When feedback voltage is sensed to be lower
than a certain threshold, the PWM oscillator frequency is
reduced in order to protect the device from damage. The
P-Channel MOSFET peak current limit remains active during this
state.
Undervoltage Lockout
The undervoltage lockout (UVLO) feature prevents abnormal
operation in the event that the supply voltage is too low to
guarantee proper operation. When the VIN voltage falls below the
UVLO threshold, the regulator is disabled.
PG Status Output
An open drain output-power-good signal is provided in the
ISL9110A. An internal window comparator is used to detect
when VOUT is significantly higher or lower than the target output
voltage. The PG output will be driven low when sensed VOUT
voltage is outside of this ‘power good’ window. When VOUT
voltage is inside the ‘power-good’ window, the PG pin goes Hi-Z.
The PG detection circuit detects this condition by monitoring
voltage on the FB pin. Hysteresis is provided for the upper and
lower PG thresholds to avoid oscillation of the PG output.
BAT Status Output
The ISL9110A provides an open drain input-power-good status
output. The BAT status pin will be driven low when VIN rises above
the VTBMON threshold. The BAT status output goes Hi-Z when
VBAT falls below the VTBMON threshold. Hysteresis is provided for
the VTBMON threshold to avoid oscillation of the BAT output.
Ultrasonic Mode (Available Upon Request)
The ISL9110A provides an ultrasonic mode that can be enabled
during IC manufacturing upon request.
In ultrasonic mode, the PFM switching frequency is forced to be
above the audio frequency range.
This ultrasonic mode applies only to PFM mode operation. When
enabled, the PFM mode switching frequency is forced well above
the audio frequency range (fSW becomes typically 60kHz). This
mode of operation, however, reduces the efficiency at light load.
FN8299.1
June 8, 2012
ISL9110A
Thermal Shutdown
A built-in thermal protection feature protects the ISL9110A, if the
die temperature reaches +155°C (typical). At this die
temperature, the regulator is completely shut down. The die
temperature continues to be monitored in this thermal-shutdown
mode. When the die temperature falls to +125°C (typical), the
device will resume normal operation.
When exiting thermal shutdown, the ISL9110A will execute its
soft-start sequence.
External Synchronization
An external sync feature is provided. Applying a clock signal with
a frequency between 2.75MHz and 3.25MHz at the MODE/SYNC
input forces the ISL9110A to synchronize to this external clock.
The MODE/SYNC input supports standard logic levels.
Buck-Boost Conversion Topology
The ISL9110A operates in either buck or boost mode. When
operating in conditions where VIN is close to VOUT, the ISL9110A
alternates between buck and boost mode as necessary to
provide a regulated output voltage.
L1
LX1
LX2
SWITCH A
SWITCH D
VOUT
PVIN
SWITCH B
SWITCH C
During PFM operation in boost mode, the ISL9110A closes
Switch A and Switch C to ramp up the current in the inductor.
When inductor current reaches a certain threshold, the device
turns off Switches A and C, then turns on Switches B and D. With
Switches B and D closed, output voltage increases as the
inductor current ramps down.
In most operating conditions, there will be multiple PFM pulses
to charge up the output capacitor. These pulses continue until
VOUT has achieved the upper threshold of the PFM hysteretic
controller. Switching then stops, and remains stopped until VOUT
decays to the lower threshold of the hysteretic PFM controller.
Operation With VIN Close to VOUT
When the output voltage is close to the input voltage, the
ISL9110A will rapidly and smoothly switch from boost to buck
mode as needed to maintain the regulated output voltage. This
behavior provides excellent efficiency and very low output
voltage ripple.
Output Voltage Programming
The ISL9110A is available in fixed and adjustable output voltage
versions. To use the fixed output version, the VOUT pin must be
connected directly to FB.
In the adjustable output voltage version (ISL9110AIITAZ), an
external resistor divider is required to program the output
voltage. The FB pin has very low input leakage current, so it is
possible to use large value resistors (e.g. R1 = 1MΩ and
R2 = 324kΩ) in the resistor divider connected to the FB input.
Applications Information
Component Selection
Figure 27 shows a simplified diagram of the internal switches
and external inductor.
PWM Operation
In buck PWM mode, Switch D is continuously closed, and
Switch C is continuously open. Switches A and B operate as a
synchronous buck converter when in this mode.
In boost PWM mode, Switch A remains closed and Switch B
remains open. Switches C and D operate as a synchronous boost
converter when in this mode.
PFM Operation
The fixed-output version of the ISL9110A requires only three
external power components to implement the buck boost
converter: an inductor, an input capacitor, and an output
capacitor.
The adjustable ISL9110A versions require three additional
components to program the output voltage. Two external
resistors program the output voltage, and a small capacitor is
added to improve stability and response.
An optional input supply filtering capacitor (“C3” in Figure 28)
can be used to reduce the supply noise on the VIN pin, which
provides power to the internal reference. In most applications,
this capacitor is not needed.
V IN =
1.8V TO 5.5V
During PFM operation in buck mode, Switch D is continuously
closed, and Switch C is continuously open. Switches A and B
operate in discontinuous mode during PFM operation.
ISL9110AIITAZ
A1
B1
PVIN
LX1
C1
10µF
C3
1µF
STATUS
OUTPUTS
C1
D3
C2
D2
D1
VIN
MODE
EN
BAT
PG
C5
D4
GND
LX2
VOUT
FB
PGND
A2
B2
A4
B4
A5
B5
D5
L1
2.2µH
R1
1M
V OUT =
3.0V/1A
C4
56pF
C2
10µF
R2
365k
A3
B3
C3
C4
FIGURE 27. BUCK BOOST TOPOLOGY
FIGURE 28. TYPICAL ISL9110AIITAZ APPLICATION
12
FN8299.1
June 8, 2012
ISL9110A
Output Voltage Programming, Adj. Version
PVIN and VOUT Capacitor Selection
Setting and controlling the output voltage of the ISL9110AIITAZ
(adjustable output version) can be accomplished by selecting the
external resistor values.
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
10µF. The recommended VOUT capacitor value is 10µF to 22µF.
Equation 1 can be used to derive the R1 and R2 resistor values:
TABLE 2. CAPACITOR VENDOR INFORMATION
R1
V OUT = 0.8V • ⎛ 1 + --------⎞
⎝
R2⎠
(EQ. 1)
When designing a PCB, include a GND guard band around the
feedback resistor network to reduce noise and improve accuracy
and stability. Resistors R1 and R2 should be positioned close to
the FB pin.
Feed-Forward Capacitor Selection
A small capacitor (C4 in Figure 28) in parallel with resistor R1 is
required to provide the specified load and line regulation. The
suggested value of this capacitor is 56pF for R1 = 1MΩ. An NPO
type capacitor is recommended.
Non-Adjustable Version FB Pin Connection
MANUFACTURER
X5R
www.avx.com
Murata
X5R
www.murata.com
Taiyo Yuden
X5R
www.t-yuden.com
TDK
X5R
www.tdk.com
Application Example 1
An application using the fixed-output ISL9110AIITNZ is shown in
Figure 30. This application requires only three external
components.
A1
B1
C1
D3
A2
B2
D2
D1
A4
B4
EN
VOUT
A5
B5
BAT
PG
FB
D5
VOUT
A5
B5
STATUS
OUTPUTS
L1
2.2µH
D1
MODE
EN
BAT
PG
FB
D5
L1
2.2µH
V OUT =
3.3V/1A
C2
10µF
PGND
GND
A3
B3
C3
C4
LX2
MODE
LX2
A4
B4
V OUT =
3.3V/1A
C2
10µF
FIGURE 30. TYPICAL ISL9110AIITNZ APPLICATION
PGND
Application Example 2
A3
B3
C3
C4
C5
D4
GND
FIGURE 29. TYPICAL ISL9110AIITNZ APPLICATION
Inductor Selection
An application requiring VOUT = 3.0V, using the adjustable-output
ISL9110AIITAZ is shown in Figure 31. This application requires
six external components.
ISL9110AIITAZ
V IN =
1.8V-5.5V
An inductor with high frequency core material (e.g. ferrite core)
should be used to minimize core losses and provide good
efficiency. The inductor must be able to handle the peak
switching currents without saturating.
A 2.2µH inductor with ≥2.4A saturation current rating is
recommended. Select an inductor with low DCR to provide good
efficiency. In applications where radiated noise must be
minimized, a toroidal or shielded inductor can be used.
A1
B1
PVIN
LX1
A2
B2
LX2
A4
B4
VOUT
A5
B5
C1
10µF
C1
D3
C2
STATUS
OUTPUTS
D2
D1
VIN
MODE
EN
BAT
PG
GND
FB
D5
PGND
L1
2.2µH
R1
1M
C4
56pF
V OUT =
3.0V/1A
C2
10µF
R2
365k
A3
B3
C3
C4
C2
VIN
D2
C5
D4
C1
D3
A2
B2
VIN
C5
D4
LX1
PVIN
LX1
PVIN
C1
10µF
C2
C1
10µF
STATUS
OUTPUTS
ISL9110AIITNZ
V IN =
1.8V-5.5V
ISL9110AIITNZ
A1
B1
WEBSITE
AVX
The fixed output versions of the ISL9110A does not require
external resistors or a capacitor on the FB pin. Simply connect
VOUT to FB, as shown in Figure 29.
V IN =
1.8V-5.5V
SERIES
TABLE 1. INDUCTOR VENDOR INFORMATION
MANUFACTURER
SERIES
WEBSITE
Coilcraft
LPS4018
www.coilcraft.com
Murata
LQH44P
www.murata.com
Taiyo Yuden
NRS4018
NRS5012
www.t-yuden.com
Sumida
CDRH3D23/HP
CDRH4D22/HP
www.sumida.com
Toko
DEM3518C
www.toko.co.jp
13
FIGURE 31. TYPICAL ISL9110AIITAZ APPLICATION
Recommended PCB Layout
Correct PCB layout is critical for proper operation of the
ISL9110A. The input and output capacitors should be positioned
as closely to the IC as possible. The ground connections of the
input and output capacitors should be kept as short as possible,
and should be on the component layer to avoid problems that are
caused by high switching currents flowing through PCB vias.
FN8299.1
June 8, 2012
ISL9110A
FIGURE 32. RECOMMENDED ISL9110AIITNZ PCB LAYOUT
14
FIGURE 33. RECOMMENDED ISL9110AIITAZ PCB LAYOUT
FN8299.1
June 8, 2012
ISL9110A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
May 29, 2012
FN8299.1
Corrected “Pin Configuration” on page 2.
May 11, 2012
FN8299.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL9110A
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN8299.1
June 8, 2012
ISL9110A
Package Outline Drawing
W4x5.20A
20 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 1, 1/12
1.200
X
1.595±0.02
Y
0.400
5
0.400
4
20x 0.270±0.03
3
2.335±0.02
1.600
2
1
0.367
(4X)
0.10
A
TOP VIEW
B
C
D
0.197
0.200
PIN 1 (A1 CORNER)
BOTTOM VIEW
Z
0.05 Z
3
SEATING PLANE
PACKAGE OUTLINE
0.225
0.300±0.025
0.400
0.270±0.03
0.275
0.10
0.05
ZXY
Z
0.175±0.03
0.530 MAX
TYPICAL RECOMMENDED LAND PATTERN
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASME Y 14.5M - 1994.
2. Dimension is measured at the maximum bump diameter
parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical
crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. There shall be a minimum clearance of 0.10mm between
the edge of the bump and the body edge.
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FN8299.1
June 8, 2012
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